PCIe device dynamic link segmentation method, PCIe device and medium

Abstract

The invention relates to the technical field of computer hardware interfaces, and discloses a PCIe device dynamic link segmentation method, a PCIe device and a medium, each port on the PCIe device is configured with a corresponding priority, a maximum link width and a minimum link width, and the method comprises the following steps: allocating a physical channel corresponding to the maximum link width to a first priority port; when the state machine of the first priority port enters a completion state, determining the actual link establishment width of the first priority port; if the actual link establishment width of the first priority port is smaller than the maximum link width of the first priority port, determining the number of physical channels for link establishment of the first priority port and physical channels without link establishment according to the actual link establishment width and the minimum link width; and allocating the physical channels of which the links are not established to the next priority port until all the physical channels are allocated or all the ports complete link establishment. According to the invention, the resource utilization rate and the link management efficiency of the PCIe equipment can be improved.

Description

Technical Field

[0001] This application relates to the technical field of computer hardware interfaces, and particularly to a method for dynamically splitting PCIe device links, a PCIe device, and a medium. Background Art

[0002] As a common technology in PCIe, bifurcation can split a PCIe physical link into multiple PCIe links to adapt to various different application scenarios (for example, a x16 physical link can be split into 1 x16, or 2 x8, or 4 x4, etc. according to the actually connected device through bifurcation).

[0003] In this traditional design, bifurcation is statically allocated, that is, it is fixed during system initialization. When the software is initialized, it needs to be initialized and configured according to the type of the connected device. If the subsequently connected PCIe device or the replaced PCIe device type is different from the software initialization configuration, the software may need to modify the bifurcation configuration. And when the bifurcation configuration needs to be modified, it will affect the normal operation of the currently established PCIe controller. Summary of the Invention

[0004] In view of this, this application provides a method for dynamically splitting PCIe device links, a PCIe device, and a medium to improve the resource utilization rate and link management efficiency of PCIe devices.

[0005] In a first aspect, this application provides a method for dynamically splitting PCIe device links. Each port on the PCIe device is configured with a corresponding priority, maximum link width, and minimum link width. The method includes: allocating a physical channel corresponding to the maximum link width to the first-priority port; when the state machine of the first-priority port enters the completion state, determining the actual established link width of the first-priority port; if the actual established link width of the first-priority port is less than the maximum link width of the first-priority port, determining the number of physical channels for the first-priority port to establish a link and the unestablished physical channels according to the actual established link width of the first-priority port and the minimum link width of the first-priority port; and allocating the unestablished physical channels to the next-priority port until all physical channels are allocated or all ports complete link establishment.

[0006] The method provided by this application improves the resource utilization rate and link management efficiency of PCIe devices by configuring priorities, maximum link widths, and minimum link widths for each port and dynamically allocating physical channels according to the actual established link width.

[0007] In an alternative embodiment, the method further includes: if the actual link establishment width of the first-priority port is equal to the maximum link width of the first-priority port, then the link establishment of the first-priority port is completed.

[0008] This alternative embodiment ensures that the port communicates with the maximum link width, gives full play to the maximum data transmission capacity, and improves the port link performance.

[0009] In an alternative embodiment, if the actual link establishment width is greater than or equal to the minimum link width, then the number of physical channels of the first-priority port is equal to the actual link establishment width.

[0010] This alternative embodiment ensures that the port can use as many available physical channels as possible on the premise of meeting the minimum link performance requirements, improving the utilization rate of the link.

[0011] In an alternative embodiment, if the actual link establishment width is less than the minimum link width, then the number of physical channels of the first-priority port is equal to the minimum link width.

[0012] This alternative embodiment can ensure that the first-priority port obtains the minimum required link width for its data transmission, improving the reliability of link management.

[0013] In a second aspect, the present application provides a PCIe device. Each port on the PCIe device is configured with a corresponding priority, maximum link width, and minimum link width; the PCIe device includes a multi-port branch management module; the multi-port branch management module is used to allocate physical channels corresponding to the maximum link width for the first-priority port; when the state machine of the first-priority port enters the completion state, determine the actual link establishment width of the first-priority port; if the actual link establishment width is less than the maximum link width, determine the number of physical channels for which the first-priority port has established a link and the physical channels for which no link has been established; allocate the physical channels for which no link has been established to the next-priority port until all physical channels are allocated or all ports complete link establishment.

[0014] The multi-port branch management module of the PCIe device provided by the present application can reasonably allocate resources according to the priorities of each port, making the resource utilization rate of the PCIe device higher.

[0015] In an alternative embodiment, the multi-port branch management module is further used for: if the actual link establishment width of the first-priority port is equal to the maximum link width of the first-priority port, then complete the link establishment of the first-priority port.

[0016] In an alternative embodiment, the multi-port branch management module is further used for: if the actual link establishment width is greater than or equal to the minimum link width, then the number of physical channels of the first-priority port is equal to the actual link establishment width.

[0017] In an alternative embodiment, the multi-port branch management module is further configured to: if the actual link establishment width is less than the minimum link width, the number of physical channels of the first-priority port is equal to the minimum link width.

[0018] In an alternative embodiment, the PCIe device further includes a priority configuration register module, a maximum link width configuration register module, and a minimum link width configuration register module; the priority configuration register module is configured to configure the priorities of the respective ports; the maximum link width configuration register module is configured to configure the maximum link widths of the respective ports; and the minimum link width configuration register module is configured to configure the minimum link widths of the respective ports.

[0019] In this alternative embodiment, by flexibly setting the priorities of the respective ports through the priority configuration register module, and flexibly setting the maximum and minimum link widths of each port through the maximum link width configuration register module and the minimum link width configuration register module, the link management efficiency is improved.

[0020] In a third aspect, the present application provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to cause a computer to execute the PCIe device dynamic link splitting method according to the first aspect or any corresponding embodiment thereof.

[0021] In a fourth aspect, the present application provides a computer program product, including computer instructions, and the computer instructions are used to cause a computer to execute the PCIe device dynamic link splitting method according to the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 is a schematic diagram of PCIe device link splitting shown in an exemplary embodiment;

[0024] Figure 2 is a flowchart of the PCIe device dynamic link splitting method according to an embodiment of the present application;

[0025] Figure 3 is a schematic diagram of a PCIe controller according to an alternative embodiment of the present application;

[0026] Figure 4It is a flowchart of the PCIe device dynamic link segmentation method according to an alternative embodiment of the present application;

[0027] Figure 5 It is a schematic diagram of the physical channel allocation of the first priority port according to an alternative embodiment of the present application;

[0028] Figure 6 It is a schematic diagram of link establishment for the first priority port according to an alternative embodiment of the present application;

[0029] Figure 7 It is a schematic diagram of link establishment for the second priority port according to an alternative embodiment of the present application;

[0030] Figure 8 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present application. Detailed implementation manners

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0032] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect corresponding relationship between two entities, or may indicate an association relationship between them, or may be a relationship such as indication and being indicated, configuration and being configured, etc.

[0033] Figure 1 It is a schematic diagram of PCIe device link segmentation shown in an exemplary embodiment. As Figure 1 shown, the PCIe device has a total of 16 Lanes (Lane is an independent data transmission channel on the PCIe bus, i.e., a physical channel). Assuming that only one PCIe x8 device is connected at the beginning and the remaining 8 physical channels are not in use. At this time, since the software cannot know which of the following two situations the newly connected PCIe device belongs to in the right figure, the software can only choose to configure according to one of the bifurcations. If the subsequently connected PCIe device is different from the bifurcation configured by the software, the software needs to reconfigure according to the connected device. After the software reconfigures the bifurcation, it will also affect the normal operation of the already established link PCIe controller, that is, a new link needs to be established.

[0034] According to an embodiment of the present application, an embodiment of a PCIe device dynamic link segmentation method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0035] In this embodiment, a PCIe device dynamic link segmentation method is provided. Each port on the PCIe device is configured with a corresponding priority, maximum link width, and minimum link width. Figure 2 It is a flowchart of the PCIe device dynamic link segmentation method according to an embodiment of the present application, as Figure 2 shown. The process includes the following steps:

[0036] Step S201, allocate physical channels corresponding to the maximum link width for the first-priority port.

[0037] The PCIe port is a link interface for connecting the PCIe device to another device. Each port on the PCIe device is configured with a priority to determine the priority order during the allocation of physical channels of the link. The port with a higher priority is allocated physical channels first. For example, if the priority of port A is higher than that of port B, then in the case of limited physical channels, port A will obtain more physical channels first. Among them, the link includes one or more physical channels. The physical channel is the basic physical unit in the PCIe link for data transmission.

[0038] Each port is configured with a maximum link width, indicating the maximum link width that the port can support. Optionally, the maximum link widths of each port can be different. The link width refers to the number of physical channels available for data transmission in the PCIe link (such as x1, x4, x8, etc.). For example, if the maximum link width of port A is configured as x8, then port A can use at most 8 physical channels for data transmission.

[0039] Each port is configured with a minimum link width, indicating the minimum link width that the port can accept, that is, the minimum number of physical channels required for the port to communicate. Optionally, the minimum link widths of each port can be different. For example, if the minimum link width of port B is configured as x4, then port B requires at least 4 channels to transmit data.

[0040] First, allocate physical channels for the first-priority port. According to the maximum link width configured for this port, allocate the corresponding number of physical channels to give priority to ensuring the link establishment requirements of the high-priority port.

[0041] Step S202: When the state machine of the first-priority port enters the completion state, determine the actual link establishment width of the first-priority port.

[0042] A state machine is a mechanism for managing the state of a device or system, controlling the behavior of a PCIe device through a series of predefined states and transitions between states.

[0043] In a PCIe device, the completion state of the state machine indicates that the negotiation of the link width of the port has been completed. At this time, the actual link establishment width of the first-priority port, that is, the negotiated link width, is determined. The actual link establishment width refers to the link width actually used by the port during the link establishment process. Among them, the actual link establishment widths of each priority port are not necessarily the same.

[0044] According to the actual link establishment width, allocate link channels, and unused physical channels can be allocated to the next-priority port to improve the utilization rate of link resources.

[0045] Step S203: If the actual link establishment width of the first-priority port is less than the maximum link width of the first-priority port, determine the number of physical channels for link establishment and the unlinked physical channels of the first-priority port according to the actual link establishment width and the minimum link width of the first-priority port.

[0046] If the actual link establishment width of the first-priority port is less than its maximum link width, it is necessary to determine the number of physical channels used for link establishment and the unused physical channels of this port according to the actual link establishment width and its preconfigured minimum link width.

[0047] Specifically, if the actual link establishment width of the first-priority port is greater than or equal to its minimum link width, the number of physical channels for link establishment is equal to the actual link establishment width. If the actual link establishment width is less than the minimum link width, then the number of physical channels for link establishment will be forced to be set to the minimum link width. After determining the number of physical channels for link establishment of the first-priority port, confirm the remaining unlinked physical channels.

[0048] Optionally, if the actual link establishment width of the first-priority port is equal to the maximum link width of the first-priority port, complete the link establishment of the first-priority port.

[0049] When the first-priority port is in the process of link establishment and the actual link establishment width is the same as the previously configured maximum link width, the link establishment process of this port has been completed. The link allocation of the first-priority port has reached its upper limit and no further adjustment is required. Therefore, it can be considered that the link establishment process of this port has been successfully completed, and normal data transmission can be carried out, ensuring that the port communicates at the maximum link width, giving full play to the maximum data transmission capacity, and improving the link performance of the port.

[0050] Optionally, if the actual link establishment width is greater than or equal to the minimum link width, the number of physical channels of the first-priority port is equal to the actual link establishment width.

[0051] When the first-priority port is in the process of link establishment and its actual link establishment width is greater than or equal to the minimum link width configured for this port, the number of physical channels used by this port will be set to the actual link establishment width. Dynamically adjust the allocation of physical channels according to the actual situation of link establishment, ensuring that the port can use as many available physical channels as possible on the premise of meeting the minimum link performance requirements, and improving the utilization rate of the link.

[0052] Optionally, if the actual link establishment width is less than the minimum link width, the number of physical channels of the first-priority port is equal to the minimum link width.

[0053] When the first-priority port is in the process of link establishment and its actual link establishment width is less than the minimum link width configured for this port, the number of physical channels used by this port will be set to the minimum link width, ensuring that the first-priority port obtains the minimum required link width for its data transmission and improving the reliability of link management.

[0054] Step S204: Allocate the unlinked physical channels to the next-priority port until all physical channels are allocated or all ports complete link establishment.

[0055] The above steps allocate physical channels to the first-priority port and determine the number of physical channels for its link establishment and the unlinked physical channels. According to the priority order of the ports, allocate the unlinked physical channels to the next-priority port. Repeat steps S101 - S103. For example, allocate physical channels corresponding to the maximum link width to the second-priority port. When the state machine of the second-priority port enters the completed state, determine the actual link establishment width of the second-priority port. According to the actual link establishment width and the minimum link establishment width of the second-priority port, determine the number of physical channels for the second-priority port's link establishment and the unlinked physical channels, and then allocate the unlinked physical channels to the next-priority port. Cycle in this way until all physical channels are allocated or all ports complete link establishment.

[0056] The PCIe device dynamic link segmentation method provided in this embodiment improves the resource utilization rate and link management efficiency of the PCIe device by configuring priorities, maximum link widths, and minimum link widths for each port and dynamically allocating physical channels according to the actual link establishment width.

[0057] In this embodiment, a PCIe device is further provided. Each port on the PCIe device is configured with corresponding priority, maximum link width, and minimum link width;

[0058] The PCIe device includes a multi-port branch management module;

[0059] The multi-port branch management module is used to allocate physical channels with the corresponding maximum link width for the first-priority port; when the state machine of the first-priority port enters the completion state, determine the actual link width of the first-priority port; if the actual link width is less than the maximum link width, determine the number of physical channels that have established links and the physical channels that have not established links for the first-priority port; allocate the physical channels that have not established links to the next-priority port until all physical channels are allocated or all ports have completed link establishment.

[0060] Specifically, the multi-port branch management module can reasonably allocate resources according to the priorities of each port. When a high-priority port requires more link resources, the module will give priority to meeting its needs, and at the same time, based on the maximum link width of the port, limit the upper limit of channel allocation to ensure that there will be no over-allocation and no less than the minimum link width of the port, thus ensuring the basic communication ability and making the resource utilization rate of the PCIe device higher.

[0061] In an alternative embodiment, the multi-port branch management module is further used for:

[0062] If the actual link width of the first-priority port is equal to the maximum link width of the first-priority port, complete the link establishment of the first-priority port.

[0063] If the actual link width is greater than or equal to the minimum link width, the number of physical channels of the first-priority port is equal to the actual link width.

[0064] If the actual link width is less than the minimum link width, the number of physical channels of the first-priority port is equal to the minimum link width.

[0065] In an alternative embodiment, the PCIe device further includes a priority configuration register module, a maximum link width configuration register module, and a minimum link width configuration register module;

[0066] The priority configuration register module is used to configure the priorities of each port;

[0067] The maximum link width configuration register module is used to configure the maximum link width of each port;

[0068] The minimum link width configuration register module is used to configure the minimum link width of each port.

[0069] Optionally, the PCIe device includes a PCIe controller, and the controller includes a priority configuration register module, a maximum link width configuration register module, a minimum link width configuration register module, and a multi-port branch management module.

[0070] In this optional embodiment, the priority of each port is flexibly set through the priority configuration register module, and the maximum link width configuration register module and the minimum link width configuration register module flexibly set the maximum and minimum link widths of each port, improving the link management efficiency.

[0071] Figure 3 It is a schematic diagram of a PCIe controller according to an optional embodiment of the present application. As Figure 3 shown, the following hardware module components are added inside the PCIe controller:

[0072] The priority configuration register module, such as the configuration register prio_port, is used to independently configure the priority of link establishment for each PCIe controller. 0 represents the highest priority, and multiple Ports can be configured with the same value;

[0073] The maximum link width configuration register module, such as the configuration register max_link_width_port, is used to independently configure the maximum link width of each PCIe controller, that is, the initial maximum link width allocated to each Port;

[0074] The minimum link width configuration register module, such as the configuration register min_link_width_port, is used to independently configure the minimum link width of each PCIe controller, that is, to force the reservation of the Lane number regardless of the actual link establishment width of this Port;

[0075] The multi-port bifurcation management module, such as the Multi-Port Bifurcation Management module (hereinafter simply referred to as MP_BIF_MGT), is used to manage the link establishment of all PCIe controllers. Optionally, the MP_BIF_MGT module further includes a Bifurcation module, which can implement Bifurcation control.

[0076] Figure 4 It is a flowchart of the PCIe device dynamic link segmentation method according to an optional embodiment of the present application. As shown in the figure, the following is the implementation process of this process:

[0077] Step 1, the prio_port register configures the priority of each port as 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7, where Port0 is the first priority port;

[0078] Step 2, the max_link_width_port register is configured as the maximum link width supported by each Port, that is, 16 / 8 / 4 / 4 / 2 / 2 / 2 / 2, so the maximum link width of the first priority port is x16;

[0079] Step 3: Allocate all the min_link_width_port registers to 0, indicating that there is no need to forcibly reserve physical channels for each Port.

[0080] Step 4: MP_BIF_MGT allocates the physical channels corresponding to the number of max_link_width_port (16 in this example) to the Port with prio_port = 0 (Port0 in this example) in the configured prio_port order. MP_BIF_MGT controls the Bifurcation module to allocate all 16 physical channels to Port0. Figure 5 It is a schematic diagram of the physical channel allocation for the first-priority port according to an alternative embodiment of the present application. As Figure 5 shown, Lane0 to Lane15 are all allocated to Port0;

[0081] Step 5: MP_BIF_MGT enables the LTSSM state machine of Port0 and starts link establishment.

[0082] Step 6: When the LTSSM of Port0 enters the Configuration.Complete state, it indicates that the negotiation of the link width has been completed. At this time, Port0 feeds back the actual link establishment width to the MP_BIF_MGT module, that is, the actual link establishment width is x8.

[0083] Step 7: After receiving the link establishment width fed back by Port0, MP_BIF_MGT controls the Bifurcation module to reserve the number of physical channels for Port0 = Max(min_link_width_port, actual link establishment width), and recycle the resources of other physical channels. Figure 6 It is a schematic diagram of the link establishment for the first-priority port according to an alternative embodiment of the present application. As Figure 6 shown, the link establishment of Port0 is x8, and min_link_width_port = 0, so 8 unlinked physical channels, that is, Lane8 to Lane15, are recycled for the link establishment of the next-priority Port.

[0084] Step 8: MP_BIF_MGT module allocates the physical channels corresponding to the number of max_link_width_port (8 in this example) to the Port with prio_port = 1 (Port1 in this example). MP_BIF_MGT controls the Bifurcation module to allocate the remaining 8 physical channels to Port1. Figure 7 It is a schematic diagram of the link establishment for the second-priority port according to an alternative embodiment of the present application. As Figure 7 shown, Lane8 to Lane15 are allocated to the second-priority port;

[0085] Step 9: MP_BIF_MGT enables the LTSSM state machine of Port1 to start link establishment.

[0086] Step 10: Repeat Steps 1 to 6 until all physical channels are used up or all Ports have completed link establishment, and the entire process ends.

[0087] The method provided in this optional embodiment solves the problem of physical channel management and allocation of multi-port PCIe devices. The hardware automatically processes the link establishment process of the entire multi-port PCIe controller. According to the link establishment results, the unused physical channels are automatically allocated to other PCIe controllers; it provides flexible software configuration, where the link establishment order of each PCIe controller can be configured, and the maximum and minimum number of physical channels can be allocated to ensure sufficient physical channel resources are reserved for the device; without affecting the devices that have already been connected, the unused physical channels can be dynamically allocated, avoiding the need for software to reconfigure bifurcation information when a new PCIe device is connected, which may affect the PCIe controllers that have already established links and require them to re-establish links.

[0088] An embodiment of this application also provides a computer device, which can be implemented as the above-mentioned PCIe device.

[0089] Please refer to Figure 8 , Figure 8 which is a schematic structural diagram of a computer device provided in an optional embodiment of this application. As shown in Figure 8 , the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Each component communicates with each other using different buses and can be installed on a common motherboard or in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional implementation manners, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (such as a server array, a set of blade servers, or a multi-processor system). Figure 8 Taking one processor 10 as an example in

[0090] The processor 10 may be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 may further include a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The above-mentioned programmable logic device may be a complex programmable logic device, a field programmable gate array, a generic array logic, or any combination thereof.

[0091] Among them, the memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiments.

[0092] The memory 20 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 may optionally include a memory remotely provided with respect to the processor 10, and these remote memories may be connected to the computer device through a network. Examples of the above-mentioned network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0093] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state drive; the memory 20 may also include a combination of the above types of memories.

[0094] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30, and the output device 40 may be connected through a bus or other means. Figure 8 Taking connection through a bus as an example.

[0095] The input device 30 can receive input digital or character information, and generate key signal inputs related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (such as an LED), and a tactile feedback device (such as a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light-emitting diode, a display, and a plasma display. In some alternative embodiments, the display device may be a touch screen.

[0096] Embodiments of the present application also provide a computer-readable storage medium. The method according to the embodiments of the present application can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code that is originally stored in a remote storage medium or a non-transitory machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0097] A part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer. Those skilled in the art should be able to understand that the forms of existence of computer program instructions in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Herein, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible by the computer.

[0098] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A PCIe device dynamic link segmentation method, characterized in that: Each port on the PCIe device is configured with a corresponding priority, a maximum link width, and a minimum link width, and the method comprises: Allocate a physical channel corresponding to the maximum link width to the first priority port; When the state machine of the first priority port enters a completion state, determining an actual link width of the first priority port; If the actual link width of the first priority port is less than the maximum link width of the first priority port, determining the number of physical channels for link establishment and unlinked physical channels of the first priority port according to the actual link width of the first priority port and the minimum link width of the first priority port; The unlinked physical channels are allocated to the next priority ports until all physical channels are allocated or all ports are linked.

2. The method according to claim 1, characterized in that The method further comprises: If the actual link width of the first priority port is equal to the maximum link width of the first priority port, link building of the first priority port is completed.

3. The method according to claim 1 or 2, characterized in that: If the actual link width is greater than or equal to the minimum link width, the number of physical channels of the first priority port is equal to the actual link width.

4. The method according to claim 1 or 2, characterized in that: If the actual link width is smaller than the minimum link width, the number of physical channels of the first priority port is equal to the minimum link width.

5. A PCIe device, characterized in that: Each port on the PCIe device is configured with a corresponding priority, a maximum link width, and a minimum link width; The PCIe device includes a multi-port branch management module; The multi-port branch management module is used to allocate a physical channel corresponding to the maximum link width to the first priority port; When the state machine of the first priority port enters a completion state, determining an actual link width of the first priority port; If the actual link width is less than the maximum link width, determine the number of physical channels for link building and physical channels that are not linked by the first priority port; The unlinked physical channels are allocated to the next priority ports until all physical channels are allocated or all ports are linked.

6. The PCIe device according to claim 5, characterized in that: The multi-port branch management module is also used for: If the actual link width of the first priority port is equal to the maximum link width of the first priority port, link building of the first priority port is completed.

7. The PCIe device according to claim 5, characterized in that: The multi-port branch management module is also used for: If the actual link width is greater than or equal to the minimum link width, the number of physical channels of the first priority port is equal to the actual link width.

8. The PCIe device according to claim 5, characterized in that: The multi-port branch management module is also used for: If the actual link width is smaller than the minimum link width, the number of physical channels of the first priority port is equal to the minimum link width.

9. The PCIe device according to claim 5, characterized in that: The PCIe device also includes a priority configuration register module, a maximum link width configuration register module and a minimum link width configuration register module; The priority configuration register module is used to configure the priority of each port; The maximum link width configuration register module is used to configure the maximum link width of each port; The minimum link width configuration register module is used to configure the minimum link width of each port.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the PCIe device dynamic link segmentation method according to any one of claims 1 to 4.

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