YUV data processing device, storage medium and electronic equipment

Abstract

The embodiment of the invention discloses a YUV data processing device, a storage medium and electronic equipment, and relates to the field of image processing. The YUV data processing device comprising the memory, the Y / U / V buffer, the preprocessing module, the asynchronous FIFO, the YUV buffer and the format processing module is constructed, efficient storage, reading, integration, buffering and format conversion of Y, U and V original data are achieved, and finally the processed YUV data are output through a parallel video interface in the form of sequential control flow of a preset protocol. The speed and the flexibility of YUV data processing are improved, and the requirements of high-definition video transmission and display are met.

Description

Technical Field

[0001] This application relates to the field of image processing, and particularly to a YUV data processing device, a storage medium, and an electronic device. Background Art

[0002] In the existing field of image processing, the processing of YUV data is a crucial link. As the core information of image color and brightness, the processing efficiency and accuracy of YUV data are directly related to the quality and performance of image display. However, when facing application scenarios with high data volume and high real-time requirements, the current YUV data processing devices on the market often expose some obvious defects.

[0003] Traditional YUV data processing devices usually adopt a single memory structure to store the three original data of Y, U, and V. This design may be acceptable when processing small-scale data, but when the data volume increases sharply, the problems of memory access conflicts and data transmission bottlenecks become increasingly prominent. Since the Y, U, and V data need to access the memory frequently during storage and reading, this single storage structure is very likely to cause data access delays and conflicts, thereby affecting the efficiency and stability of the entire processing process. Summary of the Invention

[0004] The embodiments of this application provide a method, a device, a storage medium, and a terminal device for predicting bond defaults, which can solve the problem of low processing efficiency caused by data transmission bottlenecks in YUV data in the prior art. The technical solutions are as follows:

[0005] In a first aspect, the embodiments of this application provide a YUV data processing device, including:

[0006] A memory, a Y buffer, a U buffer, a V buffer, a preprocessing module, an asynchronous FIFO, a YUV buffer, and a format processing module;

[0007] The memory is respectively connected to the input ends of the Y buffer, the U buffer, and the V buffer. The output ends of the Y buffer, the U buffer, and the V buffer are respectively connected to the input end of the preprocessing module. The output end of the preprocessing module is connected to the input end of the asynchronous FIFO. The output end of the asynchronous FIFO is connected to the output end of the YUV buffer. The output end of the YUV buffer is connected to the output end of the format processing module. The depths of the Y buffer, the U buffer, and the V buffer are 64 bits;

[0008] The memory is used to store Y original data, U original data, and V original data, and the three different types of data are stored separately in different areas;

[0009] The Y buffer is used to read 32-bit raw Y data from the memory, write it into a queue, then read 16-bit Y data from the queue, and then send the read 16-bit Y data to the preprocessing module;

[0010] The U buffer is used to read 32-bit U data from the memory, write it into a queue, and then read 8-bit U data from the queue and send it to the preprocessing module;

[0011] The V buffer is used to read 32-bit raw V data from the memory, write it into a queue, and then read 8-bit V data from the queue and send it to the preprocessing module;

[0012] The preprocessing module is used to arrange the received 16-bit Y data, 8-bit U data, and 8-bit V data in a preset order to generate 32-bit YUV data, and send the generated 32-bit YUV data to the asynchronous FIFO;

[0013] The asynchronous FIFO is used to write the 32-bit YUV data from the preprocessing module into a queue, and then read a 32-bit YUV data from the queue and send it to the YUV buffer; the data bit width of the asynchronous FIFO is 32 and the depth is 2;

[0014] The YUV buffer is used to write the YUV data from the asynchronous FIFO into a queue, and read an 8-bit data from the queue and send it to the format processing module;

[0015] The format processing module is used to convert the 8-bit data from the YUV buffer into a timing control stream of a preset protocol and output it through a parallel video interface.

[0016] In a second aspect, an embodiment of the present application provides a computer storage medium, which stores multiple instructions, and the instructions are suitable for being loaded and executed by a processor to perform the above method steps.

[0017] In a third aspect, an embodiment of the present application provides an electronic device, which may include a processing device for YUV data.

[0018] The beneficial effects brought by the technical solutions provided by some embodiments of the present application at least include:

[0019] By constructing a YUV data processing device including a memory, Y / U / V buffers, a preprocessing module, an asynchronous FIFO, a YUV buffer, and a format processing module, the efficient storage, reading, integration, buffering, and format conversion of the original Y, U, and V data are achieved. Finally, the processed YUV data is output through a parallel video interface with the timing control flow of a preset protocol, improving the speed and flexibility of YUV data processing and meeting the requirements of high-definition video transmission and display. Brief Description of the Drawings

[0020] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 It is a schematic structural diagram of the YUV data processing device provided by the embodiment of the present application;

[0022] Figure 2 It is a schematic structural diagram of the Y buffer provided by the embodiment of the present application;

[0023] Figure 3 It is a schematic structural diagram of the U buffer provided by the embodiment of the present application;

[0024] Figure 4 It is a schematic structural diagram of a YUV buffer provided by the present application. Detailed Description of the Embodiments

[0025] To make the objectives, technical solutions, and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail in conjunction with the drawings.

[0026] Figure 1 It represents a schematic structural diagram of the YUV processing device provided by the embodiment of the present application. In Figure 1 it, the YUV processing device includes: a memory, a Y buffer, a U buffer, a V buffer, a preprocessing module, an asynchronous FIFO, a YUV buffer, and a format processing module.

[0027] The connection relationships of the above components are as follows: The memory is respectively connected to the input ends of the Y buffer, U buffer, and V buffer. The output ends of the Y buffer, U buffer, and V buffer are respectively connected to the input end of the preprocessing module. The output end of the preprocessing module is connected to the input end of the asynchronous FIFO. The output end of the asynchronous FIFO is connected to the output end of the YUV buffer. The output end of the YUV buffer is connected to the output end of the format processing module; the depths of the Y buffer, U buffer, and V buffer are 64 bits.

[0028] Among them, the memory is used to store Y raw data, U raw data, and V raw data.

[0029] Among them, the memory is used to store Y raw data, U raw data, and V raw data, which are the basis of the color and brightness information of the image. The three different types of data (Y, U, V) are stored separately in different areas of the memory to ensure data independence and integrity. Although the output data bit widths of the Y, U, and V buffers are different (Y is 16 bits, and U and V are each 8 bits), the raw data stored in the memory are all 32 bits. This may be because the memory needs to store and read data with a relatively high data bit width to improve data transmission efficiency.

[0030] The Y buffer is used to read 32-bit Y raw data from the memory, write it into a queue, then read 16-bit Y data from the queue, and then send the read 16-bit Y data to the preprocessing module.

[0031] The U buffer is used to read 32-bit U data from the memory, write it into a queue, and then read 8-bit U data from the queue and send it to the preprocessing module.

[0032] The V buffer is used to read 32-bit V raw data from the memory, write it into a queue, and then read 8-bit V data from the queue and send it to the preprocessing module.

[0033] Among them, the Y buffer, U buffer, and V buffer are used to read raw data from the memory and write it into their respective queues. Then, they read data with a smaller bit width from the queues (Y is 16 bits, and U and V are each 8 bits) and send it to the preprocessing module. The buffer realizes the conversion of 32-bit data in the memory to the data bit width required by the preprocessing module. This conversion is necessary because the preprocessing module may not be able to directly process 32-bit data, or to save bandwidth and storage space, it is necessary to reduce the data bit width. The buffer uses a queue internally to manage data, which helps to ensure the order and integrity of the data. The write and read operations of the queue are synchronized to ensure the correct transmission of data.

[0034] The preprocessing module is used to generate 32-bit YUV data after arranging the received 16-bit Y data, 8-bit U data, and 8-bit V data in a preset order, and send the generated 32-bit YUV data to the asynchronous FIFO.

[0035] Among them, the preprocessing module receives 16-bit Y data, 8-bit U data, and 8-bit V data from the Y buffer, U buffer, and V buffer, and arranges these data in a preset order to generate 32-bit YUV data. The preprocessing module combines the Y, U, and V data into a 32-bit YUV data, which usually involves data splicing and format conversion. The generated 32-bit YUV data is sent to the asynchronous FIFO for subsequent processing.

[0036] The asynchronous FIFO is used to write the 32-bit YUV data from the preprocessing module into a queue, and then read a 32-bit YUV data from the queue and send it to the YUV buffer.

[0037] Among them, the asynchronous FIFO is used to provide data buffering and synchronization between the preprocessing module and the YUV buffer. It receives the 32-bit YUV data from the preprocessing module and writes it into the queue. Then, it reads a 32-bit YUV data from the queue and sends it to the YUV buffer. The asynchronous FIFO allows the preprocessing module and the YUV buffer to work in different clock domains, thus realizing asynchronous data transmission. This helps to ensure the correctness and stability of the data. The depth of the asynchronous FIFO is 2, which means it can store two 32-bit YUV data at the same time. This helps to provide sufficient data buffering between the preprocessing module and the YUV buffer to cope with data transmission delays and fluctuations.

[0038] Optionally, the Y buffer output signal YDATA1: represents the output signal DATA_REG[7:0] of the Y buffer. YDATA2: represents the output signal DATA_REG[15:8] of the Y buffer. The U buffer output signal UDATA: represents the output signal DATA_REG[7:0] of the U buffer. The V buffer output signal VDATA: represents the output signal DATA_REG[7:0] of the V buffer.

[0039] The preprocessing module combines YDATA1, YDATA2, UDATA, and VDATA into a 32-bit output signal DATA_YUV according to a preset arrangement rule. There can be various specific arrangement methods, including but not limited to the following:

[0040] Arrangement method 1: {YDATA1, UDATA, YDATA2, VDATA}

[0041] Place YDATA1 in the lower 8 bits of DATA_YUV.

[0042] Place UDATA in the next 8 bits of DATA_YUV.

[0043] Place YDATA2 in the next 8 bits of DATA_YUV after that.

[0044] Place VDATA in the highest 8 bits of DATA_YUV.

[0045] Arrangement 2: {YDATA1, VDATA, YDATA2, UDATA}

[0046] Similar to Arrangement 1, but swap the positions of UDATA and VDATA.

[0047] Arrangement 3: {UDATA, YDATA1, VDATA, YDATA2}

[0048] Place UDATA in the lower 8 bits of DATA_YUV.

[0049] Place YDATA1 in the next 8 bits of DATA_YUV.

[0050] Place VDATA in the next 8 bits of DATA_YUV after that.

[0051] Place YDATA2 in the highest 8 bits of DATA_YUV.

[0052] Arrangement 4: {VDATA, YDATA1, UDATA, YDATA2}

[0053] Similar to Arrangement 3, but swap the positions of UDATA and VDATA.

[0054] After the above arrangements and combinations, the preprocessing module outputs a 32-bit DATA_YUV signal. This signal can be used in subsequent image processing, encoding, or transmission processes.

[0055] The YUV buffer is used to write YUV data from the asynchronous FIFO into a queue and read an 8-bit data from the queue to send to the format processing module.

[0056] Among them, the YUV buffer receives 32-bit YUV data from the asynchronous FIFO and writes it into the queue. Then, it reads an 8-bit data (which may be a part of the Y, U, or V component) from the queue and sends it to the format processing module. Since the format processing module may need to process 8-bit data, the YUV buffer needs to split the 32-bit YUV data into 8-bit data for transmission. This splitting operation may involve data shifting and truncation. The split 8-bit data is sent to the format processing module for subsequent processing.

[0057] The format processing module is used to convert the 8-bit data from the YUV buffer into a timing control stream of a preset protocol and output it through the parallel video interface.

[0058] Among them, the format processing module can convert the 8-bit data in the YUV buffer into the corresponding timing control stream according to the preset protocol formats (such as BT656, BT1120, DVP, BT601, etc.). These protocol formats usually specify the data transmission method, timing relationship, synchronization signal, etc. The converted timing control stream is output through the parallel video interface to achieve parallel data transmission. This transmission method can efficiently utilize the bandwidth and improve the data transmission speed.

[0059] The specific working process of the format processing module includes: The format processing module receives 8-bit data from the YUV buffer. These data may be a part of the Y, U, or V component, depending on the output order of the YUV buffer. According to the preset protocol format, the format processing module selects the corresponding conversion rules and data format. Apply the selected conversion rules to convert the received 8-bit data into a timing control stream that conforms to the protocol format. This may involve operations such as data rearrangement, bit extension, and insertion of synchronization signals. The converted timing control stream is output through the parallel video interface for external devices to receive and process.

[0060] The technical effects of the embodiments of this application are as follows:

[0061] By storing the three original data of Y, U, and V in different areas of the memory respectively, the classification management of data is realized, which is convenient for subsequent data reading and processing. The Y buffer, U buffer, and V buffer are responsible for reading and processing the corresponding original data respectively, and splitting the large data block into smaller data packets (16-bit Y data, 8-bit U data, and 8-bit V data), which improves the flexibility and efficiency of data processing.

[0062] The preprocessing module receives data from the buffer and arranges it in a preset order to generate 32-bit YUV data. This step simplifies the subsequent data processing flow and ensures the uniformity of the data format. The asynchronous FIFO, as a bridge for data buffering and synchronization, effectively solves the speed mismatch problem between data producers and consumers, improving the reliability and stability of data transmission.

[0063] The YUV buffer can store the YUV data from the asynchronous FIFO and flexibly read the data according to the requirements of the format processing module. Its design allows reading data of any length (8 bits in this example) from the queue, providing the possibility for flexible data processing and output.

[0064] The format processing module converts the 8-bit data output by the YUV buffer into a timing control flow of a preset protocol. This step ensures the compatibility between the data format and the output interface. The processed data is output through a parallel video interface, greatly improving the data transmission speed and efficiency, and meeting the requirements for data transmission rate and real-time performance in application scenarios such as high-definition video.

[0065] Through reasonable module division and collaborative work, this technical solution realizes the overall optimization of the entire process from data reading, preprocessing, buffering to format conversion and output. The data flows smoothly between modules, effectively improving the processing capacity and response speed of the entire system.

[0066] In summary, through reasonable module design and collaborative work, this technical solution realizes the efficient management and transmission of the original Y, U, and V data, as well as flexible data preprocessing and format conversion. These technical effects together enhance the processing capacity and response speed of the entire system, providing strong technical support for application scenarios such as high-definition video.

[0067] In some embodiments of the present application, referring to Figure 2 the structural schematic diagram of the Y buffer shown, the Y buffer includes: a data integration unit, a logic control unit, a first multiplexer, a second multiplexer, a shift unit, and a data output unit.

[0068] A data integration unit is configured to read 32-bit current Y raw data from the memory, and integrate the current Y raw data with the 64-bit previous register data from the data output unit to generate current 6-channel data: First Data Data1, Second Data Data2, Third Data Data3, Fourth Data Data4, Fifth Data Data5, and Sixth Data Data6. The First Data is formed by sequentially concatenating 32 0 bits and the current Y raw data in the order from high bit to low bit. The Second Data is formed by sequentially concatenating 24 0 bits, the current Y raw data, and the lower 8 bits of the previous register data in the order from high bit to low bit. The Third Data is formed by sequentially concatenating 16 0 bits, the current Y raw data, and the lower 16 bits of the previous register data in the order from high bit to low bit. The Fourth Data is formed by sequentially concatenating 8 0 bits, the current Y raw data, and the lower 24 bits of the previous register data in the order from high bit to low bit. The Fifth Data is formed by sequentially concatenating the current Y raw data and the lower 32 bits of the previous register data in the order from high bit to low bit. The Sixth Data is the 64-bit previous register data.

[0069] A logic control unit is configured to send a counter signal to the first multiplexer according to the number of bytes BUFF_CNT of the data stored in the Y buffer, and send a buffer status signal to the first multiplexer according to the idle state of the Y buffer.

[0070] The first multiplexer is configured to determine that there is free space in the Y buffer according to the buffer status signal from the logic control unit, and then continue to judge the size of BUFF_CNT.

[0071] When BUFF_CNT = 0, the first multiplexer outputs the First Data Data1.

[0072] When BUFF_CNT = 1, the first multiplexer outputs the Second Data; the output signal DATA_BUF1 of MUX1 = Data2.

[0073] When BUFF_CNT = 2, the first multiplexer outputs the Third Data; the output signal DATA_BUF1 of MUX1 = Data3.

[0074] When BUFF_CNT = 3, the first multiplexer outputs the Fourth Data; the output signal DATA_BUF1 of MUX1 = Data4.

[0075] When BUFF_CNT = 4, the first multiplexer outputs the Fifth Data; the output signal DATA_BUF1 of MUX1 = Data5.

[0076] When BUFF_CNT > 4, the first multiplexer outputs the sixth data; MUX1 outputs the signal DATA_BUF1 = Data6;

[0077] If the buffer status signal indicates that there is no free space in the Y buffer, the first multiplexer outputs the sixth data; MUX1 outputs the signal DATA_BUF1 = Data6;

[0078] A shift unit, configured to perform a shift process on the data output by the first multiplexer to obtain shifted buffer data SHIFT_BUF. The shifted buffer data SHIFT_BUF is formed by sequentially concatenating 16 bits of 0 and the bits from the 63rd to 16th positions of the data output by the first multiplexer in the order from high to low;

[0079] The logic control unit is further configured to generate a data demand signal and a buffer status signal, and send the data demand signal and the buffer status signal to the second multiplexer; and generate a data valid signal when the number of bytes of occupied data in the Y buffer BUFF_CNT ≥ 2;

[0080] A second multiplexer, configured to select the data output by the first multiplexer as the output data DATA_BUF2 when it is determined according to the data demand signal from the logic control unit that there is a data stack - out demand and the number of bytes of stored data in the Y buffer BUFF_CNT ≥ 2, otherwise, select the data output by the shift unit as the output data DATA_BUF2;

[0081] The data output unit is configured to write the data DATA_BUF2 output by the second multiplexer into a register, and read the lower 16 - bit data from the register and output it to the pre - processing module. The bit - width of this register is 64 bits.

[0082] Among them, the data integration unit is used to integrate the current Y original data and the previous register data to generate 6 - way data.

[0083] The execution process of the data integration unit includes: reading 32 - bit current Y original data from the memory. Reading the previous register data stored in the 64 - bit register of the data output unit in the previous cycle. Generating 6 - way data (Data1 to Data6) according to the integration rule:

[0084] Component of the first data (Data1): 32 bits of 0 + current Y original data (32 bits).

[0085] Concatenation order: First, create a 32-bit zero value (i.e., 32 zero bits). Then, append the current Y raw data (32 bits) immediately after this zero value. The result is a 64-bit value where the high 32 bits are 0 and the low 32 bits are the current Y raw data.

[0086] Composition of the second data (Data2): 24 zero bits + current Y raw data (32 bits) + low 8 bits (8 bits) of the previous register data.

[0087] Concatenation order: First, create a 24-bit zero value (i.e., 24 zero bits). Then, append the current Y raw data (32 bits) immediately after this zero value. Next, extract the low 8 bits from the previous register data. Append these 8 bits immediately after the current Y raw data. The result is a 64-bit value where the high 24 bits are 0, the next 32 bits are the current Y raw data, and the low 8 bits are the low 8 bits of the previous register data.

[0088] Composition of the third data (Data3): 16 zero bits + current Y raw data (32 bits) + low 16 bits (16 bits) of the previous register data.

[0089] Concatenation order: First, create a 16-bit zero value (i.e., 16 zero bits). Then, append the current Y raw data (32 bits) immediately after this zero value. Next, extract the low 16 bits from the previous register data. Append these 16 bits immediately after the current Y raw data. The result is a 64-bit value where the high 16 bits are 0, the next 32 bits are the current Y raw data, and the low 16 bits are the low 16 bits of the previous register data.

[0090] Composition of the fourth data (Data4): 8 zero bits + current Y raw data (32 bits) + low 24 bits (24 bits) of the previous register data.

[0091] Concatenation order: First, create an 8-bit zero value (i.e., 8 zero bits). Then, append the current Y raw data (32 bits) immediately after this zero value.

[0092] Next, extract the low 24 bits from the previous register data. Append these 24 bits immediately after the current Y raw data. The result is a 64-bit value where the high 8 bits are 0, the next 32 bits are the current Y raw data, and the low 24 bits are the low 24 bits of the previous register data.

[0093] Composition of the fifth data (Data5): current Y raw data (32 bits) + low 32 bits (32 bits) of the previous register data.

[0094] Concatenation order: Directly use the current Y raw data (32 bits) as the upper 32 bits of a 64-bit value. Then, extract the lower 32 bits from the previous register data and use them as the lower 32 bits of the 64-bit value. The result is a 64-bit value where the upper 32 bits are the current Y raw data and the lower 32 bits are the lower 32 bits of the previous register data.

[0095] Composition of the sixth data (Data6): The previous register data (64 bits).

[0096] Concatenation order: Directly use the 64-bit value of the previous register data without any concatenation.

[0097] The logic control unit is used to control the data flow of the Y buffer and generate control signals.

[0098] Its execution process includes: Monitoring the number of bytes of data stored in the Y buffer (BUFF_CNT). Sending a counter signal to the first multiplexer according to BUFF_CNT. Checking the idle state of the Y buffer and sending a buffer status signal to the first multiplexer. Generating a data demand signal and a buffer status signal and sending them to the second multiplexer. When BUFF_CNT ≥ 2, generating a data valid signal.

[0099] The first multiplexer (MUX1) is used to select the output data according to the signals from the logic control unit.

[0100] Execution process: Receiving the buffer status signal and the counter signal. Judging whether there is free space in the Y buffer. If there is free space, selecting one of the data from Data1 to Data5 for output according to the value of BUFF_CNT, or outputting Data6 when BUFF_CNT > 4. If there is no free space, directly outputting Data6. Sending the selected data as DATA_BUF1 to the shift unit and the data output unit (or subsequent logic, depending on the specific implementation).

[0101] The shift unit is used to perform a shift process on the data output by MUX1.

[0102] Its execution process includes: Receiving DATA_BUF1 output by MUX1. Concatenating bits 63 to 16 of DATA_BUF1 with 16 0 bits to generate the shifted buffer data SHIFT_BUF. Outputting SHIFT_BUF to the second multiplexer (or subsequent logic, depending on the specific implementation).

[0103] The second multiplexer (MUX2) is used to select the output data to the data output unit according to the signals from the logic control unit.

[0104] Its execution process includes: receiving a data requirement signal, a buffer status signal, and possibly other control signals. Determine whether there is a data pop requirement and BUFF_CNT ≥ 2. If the condition is satisfied, select DATA_BUF1 output by MUX1 as the output data DATA_BUF2. If the condition is not satisfied, select SHIFT_BUF output by the shift unit as the output data DATA_BUF2. Output the selected data as DATA_BUF2 to the data output unit.

[0105] The data output unit is used to write the selected data into a register and output the lower 16-bit data to the preprocessing module.

[0106] Its execution process includes: receiving DATA_BUF2 output by the second multiplexer. Write DATA_BUF2 into a 64-bit register. Read the lower 16-bit data from the register. Output the lower 16-bit data to the preprocessing module.

[0107] The Y buffer of this application has the following advantages:

[0108] Through the data integration unit, the Y buffer can efficiently read the 32-bit current Y raw data in the memory and integrate it with the 64-bit previous register data from the data output unit to generate 6 different current data (Data1 to Data6). This data integration method not only makes full use of the existing data, but also expands the bit width of the data by adding different numbers of 0 bits, providing flexibility for subsequent data processing.

[0109] The logic control unit sends control signals to the first multiplexer according to the number of bytes of the data stored in the Y buffer (BUFF_CNT) and the idle state of the buffer. According to these signals, the first multiplexer can flexibly select and output different data paths (Data1 to Data6). When there is free space in the buffer, it will select the corresponding data output according to the value of BUFF_CNT; when there is no free space in the buffer, it will default to output the previous register data (Data6) to avoid data overflow.

[0110] The shift unit can perform a shift process on the data output by the first multiplexer to generate shift buffer data (SHIFT_BUF). This shift process not only retains the main part of the data, but also adjusts the data format by adding 16 0 bits to make it more in line with the requirements of the subsequent processing module.

[0111] The second multiplexer can intelligently select the output data according to the data demand signal and buffer status signal of the logic control unit. When there is a data pop-up demand and BUFF_CNT ≥ 2, it will select the data output by the first multiplexer as the output data (DATA_BUF2); otherwise, it will select the data output by the shift unit. This strategy not only ensures the real-time nature of the data but also avoids processing delays caused by insufficient data.

[0112] The data output unit writes the data output by the second multiplexer into a 64-bit register and reads the lower 16-bit data from the register for output to the preprocessing module. This design not only optimizes the data output process but also ensures the interface compatibility between the Y buffer and the preprocessing module, enabling the data to flow smoothly and be effectively processed.

[0113] Through the combined effect of the above technical effects, the Y buffer can significantly improve the performance of the entire system. It can efficiently manage the Y raw data, ensuring the real-time nature and accuracy of the data; at the same time, it can also flexibly adapt to different data processing requirements, providing strong support for subsequent steps such as preprocessing, encoding, and transmission.

[0114] In summary, through its unique data integration, selection, shifting, and output mechanisms, the Y buffer realizes the efficient management and flexible processing of Y raw data, providing stable and reliable data support for the entire video processing system.

[0115] In some embodiments of the present application, referring to Figure 3 the structural schematic diagram of the U buffer shown, the U buffer includes: a data integration unit, a logic control unit, a first multiplexer, a second multiplexer, a shift unit, and a data output unit.

[0116] A data integration unit, configured to read 32-bit current raw U data from the memory, and integrate the current raw U data with 64-bit previous register data from the data output unit to generate current 6-channel data: First data Data1, Second data Data2, Third data Data3, Fourth data Data4, Fifth data Data5, and Sixth data Data6; The first data is formed by sequentially concatenating 32 0 bits and the current raw U data in the order from high bit to low bit; The second data is formed by sequentially concatenating 24 0 bits, the current raw U data, and the lower 8 bits of the previous register data in the order from high bit to low bit; The third data is formed by sequentially concatenating 16 0 bits, the current raw U data, and the lower 16 bits of the previous register data in the order from high bit to low bit; The fourth data is formed by sequentially concatenating 8 0 bits, the current raw U data, and the lower 24 bits of the previous register data in the order from high bit to low bit; The fifth data is formed by sequentially concatenating the current raw U data and the lower 32 bits of the previous register data in the order from high bit to low bit; The sixth data is 64-bit previous register data;

[0117] A logic control unit, configured to send a counter signal to the first multiplexer according to the number of bytes BUFF_CNT of the data stored in the U buffer, and send a buffer status signal to the first multiplexer according to the idle status of the U buffer;

[0118] The first multiplexer is configured to determine that there is free space in the U buffer according to the buffer status signal from the logic control unit, and continue to judge the size of BUFF_CNT;

[0119] When BUFF_CNT = 0, the first multiplexer outputs the first data Data1;

[0120] When BUFF_CNT = 1, the first multiplexer outputs the second data; The output signal DATA_BUF1 of MUX1 = Data2;

[0121] When BUFF_CNT = 2, the first multiplexer outputs the third data; The output signal DATA_BUF1 of MUX1 = Data3;

[0122] When BUFF_CNT = 3, the first multiplexer outputs the fourth data; The output signal DATA_BUF1 of MUX1 = Data4;

[0123] When BUFF_CNT = 4, the first multiplexer outputs the fifth data; The output signal DATA_BUF1 of MUX1 = Data5;

[0124] When BUFF_CNT > 4, the first multiplexer outputs the sixth data; MUX1 outputs the signal DATA_BUF1 = Data6;

[0125] If the buffer status signal indicates invalid, the first multiplexer outputs the sixth data; MUX1 outputs the signal DATA_BUF1 = Data6;

[0126] A shift unit, configured to perform a shift process on the data output by the first multiplexer to obtain shifted buffer data SHIFT_BUF. The shifted buffer data SHIFT_BUF is formed by sequentially concatenating 16 bits of 0 and the bits from the 63rd to 16th positions of the data output by the first multiplexer in the order from high to low;

[0127] The logic control unit is further configured to generate a data demand signal and a buffer status signal, and send the data demand signal and the data occupancy signal to the second multiplexer; and generate a data valid signal when the number of bytes of occupied data in the U buffer, BUFF_CNT ≥ 2;

[0128] A second multiplexer, configured to select the data output by the first multiplexer as the output data DATA_BUF2 when it is determined from the data demand signal from the logic control unit that there is a data stack - out demand and it is determined from the occupancy signal that the number of bytes of stored data in the U buffer, BUFF_CNT ≥ 2; otherwise, select the data output by the shift unit as the output data DATA_BUF2;

[0129] The data output unit is configured to write the data DATA_BUF2 output by the second multiplexer into a register, and read the lower 8 - bit data from the register and output it to the pre - processing module. The bit - width of this register is 64 bits.

[0130] Among them, the data integration unit reads 32 - bit current U raw data from the memory. At the same time, it obtains 64 - bit previous register data from the data output unit as the integration reference. Using the read 32 - bit current U raw data and the 64 - bit previous register data, the data integration unit generates 6 channels of current data (Data1 to Data6):

[0131] Data1: It is formed by concatenating 32 high - order bits of 0 and 32 - bit current U raw data, forming a 96 - bit (but actually output as 64 - bit, maybe only taking the high 64 - bit or performing other processing) data. But according to the description, here it is simplified to 64 - bit output, that is, the first 32 bits are 0 and the last 32 bits are the current U data.

[0132] Data2: It is formed by concatenating 24 high - order bits of 0, 32 - bit current U raw data, and the lower 8 bits of the previous register data.

[0133] Data3: It is formed by concatenating 16 high - order bits of 0, 32 - bit current U raw data, and the lower 16 bits of the previous register data.

[0134] Data4: It is formed by concatenating 8 high - order bits of 0, 32 - bit current U raw data, and the lower 24 bits of the previous register data.

[0135] Data5: It is formed by concatenating 32 - bit current U raw data and the lower 32 bits of the previous register data.

[0136] Data6: Directly take the 64 - bit of the previous register data as the current data.

[0137] The logic control unit generates a counter signal according to the number of bytes (BUFF_CNT) of the data stored in the U buffer, and generates a buffer status signal according to the idle state of the U buffer. These signals are sent to the first multiplexer.

[0138] The logic control unit is also responsible for generating a data demand signal and a buffer status signal. It sends these signals to the second multiplexer and generates a data valid signal when BUFF_CNT ≥ 2.

[0139] The first multiplexer receives the buffer status signal and the counter signal from the logic control unit. It first determines whether there is free space in the U buffer according to the buffer status signal.

[0140] Data selection:

[0141] When there is free space in the U buffer, the first multiplexer selects the corresponding data output according to the value of BUFF_CNT:

[0142] When BUFF_CNT = 0, output Data1.

[0143] When BUFF_CNT = 1, output Data2.

[0144] When BUFF_CNT = 2, output Data3.

[0145] When BUFF_CNT = 3, output Data4.

[0146] When BUFF_CNT = 4, output Data5.

[0147] When BUFF_CNT > 4, output Data6 (but usually BUFF_CNT has an upper limit, and here it may be to illustrate the logic beyond the actual range).

[0148] When the U buffer has no free space (the buffer status signal is invalid), regardless of the value of BUFF_CNT, the first multiplexer outputs Data6. The first multiplexer outputs the selected data as the DATA_BUF1 signal.

[0149] The shift unit receives the DATA_BUF1 signal from the first multiplexer. Then, it concatenates the 63-16 bits of the DATA_BUF1 signal (i.e., removing the first 16 bits, keeping the last 48 bits, but padding 16 zeros in front) with 16 high-order bits of 0 in the order from high to low to generate the shifted buffer data SHIFT_BUF (but actually it is still 64-bit data, with the first 16 bits being 0 and the last 48 bits being the 63-16 bits of DATA_BUF1). The description here may be a bit confusing because shifting usually means moving bits of data, but here it is more like selecting and concatenating bit segments.

[0150] The second multiplexer receives the data demand signal and the data occupancy signal from the logic control unit. It first determines whether there is a data pop demand based on the data demand signal. Then, it determines whether the number of bytes of data stored in the U buffer, BUFF_CNT, is ≥ 2 based on the occupancy signal.

[0151] When there is a data pop demand and BUFF_CNT ≥ 2, the second multiplexer selects the DATA_BUF1 signal of the first multiplexer as the output data DATA_BUF2.

[0152] When there is no data pop demand or BUFF_CNT < 2, the second multiplexer selects the SHIFT_BUF signal of the shift unit as the output data DATA_BUF2. However, according to the previous description, SHIFT_BUF is actually a variant based on DATA_BUF1, so the selection logic here may need to be adjusted according to the actual design.

[0153] The data output unit receives the DATA_BUF2 signal from the second multiplexer and writes it into a 64-bit register. Then, the data output unit reads the lower 8 bits of data from this register and outputs it to the preprocessing module for subsequent processing. The lower 8 bits of data here may be the lowest 8 bits of the 64-bit data based on DATA_BUF2.

[0154] It should be noted that the structure of the V buffer in the embodiments of this application is the same as that of the U buffer, that is, the V buffer and the U buffer include the same components, the connection relationships between the components are the same, and the functions of the components are the same. The specific processes of the components in the U buffer can refer to the description of the V buffer and will not be elaborated here.

[0155] In some embodiments of this application, seeFigure 4 Schematic diagram of the structure of the YUV buffer shown, the YUV buffer includes: a data integration unit, a first multiplexer, a second multiplexer, a shift unit, a logic control unit, and a data output unit;

[0156] The data integration unit is used to read 32-bit current YUV data in the asynchronous FIFO, and integrate the current YUV data with the 48-bit previous register data in the data output unit to generate 4 paths of current data: the first data Data1, the second data Data2, the third data Data3, and the fourth data Data4. The first data is composed of 16-bit bit 0 and 32-bit current YUV data in sequence from high to low;

[0157] The second data is composed of 8-bit bit 0, the current YUV data, and the low 8 bits of the previous register data in sequence from high to low;

[0158] The third data is composed of the current YUV data and the low 16 bits of the previous register data in sequence from high to low;

[0159] The fourth data is the 48-bit previous register data;

[0160] The logic control unit is used to send a counter signal to the first multiplexer according to the number of bytes BUFF_CNT of the data stored in the YUV buffer, and send a buffer status signal to the first multiplexer according to the idle state of the YUV buffer;

[0161] The first multiplexer is used to continue to judge the size of BUFF_CNT when it is determined that there is free space in the YUV buffer according to the buffer status signal from the logic control unit;

[0162] When BUFF_CNT = 0, the first multiplexer outputs the first data Data1;

[0163] When BUFF_CNT = 1, the first multiplexer outputs the second data; MUX1 output signal DATA_BUF1 = Data2;

[0164] When BUFF_CNT = 2, the first multiplexer outputs the third data; MUX1 output signal DATA_BUF1 = Data3;

[0165] When BUFF_CNT = 3, the first multiplexer outputs the fourth data; MUX1 output signal DATA_BUF1 = Data4;

[0166] When the buffer status signal indicates that there is no free space in the YUV buffer, the first multiplexer outputs the fourth data; MUX1 outputs the signal DATA_BUF1 = Data4;

[0167] A shift unit for shifting the data output by the first multiplexer to obtain shifted buffer data SHIFT_BUF. The shifted buffer data SHIFT_BUF is formed by sequentially concatenating 16 bits of 0 and the bits from the 63rd to the 16th bit of the data output by the first multiplexer in the order from the highest bit to the lowest bit;

[0168] The logic control unit is further configured to process the data demand signal and the occupancy status signal, and send the data demand signal and the occupancy status signal to the second multiplexer;

[0169] A second multiplexer for selecting the data of the first multiplexer for output when it is determined according to the data demand signal from the logic control unit that there is an external data pop - stack demand and it is determined according to the occupancy status signal that the number of bytes of data stored in the YUV buffer, BUFF_CNT ≥ 1; otherwise, selecting the data of the shift unit for output;

[0170] The data output unit is configured to write the data DATA_BUF2 output by the second multiplexer into a register, and read the lower 8 - bit data from the register for output to the format processing module. The bit - width of this register is 48 bits.

[0171] Among them, the function of the data integration unit is to read 32 - bit current YUV data from the asynchronous FIFO and integrate it with the 48 - bit data of the previous register in the data output unit to generate 4 - way current data (Data1, Data2, Data3, Data4).

[0172] Its execution process includes: reading 32 - bit current YUV data. Obtaining the 48 - bit data of the previous register from the data output unit. Generating 4 - way data according to the integration rule:

[0173] Data1: It is formed by sequentially concatenating 16 high - order bits of 0 and the 32 - bit current YUV data in the order from the highest bit to the lowest bit.

[0174] Data2: It is formed by sequentially concatenating 8 high - order bits of 0, the 32 - bit current YUV data, and the lower 8 - bit data of the previous register in the order from the highest bit to the lowest bit.

[0175] Data3: It is formed by sequentially concatenating the 32 - bit current YUV data and the lower 16 - bit data of the previous register in the order from the highest bit to the lowest bit.

[0176] Data4: Directly take the 48 - bit data of the previous register as the current data.

[0177] The functions of the logic control unit include: sending control signals to the first multiplexer according to the number of bytes (BUFF_CNT) of the data stored in the YUV buffer and the idle state of the buffer.

[0178] Its execution process: Monitor the value of BUFF_CNT to understand the amount of data stored in the YUV buffer. Check the idle state of the YUV buffer. According to the above information, send a counter signal and a buffer status signal to the first multiplexer. At the same time, generate a data demand signal and an occupancy status signal, and send these signals to the second multiplexer.

[0179] The functions of the first multiplexer (MUX1) include: selecting appropriate data for output according to the signals of the logic control unit.

[0180] The execution process includes: receiving the buffer status signal from the logic control unit.

[0181] If there is free space in the YUV buffer, continue to judge the value of BUFF_CNT.

[0182] When BUFF_CNT = 0, output Data1.

[0183] When BUFF_CNT = 1, output Data2.

[0184] When BUFF_CNT = 2, output Data3.

[0185] When BUFF_CNT = 3, output Data4.

[0186] If there is no free space in the YUV buffer, output Data4 regardless of the value of BUFF_CNT.

[0187] Output the selected data as the DATA_BUF1 signal.

[0188] The function of the shift unit: perform a shift process on the data output by the first multiplexer to obtain the shifted buffer data (SHIFT_BUF).

[0189] The execution process: Receive the DATA_BUF1 signal from the first multiplexer. Concatenate the 63 - 16 bits of the DATA_BUF1 signal (i.e., remove the first 16 bits, keep the last 48 bits, but add 16 leading 0s) and the 16 high - order bits 0 in the order from high to low to generate the shifted buffer data SHIFT_BUF.

[0190] The functions of the second multiplexer (MUX2): select appropriate data for output according to the signals of the logic control unit.

[0191] Execution process: Receive the data requirement signal and occupancy status signal from the logic control unit. If there is an external data stack-out requirement and BUFF_CNT ≥ 1, select the data of the first multiplexer for output. If there is no data stack-out requirement or BUFF_CNT < 1, select the data of the shift unit for output. Output the selected data as the DATA_BUF2 signal.

[0192] Function of the data output unit: Write the data output by the second multiplexer into a register, and read the lower 8 bits of data from the register for output. Execution process: Receive the DATA_BUF2 signal from the second multiplexer. Write the DATA_BUF2 signal into a 48-bit register. Read the lower 8 bits of data from this register. Output the read lower 8 bits of data to the format processing module for subsequent processing.

[0193] The YUV buffer in this application can efficiently integrate, store, and manage 32-bit YUV data from the asynchronous FIFO. Through an intelligent data selection and shift processing mechanism, as well as a flexible data stack-out strategy, it ensures that the integrated data is stored in sequence when there is free space in the YUV buffer, and selects appropriate data for output when there is no free space or there is an external data stack-out requirement. At the same time, it optimizes the data format to meet the requirements of the format processing module, thereby improving the performance and stability of the entire video processing system.

[0194] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disc, a read-only memory, or a random access memory, etc.

[0195] The above-disclosed are only the preferred embodiments of this application. Of course, the scope of rights of this application cannot be limited by this. Therefore, equivalent changes made according to the claims of this application still fall within the scope covered by this application.

Claims

1. A YUV data processing device, characterized in that: include: Memory, Y buffer, U buffer, V buffer, pre-processing module, asynchronous FIFO, YUV buffer and format processing module; The memory is connected to the input ends of the Y buffer, the U buffer and the V buffer respectively, the output ends of the Y buffer, the U buffer and the V buffer are connected to the input end of the pre-processing module respectively, the output end of the pre-processing module is connected to the input end of the asynchronous FIFO, the output end of the asynchronous FIFO is connected to the output end of the YUV buffer, and the output end of the YUV buffer is connected to the output end of the format processing module; the depth of the Y buffer, the U buffer and the V buffer is 64 bits; The memory is used to store Y original data, U original data and V original data, and the three different data are stored separately in different areas; The Y buffer is used to read 32-bit Y original data from the memory and write it into a queue, then read 16-bit Y data from the queue, and then send the read 16-bit Y data to the preprocessing module; The U buffer is used to read 32 bits of U data from the memory and write them into a queue, and then read 8 bits of U data from the queue and send them to the preprocessing module; The V buffer is used to read 32-bit V raw data from the memory and write it into a queue, and then read 8-bit V data from the queue and send it to the preprocessing module; The preprocessing module is used to generate 32-bit YUV data after arranging the received 16-bit Y data, 8-bit U data and 8-bit V data in a preset order, and send the generated 32-bit YUV data to the asynchronous FIFO; The asynchronous FIFO is used to write the 32-bit YUV data from the pre-processing module into a queue, and then read a 32-bit YUV data in the queue and send it to the YUV buffer; the data bit width of the asynchronous FIFO is 32 and the depth is 2; The YUV buffer is used to write the YUV data from the asynchronous FIFO into the queue, and read an 8-bit data from the queue and send it to the format processing module; The format processing module is used to convert the 8-bit data from the YUV buffer into a timing control stream of a preset protocol and output it through a parallel video interface.

2. The processing device according to claim 1, characterized in that The Y buffer includes: a data integration unit, a logic control unit, a first multiplexer, a second multiplexer, a shift unit and a data output unit; The data integration unit is used to read the 32-bit current Y original data in the memory, and integrate the current Y original data and the 64-bit previous register data from the data output unit to generate the current 6-way data: the first data Data1, the second data Data2, the third data Data3, the fourth data Data4, the fifth data Data5 and the sixth data Data6; the first data is composed of 32 0 bits and the current Y original data in sequence from high to low; the second data is composed of 24 0 bits, the current Y original data and the previous register data. The lower 8 bits of the register data are concatenated in order from high to low; the third data is concatenated in order from 16 0 bits, the current Y original data and the lower 16 bits of the previous register data in order from high to low; the fourth data is concatenated in order from 8 0 bits, the current Y original data and the lower 24 bits of the previous register data in order from high to low; the fifth data is concatenated in order from the current Y original data and the lower 32 bits of the previous register data in order from high to low; the sixth data is the 64-bit previous register data; a logic control unit, configured to send a counter signal to the first multiplexer according to the number of bytes BUFF_CNT of data stored in the Y buffer, and to send a buffer status signal to the first multiplexer according to an idle state of the Y buffer; a first multiplexer, configured to determine whether there is free space in the Y buffer according to a buffer status signal from the logic control unit, and continue to determine the size of BUFF_CNT; When BUFF_CNT=0, the first multiplexer outputs the first data Data1; When BUFF_CNT=1, the first multiplexer outputs the second data; MUX1 outputs a signal DATA_BUF1=Data2; When BUFF_CNT=2, the first multiplexer outputs the third data; MUX1 outputs a signal DATA_BUF1=Data3; When BUFF_CNT=3, the first multiplexer outputs the fourth data; MUX1 outputs the signal DATA_BUF1=Data4; When BUFF_CNT=4, the first multiplexer outputs the fifth data; MUX1 outputs a signal DATA_BUF1=Data5; When BUFF_CNT>4, the first multiplexer outputs the sixth data; MUX1 outputs a signal DATA_BUF1=Data6; If the buffer status signal indicates that there is no free space in the Y buffer, the first multiplexer outputs the sixth data; MUX1 outputs a signal DATA_BUF1 = Data6; A shift unit, used for shifting the data output by the first multiplexer to obtain shift buffer data SHIFT_BUF, wherein the shift buffer data SHIFT_BUF is formed by sequentially splicing 16 bits 0 and bits 63 to 16 of the data output by the first multiplexer in a high-to-low order; The logic control unit is further used to generate a data demand signal and a buffer status signal, and send the data demand signal and the buffer status signal to the second multiplexer; a second multiplexer, for selecting the data output by the first multiplexer as the output data DATA_BUF2 when it is determined according to the data demand signal from the logic control unit that there is a data popping demand and the number of bytes of data stored in the Y buffer BUFF_CNT≥2, otherwise, selecting the data output by the shift unit as the output data DATA_BUF2; The data output unit is used to write the data DATA_BUF2 output by the second multiplexer into the register, and read the lower 16 bits of data from the register and output them to the preprocessing module. The bit width of the register is 64 bits.

3. The processing device according to claim 1 or 2, characterized in that: The U buffer comprises: a data integration unit, a logic control unit, a first multiplexer, a second multiplexer, a shift unit and a data output unit; The data integration unit is used to read the 32-bit current U original data in the memory, and integrate the current U original data and the 64-bit previous register data from the data output unit to generate the current 6-way data: the first data Data1, the second data Data2, the third data Data3, the fourth data Data4, the fifth data Data5 and the sixth data Data6; the first data is composed of 32 0 bits and the current U original data in sequence from high to low; the second data is composed of 24 0 bits, the current U original data and the previous register data. The lower 8 bits of the register data are concatenated in order from high to low; the third data is concatenated in order from 16 0 bits, the current U original data and the lower 16 bits of the previous register data in order from high to low; the fourth data is concatenated in order from 8 0 bits, the current U original data and the lower 24 bits of the previous register data in order from high to low; the fifth data is concatenated in order from the current U original data and the lower 32 bits of the previous register data in order from high to low; the sixth data is the 64-bit previous register data; A logic control unit, configured to send a counter signal to the first multiplexer according to the number of bytes BUFF_CNT of data stored in the U buffer, and to send a buffer status signal to the first multiplexer according to the idle state of the U buffer; a first multiplexer, configured to determine whether there is free space in the U buffer according to a buffer status signal from the logic control unit, and continue to determine the size of BUFF_CNT; When BUFF_CNT=0, the first multiplexer outputs the first data Data1; When BUFF_CNT=1, the first multiplexer outputs the second data; MUX1 outputs a signal DATA_BUF1=Data2; When BUFF_CNT=2, the first multiplexer outputs the third data; MUX1 outputs a signal DATA_BUF1=Data3; When BUFF_CNT=3, the first multiplexer outputs the fourth data; MUX1 outputs the signal DATA_BUF1=Data4; When BUFF_CNT=4, the first multiplexer outputs the fifth data; MUX1 outputs a signal DATA_BUF1=Data5; When BUFF_CNT>4, the first multiplexer outputs the sixth data; MUX1 outputs a signal DATA_BUF1=Data6; If the buffer status signal indicates invalid, the first multiplexer outputs the sixth data; MUX1 outputs a signal DATA_BUF1 = Data6; A shift unit, used for shifting the data output by the first multiplexer to obtain shift buffer data SHIFT_BUF, wherein the shift buffer data SHIFT_BUF is formed by sequentially splicing 16 bits 0 and bits 63 to 16 of the data output by the first multiplexer in a high-to-low order; The logic control unit is further used to generate a data demand signal and a buffer status signal, and send the data demand signal and the data occupancy signal to the second multiplexer; a second multiplexer, for selecting the data output by the first multiplexer as the output data DATA_BUF2 when it is determined according to the data demand signal from the logic control unit that there is a data popping demand and when it is determined according to the occupancy signal that the number of bytes of data stored in the U buffer BUFF_CNT≥2, otherwise, selecting the data output by the shift unit as the output data DATA_BUF2; The data output unit is used to write the data DATA_BUF2 output by the second multiplexer into the register, and read the lower 8 bits of data from the register and output them to the preprocessing module. The bit width of the register is 64 bits.

4. The processing device according to claim 3, characterized in that The V buffer and the U buffer have the same structure and the functions of the components included are the same.

5. The processing device according to claim 1, 2 or 4, characterized in that: The YUV buffer comprises: a data integration unit, a first multiplexer, a second multiplexer, a shift unit, a logic control unit and a data output unit; A data integration unit, used for reading 32 bits of current YUV data in the asynchronous FIFO, and integrating the current YUV data and the 48 bits of the previous register data in the data output unit to generate 4 channels of current data: first data Data1, second data Data2, third data Data3, and fourth data Data4. The first data is composed of 16 bits of bit 0 and 32 bits of current YUV data in order from high to low. The second data is composed of 8 bits 0, the current YUV data and the lower 8 positions of the previous register data in the order of high to low bits; The third data is composed of the current YUV data and the lower 16 bits of the previous register data in the order of high to low bits; The fourth data is 48 bits of the previous register data; a logic control unit, configured to send a counter signal to the first multiplexer according to the number of bytes BUFF_CNT of data stored in the YUV buffer, and to send a buffer status signal to the first multiplexer according to an idle state of the YUV buffer; a first multiplexer, configured to continue determining the size of BUFF_CNT when determining that the YUV buffer has free space according to the buffer status signal from the logic control unit; When BUFF_CNT=0, the first multiplexer outputs the first data Data1; When BUFF_CNT=1, the first multiplexer outputs the second data; MUX1 outputs the signal DATA_BUF1=Data2; When BUFF_CNT=2, the first multiplexer outputs the third data; MUX1 outputs the signal DATA_BUF1=Data3; When BUFF_CNT=3, the first multiplexer outputs the fourth data; MUX1 outputs the signal DATA_BUF1=Data4; If the buffer status signal indicates that there is no free space in the YUV buffer, the first multiplexer outputs the fourth data; MUX1 outputs the signal DATA_BUF1=Data4; A shift unit, used for shifting the data output by the first multiplexer to obtain shift buffer data SHIFT_BUF, wherein the shift buffer data SHIFT_BUF is formed by sequentially splicing 16 bits 0 and bits 63 to 16 of the data output by the first multiplexer in a high-to-low order; The logic control unit is also used for data demand signal and occupancy status signal, and for the second multiplexer to send the data demand signal and occupancy status signal; A second multiplexer is used for selecting the data of the first multiplexer for output when it is determined that there is an external data popping demand according to the data demand signal from the logic control unit and the number of bytes of data stored in the YUV buffer BUFF_CNT≥1 according to the occupancy state signal, otherwise, the data of the shift unit is selected for output; The data output unit is used to write the data DATA_BUF2 output by the second multiplexer into the register, and read the lower 8 bits of data from the register to output to the format processing module. The bit width of the register is 48 bits.

6. The method according to claim 5, characterized in that The preset sequences include: {YUYV}, {YVYU}, {UYVY}, {VYUV}.

7. The method according to claim 1 or 2 or 4 or 6, characterized in that: The preset protocols include: BT656, BT1120, DVP and BT601.

8. A computer storage medium, characterized in that: The computer storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing the method steps according to any one of claims 1 to 7.

9. An electronic device, characterized in that: include: A YUV data processing device as claimed in any one of claims 1 to 7.

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