Silicon carbide VDMOS resistant to drain voltage shock and preparation method

Abstract

The present invention provides a silicon carbide VDMOS resistant to drain voltage shock and a preparation method thereof. The method includes: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer, epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a blocking layer, etching, ion implanting to form a buried layer, a P-type source region, a P-type well region, a protrusion portion and an N-type source region; reforming the blocking layer, etching, depositing to form a Schottky metal layer; reforming the blocking layer, etching, depositing a set silicon carbide material, undergoing a high-temperature process, and performing thermal diffusion to form a protective layer; reforming the blocking layer, etching, depositing to form an insulating dielectric region; reforming the blocking layer, etching, depositing metal to form a gate metal layer; reforming the blocking layer, etching, depositing metal to form a source metal layer, and removing the blocking layer to complete the preparation; reducing the on-resistance of the device on the basis of ensuring the drain voltage shock resistance of the device.

Description

Technical Field

[0001] The present invention relates to a silicon carbide VDMOS resistant to drain voltage shock and a preparation method thereof. Background Art

[0002] Due to the wide bandgap characteristic of silicon carbide materials, the VDMOS devices thereof have the characteristics of high switching speed and high breakdown voltage. The VDMOS structure can achieve the characteristics of the IGBT of Si devices, so it has attracted much attention from researchers and the industrial community. Under such a background, researchers focus on the reliability and conduction characteristics of the devices to meet special applications. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a silicon carbide VDMOS resistant to drain voltage shock and a preparation method thereof, which reduces the on-resistance of the device on the basis of ensuring the drain voltage shock resistance of the device.

[0004] In a first aspect, the present invention provides a preparation method of a silicon carbide VDMOS resistant to drain voltage shock, including the following steps:

[0005] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a buried layer;

[0007] Step 3: Remove the blocking layer in Step 2, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type source region;

[0008] Step 4: Remove the blocking layer in Step 3, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type well region and a protrusion;

[0009] Step 5: Remove the blocking layer in Step 4, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form an N-type source region;

[0010] Step 6: Remove the blocking layer in Step 5, re-form a blocking layer, etch the blocking layer to form a through hole, etch the P-type well region to form a groove, and deposit metal to form a Schottky metal layer;

[0011] Step 7: Remove the blocking layer in Step 6, re-form a blocking layer, etch the blocking layer to form a through hole, deposit a set silicon carbide material, and perform thermal diffusion through a high-temperature process to form a protective layer;

[0012] Step 8: Remove the blocking layer in Step 7, re-form a blocking layer, etch the blocking layer to form a through hole, and deposit to form an insulating dielectric region;

[0013] Step 9: Remove the barrier layer in Step 8, reform the barrier layer, etch the barrier layer to form a via hole, deposit metal, and form a gate metal layer;

[0014] Step 10: Remove the barrier layer in Step 9, reform the barrier layer, etch the barrier layer to form a via hole, deposit metal, form a source metal layer, and remove the barrier layer to complete the preparation.

[0015] In a second aspect, the present invention provides a silicon carbide VDMOS resistant to drain voltage shock, which is prepared by using the preparation method of a silicon carbide VDMOS resistant to drain voltage shock described in the first aspect.

[0016] The advantages of the present invention are as follows:

[0017] First, by constructing a near-semicircular protective layer in a thermal diffusion manner at the bottom of the device insulation dielectric region, the present invention forms a structure that is thick in the middle region of the insulation dielectric region and thin near the conductive channel. This structure allows electrons to move laterally from the N-type source region through the gate control region and then move towards the drain metal layer, increasing the area of the N-type region during the movement, thereby reducing the on-resistance of the device while ensuring the device's resistance to drain voltage shock;

[0018] Second, the insulation dielectric region of the present invention is designed in a convex shape. The first insulation dielectric layer is in the longitudinal part between the device gate metal layer and the P-type well region and is relatively thin, enabling the gate to have a gate control ability for this region. Above the P-type protective layer and in the region above the non-P-type well region, there are the second insulation dielectric layer and the first insulation dielectric layer, which are relatively thick, can reduce capacitive charge, improve the switching speed of the device, and enhance the device's resistance to drain voltage shock;

[0019] Third, the present invention constructs a Schottky metal layer between the outside of the P-type well region and the middle of the P-type source region. This Schottky metal layer can reduce the on-voltage drop of the body diode of the device and reduce the loss when the device is not conducting and has a continuous current;

[0020] Fourth, the present invention constructs a buried layer below the P-type well region and below the Schottky metal layer. The main function of this buried layer is to laterally guide the current of the device during normal conduction and body diode continuous current towards the inside of the device, reducing the on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention will be further described below with reference to the accompanying drawings in conjunction with embodiments.

[0022] Figure 1 It is a schematic diagram of a silicon carbide VDMOS resistant to drain voltage shock of the present invention.

[0023] Figure 2 It is a process cross-section of a silicon carbide VDMOS resistant to drain voltage shock of the present invention Figure 1 。

[0024] Figure 3 Process cross-section of a silicon carbide VDMOS with resistance to drain voltage impact according to the present invention Figure 2 。

[0025] Figure 4 Process cross-section of a silicon carbide VDMOS with resistance to drain voltage impact according to the present invention Figure 3 。

[0026] Figure 5 Process cross-section of a silicon carbide VDMOS with resistance to drain voltage impact according to the present invention Figure 4 。

[0027] Figure 6 Process cross-section of a silicon carbide VDMOS with resistance to drain voltage impact according to the present invention Figure 5 。

[0028] Figure 7 Process cross-section of a silicon carbide VDMOS with resistance to drain voltage impact according to the present invention Figure 6 。

[0029] Figure 8 Process cross-section of a silicon carbide VDMOS with resistance to drain voltage impact according to the present invention Figure 7 。

[0030] Figure 9 Process cross-section of a silicon carbide VDMOS with resistance to drain voltage impact according to the present invention Figure 8 。

[0031] Figure 10 Process cross-section of a silicon carbide VDMOS with resistance to drain voltage impact according to the present invention Figure 9 。

[0032] Figure 11 Process cross-section of a silicon carbide VDMOS with resistance to drain voltage impact according to the present invention Figure 10 。

[0033] Figure 12 Process cross-section of a silicon carbide VDMOS with resistance to drain voltage impact according to the present invention Figure 10 One.

[0034] Figure 13 Process cross-section of a silicon carbide VDMOS with resistance to drain voltage impact according to the present invention Figure 10 Two.

[0035] Figure 14 Process cross-section of a silicon carbide VDMOS with resistance to drain voltage impact according to the present invention Figure 10 Three. Detailed implementation manners

[0036] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application will be thorough and complete.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0038] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, a first element, component, region, layer, doping type or part discussed below may be denoted as a second element, component, region, layer or part without departing from the teachings of the present invention.

[0039] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0040] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / have" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0041] As Figures 1 to 14 shown, an embodiment of the present application provides a method for preparing a silicon carbide VDMOS resistant to drain voltage shock, including the following steps:

[0042] Step 1: Deposit metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9, and epitaxially grow on the upper side of the silicon carbide substrate 1 to form a drift layer 2;

[0043] Step 2: Form a blocking layer 100 above the drift layer 2, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a buried layer 21;

[0044] Step 3: Remove the blocking layer in Step 2, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a P-type source region 3;

[0045] Step 4: Remove the blocking layer in Step 3, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a P-type well region 5 and a protrusion 22;

[0046] Step 5: Remove the blocking layer in Step 4, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form an N-type source region 51;

[0047] Step 6: Remove the blocking layer in Step 5, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, etch the P-type well region 5 to form a trench 31, deposit metal to form a Schottky metal layer 4;

[0048] Step 7: Remove the blocking layer in Step 6, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, deposit P++ silicon carbide material 200, and perform thermal diffusion through a high-temperature process to form a protective layer 221;

[0049] Step 8: Remove the blocking layer in Step 7, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, deposit, and form the first insulating dielectric layer 61; remove the blocking layer, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, deposit to form the second insulating dielectric layer 62. The insulating dielectric region 6 includes the first insulating dielectric layer 61 and the second insulating dielectric layer 62.

[0050] Step 9: Remove the blocking layer in Step 8, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, deposit metal, and form the gate metal layer 7.

[0051] Step 10: Remove the blocking layer in Step 9, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, deposit metal, and form the source metal layer 8. Remove the blocking layer 100 to complete the preparation.

[0052] In this embodiment, preferably, the insulating dielectric region 6 includes the first insulating dielectric layer 61 and the second insulating dielectric layer 62. The width of the first insulating dielectric layer 61 is greater than the width of the second insulating dielectric layer 62. The first insulating dielectric layer 61 and the second insulating dielectric layer 62 form a convex shape, and the gate metal layer 7 is an inverted concave shape, and the gate metal layer 7 matches the insulating dielectric region 6.

[0053] In this embodiment, preferably, the width of the protective layer 221 is less than the width of the convex portion 22.

[0054] In this embodiment, preferably, the N-type source region 51, the P-type well region 5, the Schottky metal layer 4, and the P-type source region 3 have the same thickness.

[0055] In this embodiment, preferably, the doping concentration of the buried layer 21 is greater than the doping concentration of the drift layer 2.

[0056] In this embodiment, preferably, the doping concentration of the P-type source region 3 is greater than or equal to the doping concentration of the P-type well region 5.

[0057] In this embodiment, preferably, the buried layer 21 is located directly below the P-type well region 5 and the Schottky metal layer 4, and the width of the buried layer 21 is less than the sum of the widths of the P-type well region 5 and the Schottky metal layer 4.

[0058] As Figure 1 shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0059] Silicon carbide substrate 1;

[0060] Drift layer 2, the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a buried layer 21 and a protrusion 22 are provided on the drift layer 2; a protective layer 221 is provided in the protrusion 22;

[0061] P-type source region 3, the lower side of the P-type source region 3 is connected to the upper side of the drift layer 2;

[0062] Schottky metal layer 4, the lower side of the Schottky metal layer 4 is connected to the upper side of the drift layer 2, and the outer side of the Schottky metal layer 4 is connected to the inner side of the P-type source region 3;

[0063] P-type well region 5, the lower side of the P-type well region 5 is connected to the upper side of the drift layer 2, the outer side of the P-type well region 5 is connected to the inner side of the Schottky metal layer 4, and the inner side of the P-type well region 5 is connected to the outer side of the protrusion 22; an N-type source region 51 is provided in the P-type well region 5;

[0064] Insulating dielectric region 6, the lower side of the insulating dielectric region 6 is respectively connected to the N-type source region 51, the P-type well region 5, the drift layer 2, and the protective layer 221;

[0065] Gate metal layer 7, the gate metal layer 7 is connected to the insulating dielectric region 6;

[0066] Source metal layer 8, the lower side of the source metal layer 8 is respectively connected to the N-type source region 51, the P-type well region 5, the Schottky metal layer 4, and the P-type source region 3;

[0067] And a drain metal layer 9, the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 1.

[0068] Another embodiment of the present invention includes a drain metal layer 9, an N+ silicon carbide substrate 1, an N-type drift layer 2, an N-type buried layer 21, a P-type source region 3, a Schottky metal layer 4, a P-type well region 5, an N-type source region 51, a P-type protective layer 221, a first insulating dielectric layer 61, a second insulating dielectric layer 62, a gate metal layer 7, and a source metal layer 8. The doping concentration of the N-type silicon carbide substrate 1 is 2 - 8e18 cm -3 , the doping concentration of the N-type drift layer 2 is 5 - 9e16 cm -3 , the doping concentration of the N-type buried layer 21 is 1 - 5e17 cm -3 , the doping concentration of the P-type source region 3 is 0.8 - 5e19 cm -3 , the doping concentration of the P-type well region 5 is 5 - 8e18 cm -3 , the doping concentration of the P-type protective layer 221 is 5 - 8e17 cm -3 , the doping concentration of the N-type source region 51 is 2 - 8e18 cm -3, the material of the insulating dielectric region can be silicon dioxide, and the gate metal layer 7, source metal layer 8, and drain metal layer 9 are one metal among Al, Cu, Ni or an alloy of several metals;

[0069] The doping concentrations of the N-type silicon carbide substrate 1, N-type drift layer 2, P-type well region 5, and P-type source region 3 are a trade-off between the on-resistance and breakdown voltage structure of the planar-gate silicon carbide VDMOS device. The doping concentration of the N-type buried layer 21 is a trade-off between the on-resistance, internal current sharing, and internal electric field distribution of the device. If the concentration is too high, it is easy to cause a high electric field region inside the device structure. If the concentration is too low, there is no lateral current sharing effect. The P-type protection layer 221 is to improve the device's drain voltage impact tolerance ability, and the lower doping concentration is to avoid the influence of the P-type region 3 on the device's on-resistance;

[0070] The width of the first insulating dielectric layer 61 of the device is 2 μm, and the width of the second insulating dielectric layer 62 is 1.4 μm. The parts where the first insulating dielectric layer 61 is wider than the second insulating dielectric layer 62 are equal on the left and right, both being 0.3 μm. The width of the P-type well region 5 inside the N-type source region 51 is 0.3 μm, and the maximum width of the P-type protection layer 221 is 1 μm. This is to control the diffusion of the space charge regions of the P-type protection layer 221 and the N-type drift layer 2 into the conductive channel and affect the device's conductive characteristics. The width of the N-type source region 51 is 1 μm, and the total width of the P-type well region 5 is 2 μm. This is to ensure the drain-source breakdown ability of the device when the drain withstands voltage. The width of the Schottky metal layer 4 is 500 nm, and the width of the P-type source region 3 is 500 nm. This is a trade-off between the distribution of the Schottky substrate diode and the PN junction body diode. The width of the N-type buried layer 21 is 2 μm, and the edge of the buried layer 21 far from the gate metal layer 7 is located at the center of the Schottky metal layer 4;

[0071] The depth of the P-type well region 5 is 1 μm, the depth of the N-type source region 51 is 500 nm, the depth of the Schottky metal layer 4 is 1 μm, and the depth of the P-type source region 3 is 1 μm. This is to ensure that the contact depths of the Schottky substrate diode and the PN junction body diode with the N-type drift layer 2 are the same, improve the interface consistency, and avoid introducing non-ideal effects due to interface defects. The maximum depth of the P-type protection layer 221 is 800 nm, which is a design for the device to withstand a drain voltage impact of 3000 V. The thickness of the N-type buried layer 21 is 600 nm, and the distance from its upper side to the lower side of the P-type well region 5 is 1 μm. This is to avoid the diffusion of the space charge region formed by the P-type well region 5 and the N-type drift layer 2 into the N-type buried layer 21 and affect the current sharing effect. The thickness of the first insulating dielectric layer 61 is 50 nm, and the thickness of the second insulating dielectric layer 62 is 100 nm. This is a combined design of gate control ability and drain voltage impact tolerance. The thickness of the source metal layer 8 is 300 nm, and the thickness of the gate metal layer 7 is 300 nm;

[0072] In the present invention, a nearly semi-circular protective layer 221 is constructed by thermal diffusion at the bottom of the device insulation dielectric region 6, forming a structure that is thick in the middle region of the insulation dielectric region 6 and thin near the conductive channel. This structure allows electrons to move laterally from the N-type source region 51 through the gate control region and then move towards the drain metal layer 9, with the area of the N-type region increasing. Thus, on the basis of ensuring the device's resistance to drain voltage impact, the on-resistance of the device is reduced.

[0073] The insulation dielectric region 6 is designed in a convex shape. The first insulation dielectric layer 61 is provided in the longitudinal parts of the device gate metal layer 7 and the P-type well region 5. The first insulation dielectric layer 61 is relatively thin, enabling the gate to have gate control ability over this region. Above the P-type protective layer 221 and above the non-P-type well region 5, there are the second insulation dielectric layer 62 and the first insulation dielectric layer 61, which are relatively thick, capable of reducing capacitive charge, increasing the switching speed of the device, and enhancing the device's resistance to drain voltage impact.

[0074] A Schottky metal layer 4 is constructed between the outside of the P-type well region 5 and the middle of the P-type source region 51 of the device. This Schottky metal layer 4 can reduce the on-voltage drop of the body diode of the device and reduce the loss when the device is not conducting and has a continuous current.

[0075] An N-type buried layer 21 is constructed below the P-type well region 5 and below the Schottky metal layer 4 of the device. The main function of this buried layer 21 is to laterally guide the current of the device during normal conduction and body diode continuous current towards the inside of the device, reducing the on-resistance of the device.

[0076] Although the specific implementation manners of the present invention are described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should all be covered within the scope protected by the claims of the present invention.

Claims

1. A silicon carbide VDMOS resistant to drain voltage shock, characterized in that: Comprising: A silicon carbide substrate; A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; An embedded layer and a protrusion are provided on the drift layer; a protective layer is provided in the protrusion; A P-type source region, the lower side of which is connected to the upper side of the drift layer; A Schottky metal layer, the lower side of which is connected to the upper side of the drift layer, and the outer side of which is connected to the inner side of the P-type source region; A P-type well region, the lower side of which is connected to the upper side of the drift layer, the outer side of which is connected to the inner side of the Schottky metal layer, and the inner side of which is connected to the outer side of the protrusion; an N-type source region is provided in the P-type well region; An insulating dielectric region, the lower side of which is respectively connected to the N-type source region, the P-type well region, the drift layer and the protective layer; A gate metal layer, which is connected to the insulating dielectric region; A source metal layer, the lower side of which is respectively connected to the N-type source region, the P-type well region, the Schottky metal layer and the P-type source region; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate; A nearly semi-circular protective layer is constructed at the bottom of the insulating dielectric region; the insulating dielectric region is convex-shaped and includes a first insulating dielectric layer and a second insulating dielectric layer; the first insulating dielectric layer is provided in the longitudinal part between the gate metal layer and the P-type well region, and the second insulating dielectric layer and the first insulating dielectric layer are provided above the P-type protective layer and above the non-P-type well region; a Schottky metal layer is constructed between the outside of the P-type well region and the P-type source region; An embedded layer is constructed below the P-type well region and below the Schottky metal layer.

2. The manufacturing method of a silicon carbide VDMOS resistant to drain voltage impact according to claim 1, wherein: Including the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form an embedded layer; Step 3: Remove the blocking layer in Step 2, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type source region; Step 4: Remove the blocking layer in Step 3, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type well region and a protrusion; Step 5: Remove the blocking layer in Step 4, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form an N-type source region; Step 6: Remove the blocking layer in Step 5, reform the blocking layer, etch the blocking layer to form a through hole, etch the P-type well region to form a groove, and deposit metal to form a Schottky metal layer; Step 7: Remove the blocking layer in Step 6, reform the blocking layer, etch the blocking layer to form a through hole, deposit a set silicon carbide material, and perform thermal diffusion through a high-temperature process to form a protective layer; Step 8: Remove the blocking layer in Step 7, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form an insulating dielectric region; Step 9: Remove the blocking layer in Step 8, reform the blocking layer, etch the blocking layer to form a through hole, and deposit metal to form a gate metal layer; Step 10: Remove the barrier layer in Step 9, reform the barrier layer, etch the barrier layer to form a via hole, deposit metal to form a source metal layer, and remove the barrier layer to complete the preparation.

3. The manufacturing method of a silicon carbide VDMOS resistant to drain voltage impact according to claim 2, characterized in that: The specific content of Step 8 is as follows: Remove the barrier layer in Step 7, reform the barrier layer, etch the barrier layer to form a via hole, and deposit to form a first insulating dielectric layer; Remove the barrier layer, reform the barrier layer, etch the barrier layer to form a via hole, and deposit to form a second insulating dielectric layer. The insulating dielectric region includes the first insulating dielectric layer and the second insulating dielectric layer; The width of the first insulating dielectric layer is greater than the width of the second insulating dielectric layer. The first insulating dielectric layer and the second insulating dielectric layer form a convex shape, and the gate metal layer is an inverted concave shape, and the gate metal layer matches the insulating dielectric region.

4. The manufacturing method of a silicon carbide VDMOS resistant to drain voltage shock according to claim 2, characterized in that: The width of the protective layer is less than the width of the protruding portion.

5. The manufacturing method of a silicon carbide VDMOS resistant to drain voltage shock as described in claim 2, characterized in that: The thicknesses of the N-type source region, the P-type well region, the Schottky metal layer, and the P-type source region are all equal.

6. The manufacturing method of a silicon carbide VDMOS resistant to drain voltage impact according to claim 2, characterized in that: The doping concentration of the buried layer is greater than the doping concentration of the drift layer.

7. The manufacturing method of a silicon carbide VDMOS resistant to drain voltage impact according to claim 2, characterized in that: The doping concentration of the P-type source region is greater than or equal to the doping concentration of the P-type well region.

8. The manufacturing method of a silicon carbide VDMOS resistant to drain voltage impact according to claim 2, wherein: The buried layer is located directly below the P-type well region and the Schottky metal layer, and the width of the buried layer is less than the sum of the widths of the P-type well region and the Schottky metal layer.

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