Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes channel structures vertically spaced apart from each other and a gate structure wrapping the channel structures. The semiconductor structure also includes a first porous layer formed over a first sidewall of the gate structure under the channel structure and a source / drain structure attached to the channel structure. Further, the source / drain structure is laterally separated from the first porous layer by a first air gap.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of manufacturing the same. Background Art

[0002] The electronics industry is experiencing an increasing demand for smaller and faster electronic devices that can implement a greater number of increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., the minimum feature size) and thereby improving production efficiency and reducing associated costs. However, such miniaturization has introduced greater complexity into semiconductor manufacturing processes. Therefore, achieving continued progress in semiconductor ICs and devices requires similar progress in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). However, the integration of the manufacture of multi-gate devices can be challenging. Summary of the Invention

[0004] Some embodiments of the present application provide a semiconductor structure, comprising: channel structures, vertically separated from each other; a gate structure, wrapping the channel structures; a first porous layer, formed above a first sidewall of the gate structure below the channel structures; and source / drain structures, attached to the channel structures, wherein the source / drain structures are laterally separated from the first porous layer by a first air gap.

[0005] Some other embodiments of the present application provide a semiconductor structure, comprising: a substrate fin structure, protruding from a substrate; a channel structure, formed above the substrate fin structure; source / drain structures, attached to the channel structure in a first direction; and a gate structure, wrapping the channel structure and longitudinally oriented in a second direction different from the first direction, wherein a bottom surface of the source / drain structures and a bottom surface of a bottommost one of the channel structures are exposed by a bottom air gap.

[0006] Some additional embodiments of the present application provide a method for manufacturing a semiconductor structure, including: alternately stacking a first semiconductor material layer and a second semiconductor material layer in a first direction to form a semiconductor stack above a substrate; patterning the semiconductor stack to form fin structures longitudinally oriented in a second direction orthogonal to the first direction; forming source / drain trenches in the fin structures; recessing the first semiconductor material layer to form notches; forming sacrificial inner spacers in the notches and forming a sacrificial bottom layer in a bottom region of the source / drain trenches; forming source / drain structures above the sacrificial bottom layer; removing the first semiconductor material layer to form gate trenches; forming a porous layer on sidewalls of the sacrificial inner spacers and sidewalls of the sacrificial bottom layer; removing the sacrificial inner spacers and the sacrificial bottom layer; and forming a gate structure in the gate trenches. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figures 1A to 1C A schematic perspective view showing an intermediate stage of manufacturing a semiconductor structure according to some embodiments is shown.

[0009] Figures 2A-1 to 2M-1 、 Figures 2A-2 to 2M-2 、 Figures 2A-3 to 2M-3 and Figures 2A-4 to 2M-4 show cross-sectional views of intermediate stages of manufacturing a semiconductor structure taken along lines Y Figure 1C -Y SD -Y SD ’, Y MG -Y MG ’, X 1 -X 1 ’ and X 2 -X 2 ’ as shown in some embodiments, respectively.

[0010] Figure 2F-5 show enlarged cross-sectional views of a region R Figure 2F-3 shown in 2F-5 according to various embodiments.

[0011] Figure 2F-6 show enlarged cross-sectional views of a region R Figure 2F-3 shown in 2F-6 according to various embodiments.

[0012] Figure 2G-5 、 Figure 2G-6 andFigure 2G-7 shows an enlarged cross-sectional view of the Figure 2G-3 region R shown in 2G .

[0013] Figure 2H-5 shows an enlarged cross-sectional view of the Figure 2H-3 region R shown in 2H-3 .

[0014] Figure 2H-6 shows an enlarged cross-sectional view of the Figure 2H-4 region R shown in 2H-4 .

[0015] Figure 2J-5 shows an enlarged cross-sectional view of the Figure 2J-3 region R shown in 2J-3 .

[0016] Figure 2J-6 shows an enlarged cross-sectional view of the Figure 2J-4 region R shown in 2J-4 .

[0017] Figure 2K-5 shows an enlarged cross-sectional view of the Figure 2K-3 region R shown in 2K-3 .

[0018] Figure 2K-6 shows an enlarged cross-sectional view of the Figure 2K-4 region R shown in 2K-4 .

[0019] Figure 2L-5 shows an enlarged cross-sectional view of the Figure 2L-3 region R shown in 2L-3 .

[0020] Figure 2L-6 shows an enlarged cross-sectional view of the Figure 2L-4 region R shown in 2L-4 .

[0021] Figure 2M-5 shows an enlarged cross-sectional view of the Figure 2M-3 region R shown in 2M-3 .

[0022] Figure 2M-6 shows an enlarged cross-sectional view of the Figure 2M-4 region R shown in 2M-4 .

[0023] Figure 2M-7shows a magnified cross-sectional view of the region R shown in Figure 2M-3 in accordance with various embodiments. 2M-3W

[0024] Figure 2M-8 shows a magnified cross-sectional view of the region R shown in Figure 2M-4 in accordance with various embodiments. 2M-4W

[0025] Figure 3A , Figure 3B , Figure 3C and Figure 3D shows a cross-sectional view of a semiconductor structure in accordance with some embodiments.

[0026] Figure 3E shows a magnified cross-sectional view of the region R shown in Figure 3C in accordance with various embodiments. 3C DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0028] Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that additional operations may be provided before, during, and after the method, and that for other embodiments of the method, some of the operations described may be replaced or eliminated.

[0029] The nanostructure transistors described below (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon FETs, and all-around gate (GAA) transistors) can be patterned by any suitable method. For example, the structure can be patterned using one or more lithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines lithography and self-alignment processes, thereby allowing the generation of patterns with, for example, a spacing that is less than that obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure.

[0030] Embodiments of semiconductor structures and methods for forming the same are provided. The semiconductor structure may include a channel structure, a gate structure encapsulating the channel structure, and a source / drain structure attached to the channel structure. In addition, an air gap is formed in the semiconductor structure to electrically and physically isolate the gate structure from the source / drain structure. Because the dielectric constant (k) value of the air gap is low, the capacitance of the resulting device may be reduced. In addition, the air gap may also be formed below the source / drain structure, thereby also preventing current from leaking from the bottom portion of the device.

[0031] Figures 1A to 1C A schematic perspective view of an intermediate stage in the fabrication of a semiconductor structure 100 is shown in accordance with some embodiments. Figures 2A-1 to 2M-1 , Figures 2A-2 to 2M-2 , Figures 2A-3 to 2M-3 and Figures 2A-4 to 2M-4 According to some embodiments, Figure 1C Line Y SD -Y SD '(i.e., in the Y direction), Y MG -Y MG '(i.e., in the Y direction), X 1 -X 1 ' (i.e., in the X direction) and X 2 -X 2 ' (ie, in the X direction) is a cross-sectional view of an intermediate stage of manufacturing the semiconductor structure 100. More specifically, Figure 2A-1 , Figure 2A-2 , Figure 2A-3 and Figure 2A-4 Shows Figure 1C , and Figures 2B-1 to 2M-1 , Figures 2B-2 to 2M-2 , Figures 2B-3 to 2M-3 and Figures 2B-4 to 2M-4 A cross-sectional view is shown of an intermediate stage in subsequent fabrication of a semiconductor structure 100 , in accordance with some embodiments.

[0032] The semiconductor structure 100 may include a multi-gate device and may be included in a microprocessor, a memory, or other IC devices. For example, the semiconductor structure 100 may be part of an IC chip that includes various passive and / or active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof.

[0033] According to some embodiments, a substrate 102 including a first region 10 and a second region 20 is formed, and a semiconductor stack including a first semiconductor material layer 106 and a second semiconductor material layer 108 is formed over the first region 10 and the second region 20 of the substrate 102, as Figure 1A shown. The first region 10 and the second region 20 may be formed adjacent to each other, or there may be other device regions formed therebetween. In some embodiments, a P-type transistor is formed in the first region 10 and an N-type transistor is formed in the second region 20. To better understand the semiconductor structure 100, an X-Y-Z coordinate reference is provided in the drawings of the embodiments of the present disclosure. The X-axis and the Y-axis are generally oriented in a lateral (or horizontal) direction parallel to the major surface of the substrate 102. The Y-axis is lateral (e.g., substantially perpendicular) to the X-axis. The Z-axis is generally oriented in a vertical direction perpendicular to the major surface of the substrate 102 (or the X-Y plane).

[0034] The substrate 102 may be a semiconductor wafer, such as a silicon wafer. Optionally or additionally, the substrate 102 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polysilicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0035] In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are alternately stacked over the substrate 102 to form a semiconductor stack. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layer 106 is made of SiGe, and the second semiconductor material layer 108 is made of silicon. In some embodiments, the Ge concentration in the first semiconductor material layer 106 is in the range from about 35 atm% to about 50 atm%.

[0036] It should be noted that although three first semiconductor material layers 106 and three second semiconductor material layers 108 are shown in Figure 1A , the semiconductor stack may include fewer or more alternately stacked first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor stack may include two to five of the first semiconductor material layer 106 and two to five of the second semiconductor material layer 108.

[0037] The first semiconductor material layer 106 and the second semiconductor material layer 108 may be formed by using low-pressure chemical vapor deposition (LPCVD), an epitaxial growth process, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0038] According to some embodiments, after the first semiconductor material layer 106 and the second semiconductor material layer 108 are formed as a semiconductor stack over the substrate 102, the semiconductor stack is patterned to form fin structures 104-1 in a first region 10 and fin structures 104-2 in a second region 20, as shown in Figure 1B . The fin structures 104-1 and 104-2 may extend longitudinally in the X direction. In some embodiments, the patterning process includes: forming a mask structure 110 over the semiconductor material stack; and etching the semiconductor material stack and the underlying substrate 102 through the mask structure 110. In some embodiments, the mask structure 110 is a multi-layer structure including a pad oxide layer and a nitride layer formed over the pad oxide layer. The pad oxide layer may be made of silicon oxide, which is formed by thermal oxidation or CVD, and the nitride layer may be made of silicon nitride, which is formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD). In some embodiments, the fin structures 104-1 and 104-2 include a base fin structure 104B and a semiconductor stack formed over the base fin structure 104B, including the first semiconductor material layer 106 and the second semiconductor material layer 108.

[0039] According to some embodiments, after forming fin structures 104-1 and 104-2, an isolation structure 116 is formed around the fin structures 104-1 and 104-2, as Figure 1C , Figure 2A-1 , Figure 2A-2 , Figure 2A-3 and Figure 2A-4 shown. According to some embodiments, the isolation structure 116 is configured to electrically isolate the active regions of the semiconductor structure (e.g., fin structures 104-1 and 104-2), and is also referred to as a shallow trench isolation (STI) component.

[0040] More specifically, an insulating layer covering the fin structures 104-1 and 104-2 can be formed around the fin structures 104-1 and 104-2, and the insulating layer can be recessed to form the isolation structure 116, wherein the fin structures 104-1 and 104-2 protrude from the top surface of the isolation structure 116. In some embodiments, the insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. Additionally, a liner layer (not shown) can be formed before forming the insulating layer, and the liner layer can also be recessed together with the insulating layer to form the isolation structure 116. In some embodiments, the liner layer includes a plurality of dielectric material layers.

[0041] After that, according to some embodiments, a dummy gate structure 130 is formed across the fin structures 104-1 and 104-2, as Figure 2B-1 , Figure 2B-2 , Figure 2B-3 , Figure 2B-4 shown. The dummy gate structure 130 can be used to define the channel regions of the resulting semiconductor structure 100.

[0042] In some embodiments, the dummy gate structure 130 includes a dummy gate dielectric layer 132 and a dummy gate electrode layer 134. In some embodiments, the dummy gate dielectric layer 132 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO 2 , HfZrO, HfSiO, HfTiO, HfAlO, or a combination thereof. In some embodiments, the dummy gate dielectric layer 132 is formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0043] In some embodiments, the dummy gate electrode layer 134 is made of a conductive material including polysilicon (poly-Si), poly-silicon germanium (poly-SiGe), or a combination thereof. In some embodiments, the dummy gate electrode layer 134 is formed using CVD, PVD, or a combination thereof.

[0044] In some embodiments, a hard mask layer 137 is formed over the dummy gate electrode layer 134. In some embodiments, the hard mask layer 137 includes multiple layers, such as an oxide layer 135 and a nitride layer 136. In some embodiments, the oxide layer 135 is made of silicon oxide, and the nitride layer 136 is made of silicon nitride.

[0045] The formation of the dummy gate structure 130 may include conformally forming a dielectric material as the dummy gate dielectric layer 132. Thereafter, a conductive material may be formed over the dielectric material as the dummy gate electrode layer 134, and the hard mask layer 137 may be formed over the conductive material. Next, the dielectric material and the conductive material may be patterned through the hard mask layer 137 to form the dummy gate structure 130.

[0046] According to some embodiments, after forming the dummy gate structure 130, a spacer layer 138 is formed to cover the top surface and sidewalls of the dummy gate structure 130 and the fin structures 104-1 and 104-2, as Figure 2C-1 、 Figure 2C-2 、 Figure 2C-3 and Figure 2C-4 shown. In some embodiments, the spacer layer 138 is made of one or more dielectric materials. The dielectric material may include silicon oxide (SiO 2 ), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof.

[0047] According to some embodiments, after forming the spacer layer 138, an etching process is performed to form gate spacers 140 and fin spacers 142 with the spacer layer 138, and to form source / drain grooves 144 in the fin structures 104-1 and 104-2, as Figure 2D-1 、 Figure 2D-2 、 Figure 2D-3 and Figure 2D-4 shown. The gate spacers 140 may be configured to separate the source / drain structures (to be formed later) from the dummy gate structure 130, and the fin spacers 142 may be configured to limit the growth of the source / drain structures formed therein.

[0048] More specifically, according to some embodiments, the spacer layer 138 is etched to form gate spacers 140 on opposite sidewalls of the pseudo-gate structure 130 and fin spacers 142 that cover the sidewalls of the fin structures 104-1 and 104-2. Additionally, according to some embodiments, during the etching process, portions of the fin structures 104-1 and 104-2 that are not covered by the pseudo-gate structure 130 and the gate spacers 140 are etched to form source / drain trenches 144. The etching process can be an anisotropic etching process, such as dry plasma etching, and the pseudo-gate structure 130 and the gate spacers 140 can be used as etching masks during the etching process. In some embodiments, the isolation structure 116 is also slightly etched during the etching process.

[0049] According to some embodiments, after forming the source / drain trenches 144, the first semiconductor material layer 106 exposed by the source / drain trenches 144 is laterally recessed to form notches 146, and the resulting structure is shown in Figure 2E-1 , Figure 2E-2 , Figure 2E-3 and Figure 2E-4 . In some embodiments, an etching process is performed to laterally recess the first semiconductor material layer 106 of the fin structures 104-1 and 104-2 from the source / drain trenches 144. In some embodiments, during the etching process, the first semiconductor material layer 106 has a higher etching rate (or etching amount) than the second semiconductor material layer 108, thereby forming notches 146 between adjacent second semiconductor material layers 108.

[0050] In some embodiments, according to some embodiments, the second semiconductor material layer 108 is also slightly etched during the etching process such that the second semiconductor material layer 108 has a thinned portion 108T exposed by the notches 146. In some embodiments, the etching process is an isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, or a combination thereof. In some embodiments, the thinned portion 108T of the topmost one of the second semiconductor material layers 108 is thicker than the other thinned portions 108T of the second semiconductor material layer 108 (i.e., in the Z direction). In some embodiments, the portion of the base fin structure 104B exposed by the source / drain trenches 144 has a stepped shape ST, as shown in Figure 2E-3 and Figure 2E-4 .

[0051] Next, according to some embodiments, a sacrificial inner spacer 148 is formed in the notches 146 between the second semiconductor material layers 108, and a bottom sacrificial layer 149 that extends to the bottom portion of the source / drain trenches 144 is formed in the bottommost one of the notches 146, and the resulting structure is shown in Figure 2F-1 , Figure 2F-2 ,Figure 2F-3 and Figure 2F-4 as shown in Figure 2F-4 . The sacrificial internal spacer 148 is configured to create a space for separating the source / drain structure and the gate structure to be formed in subsequent manufacturing processes. In addition, the bottom sacrificial layer 149 is configured to create a space for separating the source / drain structure and the substrate fin structure 104B.

[0052] As previously described, according to some embodiments, since the second semiconductor material layer 108 is also partially etched when the notch 146 is formed, the sacrificial internal spacer 148 formed in the notch 146 is thicker than the thickness of the first semiconductor material layer 106. The shapes of the sacrificial internal spacer 148 and the bottom sacrificial layer 149 can be adjusted according to their applications.

[0053] Figure 2F-5 An enlarged cross-sectional view of the region R shown in Figure 2F-3 and Figure 2F-4 as shown in Figure 2F-4 according to various possible embodiments is shown. That is, at this stage, the sacrificial internal spacers 148 in the first region 10 and the second region 20 can have substantially the same shape. More specifically, 2F the sacrificial internal spacer 148a having a convex surface extending between the second semiconductor material layers 108 is shown in (a) according to some embodiments. Figure 2F-5 (a) shows a sacrificial internal spacer 148a having a convex surface extending between the second semiconductor material layers 108 according to some embodiments. Figure 2F-5 (b) shows a sacrificial internal spacer 148b having a substantially vertical surface extending between the second semiconductor material layers 108 according to some embodiments. Figure 2F-5 (c) shows a sacrificial internal spacer 148c having a concave surface extending between the second semiconductor material layers 108 according to some embodiments.

[0054] In some embodiments, the width W of the sacrificial internal spacer 148 (e.g., the sacrificial internal spacers 148a, 148b, and 148c) 148 is in the range of about 3 nm to about 8 nm. As previously described, the sacrificial internal spacer 148 is configured to create a space for separating the source / drain structure and the gate structure to be formed later. Therefore, the sacrificial internal spacer 148 should be wide enough to separate the elements, but should not be too wide, otherwise the space for forming the gate structure may be reduced.

[0055] In addition, according to some embodiments, the second semiconductor material layer 108 has a thinned portion 108T at the edge region, and the thinned portion 108T vertically overlaps with the sacrificial internal spacer 148, as Figure 2F-5 shown in Figure 2F-5 . In addition, according to some embodiments, the thinned portion 108T has a rounded corner.

[0056] Figure 2F-6 An enlarged cross-sectional view of the region R shown inFigure 2F-3 and Figure 2F-4 the enlarged cross-sectional view of the region R shown in 2F-B More specifically, Figure 2F-6 (a) shows a bottom sacrificial layer 149a having a convex top surface according to some embodiments. Figure 2F-6 (b) shows a bottom sacrificial layer 149b having a substantially flat surface according to some embodiments. Figure 2F-6 (c) shows a bottom sacrificial layer 149c having a concave top surface according to some embodiments.

[0057] In some embodiments, the topmost vertex of the top surface of the bottom sacrificial layer 149 in the source / drain region (i.e., exposed by the source / drain recess 144) is lower than the bottom surface of the bottommost one in the second semiconductor material layer 108, so that the connection between the second semiconductor material layer 108 and the subsequently formed source / drain structure will not be damaged due to the formation of the bottom sacrificial layer.

[0058] In some embodiments, the topmost vertex of the top surface of the bottom sacrificial layer 149 in the source / drain region (i.e., exposed by the source / drain recess 144) is higher than the top surface of the base fin structure 104B, so that the bottom portion of the subsequently formed source / drain structure will be separated from the base fin structure 104B, and thus current leakage from the bottom portion of the device can be prevented. In some embodiments, the height difference H between the topmost vertex of the top surface of the bottom sacrificial layer 149 in the source / drain region and the top surface of the base fin structure 104B (i.e., the bottom surface of the bottommost one in the first semiconductor material layer 106) 149 is in the range of from about 3 nm to about 5 nm in the Z direction.

[0059] The sacrificial inner spacers 148 (e.g., sacrificial inner spacers 148a, 148b, and 148c) and the bottom sacrificial layer 149 (e.g., bottom sacrificial layers 149a, 149b, and 149c) can be made of the same material. In some embodiments, both the sacrificial inner spacers 148 and the bottom sacrificial layer 149 are made of a semiconductor material, such as SiGe. In some embodiments, the Ge in the semiconductor material used to form the sacrificial inner spacers 148 and the bottom sacrificial layer 149 is in the range of about 15 atm% to about 25 atm%. In some embodiments, the first semiconductor material layer 106, the sacrificial inner spacers 148, and the bottom sacrificial layer 149 are all made of SiGe, but the Ge concentration in the first semiconductor material layer 106 is greater than the Ge concentration in the sacrificial inner spacers 148 and the bottom sacrificial layer 149, so that they can have an etching selectivity during subsequent etching processes.

[0060] In some embodiments, the sacrificial inner spacer 148 and the bottom sacrificial layer 149 are formed using an epitaxial growth process, such as MBE, MOCVD, VPE, other suitable epitaxial growth processes, or combinations thereof. More specifically, the SiGe material can be grown from the sidewalls of the first semiconductor material layer 106 and the top surface of the substrate fin structure 104B exposed by the source / drain recess 144.

[0061] In addition, although both the second semiconductor material layer 108 and the substrate fin structure 104B can be made of Si, they can have different surface structures exposed by the source / drain recess 144. In some embodiments, the surface S of the substrate fin structure 104B exposed by the source / drain recess 144 1 (i.e., the bottom portion of the source / drain recess 144) has a Si(100) surface, and the sidewall S of the second semiconductor material layer 108 2 has a Si(110) surface. Thus, the SiG material can be mainly grown on the sidewalls of the first semiconductor material layer 106 and in the bottom portion of the source / drain recess 144 above the surface S of the substrate fin structure 104B, but not on the sidewall S of the second semiconductor material layer 108 1 . 2

[0062] According to some embodiments, after forming the sacrificial inner spacer 148 and the bottom sacrificial layer 149, a recessing process is performed on the first region 10, as shown in Figure 2G-1 , Figure 2G-2 , Figure 2G-3 and Figure 2G-4 . More specifically, the thinned portion 108T of the second semiconductor material layer 108 in the first region 10 is laterally recessed (i.e., recessed in the X direction) so that dopants in the subsequently formed source / drain structure can diffuse into the second semiconductor material layer 108 in the first region 10, and the performance of the resulting device (e.g., PFET) can be improved. In some embodiments, according to some embodiments, the sacrificial inner spacer 148 and the gate spacer 140 become protruding from the sidewalls of the second semiconductor material layer 108. During the recessing process, the structures in the second region 20 can be protected by a mask structure, and the mask structure can be removed after performing the recessing process.

[0063] Figure 2G-5 , Figure 2G-6 and Figure 2G-7 show enlarged cross-sectional views of the region R shown in Figure 2G-3 according to various embodiments. More specifically, 2G-3 Figure 2G-5 (a) shows the second semiconductor material layer 108 having a recessed sidewall surface vertically overlapping with the sacrificial inner spacer 148a according to some embodiments.Figure 2G-5 (b) shows a second semiconductor material layer 108 having a concave sidewall surface that vertically overlaps with a sacrificial internal spacer 148b, according to some embodiments. Figure 2G-5 (c) shows a second semiconductor material layer 108 having a concave sidewall surface that vertically overlaps with a sacrificial internal spacer 148c, according to some embodiments. Figure 2G-6 (a) shows a second semiconductor material layer 108 having a substantially vertical sidewall surface that vertically overlaps with a sacrificial internal spacer 148a, according to some embodiments. Figure 2G-6 (b) shows a second semiconductor material layer 108 having a substantially vertical sidewall surface that vertically overlaps with a sacrificial internal spacer 148b, according to some embodiments. Figure 2G-6 (c) shows a second semiconductor material layer 108 having a substantially vertical sidewall surface that vertically overlaps with a sacrificial internal spacer 148c, according to some embodiments. Figure 2G-7 (a) shows a second semiconductor material layer 108 having a convex sidewall surface that vertically overlaps with a sacrificial internal spacer 148a, according to some embodiments. Figure 2G-7 (b) shows a second semiconductor material layer 108 having a convex sidewall surface that vertically overlaps with a sacrificial internal spacer 148b, according to some embodiments. Figure 2G-7 (c) shows a second semiconductor material layer 108 having a convex sidewall surface that vertically overlaps with a sacrificial internal spacer 148c, according to some embodiments.

[0064] In some embodiments, the second semiconductor material layer 108 is laterally recessed by a distance D in the range of about 2 nm to about 6 nm. 1 . The recess distance D 1 should be large enough for dopant diffusion, but should not be too large, otherwise the risk of current leakage may increase. In some embodiments, the second semiconductor material layer 108 protrudes from the inner sidewall of the gate spacer 140 by a distance D in the range of about 3 nm to about 5 nm. 2 In some embodiments, the distance D 1 is greater than the distance D 2 , as shown in Figure 2G-5 . In some embodiments, the distance D 1 is substantially equal to the distance D 2 , as shown in Figure 2G-6 . In some embodiments, the distance D 1 is less than the distance D 2 , as shown in Figure 2G-7 .

[0065] According to some embodiments, after performing a recess process, source / drain structures 150-1 and 150-2 are formed in the source / drain trenches 144 in the first region 10 and the second region 20, respectively, as Figure 2H-1 , Figure 2H-2 , Figure 2H-3 and Figure 2H-4 shown. The source / drain structures described herein may refer to the source or the drain, individually or jointly depending on the context.

[0066] In some embodiments, the source / drain structures 150-1 and 150-2 are formed using an epitaxial growth process that may be implemented separately, such as MBE, MOCVD, VPE, other suitable epitaxial growth processes, or combinations thereof. In some embodiments, the source / drain structures 150-1 and 150-2 are made of any suitable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or combinations thereof. In some embodiments, the source / drain structures 150-1 and 150-2 are in-situ doped during the epitaxial growth process. In some embodiments, the source / drain structures 150-1 and 150-2 are doped in one or more implantation processes after the epitaxial growth process.

[0067] In some embodiments, the source / drain structures 150-1 and 150-2 are made of materials having different conductive types. Figure 2H-5 An enlarged cross-sectional view of the region R shown in Figure 2H-3 is shown according to various embodiments. More specifically, 2H-3 (a) shows a source / drain structure 150-1a formed adjacent to the sacrificial inner spacer 148a according to some embodiments. Figure 2H-5 (b) shows a source / drain structure 150-1b formed adjacent to the sacrificial inner spacer 148b according to some embodiments. Figure 2H-5 (c) shows a source / drain structure 150-1c formed adjacent to the sacrificial inner spacer 148c according to some embodiments. It should be noted that although the bottom sacrificial layer 149c is shown in Figure 2H-5 , it may be replaced by other types of bottom sacrificial layers, such as the bottom sacrificial layers 149a or 149b shown in Figure 2H-5 . Figure 2F-6

[0068] In some embodiments, the source / drain structure 150-1 includes a first source / drain layer 151, a second source / drain layer 152 formed over the first source / drain layer 151, and a third source / drain layer 153 formed over the second source / drain layer 152. In some embodiments, the source / drain structure 150-1 is a source / drain structure for a PMOS transistor, the Ge concentration in the third source / drain layer 153 is greater than the Ge concentration in the second source / drain layer 152, and the Ge concentration in the second source / drain layer 152 is greater than the Ge concentration in the first source / drain layer 151. In some embodiments, the first source / drain layer 151 is made of SiB. In some embodiments, the second source / drain layer 152 is made of SiGeB, and the Ge concentration in the second source / drain layer 152 is greater than 0 but less than about 25%. In some embodiments, the third source / drain layer 153 is made of SiGeB, and the Ge concentration in the third source / drain layer 153 is greater than 25%.

[0069] In some embodiments, the first source / drain layer 151 is in contact with the sidewalls of the second semiconductor material layer 108, the sacrificial inner spacers 148 (e.g., 148a, 148b, or 148c), and the bottom sacrificial layer 149 (e.g., 149a, 149b, or 149c). Additionally, according to some embodiments, since the second semiconductor material layer 108 is laterally recessed before forming the source / drain structure 150-1, the first source / drain layer 151 extends laterally over the sacrificial inner spacers 148. Due to the difference in growth rates of epitaxial materials formed on different materials, the thickness of the first source / drain 151 is different at different regions. Thus, according to some embodiments, the first source / drain layer 151 has a wavy sidewall surface, where the thicker portion is adjacent to the second semiconductor material layer 108 and the thinner portion is adjacent to the sacrificial inner spacers 148.

[0070] In some embodiments, the first source / drain layer 151 includes extensions vertically sandwiched (i.e., in the Z direction) between the gate spacer 140 and the topmost one of the second semiconductor material layers 108, between two vertically adjacent second semiconductor material layers 108, and between the bottommost one of the second semiconductor material layers 108 and the bottom sacrificial layer 149. Although Figure 2H-5 the second semiconductor material layers 108 shown Figure 2G-6 and Figure 2G-7The structure shown in. In some embodiments, the first source / drain layer 151 and the second semiconductor material layer 108 have a curved interface. In some other embodiments, the first source / drain layer 151 and the second semiconductor material layer 108 have a substantially vertical interface. In some embodiments, the first source / drain layer 151 has a curved (convex) bottom surface. In some other embodiments, the first source / drain layer 151 has a substantially flat or concave bottom surface. In some embodiments, the second source / drain layer 152 is formed above the first source / drain layer 151.

[0071] As Figure 2H-5 shown, the source / drain structure 150-1 has a width W measured in the X direction from the middle portion (in the Z direction) of the topmost one in the second semiconductor material layer 108 150-1W and a width W measured in the X direction from the middle portion (in the Z direction) of the topmost one in the first semiconductor material layer 106 (or the topmost one in the sacrificial inner spacer 148). 150-1N . In some embodiments, the width W 150-1W is greater than the width W 150-1N .

[0072] Figure 2H-6 shows, according to various embodiments, Figure 2H-4 the region R shown in 2H-4 in an enlarged cross-sectional view. More specifically, according to some embodiments, Figure 2H-6 (a) shows the source / drain structure 150-2a formed adjacent to the sacrificial inner spacer 148a. Figure 2H-6 (b) shows the source / drain structure 150-2b formed adjacent to the sacrificial inner spacer 148b according to some embodiments. Figure 2H-6 (c) shows the source / drain structure 150-2c formed adjacent to the sacrificial inner spacer 148c according to some embodiments. It should be noted that although the bottom sacrificial layer 149c is shown in Figure 2H-6 , it can be replaced by other types of bottom sacrificial layers, such as Figure 2F-6 the bottom sacrificial layer 149a or 149b shown in

[0073] In some embodiments, the source / drain structure 150-2 includes a first source / drain layer 154 and a second source / drain layer 155. In some embodiments, the P concentration in the second source / drain layer 155 is greater than the P concentration in the first source / drain layer 154. In some embodiments, the first source / drain layer 154 is made of SiAs or SiP. In some embodiments, the second source / drain layer 155 is made of SiP.

[0074] In some embodiments, the first source / drain layer 154 is in sidewall contact with the second semiconductor material layer 108, the sacrificial inner spacers 148 (e.g., 148a, 148b, or 148c), and the bottom sacrificial layer 149 (e.g., 149a, 149b, or 149c). Although Figure 2H-6 the second semiconductor material layer 108 shown in Figure 2G-6 has concave sidewall surfaces, they may have the structures shown in Figure 2G-7 . In some embodiments, the first source / drain layer 154 and the second semiconductor material layer 108 have a curved interface. In some other embodiments, the first source / drain layer 154 and the second semiconductor material layer 108 have a substantially vertical interface. In some embodiments, the first source / drain layer 154 has a curved (convex) bottom surface. In some other embodiments, the first source / drain layer 154 has a substantially flat or concave bottom surface. In some embodiments, the second source / drain layer 155 is formed above the first source / drain layer 154.

[0075] As shown in Figure 2H-6 , the source / drain structure 150-2 has a width W measured in the X direction from the middle portion (in the Z direction) of the topmost one in the second semiconductor material layer 108 150-2W and a width W measured in the X direction from the middle portion (in the Z direction) of the topmost one in the first semiconductor material layer 106 (or the topmost one in the sacrificial inner spacers 148). 150-2N In some embodiments, the width W of the source / drain structure 150-1 150-1W is greater than the width W of the source / drain structure 150-2 150-2N . In some embodiments, the width W of the source / drain structure 150-1 150-1N is substantially equal to the width W of the source / drain structure 150-2 150-2N .

[0076] According to some embodiments, after forming the source / drain structures 150-1 and 150-2, a conformal contact etch stop layer (CESL) 160 is formed to cover the source / drain structures 150-1 and 150-2, and an interlayer dielectric (ILD) layer 162 is formed above the contact etch stop layer 160, as shown in Figure 2I-1 , Figure 2I-2 , Figure 2I-3 and Figure 2I-4 .

[0077] In some embodiments, the contact etch stop layer 160 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the contact etch stop layer 160 can be conformally deposited over the semiconductor structure by implementing CVD, ALD, other applicable methods, or a combination thereof.

[0078] The interlayer dielectric layer 162 can include multiple layers made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or other applicable low-k dielectric materials. The interlayer dielectric layer 162 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes. According to some embodiments, after depositing the contact etch stop layer 160 and the interlayer dielectric layer 162, a planarization process, such as CMP or etch-back process, is implemented until the dummy gate electrode layer 134 is exposed.

[0079] Next, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form a gate trench 166, as Figure 2J-1 、 Figure 2J-2 、 Figure 2J-3 and Figure 2J-4 shown. More specifically, according to some embodiments, the dummy gate structure 130 and the first semiconductor material layer 106 are removed to form channel structures (e.g., nanostructures) 108'-1 and 108'-2 with the second semiconductor material layer 108 of the fin structures 104-1 and 104-2, respectively. As Figure 2J-3 and Figure 2J-4 shown, according to some embodiments, the channel structures 108'-1 and 108'-2 are vertically suspended above the substrate 102 and spaced apart from each other in the Z direction. In addition, according to some embodiments, the channel structures 108'-1 and 108'-2 laterally extend between the source / drain structures 150-1 and 150-2 in the X direction and are interposed between the source / drain structures 150-1 and 150-2.

[0080] The removal process can include one or more etching processes. For example, when the dummy gate electrode layer 134 can be made of polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode layer 134. After that, the dummy gate dielectric layer 132 can be removed using plasma dry etching, dry chemical etching, and / or wet etching. The first semiconductor material layer 106 can be removed by implementing a selective wet etching process, such as an APM (e.g., ammonium hydroxide - hydrogen peroxide - water mixture) etching process. For example, the wet etching process uses, such as ammonium hydroxide (NH 4etchants such as H2SO4, H2O2, TMAH, ethylenediamine pyrocatechol (EDP), and / or potassium hydroxide (KOH) solution.

[0081] As previously described, although the first semiconductor material layer 106, the sacrificial inner spacer 148, and the bottom sacrificial layer 149 are all made of SiGe, the Ge concentration in the first semiconductor material layer 106 can be higher than that in the sacrificial inner spacer 148 and the bottom sacrificial layer 149. Therefore, during the etching process for removing the first semiconductor material layer 106, the first semiconductor material layer 106, the sacrificial inner spacer 148, and the bottom sacrificial layer 149 can have good etching selectivity. In some embodiments, during the etching process for removing the first semiconductor material layer 106, the sidewalls of the sacrificial inner spacer 148 and the bottom sacrificial layer 149 are slightly removed.

[0082] Figure 2J-5 Shows according to various embodiments Figure 2J-3 the region R shown in 2J-3 magnified cross-sectional view. More specifically, Figure 2J-5 (a-1) shows a sacrificial inner spacer 148a-1 having a concave inner sidewall in the first region 10 according to some embodiments. Figure 2J-5 (a-2) shows a sacrificial inner spacer 148a-2 having a substantially vertical inner sidewall in the first region 10 according to some embodiments. Figure 2J-5 (b-1) shows a sacrificial inner spacer 148b-1 having a concave inner sidewall in the first region 10 according to some embodiments. Figure 2J-5 (b-2) shows a sacrificial inner spacer 148b-2 having a substantially vertical inner sidewall in the first region 10 according to some embodiments. Figure 2J-5 (c-1) shows a sacrificial inner spacer 148c-1 having a concave inner sidewall in the first region 10 according to some embodiments. Figure 2J-5 (c-2) shows a sacrificial inner spacer 148c-2 having a substantially vertical inner sidewall in the first region 10 according to some embodiments.

[0083] Figure 2J-6 Shows according to various embodiments Figure 2J-4 the region R shown in 2J-4 magnified cross-sectional view. More specifically, Figure 2J-6 (a-1) shows a sacrificial inner spacer 148a-1 having a concave inner sidewall in the second region 20 according to some embodiments. Figure 2J-6 (a-2) shows a sacrificial inner spacer 148a-2 having a substantially vertical inner sidewall in the second region 20 according to some embodiments. Figure 2J-6(b-1) shows a sacrificial internal spacer 148b-1 with a concave inner sidewall in the second region 20 according to some embodiments. Figure 2J-6 (b-2) shows a sacrificial internal spacer 148b-2 with a substantially vertical inner sidewall in the second region 20 according to some embodiments. Figure 2J-6 (c-1) shows a sacrificial internal spacer 148c-1 with a concave inner sidewall in the second region 20 according to some embodiments. Figure 2J-6 (c-2) shows a sacrificial internal spacer 148c-2 with a substantially vertical inner sidewall in the second region 20 according to some embodiments.

[0084] According to some embodiments, after forming the gate trench 166, a porous layer 170 is formed over the inner sidewalls of the sacrificial internal spacers 148 in the first region 10 and the second region 20, as Figure 2K-1 、 Figure 2K-2 、 Figure 2K-3 and Figure 2K-4 shown. The porous layer 170 is configured to ensure a spacing between the gate structure and the source / drain structures 150-1 and 150-2.

[0085] In some embodiments, the porous layer 170 is made of SiO 2 . In some embodiments, the porous layer 170 has a thickness in the range from about 0.5 nm to about 2 nm measured in the X direction. The porous layer 170 should be thick enough, or they can be removed during an etching process implemented later. On the other hand, the porous layer 170 should not be too thick, otherwise the sacrificial internal spacers 148 and the bottom sacrificial layer 149 may not be completely removed (details will be described later). In some embodiments, the porous layer 170 is formed by implementing a wet process. In some embodiments, the wet process includes: spraying a reaction liquid onto the sidewall surfaces of the sacrificial internal spacers 148 and the bottom sacrificial layer 149 exposed by the gate trench 166 to form the porous layer 170; and removing the reaction liquid after forming the porous layer 170. In some embodiments, the porous layer 170 has a curved profile in a cross-sectional view.

[0086] Figure 2K-5 shows an enlarged cross-sectional view of the region R Figure 2K-3 shown in 2K-3 according to various embodiments. More specifically, Figure 2K-5 (a-1) shows a porous layer 170a-1 formed on the concave inner sidewall of a sacrificial internal spacer 148a-1 formed in the first region 10 according to some embodiments. Figure 2K-5 (a-2) shows a porous layer 170a-2 formed on the substantially vertical inner sidewall of a sacrificial internal spacer 148a-2 formed in the first region 10 according to some embodiments. Figure 2K-5(b-1) shows a porous layer 170b-1 formed on the concave inner sidewall of a sacrificial inner spacer 148b-1 in a first region 10 according to some embodiments. Figure 2K-5 (b-2) shows a porous layer 170b-2 formed on the substantially vertical inner sidewall of a sacrificial inner spacer 148b-2 in a first region 10 according to some embodiments. Figure 2K-5 (c-1) shows a porous layer 170c-1 formed on the concave inner sidewall of a sacrificial inner spacer 148c-1 in a first region 10 according to some embodiments. Figure 2K-5 (c-2) shows a porous layer 170c-2 formed on the substantially vertical inner sidewall of a sacrificial inner spacer 148c-2 in a first region 10 according to some embodiments.

[0087] Figure 2K-6 shows according to various embodiments Figure 2K-4 the region R shown in 2K-4 a magnified cross-sectional view. More specifically, Figure 2K-6 (a-1) shows a porous layer 170a-1 formed on the concave inner sidewall of a sacrificial inner spacer 148a-1 in a second region 20 according to some embodiments. Figure 2K-6 (a-2) shows a porous layer 170a-2 formed on the substantially vertical inner sidewall of a sacrificial inner spacer 148a-2 in a second region 20 according to some embodiments. Figure 2K-6 (b-1) shows a porous layer 170b-1 formed on the concave inner sidewall of a sacrificial inner spacer 148b-1 in a second region 20 according to some embodiments. Figure 2K-6 (b-2) shows a porous layer 170b-2 formed on the substantially vertical inner sidewall of a sacrificial inner spacer 148b-2 in a second region 20 according to some embodiments. Figure 2K-6 (c-1) shows a porous layer 170c-1 formed on the concave inner sidewall of a sacrificial inner spacer 148c-1 in a second region 20 according to some embodiments. Figure 2K-6 (c-2) shows a porous layer 170c-2 formed on the substantially vertical inner sidewall of a sacrificial inner spacer 148c-2 in a second region 20 according to some embodiments.

[0088] According to some embodiments, after forming the porous layer 170, an etching process is performed from the gate trench 166 to remove the sacrificial inner spacer 148 and the bottom sacrificial layer 149, as Figure 2L-1 、 Figure 2L-2 、 Figure 2L-3 and Figure 2L-4As shown. More specifically, according to some embodiments, during the etching process, the etchant penetrates the holes in the porous layer 170 and reaches the sacrificial inner spacer 148 and the bottom sacrificial layer 149. Then, according to some embodiments, the sacrificial inner spacer 148 and the bottom sacrificial layer 149 are etched by the etchant and removed by the etchant, thereby forming air gaps 172-1 and 172-2 and bottom air gaps 174-1 and 174-2 in the first region 10 and the second region 20, respectively.

[0089] In some embodiments, the etching process is a dry etching process. In some embodiments, the etchant used in the etching process includes fluorine radicals, hydrogen radicals, etc. As previously described, the source / drain structure 150-1 includes a first source / drain layer 151 that can be made of SiB, and the first source / drain layer 151 can be used as a protective layer for the source / drain structure 150-1, so that the second source / drain layer 152 (which can be made of SiGeB) is not damaged during the etching process.

[0090] In some embodiments, the air gaps 172-1 and 172-2 are formed by removing the sacrificial inner spacer 148, and the bottom air gaps 174-1 and 174-2 are formed by removing the bottom sacrificial layer 149. Therefore, according to some embodiments, the air gap 172-1 is laterally sandwiched (i.e., in the X direction) between the porous layer 170 and the first source / drain layer 151 in the first region 10, and the air gap 172-2 is laterally sandwiched (i.e., in the X direction) between the porous layer 170 and the first source / drain layer 154 in the second region 20. In addition, according to some embodiments, the bottom air gaps 174-1 and 174-2 are vertically sandwiched (i.e., in the Z direction) between the substrate fin structure 104B and the source / drain structures 150-1 and 150-2. In addition, according to some embodiments, the bottom air gaps 174-1 and 174-2 are laterally sandwiched (i.e., in the X direction) between two porous layers 170.

[0091] Figure 2L-5 Shows according to various embodiments Figure 2L-3 The region R shown in 2L-3 An enlarged cross-sectional view. More specifically, according to some embodiments, Figure 2L-5 (a-1) shows an air gap 172-1a1 that exposes the porous layer 170a-1 and has substantially the same shape as the sacrificial inner spacer 148a-1 in the first region 10. Figure 2L-5 (a-2) shows an air gap 172-1a2 that exposes the porous layer 170a-2 and has substantially the same shape as the sacrificial inner spacer 148a-2 in the first region 10 according to some embodiments. Figure 2L-5(b-1) shows an air gap 172-1b1 that exposes a porous layer 170b-1 and has substantially the same shape as a sacrificial internal spacer 148b-1 in the first region 10. Figure 2L-5 (b-2) shows an air gap 172-1b2 that exposes a porous layer 170b-2 and has substantially the same shape as a sacrificial internal spacer 148b-2 in the first region 10. Figure 2L-5 (c-1) shows an air gap 172-1c1 that exposes a porous layer 170c-1 and has substantially the same shape as a sacrificial internal spacer 148c-1 in the first region 10. Figure 2L-5 (c-2) shows an air gap 172-1c2 that exposes a porous layer 170c-2 and has substantially the same shape as a sacrificial internal spacer 148c-2 in the first region 10.

[0092] Figure 2L-6 shows according to various embodiments Figure 2L-4 the region R shown in 2L-4 a magnified cross-sectional view. More specifically, according to some embodiments, Figure 2L-6 (a-1) shows an air gap 172-2a1 that exposes a porous layer 170a-1 and has substantially the same shape as a sacrificial internal spacer 148a-1 in the second region 20. Figure 2L-6 (a-2) shows an air gap 172-2a2 that exposes a porous layer 170a-2 and has substantially the same shape as a sacrificial internal spacer 148a-2 in the second region 20. Figure 2L-6 (b-1) shows an air gap 172-2b1 that exposes a porous layer 170b-1 and has substantially the same shape as a sacrificial internal spacer 148b-1 in the second region 20. Figure 2L-6 (b-2) shows an air gap 172-2b2 that exposes a porous layer 170b-2 and has substantially the same shape as a sacrificial internal spacer 148b-2 in the second region 20. Figure 2K-6 (c-1) shows an air gap 172-2c1 that exposes a porous layer 170c-1 and has substantially the same shape as a sacrificial internal spacer 148c-1 in the second region 20. Figure 2L-6 (c-2) shows an air gap 172-2c2 that exposes a porous layer 170c-2 and has substantially the same shape as a sacrificial internal spacer 148c-2 in the second region 20.

[0093] According to some embodiments, after forming the air gaps 172-1 and 172-2 and the bottom air gaps 174-1 and 174-2, a gate structure 180 is formed in the gate trench 166, as Figure 2M-1 , Figure 2M-2 , Figure 2M-3 and Figure 2M-4 shown. In some embodiments, the gate structure 180 wraps the channel structures 108'-1 and 108'-2 in the first region 10 and the second region 20, and extends longitudinally in the Y direction. In some embodiments, the gate structure 180 includes an interface layer 182, a gate dielectric layer 184, and a gate stack layer 186.

[0094] The interface layer 182 can be used to improve the interface between the channel structures 108'-1 and 108'-2 and the dielectric layer formed later. In addition, the interface layer 182 can be capable of helping to suppress the mobility degradation of charge carriers in the channel structures 108'-1 and 108'-2 that serve as the channel regions of the transistors. In some embodiments, the interface layer 182 is an oxide layer formed by implementing a thermal process. In some embodiments, the interface layer 182 has a thickness in the range from about 0.5 nm to about 1.5 nm.

[0095] According to some embodiments, after forming the interface layer 182, the gate dielectric layer 184 is conformally formed to cover the interface layer 182 and the bottom and sidewalls of the gate trench 166. In some embodiments, the gate dielectric layer 184 is made of a dielectric material such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titanium oxide, hafnium oxide-aluminum oxide (HfO 2 -Al 2 O 3 ) alloy, La 2 O 3 -Al 2 O 3 or LaO, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 184 is formed using CVD, ALD, other suitable methods, or combinations thereof. In some embodiments, the gate dielectric layer 184 has a thickness in the range from about 1 nm to about 2 nm.

[0096] According to some embodiments, after forming the gate dielectric layer 184, the gate stack layer 186 is formed above the gate dielectric layer 184. In some embodiments, the gate stack layer 186 includes multiple layers. In some embodiments, the gate stack layer 186 includes a work function metal layer. In some embodiments, the work function layers in the first region 10 and the second region 20 are made of different materials. In some embodiments, the work function metal layer is made of titanium nitride, tantalum nitride, tungsten nitride, tantalum, etc.

[0097] In some embodiments, the gate stack layer 186 includes a gate fill layer formed over the work function layer. In some embodiments, the gate fill layer is made of a conductive material such as tungsten, titanium, tantalum, cobalt, copper, etc. In some embodiments, the gate fill layer is formed using CVD, ALD, electroplating, another suitable method, or a combination thereof. In some embodiments, after depositing the gate dielectric layer 184 and the gate stack layer 186, a polishing process such as a CMP process is performed.

[0098] Figure 2M-5 An enlarged cross-sectional view of the Figure 2M-3 region R shown in 2M-3 is shown. More specifically, Figure 2M-5 (a-1) shows an air gap 172-1a1 and a gate structure 180 at opposite sides of a porous layer 170a-1 in a first region 10 according to some embodiments. Figure 2M-5 (a-2) shows an air gap 172-1a2 and a gate structure 180 at opposite sides of a porous layer 170a-2 in a first region 10 according to some embodiments. Figure 2M-5 (b-1) shows an air gap 172-1b1 and a gate structure 180 at opposite sides of a porous layer 170b-1 in a first region 10 according to some embodiments. Figure 2M-5 (b-2) shows an air gap 172-1b2 and a gate structure 180 at opposite sides of a porous layer 170b-2 in a first region 10 according to some embodiments. Figure 2M-5 (c-1) shows an air gap 172-1c1 and a gate structure 180 at opposite sides of a porous layer 170c-1 in a first region 10 according to some embodiments. Figure 2M-5 (c-2) shows an air gap 172-1c2 and a gate structure 180 at opposite sides of a porous layer 170c-2 in a first region 10 according to some embodiments.

[0099] Figure 2M-6 An enlarged cross-sectional view of the Figure 2M-4 region R shown in 2M-4 is shown. More specifically, Figure 2M-6 (a-1) shows an air gap 172-2a1 and a gate structure 180 at opposite sides of a porous layer 170a-1 in a second region 20 according to some embodiments. Figure 2M-6 (a-2) shows an air gap 172-2a2 and a gate structure 180 at opposite sides of a porous layer 170a-2 in a second region 20 according to some embodiments. Figure 2M-6(b-1) shows an air gap 172-2b1 and a gate structure 180 at opposite sides of a porous layer 170b-1 in a second region 20 according to some embodiments. Figure 2M-6 (b-2) shows an air gap 172-2b2 and a gate structure 180 at opposite sides of a porous layer 170b-2 in a second region 20 according to some embodiments. Figure 2M-6 (c-1) shows an air gap 172-2c1 and a gate structure 180 at opposite sides of a porous layer 170c-1 in a second region 20 according to some embodiments. Figure 2M-6 (c-2) shows an air gap 172-2c2 and a gate structure 180 at opposite sides of a porous layer 170c-2 in a second region 20 according to some embodiments.

[0100] According to some embodiments, after forming the gate structure 180, a silicide layer 190 and source / drain contacts 192 are formed over the source / drain structures 150-1 and 150-2, as Figure 2M-1 、 Figure 2M-3 and Figure 2M-4 shown. More specifically, contact trenches may be formed through the contact etch stop layer 160 and the interlayer dielectric layer 162 to expose the source / drain structures 150-1 and 150-2. Thereafter, according to some embodiments, the silicide layer 190 is formed over the exposed portions of the source / drain structures 150-1 and 150-2, and the source / drain contacts 192 are formed in the contact trenches over the silicide layer 190.

[0101] The silicide layer 190 may be formed by: forming a metal layer over the top surfaces of the source / drain structures 150-1 and 150-2; and annealing the metal layer such that the metal layer reacts with the source / drain structures 150-1 and 150-2 to form the silicide layer 190. After forming the silicide layer 190, the unreacted metal layer may be removed.

[0102] In some embodiments, the source / drain contacts 192 are made of a conductive material, including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or combinations thereof.

[0103] The source / drain contact 192 may also include a liner and / or a barrier layer. For example, a liner (not shown) may be formed on the sidewalls and bottom of the contact trench. The liner may be made of silicon nitride, but any other suitable dielectric may be used as an alternative material. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, but other suitable processes (such as physical vapor deposition or thermal processes) may also be used as alternative processes. A barrier layer (not shown) may be formed on top of the liner (if present) and may cover the sidewalls and bottom of the opening. The barrier layer may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process. The barrier layer may be made of tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, etc. may also be used.

[0104] Figure 2M-7 An enlarged cross-sectional view of region R shown in accordance with various embodiments is Figure 2M-3 as shown in 2M-3W More specifically, Figure 2M-7 (a) shows a source / drain structure 150-1a according to some embodiments, where four air gaps 172-1a partially expose portions of their sidewalls, and where the bottom air gap 174-1 exposes its bottom portion in the first region 10. Figure 2M-7 (b) shows a source / drain structure 150-1b according to some embodiments, where four air gaps 172-1b partially expose portions of their sidewalls, and where the bottom air gap 174-1 exposes its bottom portion in the first region 10. Figure 2M-7 (c) shows a source / drain structure 150-1c according to some embodiments, where four air gaps 172-1c partially expose portions of their sidewalls, and where the bottom air gap 174-1 exposes its bottom portion in the first region 10.

[0105] Figure 2M-8 An enlarged cross-sectional view of region R shown in accordance with various embodiments is Figure 2M-4 as shown in 2M-4W More specifically, Figure 2M-8 (a) shows a source / drain structure 150-2a according to some embodiments, where four air gaps 172-2a partially expose portions of their sidewalls, and where the bottom air gap 174-2 exposes its bottom portion in the second region 20. Figure 2M-8 (b) shows a source / drain structure 150-2b according to some embodiments, where four air gaps 172-1b partially expose portions of their sidewalls, and where the bottom air gap 174-2 exposes its bottom portion in the second region 20. Figure 2M-8(c) shows a source / drain structure 150-2c according to some embodiments, where four air gaps 172-2c partially expose portions of their sidewalls, and where a bottom air gap 174-2 exposes its bottom portion in the second region 20.

[0106] In some embodiments, the widths of the air gaps 172-1 and 172-2 are in the range from about 3 nm to about 8 nm. The air gaps 172-1 and 172-2 should be wide enough to separate the gate structure 180 and the source / drain structures 150-1 and 150-2. On the other hand, the air gaps 172-1 and 172-2 should not be too wide, otherwise the spacer used to form the gate structure 180 may be reduced. In some embodiments, the widths of the air gaps 172-1 and 172-2 are less than the width of the gate spacer 140 in the X direction.

[0107] In some embodiments, the width of the portion of the first source / drain layer 151 that is laterally sandwiched between the air gap 172-1 and the second source / drain layer 152 is in the range from about 2 nm to about 3 nm. As previously described, the first source / drain layer 151 is formed to prevent damage to the source / drain structure 150-1 during the etching process for removing the sacrificial inner spacer 148 and the bottom sacrificial layer 149. Therefore, the portion of the first source / drain layer 151 that is located between the air gap 172-1 and the second source / drain layer 152 should not be too thin, otherwise the risk of source / drain damage may increase. In some embodiments, the first source / drain layer 151 has a waveform profile that contacts the second source / drain layer 152.

[0108] In some embodiments, the width of the portion of the first source / drain layer 154 that is laterally sandwiched between the air gap 172-2 and the second source / drain layer 155 is in the range from about 3 nm to about 4 nm. In some embodiments, the first source / drain layer 154 has a waveform profile that contacts the second source / drain layer 155. In some embodiments, the width of the portion of the first source / drain layer 154 that is laterally sandwiched between the air gap 172-2 and the second source / drain layer 155 is greater than the width of the portion of the first source / drain layer 151 that is laterally sandwiched between the air gap 172-1 and the second source / drain layer 152.

[0109] In some embodiments, the bottom air gap 174-1 has a height H 1 (in the Z direction) below the middle portion (in the X direction) of the source / drain structure 150-1, and the bottom air gap 174-2 has a height H 2 (in the Z direction) below the middle portion (in the X direction) of the source / drain structure 150-2. The height H 1can be defined as the distance between the bottommost point of the source / drain structure 150-1 measured in the Z direction and the bottommost point of the bottom air gap 174-1. Height H 2 can be defined as the distance between the bottommost point of the source / drain structure 150-2 measured in the Z direction and the bottommost point of the bottom air gap 174-2. In some embodiments, height H 1 is substantially equal to height H 2 .

[0110] Because the bottom portions of the source / drain structures 150-1 and 150-2 are lower than the topmost surface of the bottom air gaps 174-1 and 174-2, there are necking regions in the bottom air gaps 174-1 and 174-2 that have the narrowest distance between the source / drain structures 150-1 / 150-2 and the substrate fin structure 104B. In some embodiments, the dimension D of the necking regions in the bottom air gaps 174-1 and 174-2 N is greater than about 2 nm. The necking regions should be large enough such that the bottom sacrificial layer 149 can be completely removed in the etching process shown in Figures 2L-1 to 2L-4 .

[0111] As Figures 2M-1 to 2M-8 shown, according to some embodiments, the semiconductor structure 100 includes channel structures 108'-1 / 108'-2 that are vertically separated from each other and a gate structure 180 that wraps the channel structures. Additionally, according to some embodiments, a porous layer 170 is formed above the sidewalls of the gate structure 180 below the channel structures 108'-1 / 108'-2. Additionally, the source / drain structures 150-1 / 150-2 are attached to the channel structures 108'-1 / 108'-2, and the source / drain structures 150-1 / 150-2 are laterally separated from the porous layer by air gaps 172. In some embodiments, the porous layer 170 and the gate structure 180 have a curved interface. In some embodiments, the bottommost one of the porous layer 170 connects the bottommost one of the channel structures 108'-1 / 108'-2 and the top surface of the substrate fin structure 104B.

[0112] In some embodiments, the bottom surfaces of the source / drain structures 150-1 / 150-2 and the bottommost one of the channel layers 108'-1 / 108'-2 are exposed by the bottom air gaps 174-1 / 174-2. In some embodiments, the bottom air gap 174 is wider than the air gap 172. In some embodiments, the bottom air gaps 174-1 / 174-2 overlap the gate spacers 140 in the Z direction. In some embodiments, the dimension of the bottom air gaps 174-1 / 174-2 is greater than the dimension of the source / drain structures 150-1 / 150-2 in the X direction.

[0113] In some embodiments, the source / drain structure 150-1 has a laterally extending portion that contacts the channel structure 108'-1, and the bottom surface of the extending portion of the source / drain structure 150-1 is exposed by the air gap 172. In some embodiments, the source / drain structure 150-1 has a first portion that contacts the sidewall surface of the bottommost one of the channel structures 108'-1 and a second portion located above the first portion, and the first portion is wider than the second portion in the X direction. In some embodiments, the gate spacer 140 is formed above the topmost one of the channel structures 108'-1, and the extending portion of the source / drain structure 150-1 contacts the bottom surface of the gate spacer.

[0114] Figure 3A , Figure 3B , Figure 3C and Figure 3D FIG. shows a cross-sectional view of a semiconductor structure 100' according to some embodiments. According to some embodiments, the semiconductor structure 100' may be similar to the previously described semiconductor structure 100, except that the second semiconductor material layer 108 in the first region 10 is not recessed before forming the source / drain structure 150-1. The processes and materials used to form the semiconductor structure 100' may be similar to or the same as those previously described for forming the semiconductor structure 100, and are not repeated herein.

[0115] More specifically, according to some embodiments, the processes shown in Figures 2A-1 to 2F-1 , Figures 2A-2 to 2F-2 , Figures 2A-3 to 2F-3 and Figures 2A-4 to 2F-4 are implemented to form the sacrificial inner spacer 148 and the bottom sacrificial layer 149, and then, the processes shown in Figures 2H-1 to 2M-1 , Figures 2H-2 to 2M-2 , Figures 2H-3 to 2M-3 and Figures 2H-4 to 2M-4 are implemented to form the semiconductor structure 100', as shown in Figure 3A , Figure 3B , Figure 3C and Figure 3E shown. According to some embodiments, since the recessing process shown in Figures 2G-1 to 2G-4 is not implemented, the sidewalls of the channel structures 108'-1 and 108'-2 are substantially aligned with the sidewalls of the gate spacer 140.

[0116] In some embodiments, a source / drain structure 150'-1 is formed in a semiconductor structure 100'. Further, the source / drain structure 150'-1 includes a first source / drain layer 151', a second source / drain layer 152, and a third source / drain layer 153. The source / drain layer 151' is the same as the source / drain layer 151, except that the source / drain layer 151' does not extend under the gate spacer 140.

[0117] Figure 3E An enlarged cross-sectional view of a region R shown in accordance with various embodiments is shown. More specifically, Figure 3C the region R shown in 3C is shown. Figure 3E (a) shows a source / drain structure 150'-1a according to some embodiments, in which four air gaps 172-1a partially expose portions of the sidewalls of its first source / drain layer 151', and in which a bottom air gap 174-1 exposes a bottom portion of its first source / drain layer 151' in a first region 10. Figure 3E (b) shows a source / drain structure 150'-1b according to some embodiments, in which four air gaps 172-1b partially expose portions of the sidewalls of its first source / drain layer 151', and in which a bottom air gap 174-1 exposes a bottom portion of its first source / drain layer 151' in a first region 10. Figure 3E (c) shows a source / drain structure 150-1c according to some embodiments, in which four air gaps 172-1c partially expose portions of the sidewalls of its first source / drain layer 151', and in which a bottom air gap 174-1 exposes a bottom portion of its first source / drain layer 151' in a first region 10.

[0118] Generally, an internal spacer can be formed to separate the gate structure and the source / drain structure, and to provide a low capacitance for electrical characteristics. According to embodiments of the present application, air gaps 172 and a bottom air gap 174 having a low k value are formed as internal spacers. The formation of the air gaps 172 and the bottom air gap 174 can help to improve the capacitance of the resulting device, and can prevent current leakage from the bottom of the device.

[0119] Further, according to some embodiments, a sacrificial internal spacer 148 and a bottom sacrificial layer 149 are formed before forming the air gaps 172 and the bottom air gap 174, and the source / drain structures 150-1 and 150-2 are formed between and above the sacrificial internal spacer 148 and the bottom sacrificial layer 149. Since the sacrificial internal spacer 148 and the bottom sacrificial layer 149 are formed of a semiconductor material (such as SiGe), the source / drain structures 150-1 and 150-2 formed thereon can have a smoother profile.

[0120] It should be understood that the elements shown in semiconductor structures 100 and 100' can be combined and / or exchanged. Additionally, it should be noted that Figures 1A to 3E the same elements in Figures 1A to 3E are described in terms of a method, but it should be understood that Figures 1A to 3E the structures disclosed in Figures 1A to 3E are not limited to the method, but can exist independently as structures independent of the method. Similarly,

[0121] the methods shown in

[0122] are not limited to the disclosed structures, but can exist independently of the structures. Additionally, according to some embodiments, the channel structures (e.g., nanostructures) described above can include nanowires, nanosheets, or other suitable nanostructures.

[0123] Embodiments for forming a semiconductor structure can be provided. The semiconductor structure can include forming a gate dielectric layer in a first region and a second region, and modifying the gate dielectric layer with a first metal element in the first region but not in the second region. Thereafter, a capping layer can be formed over the modified gate dielectric layer to densify the gate dielectric layer, and thus the quality of the gate dielectric layer can be improved. Next, a work function metal layer can be formed in the first region and the second region. Because the gate dielectric layer in the first region is doped with the first metal element, the threshold voltages of the first transistor and the second transistor can be different.

[0124] A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a channel structure vertically separated from each other and a gate structure surrounding the channel structure. The semiconductor structure further includes a first porous layer formed above a first sidewall of the gate structure below the channel structure and a source / drain structure attached to the channel structure. In addition, the source / drain structure is laterally separated from the first porous layer by a first air gap.

[0125] A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate fin structure protruding from a substrate and a channel structure formed above the substrate fin structure. The semiconductor structure further includes a source / drain structure attached to the channel structure in a first direction and a gate structure surrounding the channel structure and longitudinally oriented in a second direction different from the first direction. The semiconductor structure further includes a porous layer covering sidewalls of the gate structure. In addition, the bottommost one of the porous layers connects the bottommost one of the channel structures and the top surface of the substrate fin structure. In addition, the bottom surface of the source / drain structure and the bottom surface of the bottommost one of the channel layers are exposed by a bottom air gap.

[0126] A method of forming a semiconductor structure is provided. The method includes: alternately stacking a first semiconductor material layer and a second semiconductor material layer in a first direction to form a semiconductor stack above a substrate; and patterning the semiconductor stack to form a fin structure longitudinally oriented in a second direction orthogonal to the first direction. The method further includes: forming source / drain trenches in the fin structure; and recessing the first semiconductor material layer to form notches. The method further includes: forming sacrificial inner spacers in the notches and forming a sacrificial bottom layer in a bottom region of the source / drain trenches; and forming a source / drain structure above the sacrificial bottom layer. The method further includes: removing the first semiconductor material layer to form gate trenches; and forming a porous layer on sidewalls of the sacrificial inner spacers and sidewalls of the sacrificial bottom layer. The method further includes: removing the sacrificial inner spacers and the sacrificial bottom layer; and forming a gate structure in the gate trenches.

[0127] Some embodiments of the present application provide a semiconductor structure, including: a channel structure, vertically separated from each other; a gate structure, surrounding the channel structure; a first porous layer, formed above a first sidewall of the gate structure below the channel structure; and a source / drain structure, attached to the channel structure, wherein the source / drain structure is laterally separated from the first porous layer by a first air gap.

[0128] In some embodiments, the bottom surface of the source / drain structure is exposed by the first air gap. In some embodiments, the semiconductor structure further includes: a second porous layer covering the second sidewalls of the gate structure and contacting the bottom surface of the topmost one of the channel structures, wherein the source / drain structure is laterally separated from the second porous layer by a second air gap. In some embodiments, the first air gap is wider than the second air gap. In some embodiments, the source / drain structure has a laterally extending portion in contact with the channel structure, and the bottom surface of the laterally extending portion of the source / drain structure is exposed by the first air gap. In some embodiments, the first porous layer includes SiO 2 . In some embodiments, the first porous layer has a curved profile in a cross-sectional view.

[0129] Some other embodiments of the present application provide a semiconductor structure, including: a substrate fin structure protruding from a substrate; a channel structure formed above the substrate fin structure; a source / drain structure attached to the channel structure in a first direction; and a gate structure wrapping the channel structure and longitudinally oriented in a second direction different from the first direction, wherein the bottom surface of the source / drain structure and the bottom surface of the bottommost one of the channel structures are exposed by a bottom air gap.

[0130] In some embodiments, the semiconductor structure further includes: a porous layer covering the sidewalls of the gate structure, wherein the bottommost one of the porous layers connects the bottommost one of the channel structures and the top surface of the substrate fin structure, and the source / drain structure is separated from the porous layer by an air gap in the first direction. In some embodiments, the semiconductor structure further includes: a gate spacer formed above the topmost one of the channel structures, wherein an extending portion of the source / drain structure contacts the bottom surface of the gate spacer. In some embodiments, the bottom air gap overlaps with the gate spacer in a third direction different from the first direction and the second direction. In some embodiments, the size of the bottom air gap is larger than the size of the source / drain structure in the first direction. In some embodiments, the source / drain structure has a first portion in contact with the sidewall surface of the bottommost one of the channel structures and a second portion located above the first portion, and the first portion is wider than the second portion in the first direction.

[0131] Some further embodiments of the present application provide a method for manufacturing a semiconductor structure, including: alternately stacking a first semiconductor material layer and a second semiconductor material layer in a first direction to form a semiconductor stack above a substrate; patterning the semiconductor stack to form fin structures longitudinally oriented in a second direction orthogonal to the first direction; forming source / drain trenches in the fin structures; recessing the first semiconductor material layer to form notches; forming sacrificial inner spacers in the notches and forming a sacrificial bottom layer in a bottom region of the source / drain trenches; forming source / drain structures above the sacrificial bottom layer; removing the first semiconductor material layer to form gate trenches; forming a porous layer on sidewalls of the sacrificial inner spacers and sidewalls of the sacrificial bottom layer; removing the sacrificial inner spacers and the sacrificial bottom layer; and forming a gate structure in the gate trenches.

[0132] In some embodiments, the method for manufacturing the semiconductor structure further includes: applying an etchant from the gate trenches to remove the sacrificial inner spacers and the sacrificial bottom layer through the porous layer. In some embodiments, the method for manufacturing the semiconductor structure further includes: recessing the second semiconductor material layer after forming the sacrificial inner spacers in the notches. In some embodiments, the source / drain structures partially cover the sacrificial inner spacers in the first direction. In some embodiments, a bottom air gap is formed by removing the sacrificial bottom layer, and a bottom surface of the source / drain structures is exposed by the bottom air gap. In some embodiments, an air gap is formed by removing the sacrificial inner spacers, and the source / drain structures are separated from the porous layer by the air gap. In some embodiments, the porous layer and the gate structure have a curved interface.

[0133] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the embodiments of the present disclosure, and various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor structure comprising: channel structures, vertically separated from each other; A gate structure wrapping the channel structure; a first porous layer formed on a first sidewall of the gate structure below the channel structure; as well as A source / drain structure is attached to the channel structure, wherein the source / drain structure is laterally separated from the first porous layer by a first air gap.

2. The semiconductor structure according to claim 1, wherein: A bottom surface of the source / drain structure is exposed by the first air gap.

3. The semiconductor structure according to claim 1, further comprising: A second porous layer covers a second sidewall of the gate structure and contacts a bottom surface of a topmost one of the channel structures, wherein the source / drain structure is laterally separated from the second porous layer by a second air gap.

4. The semiconductor structure according to claim 3, wherein: The first air gap is wider than the second air gap.

5. The semiconductor structure according to claim 1, wherein: The source / drain structure has a lateral extension portion contacting the channel structure, and a bottom surface of the lateral extension portion of the source / drain structure is exposed by the first air gap.

6. The semiconductor structure according to claim 1, wherein: The first porous layer includes SiO2.

7. The semiconductor structure according to claim 1, wherein: The first porous layer has a curved profile in a cross-sectional view.

8. A semiconductor structure comprising: a base fin structure, protruding from the substrate; a channel structure formed above the substrate fin structure; a source / drain structure attached to the channel structure in a first direction; as well as a gate structure wrapping the channel structure and longitudinally oriented along a second direction different from the first direction, Wherein, the bottom surface of the source / drain structure and the bottom surface of the bottommost one of the channel structures are exposed by a bottom air gap.

9. The semiconductor structure according to claim 8, further comprising: A porous layer covers the sidewalls of the gate structure, wherein a bottommost one of the porous layers connects a bottommost one of the channel structures and a top surface of the substrate fin structure, and the source / drain structure is separated from the porous layer by an air gap in the first direction.

10. A method for manufacturing a semiconductor structure, comprising: Alternatingly stacking first semiconductor material layers and second semiconductor material layers in a first direction to form a semiconductor stack above a substrate; patterning the semiconductor stack to form a fin structure longitudinally oriented along a second direction orthogonal to the first direction; forming source / drain trenches in the fin structure; recessing the first semiconductor material layer to form a notch; forming a sacrificial inner spacer in the notch and forming a sacrificial bottom layer in a bottom region of the source / drain trench; forming a source / drain structure over the sacrificial bottom layer; removing the first semiconductor material layer to form a gate trench; forming a porous layer on sidewalls of the sacrificial inner spacer and sidewalls of the sacrificial bottom layer; removing the sacrificial inner spacer and the sacrificial bottom layer; as well as A gate structure is formed in the gate trench.

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