Middle-high voltage shielding grid power MOSFET layout and MOSFET

Abstract

According to the medium-high voltage shielding grid power MOSFET layout and the MOSFET provided by the embodiment of the invention, charge balance can be optimized and point discharge can be avoided by changing the space between the first groove region, closest to the cellular region, of the terminal region and the second groove region of the cellular region, so that IDSS is optimized and breakdown voltage is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a layout of a medium-voltage shield gate power MOSFET and a MOSFET. Background Art

[0002] In the existing layout design of shield gate power MOSFETs, the source polysilicon electrode, the gate electrode, and the source electrode need to be led out separately, and the source polysilicon electrode is isolated from the gate electrode. Before design optimization, as Figure 1 shown, the distance between the first trench region closest to the cell region in the terminal region and the second trench region in the cell region is 0, which increases the risk of leakage. Summary of the Invention

[0003] To solve or alleviate the above technical problems, in a first aspect, an embodiment of the present application provides a layout of a medium-voltage shield gate power MOSFET, including a cell region and a terminal region;

[0004] The terminal region includes a plurality of first trench regions arranged at intervals, the cell region includes a plurality of second trench regions arranged at intervals, and gate contact hole regions are provided in the second trench regions;

[0005] The first trench regions are arranged on the periphery of the second trench regions;

[0006] There is a first distance between the first trench region closest to the cell region in the terminal region and the second trench region in the cell region.

[0007] As a preferred embodiment of the present application, the distance between the second trenches is a second distance, and the first distance is less than the second distance.

[0008] As a preferred embodiment of the present application, the first distance is 65%-75% of the second distance.

[0009] In a second aspect, an embodiment of the present application provides a medium-voltage shield gate power MOSFET fabricated by the layout according to any one of the first aspects.

[0010] Compared with the prior art, the layout of a medium-voltage shield gate power MOSFET and the MOSFET provided by the embodiment of the present application can optimize charge balance and avoid tip discharge by changing the distance between the first trench region closest to the cell region in the terminal region and the second trench region in the cell region, thereby optimizing IDSS and increasing the breakdown voltage. Description of the Drawings

[0011] The accompanying drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. Some specific embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings in an exemplary rather than restrictive manner. The same reference numerals in the drawings denote the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0012] Figure 1 is a layout of a medium- and high-voltage shielded gate power MOSFET in the prior art;

[0013] Figure 2 is a layout of a medium- and high-voltage shielded gate power MOSFET provided by an embodiment of the present application. Detailed implementation manners

[0014] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0015] As Figure 2 shown, an embodiment of the present application provides a layout of a medium- and high-voltage shielded gate power MOSFET, including a cell region and a terminal region;

[0016] The terminal region includes a plurality of first communication regions 1 arranged at intervals, the cell region includes a plurality of second communication regions 1 arranged at intervals, and gate contact hole regions 3 are arranged in the second communication regions 2;

[0017] The first communication regions 1 are arranged on the periphery of the second communication regions 2;

[0018] There is a first distance D1 between the first communication region 1 closest to the cell region in the terminal region and the second communication region 2 of the cell region.

[0019] Preferably, the distance between the second communication regions 2 is a second distance D2, and the first distance D1 is less than the second distance D2.

[0020] Preferably, the first distance D1 is 65%-75% of the second distance D2.

[0021] Second, an embodiment of the present application provides a medium- and high-voltage shielded gate power MOSFET fabricated by the layout according to any one of the first aspects.

[0022] A layout of a medium - high voltage shielded gate power MOSFET and a MOSFET provided by an embodiment of the present application can optimize charge balance and avoid tip discharge by changing the distance between the first trench region 1 closest to the cell region in the terminal region and the second trench region 2 in the cell region, thereby optimizing IDSS and increasing the breakdown voltage.

[0023] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A medium-high voltage shielded gate power MOSFET layout, characterized in that: cellular region and terminal region; The terminal region includes a plurality of first trench regions arranged at intervals, the cell region includes a plurality of second trench regions arranged at intervals, and a gate contact hole region is arranged in the second trench region; The first trench region is disposed at the periphery of the second trench region; There is a first distance between the first trench region of the terminal region, which is closest to the cell region, and the second trench region of the cell region.

2. A medium-high voltage shielded gate power MOSFET layout as claimed in claim 1, characterized in that: The distance between the second grooves is a second distance, and the first distance is smaller than the second distance.

3. A medium-high voltage shielded gate power MOSFET layout as claimed in claim 2, characterized in that: The first distance is 65%-75% of the second distance.

4. A medium-to-high voltage shielded gate power MOSFET, characterized in that: Prepared by the layout according to any one of claims 1 to 3.

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