Contact hole forming method and image sensor

Abstract

The invention discloses a contact hole forming method and an image sensor, and the method comprises the steps: completing the device structures of a logic region and a pixel region of the image sensor in advance, and enabling the device structure of the pixel region to be one more thinned protection layer than the logic region; a thinned sacrificial barrier layer is formed on the protection layer of the pixel area, the thickness of the thinned sacrificial barrier layer is the same as the thinned thickness of the protection layer, and materials are different; the material and the thickness of the compensation layer are the same as those of the protection layer; forming a mask on the compensation layer of the logic region through the negative photoresist layer to remove the compensation layer of the pixel region, and further removing the residual compensation layer, the negative photoresist layer and the sacrificial barrier layer of the junction region of the pixel region and the logic region; forming a contact hole etching stop layer; filling an interlayer dielectric layer; and forming mask patterns of contact holes on the interlayer dielectric layer, etching the contact holes, and filling all the contact holes. According to the invention, the height difference between the logic region and the pixel region can be eliminated, the over-etching of the substrate is avoided, and the electrical stability can be maintained.

Description

Technical Field

[0001] The present invention relates to the field of manufacturing semiconductor devices, and particularly to a method for forming contact holes and an image sensor. Background Art

[0002] As Figure 1 shown, a CIS device (CMOS IMAGE SENSOR) includes a logic area and a pixel area. In traditional processes, before forming contact holes, in order to reduce contact resistance, a metal silicide 105 is formed in the logic area; at the same time, a Self-Aligned Barrier Oxide (SAB OX for short) is formed in the pixel area in advance as a protective layer 104 to prevent the pixel area from contacting metal, resulting in metal contamination, which in turn causes an increase in electrical offset, dark current, and white dot defects of the image sensor, and a decrease in the imaging quality of the image sensor.

[0003] Since the pixel area has an additional SAB OX layer compared to the logic area, it is likely to cause over-etching damage to the substrate 101 and difficult filling of the Inter Layer Dielectric (ILD) 102 during the etching process of the contact hole 106. Specifically: 1) On the plane of the active area (AA) and the top of the gate in the logic area, there is only a contact hole etch stop layer 103 (CESL for short), while on the AA plane and the top of the gate in the pixel area, there is a stack of SAB OX and CESL. Therefore, a stack difference is formed between the logic area and the pixel area. During the contact hole etching process, when etching the SAB OX, it is easy to cause over-etching of the logic area substrate (as shown at the position of the dotted circle in Figure 1 ), which is likely to cause abnormal metal silicide and unstable resistance value. 2) Because of the stack difference between the logic area and the pixel area, a thicker CESL is required to eliminate the etching load effect. However, the thickened CESL will increase the aspect ratio of the filling of the interlayer dielectric layer ILD, thereby causing a High Aspect Ratio Process (HARP), and holes 107 and gaps will appear during filling, resulting in a decrease in isolation performance. Summary of the Invention

[0004] The main purpose of the present invention is to provide a method for forming contact holes and an image sensor, which can prevent over-etching damage to the device and stabilize the contact resistance when forming contact holes.

[0005] The technical solution adopted by the present invention is as follows: Provide a method for forming contact holes, including the following steps: Pre - complete the device structures of the logic region and the pixel region of the image sensor, where the device structure of the pixel region has one more layer of a thinned protective layer than the logic region; Form a thinned sacrificial barrier layer on the protective layer of the pixel region, with its thickness being the same as the thinned thickness of the protective layer and the material being different from that of the protective layer; Form a compensation layer on both the logic region and the pixel region, with its material and thickness being the same as those of the protective layer; Form a negative photoresist layer on the compensation layer of the logic region. Using this negative photoresist layer as a mask, remove the compensation layer of the pixel region, further remove the remaining compensation layer in the junction area between the pixel region and the logic region, and finally remove the negative photoresist layer; Remove the sacrificial barrier layer of the pixel region; Form a contact hole etch stop layer on both the compensation layer of the logic region and the protective layer of the pixel region; Fill an inter - layer dielectric layer on the contact hole etch stop layer; Form a mask pattern for the contact holes on the inter - layer dielectric layer, perform the etching of the contact holes, and fill all the contact holes.

[0006] According to the above - mentioned technical solution, the formed contact hole etch stop layer is a thinned contact hole etch stop layer.

[0007] According to the above - mentioned technical solution, the thickness of the protective layer is thinned by half, and the thickness of the sacrificial barrier layer is the same as the thickness of the protective layer.

[0008] According to the above - mentioned technical solution, the photomask used when forming the negative photoresist layer is the same as the photomask used when forming the sacrificial barrier layer.

[0009] According to the above - mentioned technical solution, specifically use dry etching to remove the compensation layer of the pixel region, and use wet etching to remove the remaining compensation layer in the junction area between the pixel region and the logic region.

[0010] According to the above - mentioned technical solution, the protective layer is self - aligned blocking silicon oxide, and the sacrificial barrier layer is a self - aligned silicon nitride layer or a self - aligned silicon oxynitride layer.

[0011] According to the above - mentioned technical solution, when removing the sacrificial barrier layer of the pixel region, specifically use hot phosphoric acid etching.

[0012] According to the above - mentioned technical solution, when removing the remaining compensation layer in the junction area between the pixel region and the logic region, specifically use hydrofluoric acid DHF to clean the remaining compensation layer in the junction area below the negative photoresist layer.

[0013] The present invention also provides an image sensor, which prepares the contact holes of the pixel region and the logic region by using the contact hole forming method described in the above - mentioned technical solution.

[0014] The beneficial effects of the present invention are as follows: Compared with the prior art, in the present invention, the pixel area protective layer that causes the height difference between the logic area and the pixel area is divided into two layers with different materials. The first layer is thinned (thinned compared to the thickness of the protective layer in the prior art), and the second layer serves as a sacrificial barrier layer with a thickness equal to the thinned thickness of the first layer. Then, a compensation layer is added to the logic area with the same thickness as the thinned protective layer. The unexpected effect is that when the sacrificial barrier layer in the pixel area is removed, the height difference between the two areas can be cleverly eliminated, and during the subsequent contact hole etching process, over-etching of the logic area substrate will not occur; moreover, the thinned protective layer reduces the aspect ratio during the subsequent filling of the interlayer dielectric layer, preventing holes and gaps from appearing during filling and causing a decline in isolation performance; also, because the material of the sacrificial barrier layer is different from that of the protective layer, when etching the compensation layer in the pixel area, the sacrificial barrier layer serves as a barrier layer for the pixel area, preventing the protective layer below it from being etched; during this process, since a negative photoresist layer is used as a mask, no additional photomask is added, thus saving costs; and under the combined action of the negative photoresist layer and the sacrificial protective layer, the remaining compensation layer in the junction area between the pixel area and the logic area can be better removed.

[0015] Furthermore, by thinning the contact hole etch stop layer, together with the thinned protective layer, the aspect ratio during the subsequent filling of the interlayer dielectric layer is reduced, avoiding holes and gaps from appearing during filling and causing a decline in isolation performance.

[0016] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 is a cross-sectional schematic diagram of a CIS device with contact holes in the related art; Figure 2 is a flowchart of a method for forming contact holes in an embodiment of the present invention; Figure 3A is a cross-sectional schematic diagram of forming a sacrificial barrier layer on a device in an embodiment of the present invention; Figure 3B is a cross-sectional schematic diagram of forming a compensation layer in an embodiment of the present invention; Figure 3C is a cross-sectional schematic diagram of forming a negative photoresist layer in the logic area and after exposure and development in an embodiment of the present invention; Figure 3Dis a cross-sectional schematic diagram of an embodiment of the present invention after etching the compensation layer in the pixel area; Figure 3E is a cross-sectional schematic diagram of removing an additional compensation layer in the junction area between the pixel area and the logic area according to an embodiment of the present invention; Figure 3F is a cross-sectional schematic diagram of an embodiment of the present invention after the negative photoresist layer is removed; Figure 3G is a cross-sectional schematic diagram of an embodiment of the present invention after removing the sacrificial barrier layer in the pixel area; Figure 3H is a cross-sectional schematic diagram of forming a contact hole etching stop layer according to an embodiment of the present invention; Figure 3I is a cross-sectional schematic diagram of a filling interlayer dielectric layer according to an embodiment of the present invention; Figure 3J is a cross-sectional schematic diagram of forming a contact hole according to an embodiment of the present invention; In the figure: 101, substrate; 102, interlayer dielectric layer; 103, contact hole etch stop layer; 104, protective layer; 105, metal silicide; 106, contact hole; 107, hole; 301, substrate; 302, gate oxide layer; 303, polysilicon gate; 304, contact layer; 305, protective layer; 306, sacrificial blocking layer; 307, compensation layer; 308, negative photoresist layer; 309, remaining compensation layer; 310, contact hole etch stop layer; 311, interlayer dielectric layer; 312, contact hole. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] It should be noted that the illustrations provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout type may also be more complicated.

[0021] In the present invention, it should also be noted that for terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application. In addition, for terms such as "first" and "second", they are only used for descriptive and distinguishing purposes and cannot be construed as indicating or implying relative importance.

[0022] In addition, it should also be noted that the features of various embodiments of the present invention can be partially or wholly combined or integrated, and as can be understood by those skilled in the art, they can interact and operate in different ways. Each embodiment can be implemented independently of each other or in an associated relationship.

[0023] In order to overcome the problem that the height difference between the logic region and the image region of the CIS device due to different structures affects the etching of subsequent contact holes, the solution of the present invention is mainly to divide the pixel region protective layer that causes the height difference between the logic region and the pixel region into two layers with different materials. The first layer is thinned, and the second layer is used as a sacrificial barrier layer, and its thickness is exactly the same as the thickness by which the first layer is thinned. This is equivalent to not changing the height difference in the prior art, and thus will not increase the aspect ratio when filling the interlayer dielectric layer. Then, by adding a compensation layer in the logic region with the same thickness as the thinned protective layer, when the sacrificial barrier layer in the pixel region is removed, the height difference between the two regions can be cleverly eliminated, and during the subsequent contact hole etching process, the over-etching problem caused by the height difference can be avoided.

[0024] As Figure 2 shown, the method for forming contact holes in the embodiment of the present invention mainly includes the following steps: S1. The device structures of the logic region and the pixel region of the image sensor are completed in advance, where the device structure of the pixel region has one more thinned protective layer than the logic region; S2. A thinned sacrificial barrier layer is formed on the protective layer in the pixel region, with the same thickness as the thickness by which the protective layer is thinned and a different material from the protective layer; S3. A compensation layer is formed on both the logic region and the pixel region, with the same material and thickness as the protective layer; S4. A negative photoresist layer is formed on the compensation layer in the logic region. Using this negative photoresist layer as a mask, the compensation layer in the pixel region is removed, and further the remaining compensation layer in the junction region between the pixel region and the logic region is removed, and finally the negative photoresist layer is removed; S5. The sacrificial barrier layer in the pixel region is removed; S6. A contact hole etching stop layer is formed on both the compensation layer in the logic region and the protective layer in the pixel region; S7. Fill an interlayer dielectric layer on the contact hole etching stop layer; S8. Form a mask pattern for the contact holes on the interlayer dielectric layer, etch the contact holes, and fill all the contact holes.

[0025] As Figure 3A shown, the device structures of the logic region and the pixel region of the image sensor have been completed in advance, which mainly includes a substrate 301. Above the substrate 301, it is divided into a logic region and a pixel region. The logic region includes a gate oxide layer 302 (Gate OX, abbreviated as GOX), a polysilicon gate 303, and a contact layer 304 from bottom to top. The contact layer 304 is located on top of the gate and is a metal silicide, such as nickel silicide or cobalt silicide. The film thickness of the contact layer 304 is relatively thin and is mainly used to reduce the contact resistance. Among them, the substrate 301 can be a silicon substrate, a silicon-germanium substrate, or other semiconductor material substrates well-known to those skilled in the art. The pixel region includes a gate oxide layer GOX and a polysilicon gate 303 from bottom to top. In some embodiments, a spacer structure (for example, a spacer with an ONO structure) will also be formed on the side of the polysilicon gate 303. It should be noted that the polysilicon gate, contact layer, spacer, gate oxide layer, etc. in this embodiment can all be formed by traditional or known processes, and the specific details of these structures are not elaborated in this invention. In addition, an active region is also formed on the substrate 301, which can be prepared by known technologies, and this invention does not explain too much about the active region.

[0026] As Figure 3A shown, in step S1 of this embodiment, a protective layer 305 (silicon oxide can be selected) is mainly formed on the entire pre-completed device structure. In the prior art, the thickness of the protective layer 305 is generally 350 angstroms, and in this embodiment, it can be thinned to 150 angstroms, that is, thinned by nearly 60%. In a preferred embodiment of the present invention, the protective layer 305 can be thinned by half, which is 50% of that in the prior art. The reason why it can be thinned by half is that the present invention cleverly divides the existing protective layer into two parts. One part is the protective layer 305; the other part is the sacrificial barrier layer 306 described below.

[0027] Continuing to refer to Figure 3A , step S2 is mainly to form a sacrificial barrier layer 306 on the protective layer 305. Its thickness is exactly the thickness by which the protective layer 305 is thinned. It combines with the protective layer 305 to form a complete protective layer together to protect the pixel region from metal contamination. As the name implies, the sacrificial barrier layer 306 has at least two functions. One is to act as a barrier layer for subsequent etching and protect the underlying structure (protective layer 305). The other is to act as a sacrificial layer and can be removed finally without increasing additional thickness. It can be seen that the setting of the sacrificial barrier layer 306 is very ingenious.

[0028] As Figure 3BAs shown, in step S3, a compensation layer 307 is formed on both the logic region and the pixel region, and its material and thickness are the same as those of the protective layer 305. The setting of the compensation layer 307 is mainly to make up for the height difference between the logic region and the pixel region, which is mainly caused by the protective layer 305 in the pixel region.

[0029] As Figure 3C - 3F shown, in step S4, a negative photoresist layer 308 is formed on the compensation layer 307 in the logic region. Using the negative photoresist layer 308 as a mask, the compensation layer 307 in the pixel region is removed, and the remaining compensation layer 309 in the junction area between the pixel region and the logic region is further removed. Finally, the negative photoresist layer 308 is removed. The reason for using negative photoresist is to save costs by not adding an extra mask and sharing the mask used to form the protective layer 305. Specifically, the negative photoresist layer 308 is first coated, and then exposed and developed on the negative photoresist layer 308 through a mask to remove the negative photoresist layer 308 in the pixel region, leaving only the negative photoresist layer in the logic region as a mask layer to protect the logic region, thereby protecting the compensation layer 307 in the logic region from being etched. The removal of the negative photoresist layer 308 can be carried out by dry or wet processes. The wet process is preferred to reduce costs. Specifically, SPM (Sulfuric Peroxide Mixture) can be used for cleaning. SPM is a mixture of sulfuric acid and hydrogen peroxide and is a strong oxidant that can effectively decompose and remove organic substances remaining on the silicon wafer surface, including the residues of the negative photoresist layer 308. The removal of the compensation layer 307 in the pixel region is carried out by dry etching.

[0030] When the compensation layer 307 is deposited, a thicker compensation layer protrusion will be formed at the junction of the logic area and the pixel area. After the compensation layer in the pixel area is etched, the remaining compensation layer 309 in the junction area will not be etched due to the protection of the negative photoresist layer 308, which will affect the subsequent filling of the interlayer dielectric layer 311. In order to remove the remaining compensation layer 309, an additional process is required. In a preferred embodiment of the present invention, a wet process can be used, specifically, by using an appropriate amount of DHF (Dilute Hydrofluoric Acid, referring to dilute hydrofluoric acid) to clean the remaining compensation layer 309 in the junction area. DHF can only clean the protruding protective layer, i.e., the remaining compensation layer 309, along the path between the negative photoresist layer 308 and the sacrificial barrier layer 306. By controlling a certain etching time, the result of the protective layer being flush can be achieved. At this time, the ingenuity of designing the sacrificial barrier layer is well demonstrated, because the material of the sacrificial barrier layer 306 is different from that of the protective layer 305 and the compensation layer 307, while the materials of the protective layer 305 and the compensation layer 307 are the same. When the compensation layer 307 in the junction area is removed at this time, the sacrificial barrier layer 306 can play a blocking role to prevent the protective layer 305 from being etched. Since this area is the overlapping area of ​​the logic area and the pixel area, even if the remaining compensation layer 309 is over-etched or under-etched when cleaning with DHF, it will be covered by the subsequent contact hole etching stop layer 310.

[0031] like Figure 3G As shown, in step S5, the sacrificial barrier layer 306 of the pixel area is removed, and a dry process or a wet process can be used, and a wet process is preferred to reduce costs. Among them, hot phosphoric acid etching is preferred for the wet process. After removing the sacrificial barrier layer 306 of the pixel area, a protective layer 305 is left in the pixel area, and its thickness is the same as that of the compensation layer 307 of the logic area. At this time, the stacking height of the logic area and the pixel area is consistent, eliminating the original height difference.

[0032] like Figure 3H As shown, in step S6, a contact hole etch stop layer 310 is formed on both the compensation layer 307 in the logic area and the protection layer 305 in the pixel area. Its thickness can be appropriately thinned to reduce the depth-to-width ratio when the interlayer dielectric layer is subsequently filled. The thickness of the contact hole etch stop layer 310 can be thinned to about 300 angstroms (the original thickness in the prior art is about 350 angstroms). The contact hole etch stop layer 310 only balances the height load of the active area and the polysilicon gate 303, without considering the additional height load brought by the protection layer 305.

[0033] like Figure 3IAs shown, in step S7, an interlayer dielectric layer 311 is filled on the contact hole etching stop layer 310. The material of the interlayer dielectric layer 311 is generally an oxide layer, such as silicon dioxide, which mainly serves as a dielectric material between the device and the metal layer to form electrical isolation. The contact holes are many small vertical through holes formed in the interlayer dielectric layer 311 and are the connection channels between the transistors and the metal layer. Since the thickness of the protective layer 305 is thinned and the contact hole etching stop layer 310 is also appropriately thinned, the aspect ratio during the filling of the interlayer dielectric layer can be further reduced, thus avoiding the situation where holes and gaps appear in the filled interlayer dielectric layer 311, resulting in a decrease in isolation performance.

[0034] As Figure 3J As shown, in step S8, a mask pattern for the contact holes 312 is formed on the interlayer dielectric layer 311, the contact holes 312 are etched, and all the contact holes 312 are filled. Specifically, a photoresist layer (abbreviated as PR) can be formed on the interlayer dielectric layer 311 in the logic region and the pixel region, and an anti-reflection coating (abbreviated as BARC) can also be formed thereon; through exposure and development, a contact hole mask pattern in the logic region and the pixel region is formed. Using the mask pattern as a mask, the contact holes are etched downward, and finally the photoresist layer and the anti-reflection coating are removed.

[0035] The image sensor according to an embodiment of the present invention mainly uses the above-described contact hole forming method to prepare the contact holes in the pixel region and the logic region. The contact holes formed by this method will not over-etch the substrate, and the finally filled interlayer dielectric layer has no gaps and no holes, and the isolation performance is stable.

[0036] In summary, in the present invention, the protective layer in the pixel region is divided into two layers with different materials and formed in two times. The two layers have different materials, the first layer is thinned, and the second layer serves as a sacrificial barrier layer. Then, by adding a compensation layer with the same thickness as the protective layer in the logic region to eliminate the height difference between the two regions, an unexpected effect is that during the subsequent contact hole etching process, the substrate in the logic region will not be over-etched; and because the material of the sacrificial barrier layer is different from that of the protective layer, when etching the compensation layer in the pixel region, the sacrificial barrier layer serves as a barrier layer in the pixel region, so that the protective layer below it will not be etched; during this process, since a negative photoresist layer is used as a mask, no additional photomask is added, thus saving costs; and under the combined action of the negative photoresist layer and the sacrificial barrier layer, the remaining compensation layer in the junction area between the pixel region and the logic region can be better removed.

[0037] Furthermore, by thinning the contact hole etching stop layer and jointly thinning the protective layer, the aspect ratio during the subsequent filling of the interlayer dielectric layer is reduced, avoiding the situation where holes and gaps appear in the filling, resulting in a decrease in isolation performance.

[0038] It should be noted that according to the needs of implementation, each step / component described in this application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0039] In the above embodiments, the magnitudes of the sequence numbers of the steps do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this application.

[0040] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A contact hole forming method, characterized in that: The following steps are involved: Pre-completing the device structures of the logic area and the pixel area of ​​the image sensor, wherein the device structure of the pixel area has an additional thinned protective layer than that of the logic area; forming a thinned sacrificial barrier layer on the protective layer in the pixel area, the thickness of which is the same as the thickness of the thinned protective layer, and the material of which is different from that of the protective layer; A compensation layer is formed on both the logic area and the pixel area, and the material and thickness of the compensation layer are the same as those of the protection layer; Forming a negative photoresist layer on the compensation layer in the logic area, removing the compensation layer in the pixel area using the negative photoresist layer as a mask, further removing the remaining compensation layer in the junction area between the pixel area and the logic area, and finally removing the negative photoresist layer; removing the sacrificial barrier layer in the pixel area; forming a contact hole etching stop layer on both the compensation layer in the logic area and the protection layer in the pixel area; filling an interlayer dielectric layer on the contact hole etch stop layer; A mask pattern of contact holes is formed on the interlayer dielectric layer, the contact holes are etched, and all the contact holes are filled.

2. The contact hole forming method according to claim 1, wherein: The formed contact hole etch stop layer is a thinned contact hole etch stop layer.

3. The contact hole forming method according to claim 1, wherein: The thickness of the protective layer is reduced by half, and the thickness of the sacrificial barrier layer is the same as that of the protective layer.

4. The contact hole forming method according to claim 1, characterized in that: The photomask used in forming the negative photoresist layer is the same as the photomask used in forming the sacrificial barrier layer.

5. The contact hole forming method according to claim 1, wherein: Specifically, a dry etching method is used to remove the compensation layer in the pixel area, and a wet etching method is used to remove the remaining compensation layer in the junction area between the pixel area and the logic area.

6. The contact hole forming method according to any one of claims 1 to 5, characterized in that: The protection layer is a self-aligned blocking silicon oxide layer, and the sacrificial blocking layer is a self-aligned silicon nitride layer or a self-aligned silicon nitride oxide layer.

7. The contact hole forming method according to claim 6, characterized in that: When removing the sacrificial barrier layer in the pixel area, hot phosphoric acid etching is specifically used.

8. The contact hole forming method according to claim 6, wherein: When removing the remaining compensation layer at the junction of the pixel area and the logic area, hydrofluoric acid DHF is specifically used to clean the remaining compensation layer at the junction below the negative photoresist layer.

9. An image sensor, characterized in that: The contact holes of the pixel area and the logic area are prepared by using the contact hole forming method described in any one of claims 1 to 8.

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