Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a display area and a non-display area adjacent to the display area. The display panel further comprises a substrate, a first conductive layer, a packaging layer and a protection part. The first conductive layer comprises a signal line arranged on the substrate, the signal line is at least arranged in the non-display area, and the signal line comprises a top surface far away from one side of the substrate and a side surface connected to the top surface; the packaging layer is arranged on the side, away from the substrate, of the first conductive layer, the packaging layer is located in the display area and extends to the non-display area, and the packaging layer and the signal lines have overlapped parts in the thickness direction of the display panel; the protection part covers the side surface; wherein the orthographic projection of the protection part on the substrate is partially overlapped with the orthographic projection of the packaging layer on the substrate; the display panel can prevent the side surface of the signal line from forming a water vapor invasion channel due to side etching, can reduce the probability of packaging failure of the display panel, improves the stability of the display panel, and prolongs the service life of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display devices are widely used in various fields because of their light weight, wide viewing angle, fast response, low-temperature resistance, high luminous efficiency, and the ability to fabricate flexible curved display screens.

[0003] In an OLED display panel, signal traces usually extend from the non-display area to the display area for signal input, such as VDD signal traces and VSS signal traces. However, currently, a stacked metal film is often used to form the signal traces, such as Ti / Al / Ti. Since the materials of the stacked metal film are different, the etching characteristics of different metal films are different. As a result, in subsequent processes, some metal films in the signal traces are prone to side etching under the action of the etching solution, forming an undercut opening, and then forming a water vapor intrusion channel, which easily causes the display panel to have a packaging failure phenomenon, thereby reducing the stability and service life of the display panel. Summary of the Invention

[0004] Embodiments of this application provide a display panel and a display device, which can reduce the probability of packaging failure of the display panel and improve the stability and service life of the display panel.

[0005] To achieve the above object, an embodiment of this application provides a display panel. The display panel includes a display area and a non-display area adjacent to the display area. The display panel further includes:

[0006] A substrate;

[0007] A first conductive layer, including signal lines disposed on the substrate, the signal lines being disposed at least in the non-display area, the signal lines including a top surface on a side away from the substrate and a side surface connected to the top surface;

[0008] A packaging layer, disposed on a side of the first conductive layer away from the substrate, the packaging layer being located in the display area and extending to the non-display area, and the packaging layer and the signal lines having an overlapping portion in the thickness direction of the display panel;

[0009] A protection part, covering the side surface;

[0010] Wherein, a positive projection of the protection part on the substrate partially overlaps with a positive projection of the packaging layer on the substrate.

[0011] In an embodiment of the present application, the signal line includes a first line segment, the first line segment is within the coverage of the encapsulation layer, and the protection part covers at least the side surface of the first line segment.

[0012] In an embodiment of the present application, the signal line further includes a second line segment connected to at least one end of the first line segment, and a first undercut opening is formed at the side surface of the second line segment.

[0013] In an embodiment of the present application, the signal line includes a first sub-layer, a second sub-layer, and a third sub-layer stacked, and the second sub-layer is located between the first sub-layer and the third sub-layer;

[0014] At the second line segment, the edge of the second sub-layer is retracted towards the center of the second sub-layer relative to the edges of the first sub-layer and the third sub-layer to form the first undercut opening.

[0015] In an embodiment of the present application, a second undercut opening is formed at the side surface of the first line segment near the end connected to the second line segment.

[0016] In an embodiment of the present application, the protection part also covers one side of the top surface near the side surface.

[0017] In an embodiment of the present application, the display panel further includes:

[0018] A flat layer disposed between the first conductive layer and the encapsulation layer;

[0019] A pixel definition layer disposed between the flat layer and the encapsulation layer, the pixel definition layer includes a barrier rib disposed in the non-display area, and part of the barrier rib is located on the side of the signal line away from the substrate;

[0020] A second conductive layer disposed between the flat layer and the pixel definition layer, the second conductive layer includes an anode disposed in the display area and the protection part.

[0021] In an embodiment of the present application, the pixel definition layer covers the edge of the anode;

[0022] The material of the anode includes metal oxide and silver, and the material of the protection part includes a crystalline material of metal oxide.

[0023] In an embodiment of the present application, the signal line includes a VDD power signal line and / or a VSS power signal line.

[0024] For the above object of the present application, an embodiment of the present application further provides a display device, and the display device includes the display panel.

[0025] The present application provides a display panel and a display device. By providing a protection part on the side surface of a signal line, and the protection part overlapping with the encapsulation layer, the side surface of the signal line can be covered and protected, so as to avoid the formation of a water vapor intrusion channel on the side surface of the signal line due to side etching, reduce the probability of water vapor intruding into the display panel to damage the device, reduce the probability of encapsulation failure of the display panel, and improve the stability and service life of the display panel.

[0026] Other features and advantages of the present application will be described in detail in the following specific implementation part. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative efforts.

[0028] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, where the same reference numerals represent the same parts in the following description.

[0029] Figure 1 It is a schematic plan view of a display panel provided for an embodiment;

[0030] Figure 2 For Figure 1 a schematic cross-sectional structure diagram taken along line aa in;

[0031] Figure 3 It is a schematic structure diagram of a display panel provided for an embodiment of the present application;

[0032] Figure 4 It is a first schematic plan view of a display panel provided for an embodiment of the present application;

[0033] Figure 5 For an embodiment of the present application Figure 4 a schematic cross-sectional structure diagram taken along line AA in;

[0034] Figure 6 It is a second schematic plan view of a display panel provided for an embodiment of the present application;

[0035] Figure 7 For an embodiment of the present application Figure 6 a schematic cross-sectional structure diagram taken along line BB in;

[0036] Figure 8 For an embodiment of the present applicationFigure 6 A schematic cross-sectional structure diagram taken along line CC;

[0037] Figure 9 The third planar distribution schematic diagram of the display panel provided by the embodiment of the present application;

[0038] Figure 10 The fourth planar distribution schematic diagram of the display panel provided by the embodiment of the present application;

[0039] Figure 11 and Figure 12 The schematic diagram of the manufacturing process structure of the protection part in the display panel provided by the embodiment of the present application.

[0040] Explanation of reference numerals:

[0041] 1. Array substrate; 1a. Display area; 1b. Non-display area; 2. Signal trace; 3. Undercut opening;

[0042] 10. Substrate; 101. Display area; 102. Non-display area; 11. Flat layer; 12. Light-emitting device layer; 121. Anode; 122. Light-emitting part; 123. Cathode; 13. Cover plate;

[0043] 20. First conductive layer; 21. Signal line; 201. Top surface; 202. Side surface; 211. First line segment; 212. Second line segment; 213. First sub-layer; 214. Second sub-layer; 215. Third sub-layer; 210. First undercut opening; 220. Second undercut opening;

[0044] 30. Encapsulation layer;

[0045] 40. Protection part; 41. First material layer; 42. Second material layer; 43. Third material layer; 420. Silver oxide layer; 430. Oxide crystal layer;

[0046] 50. Pixel definition layer; 51. Barrier wall; 52. Pixel barrier wall. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0048] Please refer to Figure 1 and Figure 2, the display panel includes a display area 1a, a non-display area 1b adjacent to the display area 1a, and signal traces 2 disposed at least on the array substrate 1 and within the non-display area 1b. The signal traces 2 can extend into the display area 1a and be connected to pixel circuits within the display area 1a. For example, the signal traces 2 can be VDD signal traces and VSS signal traces. Among them, the signal traces 2 are often formed by a stacked metal film, such as Ti / Al / Ti. Due to different materials in the stacked metal film, the etching characteristics of different metal films are different. Consequently, in subsequent manufacturing processes, some metal films in the signal traces 2 are prone to side etching under the action of the etching solution, forming undercut openings 3, thereby forming a water vapor intrusion channel, which easily causes the display panel to exhibit a packaging failure phenomenon, thereby reducing the stability and service life of the display panel.

[0049] Please refer to Figure 3 and Figure 4 , an embodiment of the present application provides a display panel. The display panel includes a display area 101 and a non-display area 102 adjacent to the display area 101. The display panel further includes a substrate 10, a first conductive layer 20, a packaging layer 30, and a protection portion 40.

[0050] The first conductive layer 20 includes signal lines 21 disposed on the substrate 10. The signal lines 21 are disposed at least within the non-display area 102. The signal lines 21 include a top surface 201 on a side away from the substrate 10 and a side surface 202 connected to the top surface 201. The packaging layer 30 is disposed on a side of the first conductive layer 20 away from the substrate 10. The packaging layer is located in the display area 101 and extends into the non-display area 102, and the packaging layer 30 and the signal lines 21 have an overlapping portion in the thickness direction of the display panel. The protection portion 40 covers the side surface 202.

[0051] Among them, the orthographic projection of the protection portion 40 on the substrate 10 partially overlaps with the orthographic projection of the packaging layer 30 on the substrate 10.

[0052] During the implementation and application process, in the embodiment of the present application, by disposing the protection portion 40 on the side surface 202 of the signal lines 21, and the protection portion 40 partially overlaps with the packaging layer 30, the side surface 202 of the signal lines 21 can be covered and protected, so as to avoid the formation of a water vapor intrusion channel due to side etching on the side surface 202 of the signal lines 21, which can reduce the probability of water vapor invading the interior of the display panel and damaging the devices, and can reduce the probability of the display panel having a packaging failure, and improve the stability and service life of the display panel.

[0053] Specifically, please continue to combine Figure 3 , Figure 4 andFigure 5 , the display panel includes a display area 101 and a non-display area 102 adjacent to the display area 101. A plurality of pixel units are provided in the display area 101, and a driving circuit, signal traces, driving components, etc. can be provided in the non-display area 102.

[0054] In some embodiments, the display panel further includes a planarization layer 11 provided on the substrate 10, a pixel definition layer 50 provided on a side of the planarization layer 11 away from the substrate 10, a light-emitting device layer 12 provided on a side of the planarization layer 11 away from the substrate 10 and within the display area 101, a signal line 21 provided on the substrate 10 and at least within the non-display area 102, and a packaging layer 30 provided in the display area 101 and extending into the non-display area 102. The packaging layer 30 covers the light-emitting device layer 12 and at least a part of the signal line 21. The display panel further includes a cover plate 13 provided on a side of the packaging layer 30 away from the substrate 10.

[0055] In some embodiments, the display panel further includes a thin-film transistor layer (not shown in the figure) provided in the display area 101 and the non-display area 102, and the functional layer 11 is located on a side of the thin-film transistor layer away from the substrate 10. Among them, the signal line 21 can be located in the thin-film transistor layer, or the signal line 21 can also be located in a conductive layer on a side of the thin-film transistor layer 20 away from the substrate 10. This is not limited herein. In the embodiments of the present application, taking the signal line 21 being located in the conductive layer on a side of the thin-film transistor layer 20 away from the substrate 10 as an example for illustration, and further the signal line 21 is located on a side of the thin-film transistor layer away from the substrate 10.

[0056] In some embodiments, the substrate 10 can be a rigid substrate, such as a glass substrate; or, the substrate 10 can be a flexible substrate. For example, the substrate 10 can be a substrate formed of polyimide. When the substrate is a flexible substrate, the substrate 10 can be formed by multiple sub-substrates of the same material such as polyimide, and adjacent sub-substrates are bonded by a bonding sub-layer.

[0057] In some embodiments, the thin film transistor layer includes thin film transistors. The thin film transistors include a semiconductor located on the substrate, and the semiconductor can be formed of polysilicon or metal oxide (such as indium gallium zinc oxide). Among them, the semiconductor is divided into a channel region, a source region formed on both sides of the channel region, and a drain region. The thin film transistor layer further includes a first gate insulating layer that covers the semiconductor. The thin film transistor further includes a first gate formed on the first gate insulating layer, and the first gate overlaps with the channel region. The first gate can be formed to include multiple layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high anti-corrosion performance. The thin film transistor layer further includes a second gate insulating layer that covers the first gate. The thin film transistor further includes a second gate located on the second gate insulating layer, and the second gate overlaps with the first gate. The second gate can be formed to include multiple layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high anti-corrosion performance. The thin film transistor layer further includes a first interlayer insulating layer formed on the second gate. Among them, the first interlayer insulating layer, the first gate insulating layer, and the second gate insulating layer include a source contact hole and a drain contact hole, and the source region and the drain region are respectively exposed through the source contact hole and the drain contact hole.

[0058] The thin film transistor further includes a source and a drain disposed on the same layer. The source and the drain are both formed on the first interlayer insulating layer. The source passes through the source contact hole and is connected to the source region, and the drain passes through the drain contact hole and is connected to the drain region. Among them, the source and the drain can be formed of multiple layers or a single layer of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high anti-corrosion performance. For example, the source and the drain can be a triple layer such as Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti, or Mo / Al / Mo, or other single-layer or multi-layer structures.

[0059] It should be noted that the pixel unit can include a pixel driving circuit, and the pixel driving circuit can include multiple thin film transistors to control signal transmission; the driving circuit can also include multiple thin film transistors to control the signal to be input from the non-display area 102 into the pixel driving circuit.

[0060] In some embodiments, the display panel further includes a first conductive layer 20 disposed on a side of the thin film transistor layer away from the substrate 10. The first conductive layer 20 may include a jumper wire disposed in the display area 101 and at least a signal line 21 located in the non-display area 102. Wherein, the jumper wire may be connected to the thin film transistor in the pixel driving circuit, and the signal line 21 may be used to transmit signals to the pixel units in the display area 101. For example, the signal line 21 may include a VDD power signal line and / or a VSS power signal line. Further, the signal line 21 may extend from the non-display area 102 to the display area 101 and be electrically connected to the pixel driving circuit to transmit a VDD power signal and / or a VSS power signal.

[0061] In some embodiments, the planarization layer 11 is disposed on a side of the thin film transistor layer away from the substrate 10, and the planarization layer 11 is disposed in the display area 101. The planarization layer may include a plurality of planarization sub-layers, and the jumper wire may be located between adjacent planarization sub-layers.

[0062] It can be understood that the planarization layer 11 is formed of an organic material and has a poor water and oxygen barrier effect. Therefore, a part of the planarization layer 11 in the non-display area 102 may be removed to improve the water and oxygen barrier ability of the display panel.

[0063] In some embodiments, the display panel further includes a pixel definition layer 50 disposed in the display area 101 and the non-display area 102. The pixel definition layer 50 is disposed on a side of the planarization layer 11 away from the substrate 10 and includes a pixel barrier 52 disposed in the display area 101 and a barrier 51 disposed in the non-display area 102. Wherein, the pixel units enclose to form a plurality of pixel openings, and the barrier 51 surrounds the display area 101.

[0064] In some embodiments, the light emitting device layer 12 may include a plurality of anodes 121, a plurality of light emitting portions 122, and a cathode 123. The plurality of anodes 121 are disposed on the planarization layer 11, and the plurality of anodes 121 are disposed corresponding to the plurality of pixel openings. The pixel openings expose the surface of the corresponding anode 121 on a side away from the planarization layer 11. The plurality of light emitting portions 122 are disposed corresponding to the plurality of pixel openings and on the anodes 121 in the corresponding pixel openings. The cathode 123 covers the pixel definition layer 50 and extends to the pixel openings on a side of the light emitting portion 122 away from the anode 121.

[0065] Among them, the anode 121 can pass through the flat layer 11 and be connected to the transfer wire, and then the anode 121 can be connected to the thin film transistor through the transfer wire to achieve signal transmission.

[0066] Furthermore, the encapsulation layer 30 covers the display area 101 and extends to the non-display area 102. The encapsulation layer 30 can cover the light-emitting device layer 12, the barrier wall 51, and at least part of the signal line 21.

[0067] In some embodiments, the encapsulation layer 30 may include an inorganic encapsulation layer and an organic encapsulation layer arranged in a stacked manner, and the coverage boundary of the organic encapsulation layer stops at one side of the barrier wall 51 close to the display area 101. The inorganic encapsulation layer can cover the organic encapsulation layer and the barrier wall 51.

[0068] It should be noted that the encapsulation layer 30 can cover one side of the signal line 21 close to the display area 101; among them, in the manufacturing process of the display panel, when forming a plurality of the anodes 121, an etching solution is used to pattern the anode material layer to form a plurality of the anodes 121, and the signal line 21 is formed before the plurality of the anodes 121, and thus will also be affected by the etching solution, which easily causes undercut openings to be formed on the side surface of the signal line 21 due to side etching, and then a water vapor intrusion conduction will be formed, resulting in encapsulation failure.

[0069] In the embodiments of the present application, the signal line 21 includes a top surface 201 on a side away from the substrate 10 and a side surface 202 connected to the top surface 201. The display panel further includes a protection part 40 covering the side surface 202, and the protection part 40 partially overlaps with the encapsulation layer 30, and thus can cover and protect the side surface 202 of the signal line 21 to prevent a water vapor intrusion channel from being formed on the side surface 202 of the signal line 21 due to side etching within the coverage range of the encapsulation layer 30, which can reduce the probability of water vapor intruding into the interior of the display panel to damage the device, and can reduce the probability of the display panel having encapsulation failure, and improve the stability and service life of the display panel.

[0070] Among them, the protection part 40 covers the side surface 202, that is, the protection part 40 can cover the entire side surface 202 or cover a part of the side surface 202.

[0071] In some embodiments, the protection part 40 can also cover one side of the top surface 201 close to the side surface 202 to improve the protection effect of the protection part 40 on the side surface 202.

[0072] It should be noted that the flat layer 11 is disposed between the first conductive layer 20 and the encapsulation layer 30, and the pixel definition layer 50 is disposed between the flat layer 11 and the encapsulation layer 30. The barrier rib 51 is prepared with the same layer material as the pixel definition layer 50. Thus, a part of the barrier rib 51 is located on the side of the signal line 21 away from the substrate 10. In some embodiments, the barrier rib 51 can be prepared with the same layer material as the flat layer 11 and the pixel definition layer 50 to form a stacked structure. Continuing from the above, since the flat layer 11 is prepared before the anode 121, after the flat layer 11 is formed, the part of the barrier rib 51 belonging to the flat layer 11 will cover the side surface 202 of the signal line 21. Thus, when the anode 121 is etched subsequently, no undercut opening 202 will be generated at the side surface 202 of the part of the signal line 21 covered by the flat layer 11, and thus no water vapor intrusion channel will be formed, which can further improve the water and oxygen barrier ability of the display panel.

[0073] In other embodiments, the barrier rib 51 is prepared with the same layer material as the pixel definition layer 50, that is, the pixel definition layer 50 includes the barrier rib 51. Since the barrier rib 51 is not prepared with the same layer material as the flat layer 11, the barrier rib 51 is formed after the anode 121 is etched and will not provide a protective effect on the side surface 202 of the signal line 21. However, the protection part 40 added in the embodiments of the present application can provide a covering protection effect on the side surface 202 of the signal line 21 to avoid forming a water vapor intrusion channel. Therefore, when the barrier rib 51 is not prepared with the flat layer 11, the display panel requires the setting of the protection part 40 more to effectively improve the encapsulation effect of the display panel.

[0074] In the embodiments of the present application, the signal line 21 includes a first line segment 211. The first line segment 211 is within the coverage of the encapsulation layer 30, and the protection part 40 at least covers the side surface 202 of the first line segment 211. Thus, the water vapor intrusion channel can be blocked at the side surface 202 of the first line segment 211 to prevent water vapor from invading the interior of the display panel.

[0075] In some embodiments, the signal line 21 includes a first sub-layer 213, a second sub-layer 214, and a third sub-layer 215 that are stacked. The second sub-layer 214 is located between the first sub-layer 213 and the third sub-layer 215, and the first sub-layer 213 is located between the second sub-layer 214 and the substrate 10. Among them, the material of the second sub-layer 214 is more easily etched relative to the materials of the first sub-layer 213 and the third sub-layer 215. For example, the material of the second sub-layer 214 can be aluminum, and the materials of the first sub-layer 213 and the third sub-layer 215 can be titanium.

[0076] As Figure 5 shown, since the protection part 40 covers the side surface 202 of the signal line 21, it can isolate the side surface 202 from contact with the etching solution, prevent the second sub-layer 214 from being etched to produce an undercut opening, and avoid the generation of a water vapor intrusion channel.

[0077] Please refer to Figure 6 、 Figure 7 and Figure 8 In some embodiments of the present application, the signal line 21 includes a first line segment 211 and a second line segment 212 that are connected. The first line segment 211 can be located in the non-display area 102 and covered by the encapsulation layer 30, and the second line segment 212 is located in the non-display area 102 and outside the coverage of the encapsulation layer 30, and the second line segment 212 can be connected to one end of the first line segment 211 away from the display area 101.

[0078] The protection part 40 covers the side surface 202 of the first line segment 211. Thus, the protection part 40 can protect the side surface 202 of the first line segment 211, but cannot protect the side surface 202 of the second line segment 212. Therefore, a first undercut opening 210 is formed at the side surface 202 of the second line segment 212, and the first undercut opening 210 extends along the side surface 202 of the second line segment 212 in the direction of the display area 101. However, since the side surface 202 of the first line segment 211 is covered by the protection part 40, the first undercut opening 210 stops at the first line segment 211 and cannot extend into the display area 101.

[0079] Among them, at the second line segment 212, the edge of the second sub-layer 214 is retracted inward relative to the edges of the first sub-layer 213 and the third sub-layer 215 in the direction towards the center of the second sub-layer 214 to form the first undercut opening 210, as Figure 7 shown.

[0080] It should be noted that a second undercut opening 220 is formed on the side surface 202 of the first line segment 211 near one end of the second line segment 212, as Figure 8 shown; wherein, when side etching occurs at the side surface 202 of the second line segment 212, since the side of the first line segment 211 close to the second line segment 212 will also come into contact with the etching solution, therefore, side etching may also occur on the side of the first line segment 211 close to the second line segment 212, and then a second undercut opening 220 will be formed at the side surface 202 of the first line segment 211 near one end of the second line segment 212; however, since the protection part 40 covers the side surface 202 of the first line segment 211, the contact area between the first line segment 211 and the etching solution is limited, and the extension distance of the second undercut opening 220 is small, and it only exists at one end of the first line segment 211 close to the second line segment 212.

[0081] As Figure 5 shown, Figure 5 It can also be Figure 6 the schematic cross-sectional structure diagram taken along line DD in, on the side of the first line segment 211 away from the second line segment 212, due to the coverage of the protection part 40, no undercut opening will be generated at the side surface 202 of the first line segment 211, and thus no water vapor intrusion channel will be generated either.

[0082] It can be understood that in the Figure 4 and Figure 6 shown embodiments, the signal lines 21 located in the non-display area 101 and covered by the encapsulation layer 30 are all located on the first line segment 211, and the signal lines 21 not covered by the encapsulation layer 30 are the second line segment 212.

[0083] In another embodiment of the present application, please refer to Figure 9 , the first line segment 211 is the signal line 21 located in the non-display area 102, that is, all the signal lines 21 located in the non-display area 102 are the first line segment 211, the protection part 40 covers the side surface 202 of the first line segment 211, and the side surface 202 of the signal lines 21 located in the non-display area 102 is covered with the protection part 40, so as to reduce the probability of generating a water vapor intrusion channel to the greatest extent.

[0084] In yet another embodiment of the present application, please refer to Figure 10, the signal line 21 includes a first line segment 211 and a second line segment 212 connected to each other. The first line segment 211 may be located within the non-display area 102 and covered by the encapsulation layer 30. The second line segment 212 is connected to opposite ends of the first line segment 211. The second line segment 212 connected to the end of the first line segment 211 close to the display area 101 is covered by the encapsulation layer 30, and the second line segment 212 connected to the end of the display area 101 far from the display area 101 is located outside the coverage of the encapsulation layer 30.

[0085] Wherein, the first undercut opening 210 is formed at the side surface 202 of the second line segment 212, and no undercut opening is formed at the side surface 202 corresponding to the position of the first line segment 211 far from the second line segment 212. Therefore, the first undercut opening 210 on the side of the first line segment 211 far from the display area 101 will be blocked by the first line segment 211, and thus water vapor cannot invade the display panel through the first undercut opening 210 on the side of the first line segment 211 far from the display area 101; the first undercut opening 210 on the side of the first line segment 211 close to the display area 101 is covered by the encapsulation layer 30 and does not contact the outside world, so no water vapor invasion channel will be formed either.

[0086] It should be noted that in Figure 10 the illustrated embodiment, both the end of the first line segment 211 close to the display area 101 and the end far from the display area 101 are connected to the second line segment 212. Therefore, the second undercut opening 220 may be formed at the corresponding side surface 202 at both the end of the first line segment 211 close to the display area 101 and the end far from the display area 101.

[0087] Furthermore, the protection part 40 in the embodiment of the present application needs to be formed at least in the same process as the anode 121 or before the anode 121 to avoid the side surface 202 of the signal line 21 being etched by the etching solution of the anode 121.

[0088] Please refer to Figure 3 , Figure 5 , Figure 11 and Figure 12 . In some embodiments, the display panel includes a second conductive layer disposed between the planarization layer 11 and the pixel definition layer 50, and the second conductive layer includes the anode 121 and the protection part 40, that is, the protection part 40 is prepared using the same layer metal as the anode 121.

[0089] In some embodiments, the anode 121 may adopt a laminated structure of three metal films. Further, the material of the anode 121 may include metal oxides and silver, while the material of the protection part 40 may include a crystalline material of metal oxides.

[0090] Specifically, the anode 121 includes two metal oxide layers and a silver layer located between the two metal oxide layers, and the protection intermediate in the manufacturing process of the protection part 40 may include the stacked first material layer 41, second material layer 42, and third material layer 43. The second material layer 42 is a silver layer, and the first material layer 41 and the third material layer 43 are metal oxide layers; wherein, the metal oxide layer may be indium tin oxide.

[0091] When forming a plurality of the anodes 121, a protection intermediate will be formed on the side surface 202 of the signal line 21 at the same time.

[0092] Then, the pixel definition layer 50 is formed on the second conductive layer, and a plurality of the anodes 121 are located between the flat layer 11 and the pixel definition layer 50, and the pixel definition layer 50 covers the edges of the anodes 121.

[0093] During the baking process of the pixel definition layer 50, nitrogen and air can be added for baking; wherein, the second material layer 42 in the protection intermediate is a silver layer, which will be oxidized during the baking process to form a silver oxide layer 420, and the first material layer 41 and the third material layer 43 will crystallize during the baking process to respectively form the protection part 40 and an oxide crystal layer 430.

[0094] It should be noted that since the edges of the anode 121 are covered by the pixel definition layer 50, the side surfaces of the anode 121 will not contact with oxygen in the air and thus will not be oxidized.

[0095] Then, the silver oxide layer 420 can be removed by etching, and the oxide crystal layer 430 located on the silver oxide layer 420 will also be removed together. However, the protection part 40 will be retained to cover the side surface 202 of the signal line 21, and thus the material of the protection part 40 can be a crystalline material of metal oxides.

[0096] In other embodiments of the present application, the protection part 40 can be prepared using other materials. For example, before forming the anode 121, an organic or inorganic material can be used to cover the side surface 202 of the signal line 21 to prevent the signal line 21 from being side-etched during the etching of the anode 121.

[0097] In summary, in the embodiment of the present application, the protection portion 40 is provided on the side surface 202 of the signal line 21, and the protection portion 40 partially overlaps with the encapsulation layer 30. Thus, the side surface 202 of the signal line 21 can be covered and protected to avoid the formation of a water vapor intrusion channel on the side surface 202 of the signal line 21 due to side etching, which can reduce the probability of water vapor invading into the display panel to damage the device, and can reduce the probability of encapsulation failure of the display panel, improving the stability and service life of the display panel.

[0098] In addition, the embodiment of the present application further provides a display device, and the display device includes the display panel described in the above embodiment.

[0099] It can be understood that since the display device has the same display panel as that in the above embodiment, the display device has the same beneficial effects as the display panel, which will not be elaborated herein.

[0100] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0101] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not elaborated in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0102] In the embodiments, embodiments, and related technical features of the present application, they can be combined and replaced with each other without conflict.

[0103] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. However, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area adjacent to the display area, and the display panel further includes: substrate; A first conductive layer, comprising a signal line disposed on the substrate, wherein the signal line is disposed at least in the non-display area, and the signal line comprises a top surface away from a side of the substrate and a side surface connected to the top surface; an encapsulation layer, disposed on a side of the first conductive layer away from the substrate, the encapsulation layer being located in the display area and extending to the non-display area, and the encapsulation layer and the signal line having an overlapping portion along a thickness direction of the display panel; A protection portion, covering the side surface; The orthographic projection of the protection portion on the substrate partially overlaps with the orthographic projection of the packaging layer on the substrate.

2. The display panel according to claim 1, characterized in that: The signal line includes a first line segment, the first line segment is located within the coverage range of the packaging layer, and the protection portion at least covers the side surface of the first line segment.

3. The display panel according to claim 2, characterized in that: The signal line further includes a second line segment connected to at least one end of the first line segment, and a first undercut opening is formed at the side surface of the second line segment.

4. The display panel according to claim 3, characterized in that: The signal line includes a first sublayer, a second sublayer and a third sublayer which are stacked, and the second sublayer is located between the first sublayer and the third sublayer; At the second line segment, the edge of the second sub-layer is retracted inwardly toward the center of the second sub-layer relative to the edge of the first sub-layer and the edge of the third sub-layer to form the first undercut opening.

5. The display panel according to claim 3, characterized in that: A second undercut opening is formed at the side surface of the first line segment close to one end of the second line segment.

6. The display panel according to claim 1, characterized in that: The protection portion also covers a side of the top surface close to the side surface.

7. The display panel according to any one of claims 1 to 6, characterized in that: The display panel further includes: A planar layer, disposed between the first conductive layer and the packaging layer; A pixel definition layer is disposed between the planar layer and the encapsulation layer, wherein the pixel definition layer includes a retaining wall disposed in the non-display area, and a portion of the retaining wall is located on a side of the signal line away from the substrate; The second conductive layer is arranged between the planar layer and the pixel definition layer, and the second conductive layer includes an anode arranged in the display area and the protection part.

8. The display panel according to claim 7, characterized in that: The pixel definition layer covers the edge of the anode; The material of the anode includes metal oxide and silver, and the material of the protection portion includes a crystalline material of the metal oxide.

9. The display panel according to any one of claims 1 to 6, characterized in that: The signal line includes a VDD power signal line and / or a VSS power signal line.

10. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 9.

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