Display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel and electronic equipment, and relates to the technical field of display. In the display panel, data signal wires and reset signal wires are arranged between power signal wires of corresponding pixels, and due to the fact that the two opposite sides of the data signal wires and the reset signal wires have similar wire layouts, in the process of forming the data signal wires and the first reset signal wires in a patterning mode, the data signal wires and the first reset signal wires are arranged in a staggered mode. According to the embodiment of the invention, two opposite sides of the data signal line and the first reset signal line can be uniformly etched, so that the line with uniform line width is formed, and the problem of line breakage caused by non-uniform etching when the data signal line and / or the first reset signal line are arranged at the edge of the pixel unit due to the existence of the light-transmitting opening is avoided; and the display panel is ensured to have a good display effect.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and more particularly, to a display panel and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) is considered to be the next-generation display technology after liquid crystal display technology. It has been widely used in various consumer electronic products such as smart phones, TVs, laptop computers, desktop computers, in-vehicle displays, and wearable devices due to its excellent color and image quality, and has become the mainstream technology in display panels.

[0003] In the preparation process of traditional display panels, the light-emitting pixel patterning is usually achieved through a Fine Metal Mask (FMM). The FMM technology is mature and has rich mass production experience. However, the FMM technology also has problems such as limited precision, high development cost, and long development cycle. The fine metal maskless technology eliminates the limitations of traditional OLED processes on display screen size, resolution, and other screen body performances, and has the advantages of high performance, full-domain size, and agile delivery. Patents CN118251982A, CN116648095A, CN117062489A, CN118742138A, CN118678783A, CN118660598A, CN118675450A, CN118824188A, CN118781966A record the relevant content of the fine metal maskless technology for reference.

[0004] However, the process performance of current OLED display products still needs to be further improved. Summary of the Invention

[0005] In order to overcome the technical problems mentioned in the above technical background, the present application provides a display panel and an electronic device.

[0006] In a first aspect of the present application, a display panel is provided, and the display panel further includes:

[0007] A substrate;

[0008] An array trace layer, located on one side of the substrate, and the array trace layer includes a power signal trace, a data signal trace, and a first reset signal trace in which at least part of the trace segments extend in a first direction;

[0009] The light-emitting devices are located on the side of the array wiring layer away from the substrate. Multiple light-emitting devices form a pixel unit. Multiple power signal traces are respectively connected to different light-emitting devices in the pixel unit. Multiple data signal traces respectively provide data signals for different light-emitting devices in the pixel unit. The first reset signal trace provides a reset signal for the light-emitting devices in the pixel unit;

[0010] Among them, for multiple data signal traces and one first reset signal line in the same pixel unit, they are located between two power signal traces corresponding to the same pixel unit.

[0011] In a possible implementation manner of the present application, the line widths of the data signal trace and the first reset signal trace are smaller than the line width of the power signal trace;

[0012] Preferably, the line widths of the data signal trace and the first reset signal trace are greater than or equal to 1.8 μm and less than or equal to 2.6 μm.

[0013] In a possible implementation manner of the present application, the display panel includes a first display area and at least a second display area partially surrounding the first display area. The first display area includes a pixel area and a light-transmitting area located between adjacent pixel areas;

[0014] In the first display area, the pixel unit is located in the pixel area, and the light-transmitting opening is located in the light-transmitting area. There is a first distance between two adjacent light-emitting devices in the same pixel unit, and there is a second distance between two adjacent light-emitting devices in different pixel units. Among them, the first distance is less than the second distance.

[0015] In a possible implementation manner of the present application, the pixel unit includes a first light-emitting device, a second light-emitting device, and a third light-emitting device arranged in sequence and having different light-emitting colors. The power signal traces include a first power signal trace, a second power signal trace, and a third power signal trace respectively connected to the first light-emitting device, the second light-emitting device, and the third light-emitting device. The data signal traces include a first data signal trace, a second data signal trace, and a third data signal trace respectively providing data signals for the first light-emitting device, the second light-emitting device, and the third light-emitting device;

[0016] The first data signal trace and the second data signal trace are located between the adjacent first power signal trace and the second power signal trace. The third data signal trace and the first reset signal trace are located between the adjacent second power signal trace and the third power signal trace;

[0017] Preferably, a third distance is provided between the first data signal trace and the first power signal trace, a fourth distance is provided between the second data signal trace and the second power signal trace, a fifth distance is provided between the first reset signal trace and the second power signal trace, and a sixth distance is provided between the third data signal trace and the third signal trace. The third distance is equal to the fourth distance, and the fifth distance is equal to the sixth distance.

[0018] In a possible implementation manner of the present application, the array trace layer includes a plurality of metal layers stacked in sequence and insulating layers located between adjacent metal layers.

[0019] Preferably, the array trace layer includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer stacked in sequence in a direction away from the substrate. At least a part of the power signal trace is formed by the fourth metal layer, the data signal trace is formed by the fourth metal layer, and the first reset signal trace is formed by the fourth metal layer.

[0020] In a possible implementation manner of the present application, the display panel further includes a second reset signal trace extending in a second direction, where the first direction and the second direction intersect.

[0021] The second reset signal trace and the first reset signal trace are formed by different metal layers, and the first reset signal trace and the second reset signal trace are connected through a wire-changing hole at their overlapping position.

[0022] In the first display area, the orthographic projection of the wire-changing hole on the substrate is located within the orthographic projection of the pixel area on the substrate.

[0023] In a possible implementation manner of the present application, the display panel further includes:

[0024] An isolation structure located on a side of the array trace layer away from the substrate. The isolation structure includes an isolation opening, and at least a part of the light-emitting device is located within the isolation opening.

[0025] In a possible implementation manner of the present application, the isolation structure encloses to form the light-transmitting opening.

[0026] In a possible implementation manner of the present application, the display panel further includes a pixel defining layer. The pixel defining layer is located on a side of the isolation structure facing the array trace layer, and the isolation structure is located on a side of the pixel defining layer away from the substrate.

[0027] The pixel defining layer comprises a pixel opening, the orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the isolation opening on the substrate, and at least part of the light emitting device is located within the pixel opening;

[0028] Preferably, the pixel defining layer is an inorganic pixel defining layer;

[0029] Preferably, the pixel defining layer is a single-layer structure of silicon oxide or silicon nitride, or a stacked-layer structure formed alternately of silicon oxide and silicon nitride.

[0030] In a possible implementation of the present application, in a direction away from the substrate, the light-emitting device includes a first electrode, a light-emitting material layer, and a second electrode which are stacked; wherein the second electrode is connected to the isolation structure;

[0031] The first electrode is disposed on a side of the pixel definition layer close to the substrate, and at least a portion of the first electrode is exposed from the pixel opening;

[0032] Preferably, an orthographic projection of the light emitting device on the substrate does not overlap with an orthographic projection of the light-transmitting opening on the substrate.

[0033] In a possible implementation of the present application, the isolation structure includes a first isolation portion and a second isolation portion that are stacked, the second isolation portion is arranged on a side of the first isolation portion that is away from the substrate, and an orthographic projection of the first isolation portion on the substrate is located within an orthographic projection of the second isolation portion on the substrate;

[0034] Preferably, the second isolation portion is a conductive isolation portion, and the first electrode is connected to the second isolation portion;

[0035] Preferably, the isolation structure further comprises a third isolation portion, and in a direction away from the substrate, the third isolation portion, the first isolation portion and the second isolation portion are stacked in sequence, and the orthographic projection of the first isolation portion on the substrate is located within the orthographic projection of the third isolation portion on the substrate;

[0036] Preferably, the orthographic projection of the third isolation portion on the substrate is located within the orthographic projection of the second isolation portion on the substrate;

[0037] Preferably, the third isolating portion is a conductive isolating portion, and the first electrode is also connected to the third isolating portion;

[0038] Preferably, the material of the first isolation portion includes aluminum, silver or copper, the material of the second isolation portion includes titanium or molybdenum, and the material of the third isolation portion includes molybdenum or titanium.

[0039] In a possible implementation manner of the present application, the display panel further includes a first encapsulation layer, the first encapsulation layer includes a plurality of encapsulation units, and the encapsulation units are used to encapsulate the light-emitting devices in the isolation openings;

[0040] Preferably, the display panel further includes a second encapsulation layer, the second encapsulation layer is located on a side of the encapsulation unit away from the substrate, and the second encapsulation layer at least covers the encapsulation unit;

[0041] Preferably, the second encapsulation layer fills the isolation opening and the light-transmitting opening, and the second encapsulation layer includes a flat surface on a side away from the substrate;

[0042] Preferably, the display panel further includes a third encapsulation layer, and the third encapsulation layer is located on a side of the second encapsulation layer away from the substrate;

[0043] Preferably, the first encapsulation layer and the third encapsulation layer are inorganic encapsulation layers, and the second encapsulation layer is an organic encapsulation layer.

[0044] In a second aspect of the present application, there is also provided a display panel, the display panel includes:

[0045] A substrate;

[0046] An array wiring layer, located on one side of the substrate, the array wiring layer includes a power signal wiring, a data signal wiring, and a first reset signal wiring in which at least part of the wiring segments extend in a first direction;

[0047] An isolation structure, located on a side of the array wiring layer away from the substrate, the isolation structure includes an isolation opening and a light-transmitting opening;

[0048] Light-emitting devices, at least part of which are located in the isolation openings, and a plurality of light-emitting devices form a pixel unit, the light-transmitting opening is located between at least some adjacent pixel units, a plurality of the power signal wirings are respectively connected to different light-emitting devices in the pixel unit, a plurality of data signal wirings respectively provide data signals for different light-emitting devices in the pixel unit, and the first reset signal wiring provides a reset signal for the light-emitting devices in the pixel unit;

[0049] Wherein, for multiple data signal wirings and one first reset signal line in the same pixel unit, they are located between two power signal wirings corresponding to the same pixel unit.

[0050] In a possible implementation manner of the present application, the display panel includes a first display area and at least part of a second display area surrounding the first display area, the first display area includes a pixel area and a light-transmitting area located between adjacent pixel areas;

[0051] In the first display area, the pixel units are located within the pixel area. There is a first distance between two adjacent light-emitting devices in the same pixel unit, and a second distance between two adjacent light-emitting devices in different pixel units, where the first distance is less than the second distance.

[0052] Preferably, in the first display area, the orthographic projection of the light-transmitting opening on the substrate coincides with the orthographic projection of the light-transmitting area on the substrate.

[0053] Preferably, the line widths of the data signal traces and the first reset signal traces are less than the line width of the power signal trace.

[0054] In a third aspect of the present application, an electronic device is further provided, and the electronic device includes the display panel in any possible implementation manner of the first aspect or the second aspect. Description of the Drawings

[0055] To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0056] Figure 1 Schematic diagram of a partial film layer structure of the display panel provided in this embodiment is exemplified;

[0057] Figure 2 Exemplification Figure 1 One of the wiring schematic diagrams of the array trace layer in the exemplification;

[0058] Figure 3 Schematic diagram of the partition of the display panel provided in this embodiment is exemplified;

[0059] Figure 4 Exemplification Figure 3 Distribution schematic diagram of the pixel area and the light-transmitting area in the first display area in the exemplification;

[0060] Figure 5 Exemplification Figure 1 Another wiring schematic diagram of the array trace layer in the exemplification;

[0061] Figure 6 Schematic diagram of the film layer structure of the array trace layer is exemplified;

[0062] Figure 7 Exemplification of Figure 5 Cross-sectional schematic diagram at the AA position in the exemplification;

[0063] Figure 8 Exemplification of Figure 4One of the schematic cross-sectional views at position BB;

[0064] Figure 9 Illustrates Figure 4 Another schematic cross-sectional view at position BB;

[0065] Figure 10 Illustrates a schematic cross-sectional view of an isolation structure;

[0066] Figure 11 Illustrates another schematic cross-sectional view of the isolation structure;

[0067] Figure 12 Illustrates Figure 4 The third schematic cross-sectional view at position BB;

[0068] Figure 13 Illustrates Figure 4 The fourth schematic cross-sectional view at position BB. Detailed implementation manners

[0069] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. The components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations.

[0070] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this application is usually placed when in use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0071] Please refer to Figure 1 and Figure 2 , Figure 1 Illustrates a schematic diagram of a partial film layer structure of a display panel, Figure 2 Illustrates Figure 1 The wiring schematic diagram of the array wiring layer in. In this embodiment, the display panel 1 includes a substrate 11, an array wiring layer 12 and a light-emitting device 13. The array wiring layer 12 is located on one side of the substrate 11. The array wiring layer 12 includes a power signal wiring 12A, a data signal wiring 12B and a first reset signal wiring 12C1 in which at least part of the wiring segments extend in the first direction (Y direction in the figure).

[0072] The light-emitting devices 13 are located on the side of the array trace layer 12 away from the substrate 11. A plurality of light-emitting devices 13 form a pixel unit. Exemplarily, three light-emitting devices 13 with different light-emitting colors can form a pixel unit 30. A plurality of power signal traces 12A are respectively connected to different light-emitting devices 13 in the pixel unit 30 to provide power signals (such as ELVDD signals) for different light-emitting devices 13. A plurality of data signal traces 12B respectively provide data signals (such as Vdata signals) for different light-emitting devices 13 in the pixel unit. The first reset signal trace 12C1 provides a reset signal (such as Vref signal) for the light-emitting devices in the pixel unit. Exemplarily, three light-emitting devices 13 with different light-emitting colors can form a pixel unit 30. Three power signal traces 12A respectively provide power signals for different light-emitting devices 13. Three data signal traces 12B respectively provide data signals for different light-emitting devices 13. One first reset signal trace 12C1 provides a reset signal for the light-emitting devices 13 in the pixel unit 30. The light-transmitting openings are located between some adjacent pixel units 30. Exemplarily, the light-transmitting openings can be located between all adjacent pixel units 30 in the entire display panel 1, or can be located between adjacent pixel units 30 in a local area.

[0073] In this embodiment, among the traces that provide signals for the light-emitting devices 13 in the same pixel unit 30, the data signal trace 12B and the first reset signal trace 12C1 are located between two power signal traces 12A, that is, the multiple data signal traces and one first reset signal trace 12C1 corresponding to the same pixel unit 30 are located between two power signal traces 12A corresponding to the same pixel unit 30.

[0074] In the above solution, the data signal trace 12B and the first reset signal trace 12C1 are arranged between two power signal traces 12A. Since the trace layouts on the relative two sides of the two are similar, during the patterning process of forming the data signal trace 12B and the first reset signal trace 12C1, it can be ensured that the relative two sides of the data signal trace 12B and the first reset signal trace 12C1 can be etched evenly, so as to form traces with uniform line widths, avoiding the problem of trace disconnection caused by uneven etching when the data signal trace 12B and / or the first reset signal trace 12C1 are arranged at the edge of the pixel unit 30 due to the existence of the light-transmitting openings, and ensuring that the display panel 1 has a good display effect.

[0075] Further, in this embodiment, the line widths of the data signal trace 12B and the first reset signal trace 12C1 are smaller than the line width of the power signal trace 12A. Among them, the line widths of the data signal trace 12B and the first reset signal trace 12C1 can be much smaller than the line width of the power signal trace 12A. Exemplarily, the line widths of the data signal trace 12B and the first reset signal trace 12C1 can be comparable, and the line width of the power signal trace 12A can be at least 10 times or more the line widths of the data signal trace 12B and the first reset signal trace 12C1. With such a design, even if the power signal trace 12A is arranged close to the edge of the pixel unit 30 and the wiring on its opposite sides is uneven, the power signal trace 12A will not be etched and disconnected due to uneven etching during the patterning process.

[0076] Optionally, the line width ranges of the data signal trace 12B and the first reset signal trace 12C1 are greater than or equal to 1.8 μm and less than or equal to 2.6 μm. Exemplarily, the line widths of the data signal trace 12B and the first reset signal trace 12C1 include 1.8 μm, 1.85 μm, 1.92 μm, 2.1 μm, 2.23 μm, 2.35 μm, 2.48 μm, or 2.6 μm.

[0077] Further, in the under-screen camera scenario, since the area where the under-screen camera is set needs to increase the light transmittance, a light-transmitting area needs to be added in this area. Please refer to Figure 3 and Figure 4 , the display panel 1 includes a first display area AA1 and a second display area AA2 that at least partially surrounds the first display area AA1. The first display area AA1 includes a pixel area AA11 and a light-transmitting area AA12 located between adjacent pixel areas AA11.

[0078] In the first display area AA1, the pixel unit 30 is located in the pixel area AA11, and the light-transmitting opening 1402 is located in the light-transmitting area AA12. There is a first distance d1 between two adjacent light-emitting devices 13 in the same pixel unit 30, and there is a second distance d2 between two adjacent light-emitting devices 13 in different pixel units. Due to the presence of the light-transmitting opening 1402 in the light-transmitting area AA12, the pitch between adjacent pixel units 30 will be increased, that is, the second distance d2 will be increased, and the first distance d1 will be smaller than the second distance d2. When the thinner signal traces are located at the edge of the pixel unit and the wiring layout on its opposite sides is asymmetric, the traces will be broken due to uneven etching during the patterning process, affecting the display of the display panel. The above solution provided in this embodiment can well solve the above technical problems.

[0079] Further, in this embodiment, please refer to Figure 5, the pixel unit 30 includes a first light-emitting device 13a, a second light-emitting device 13b, and a third light-emitting device 13c that are arranged in sequence and have different light-emitting colors. Exemplarily, the first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c may be a red light-emitting device, a green light-emitting device, and a blue light-emitting device, respectively. The power signal trace 12A includes a first power signal trace 12A1, a second power signal trace 12A2, and a third power signal trace 12A3. Among them, the first power signal trace 12A1 provides a power signal for the first light-emitting device 13a, the second power signal trace 12A2 provides a power signal for the second light-emitting device 13b, and the third power signal trace 12A3 provides a power signal for the first light-emitting device 13c. The data signal trace 12B includes a first data signal trace 12B1, a second data signal trace 12B2, and a third data signal trace 12C. Among them, the first data signal trace 12B1 provides a data signal for the first light-emitting device 13a, the second data signal trace 12B2 provides a data signal for the second light-emitting device 13b, and the third data signal trace 12B3 provides a data signal for the third light-emitting device 13c.

[0080] Exemplarily, the first data signal trace 12B1 and the second data signal trace 12B2 are located between the adjacent first power signal trace 12A1 and the second power signal trace 12A2, and the third data signal trace 12B3 and the first reset signal trace 13c1 are located between the adjacent second power signal trace 12A2 and the third power signal trace 12A3.

[0081] In this embodiment, please refer to Figure 6 , the array trace layer 12 includes a plurality of metal layers stacked in sequence and insulating layers located between adjacent metal layers.

[0082] Optionally, the array trace layer 12 includes a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 stacked in sequence in a direction away from the substrate 11. The power signal trace 12A is at least partially formed by the fourth metal layer M4, the data signal trace 12B is formed by the fourth metal layer M4, and the first reset signal trace 12C1 is formed by the fourth metal layer M4.

[0083] Specifically, the specific film layer structure of the array trace layer 12 will be introduced below in conjunction with Figure 6 for description.

[0084] The array trace layer 12 includes a buffer layer 1203, an active layer 1204, a plurality of metal layers, and insulating layers located between adjacent metal layers, which are stacked in sequence on the substrate 11.

[0085] The buffer layer 1203 is located on one side of the substrate 11, and the active layer 1204 is located on the side of the buffer layer 1203 away from the substrate 11. In this embodiment, the buffer layer 1203 can be formed of an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, etc. In this embodiment, the buffer layer 1203 can be a double-layer structure of a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer formed on the substrate 11 in sequence.

[0086] The active layer 1204 is formed on the buffer layer 1203 and partially covers the buffer layer 1203. The active layer 1204 can be formed of an inorganic semiconductor (such as amorphous silicon or polycrystalline silicon), an organic semiconductor, or an oxide semiconductor. The active layer 1204 can include a source region (S), a drain region (D), and a channel region (P-Si).

[0087] A plurality of metal layers and insulating layers located between adjacent metal layers form a gate insulating layer 1210, a gate 1205, a source electrode 1206, a drain electrode 1207, a first insulating layer 1208, a second insulating layer 1209, and a first capacitor electrode 1211 and a second capacitor electrode 1212 for forming a capacitor.

[0088] The gate insulating layer 1210 is formed on the active layer 1204 and the buffer layer 1203 not covered by the active layer 1204 to insulate and isolate the active layer 1204 and the gate 1205. The gate insulating layer 1210 can be made of materials such as silicon oxide or silicon nitride, but is not limited thereto.

[0089] The gate 1205 is formed on one side of the gate insulating layer 1210 corresponding to the position of the active layer 1204. The gate 1205 can be formed of one or more of metal materials such as Al, Mo, Cu, Ti, or other metals with low resistivity. At the same time, a first capacitor electrode 1211 of the capacitor is also formed on the gate insulating layer 1210. The first capacitor electrode 1211 is formed on the gate insulating layer 1210 and partially covers the gate insulating layer 1210. The material of the first capacitor electrode 1211 and the gate 1205 can be the same. Exemplarily, a first metal layer M1 can be fabricated on the gate insulating layer 1210, and the first capacitor electrode 1211 and the gate 1205 are formed by the first metal layer M1 to achieve the purpose of fabricating the gate 1205 and the first capacitor electrode 1211 simultaneously.

[0090] The first insulating layer 1208 is formed on the gate insulating layer 1210 and covers the gate 1205 and the first capacitive electrode 1211. The second capacitive electrode 1212 is located on the side of the first insulating layer 1208 corresponding to the first capacitive electrode 1211 away from the substrate 11. The orthographic projection of the second capacitive electrode 1212 on the substrate 11 overlaps with the orthographic projection of the first capacitive electrode 1211 on the substrate 11. The first insulating layer 1208 is used to insulate and isolate the gate 1205 from the source 1206 and the drain 1207, and to insulate and isolate the first capacitive electrode 1211 from the second capacitive electrode 1212. The first insulating layer 1208 electrically insulates the gate 1205 from the source 1206 and the drain 1207 respectively, and forms a capacitor between the first capacitive electrode 1211 and the second capacitive electrode 1212. The first insulating layer 1208 can also be formed of inorganic materials such as silicon nitride and silicon oxide. The second capacitive electrode 1212 is located in the second metal layer M2 fabricated above the first insulating layer 1208.

[0091] The second insulating layer 1209 is formed on the first insulating layer 1208 and covers the second capacitive electrode 1212, and is used to isolate the source 1206, the drain 1207 from the second capacitive electrode 1212, so that the source 1206, the drain 1207 and the second capacitive electrode 1212 are insulated from each other. The second insulating layer 1209 can also be formed of inorganic materials (such as silicon nitride and silicon oxide). The structure of the second insulating layer 1209 can be a double-layer or a structure with three or more layers formed by silicon nitride and silicon oxide.

[0092] The source 1206 and the drain 1207 are formed on the second insulating layer 1209. The source 1206 is electrically connected to the source region (S) in the active layer 1204 through a via hole, and the drain 1207 is electrically connected to the drain region (D) in the active layer 1204 through a via hole. The electrode materials of the gate 1205, the source 1206, the drain 1207, the first capacitive electrode 1211, and the second capacitive electrode 1212 can be the same metal such as Al, Mo, Cu, Ti or one or more of other metal materials with low resistivity. The source 1206 and the drain 1207 are located in the third metal layer M3 fabricated on the second insulating layer 1209. In this embodiment, a thin film transistor 120 (Thin Film Transistor, TFT) is formed by the gate 1205, the source 1206, the drain 1207, and the active layer 1204, etc. As Figure 6 shown, a fourth metal layer M4 is further provided on the side of the third metal layer M3 away from the substrate 11.

[0093] In this embodiment, please refer to again Figure 5 and Figure 7, the display panel 1 further includes a second reset signal trace 12C2 that extends at least partially in the second direction (the X direction in the figure), where the first direction and the second direction intersect, and preferably, the first direction and the second direction are perpendicular.

[0094] The second reset signal trace 12C1 and the first reset signal trace 12C2 are formed by different metal layers. Exemplarily, the second reset signal trace 12C2 can be formed by using the first metal layer M1 or the second metal layer M2. The first reset signal trace 12C1 and the second reset signal trace 12C2 can be connected through a via hole 201 at their overlapping position. Since the first reset signal trace 12C1 is located between two power signal traces 12A, when connecting to the second reset signal trace 12C2 through the via hole 201, the position of the via hole 201 is in the pixel region AA11, that is, in the first display region AA1. The orthographic projection of the via hole 201 on the substrate 11 is within the orthographic projection of the pixel region AA11 on the substrate 11. With such a design, it is possible to avoid the via hole 201 being located in the light-transmitting region and reducing the light-transmitting area, ensuring that the light-transmitting region AA12 has good light-transmitting performance.

[0095] Further, please refer to again Figure 7 , there is a third distance d3 between the first data signal trace 12B1 and the first power signal trace 12A1, a fourth distance d4 between the second data signal trace 12B2 and the second power signal trace 12A2, a fifth distance d5 between the first reset signal trace 12C1 and the second power signal trace 12A2, and a sixth distance d6 between the third data signal trace 12B3 and the third power signal trace 12A3. The third distance d3 and the fourth distance d4 are equal, and the fifth distance d5 and the sixth distance d6 are equal. With such a design, it is possible to make the relative sides of the first data signal trace 12B1 and the second data signal trace 12B2 have a symmetric trace distribution, and the relative sides of the first reset signal trace 12C1 and the third data signal trace 12B3 also have a symmetric trace distribution, so as to ensure that when etching to form the above traces, these traces have a uniform line width. Exemplarily, the third distance d3, the fourth distance d4, the fifth distance d5, and the sixth distance d6 can also be equal.

[0096] Please refer to Figure 8 , the display panel 1 provided in this embodiment further includes an isolation structure 14. The isolation structure 14 is located on the side of the array trace layer 12 away from the substrate 11. The isolation structure 14 includes an isolation opening 1401, and at least part of the light-emitting device 13 is located within the isolation opening 1401.

[0097] Further, the light-transmitting opening 1402 can be formed by enclosing with the isolation structure 14. In the first display area AA1, the orthographic projection of the light-transmitting opening 1402 on the substrate 11 coincides with the orthographic projection of the light-transmitting area AA12 on the substrate 11. By removing the corresponding isolation structure 14 at the position of the light-transmitting area AA12 to form the light-transmitting opening 1402, the light-transmitting performance of the first display area AA1 can be increased, which is beneficial to the implementation of the under-screen camera solution.

[0098] Furthermore, please refer to Figure 9 , the display panel 1 further includes a pixel definition layer 15. The pixel definition layer 15 is located on one side of the substrate 11, and the isolation structure 15 is located on the side of the pixel definition layer 14 away from the substrate 11. The pixel definition layer 15 includes a plurality of pixel openings 1501. In this embodiment, the pixel definition layer 15 can be an organic pixel definition layer or an inorganic pixel definition layer. Preferably, the pixel definition layer 15 is an inorganic pixel definition layer. When the pixel definition layer 15 is an inorganic pixel definition layer, the pixel definition layer 15 can be a single-layer structure of silicon oxide (SiOx) or silicon nitride (SiNx), or a stacked structure formed by alternating silicon oxide and silicon nitride.

[0099] In this embodiment, the pixel opening 1501 communicates with the corresponding isolation opening 1401. Exemplarily, the orthographic projection of the pixel opening 1501 on the substrate 11 is located within the orthographic projection of the isolation opening 1401 on the substrate 11. At least part of the light-emitting device 13 is located within the corresponding pixel opening 1501.

[0100] Further, please refer to Figure 9 again. In the direction away from the substrate 11 (the Z direction in the figure), the light-emitting device 13 includes a first electrode 131, a light-emitting material layer 132, and a second electrode 133 stacked. The first electrode 131 is located on the side of the pixel definition layer 15 facing the substrate 11, and the pixel opening 1501 exposes part of the first electrode 131. The second electrode 133 is connected to the isolation structure 15. Exemplarily, the second electrode 133 is connected to the isolation structure 15 by a lap joint method. The first electrode 131 can be connected to a thin-film transistor formed in the array wiring layer. In this embodiment, the first electrode 131 can be the anode of the light-emitting device 13, and the second electrode 133 can be the cathode of the light-emitting device 13.

[0101] Further, please refer to Figure 10The isolation structure 14 includes a first isolation portion 141 and a second isolation portion 142 which are stacked in sequence. The orthographic projection of the first isolation portion 141 on the substrate 11 is located within the orthographic projection of the second isolation portion 142 on the substrate 11. The second isolation portion 142 extends toward the corresponding isolation opening 1401 relative to the first isolation portion 141. In a cross section perpendicular to the plane where the substrate 11 is located and passing through the center of the isolation opening 1401, the cross section of the isolation structure 14 may be T-shaped. The first isolation portion 141 is a conductive isolation portion, and the second electrode 133 may also be electrically connected to the first isolation portion 141. Exemplarily, the second electrode 133 is electrically connected by overlapping with the first isolation portion 141.

[0102] For further information, please refer to Figure 11 In this embodiment, the isolation structure 14 further includes a third isolation portion 143. In the direction away from the substrate 11, the third isolation portion 143, the first isolation portion 141 and the second isolation portion 142 are stacked in sequence. Among them, the orthographic projection of the first isolation portion 141 on the substrate 11 can be located within the orthographic projection of the third isolation portion 143 on the substrate 11. In the cross section perpendicular to the plane where the substrate 11 is located and passing through the center of the isolation opening 1401, the cross section of the isolation structure 14 can be I-shaped. The third isolation portion 143 is a conductive isolation portion, and the second electrode 133 can also be electrically connected to the third isolation portion 143. Exemplarily, the second electrode 133 is electrically connected by overlapping with the third isolation portion 143.

[0103] Optionally, the material of the first isolation portion 141 includes aluminum, silver or copper, the material of the second isolation portion 142 includes titanium or molybdenum, and the material of the third isolation portion 143 includes molybdenum or titanium.

[0104] In this embodiment, please refer to Figure 12 The display panel 1 further includes a first encapsulation layer 161. In the display area AA, the first encapsulation layer 161 includes a plurality of encapsulation units 1611 for encapsulating different light-emitting devices 13. The encapsulation units 1611 are located on a side of the light-emitting device 13 away from the substrate 11. The encapsulation units 1611 extend from the surface of the light-emitting device 13 via the isolation structure 13 toward the sidewall of the isolation opening 1401 to the side of the isolation structure 13 away from the substrate 11. Optionally, two adjacent encapsulation units 1611 for encapsulating light-emitting devices 13 of different colors are disconnected on a side of the isolation structure 13 away from the substrate 11, and a gap exists between the encapsulation units 1611 located on a side of the isolation structure 13 away from the substrate 11 and the isolation structure 13. The orthographic projection of the encapsulation unit 1611 on the substrate 11 is located outside the orthographic projection of the light-transmitting area on the substrate 11. Two adjacent encapsulation units 1611 for encapsulating light-emitting devices 13 of the same color are connected to each other on a side of the isolation structure 13 away from the substrate 11.

[0105] For further information, please refer to Figure 13, the display panel 1 further includes a second encapsulation layer 162. The second encapsulation layer 162 is located on the side of the encapsulation unit 1611 away from the substrate 11. The second encapsulation layer 162 at least covers the encapsulation unit 1611, and the second encapsulation layer 162 fills the isolation opening 1401 and the light-transmitting opening 1402. Optionally, the second encapsulation layer 162 has a flat surface on the side away from the substrate 11.

[0106] Furthermore, the display panel 1 further includes a third encapsulation layer 163. The third encapsulation layer 163 is located on the side of the second encapsulation layer 162 away from the substrate 11.

[0107] Optionally, the materials of the first encapsulation layer 161 and the third encapsulation layer 163 include inorganic encapsulation materials, and the material of the second encapsulation layer 162 includes an organic encapsulation material, that is, the first encapsulation layer 161 and the third encapsulation layer 163 are inorganic encapsulation layers, and the second encapsulation layer 162 is an organic encapsulation layer. For example, the first encapsulation layer 161 and the third encapsulation layer 163 can be formed by Chemical Vapor Deposition (CVD), and the second encapsulation layer 162 can be formed by Ink-jet Printing (IJP).

[0108] It can be understood that the display panel 1 may further include film layers such as a touch control function layer, an optical adhesive layer, a polarizer, and a cover plate that are sequentially stacked on the side of the third encapsulation layer 163 away from the substrate 11. The above film layers are conventional film layers of the display panel and will not be elaborated here.

[0109] Based on the same inventive concept, this embodiment further provides a display panel. Please refer to again Figure 8 , the display panel 1 includes a substrate 11, an array wiring layer 12, an isolation structure 14, and a light-emitting device 13. The array wiring layer 12 is located on one side of the substrate 11. Please refer to again Figure 2 , the array wiring layer 12 includes a power signal wiring 12A, a data signal wiring 12B, and a first reset signal wiring 12C1 in which at least part of the wiring segments extend in the first direction (the Y direction in the figure). A pixel circuit for driving the light-emitting device 13 to emit light may also be formed in the array wiring layer 12.

[0110] The isolation structure 14 is located on the side of the array trace layer 12 away from the substrate 11. The isolation structure 14 includes an isolation opening 1401 and a light-transmitting opening 1402. At least part of the light-emitting devices 13 are located within the isolation opening 1401. A plurality of light-emitting devices 13 form a pixel unit 30. The light-transmitting opening 1402 is located between at least some adjacent pixel units 30. Exemplarily, three light-emitting devices 13 of different light-emitting colors can form a pixel unit 30. A plurality of power signal traces 12A are respectively connected to different light-emitting devices 13 in the pixel unit 30 to provide power signals (such as ELVDD signals) for different light-emitting devices 13. A plurality of data signal traces 12B respectively provide data signals (such as Vdata signals) for different light-emitting devices 13 in the pixel unit 30. The first reset signal trace 12C1 provides a reset signal (such as Vref signal) for the light-emitting devices 13 in the pixel unit 30. Exemplarily, three light-emitting devices 13 of different light-emitting colors can form a pixel unit 30. Three power signal traces 12A respectively provide power signals for different light-emitting devices 13. Three data signal traces 12B respectively provide data signals for different light-emitting devices 13. One first reset signal trace 12C1 provides a reset signal for the light-emitting devices 13 in the pixel unit.

[0111] In this embodiment, among the traces for providing signals to the light-emitting devices 13 in the same pixel unit 30, the data signal trace 12B and the first reset signal trace 12C1 are located between two power signal traces 12A, that is, multiple data signal traces and one first reset signal trace 12C1 corresponding to the same pixel unit 30 are located between two power signal traces 12A corresponding to the same pixel unit 30.

[0112] Further, in the under-screen camera scenario, since the light transmittance needs to be increased in the area where the under-screen camera is set, a light-transmitting area needs to be added in this area. Please refer to Figure 3 and Figure 4 , the display panel 1 includes a first display area AA1 and a second display area AA2 at least partially surrounding the first display area AA1. The first display area AA1 includes a pixel area AA11 and a light-transmitting area AA12 located between adjacent pixel areas AA11.

[0113] In the first display area AA1, the pixel unit 30 is located within the pixel area AA11. There is a first distance d1 between two adjacent light-emitting devices 13 in the same pixel unit 30, and a second distance d2 between two adjacent light-emitting devices 13 in different pixel units. Due to the presence of the light-transmitting area AA12, the pitch between adjacent pixel units will be increased, that is, the second distance d2 will be increased, and the first distance d1 will be less than the second distance d2. When the thinner signal traces are located at the edge of the pixel unit, the trace layouts on its relative two sides are asymmetric, and the traces will be broken due to uneven etching during the patterning process, affecting the display of the display panel. The above solution provided in this embodiment can well solve the above technical problems.

[0114] Further, in the first display area AA1, the orthographic projection of the light-transmitting opening 1402 on the substrate 11 coincides with the orthographic projection of the light-transmitting area on the substrate 11. By removing the corresponding isolation structure 14 at the position of the light-transmitting area to form the light-transmitting opening 1402, the light-transmitting performance of the first display area AA1 can be increased, which is beneficial to the implementation of the under-screen camera solution.

[0115] Optionally, the line widths of the data signal trace 12B and the first reset signal trace 12C1 are smaller than the line width of the power signal trace 12A.

[0116] Based on the same inventive concept, an embodiment of the present application further provides an electronic device. The electronic device includes the display panel provided in the present application, and the electronic device may include a smart phone, a tablet computer, an in-vehicle display device, a smart wearable device, a television, a notebook computer, and other devices with a display function.

[0117] An embodiment of the present application provides a display panel and an electronic device. In the display panel, the data signal trace and the reset signal trace are arranged between two power signal traces corresponding to the pixel. Since the relative two sides of the two traces have similar trace layouts, during the patterning process of forming the data signal trace and the first reset signal trace, it can be ensured that the relative two sides of the data signal trace and the first reset signal trace can be etched evenly, so as to form traces with uniform line widths, avoiding the problem of trace breakage caused by uneven etching when the data signal trace and / or the first reset signal trace are arranged at the edge of the pixel unit due to the presence of the light-transmitting opening, and ensuring that the display panel has a good display effect.

[0118] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: substrate; An array wiring layer, located on one side of the substrate, the array wiring layer comprising a power signal wiring, a data signal wiring and a first reset signal wiring, at least part of which extends in a first direction; A light-emitting device is located on a side of the array wiring layer away from the substrate, a plurality of light-emitting devices form a pixel unit, a plurality of power signal wirings are respectively connected to different light-emitting devices in the pixel unit, a plurality of data signal wirings respectively provide data signals to different light-emitting devices in the pixel unit, and the first reset signal wiring provides a reset signal for the light-emitting device in the pixel unit; A light-transmitting opening is located between at least some of the adjacent pixel units; Wherein, a plurality of data signal lines and a first reset signal line corresponding to the same pixel unit are located between the two power signal lines corresponding to the same pixel unit.

2. The display panel according to claim 1, wherein: The line widths of the data signal line and the first reset signal line are smaller than the line width of the power signal line; Preferably, the line width of the data signal wiring and the first reset signal wiring is greater than or equal to 1.8 μm and less than or equal to 2.6 μm.

3. The display panel according to claim 1, wherein: The display panel comprises a first display area and a second display area at least partially surrounding the first display area, wherein the first display area comprises a pixel area and a light-transmitting area located between adjacent pixel areas; In the first display area, the pixel unit is located in the pixel area, the light-transmitting opening is located in the light-transmitting area, there is a first distance between two adjacent light-emitting devices in the same pixel unit, and there is a second distance between two adjacent light-emitting devices in different pixel units, wherein the first distance is smaller than the second distance.

4. The display panel according to claim 3, wherein: The pixel unit includes a first light-emitting device, a second light-emitting device and a third light-emitting device which are arranged in sequence and have different light-emitting colors, the power signal routing includes a first power signal routing, a second power signal routing and a third power signal routing which are respectively connected to the first light-emitting device, the second light-emitting device and the third light-emitting device, and the data signal routing includes a first data signal routing, a second data signal routing and a third data signal routing which respectively provide data signals to the first light-emitting device, the second light-emitting device and the third light-emitting device; The first data signal routing line and the second data signal routing line are located between the adjacent first power signal routing line and the second power signal routing line, and the third data signal routing line and the first reset signal routing line are located between the adjacent second power signal routing line and the third power signal routing line; Preferably, there is a third distance between the first data signal line and the first power signal line, there is a fourth distance between the second data signal line and the second power signal line, there is a fifth distance between the first reset signal line and the second power signal line, there is a sixth distance between the third data signal line and the third power signal line, the third distance is equal to the fourth distance, and the fifth distance is equal to the sixth distance.

5. The display panel according to claim 4, wherein: The array wiring layer includes a plurality of metal layers stacked in sequence and an insulating layer located between adjacent metal layers; Preferably, the array routing layer includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are stacked in sequence in a direction away from the substrate, the power signal routing is at least partially formed by the fourth metal layer, the data signal routing is formed by the fourth metal layer, and the first reset signal routing is formed by the fourth metal layer.

6. The display panel according to claim 5, wherein: The display panel further includes a second reset signal wiring extending along a second direction, wherein the first direction intersects with the second direction; The second reset signal routing line and the first reset signal routing line are formed by different metal layers, and the first reset signal routing line and the second reset signal routing line are connected via a wiring hole at an overlapping position of the first reset signal routing line and the second reset signal routing line; In the first display area, the orthographic projection of the line switching hole on the substrate is located within the orthographic projection of the pixel area on the substrate.

7. The display panel according to any one of claims 1 to 6, characterized in that: The display panel further includes: The isolation structure is located on a side of the array wiring layer away from the substrate, the isolation structure comprises an isolation opening, and the light emitting device is at least partially located in the isolation opening.

8. The display panel according to claim 7, wherein: The isolation structure encloses and forms the light-transmitting opening.

9. The display panel according to claim 8, wherein: The display panel further comprises a pixel defining layer, wherein the pixel defining layer is located on a side of the isolation structure facing the array wiring layer, and the isolation structure is located on a side of the pixel defining layer away from the substrate; The pixel defining layer comprises a pixel opening, the orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the isolation opening on the substrate, and at least part of the light emitting device is located within the pixel opening; Preferably, the pixel defining layer is an inorganic pixel defining layer; Preferably, the pixel defining layer is a single-layer structure of silicon oxide or silicon nitride, or a stacked-layer structure formed alternately of silicon oxide and silicon nitride.

10. The display panel according to claim 9, wherein: In a direction away from the substrate, the light emitting device comprises a first electrode, a light emitting material layer and a second electrode which are stacked; wherein the second electrode is connected to the isolation structure; The first electrode is disposed on a side of the pixel definition layer close to the substrate, and at least a portion of the first electrode is exposed from the pixel opening; Preferably, an orthographic projection of the light emitting device on the substrate does not overlap with an orthographic projection of the light-transmitting opening on the substrate.

11. The display panel according to claim 10, wherein: The isolation structure comprises a first isolation portion and a second isolation portion which are stacked, wherein the second isolation portion is arranged on a side of the first isolation portion away from the substrate, and an orthographic projection of the first isolation portion on the substrate is located within an orthographic projection of the second isolation portion on the substrate; Preferably, the second isolation portion is a conductive isolation portion, and the first electrode is connected to the second isolation portion; Preferably, the isolation structure further comprises a third isolation portion, and in a direction away from the substrate, the third isolation portion, the first isolation portion and the second isolation portion are stacked in sequence, and the orthographic projection of the first isolation portion on the substrate is located within the orthographic projection of the third isolation portion on the substrate; Preferably, the orthographic projection of the third isolation portion on the substrate is located within the orthographic projection of the second isolation portion on the substrate; Preferably, the third isolating portion is a conductive isolating portion, and the first electrode is also connected to the third isolating portion; Preferably, the material of the first isolation portion includes aluminum, silver or copper, the material of the second isolation portion includes titanium or molybdenum, and the material of the third isolation portion includes molybdenum or titanium.

12. The display panel according to claim 9, wherein: The display panel further includes a first encapsulation layer, the first encapsulation layer includes a plurality of encapsulation units, and the encapsulation units are used to encapsulate the light-emitting device in the isolation opening; Preferably, the display panel further comprises a second encapsulation layer, the second encapsulation layer is located on a side of the encapsulation unit away from the substrate, and the second encapsulation layer at least covers the encapsulation unit; Preferably, the second encapsulation layer fills the isolation opening and the light-transmitting opening, and the second encapsulation layer comprises a flat surface on a side away from the substrate; Preferably, the display panel further comprises a third encapsulation layer, and the third encapsulation layer is located on a side of the second encapsulation layer away from the substrate; Preferably, the first encapsulation layer and the third encapsulation layer are inorganic encapsulation layers, and the second encapsulation layer is an organic encapsulation layer.

13. A display panel, characterized in that: The display panel comprises: substrate; An array wiring layer, located on one side of the substrate, the array wiring layer comprising a power signal wiring, a data signal wiring and a first reset signal wiring, at least part of which extends in a first direction; An isolation structure, located at a side of the array wiring layer away from the substrate, the isolation structure comprising an isolation opening and a light-transmitting opening; A light-emitting device, at least part of which is located in the isolation opening, a plurality of light-emitting devices form a pixel unit, the light-transmitting opening is located between at least part of adjacent pixel units, a plurality of power signal lines are respectively connected to different light-emitting devices in the pixel units, a plurality of data signal lines respectively provide data signals for different light-emitting devices in the pixel units, and the first reset signal line provides a reset signal for the light-emitting devices in the pixel units; Wherein, a plurality of data signal lines and a first reset signal line corresponding to the same pixel unit are located between the two power signal lines corresponding to the same pixel unit.

14. The display panel according to claim 13, wherein: The display panel comprises a first display area and a second display area at least partially surrounding the first display area, wherein the first display area comprises a pixel area and a light-transmitting area located between adjacent pixel areas; In the first display area, the pixel unit is located in the pixel area, a first distance exists between two adjacent light emitting devices in the same pixel unit, and a second distance exists between two adjacent light emitting devices in different pixel units, wherein the first distance is smaller than the second distance; Preferably, in the first display area, the orthographic projection of the light-transmitting opening on the substrate coincides with the orthographic projection of the light-transmitting area on the substrate; Preferably, the line widths of the data signal line and the first reset signal line are smaller than the line width of the power signal line.

15. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1 to 14.

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