Power amplifier

Abstract

This power amplifier is provided with: a stacked circuit (19) having n (n is an integer of 2 or more) FETs, the FETs being numbered from 1 to n, i being an integer of 2 or more and (n-1) or less, a first FET (12) having a gate terminal to which an input signal is input, a drain terminal connected to a source terminal of a second FET (12), the source terminal being a terminal connected to GND, and a second FET (12) having a gate terminal to which an input signal is input and a drain terminal connected to a drain terminal of the second FET (12); the drain terminal of the i-th FET is connected to the source terminal of the (i + 1)-th FET, the drain terminal of the n-th FET (18) outputs an output signal, and the drain terminal is a terminal connected to a power supply; resistors that are respectively connected to the gate terminals of the second to n-th FETs of the stacked circuit (19); capacitors each connected to an electrode of the resistor on the opposite side from the gate terminal; and a first switch connected in parallel with each of the resistors.

Description

Technical Field

[0001] The present disclosure relates to a stacked power amplifier. Background Art

[0002] In power amplifiers for mobile terminals, power amplifiers using GaAs HBT (Heterojunction Bipolar Transistor) are currently mainly used. The reasons therefor include that single power supply operation can be performed under normal off state, operation can be performed at a Li-ion battery voltage of 3.7 V, and when in the output power range of several W, the power density is higher than that of GaAs FET (Field Effect Transistor), so the chip area is small when fabricated into an integrated circuit, and a very high yield can be achieved compared with GaAs-based FETs.

[0003] However, in recent years' power amplifiers, band switching switches, and antenna switches, in order to simplify the control within the terminal, a CMOS (Complementary Metal-Oxide-Semiconductor) control circuit capable of being digitally controlled separately from the GaAs HBT is mounted on the amplifier and the switch. In addition, since GaAs HBT chips that are not Si-based cannot be integrated with the control circuit and the cost is high during mass production compared with CMOS chips, there is a strong desire for CMOSification of power amplifiers.

[0004] The standard voltage of CMOS FET is 1.2 V in the 65 nm process and 1.8 V in the 0.18 μm process, which is much lower than the battery voltage (3.7 V). Therefore, a power amplifier composed of a single-stage CMOS FET cannot be used.

[0005] Against this background, attention has been paid to a stacked power amplifier that effectively operates CMOS as a power amplifier at as high a supply voltage as possible (for example, refer to Non-Patent Document 1).

[0006] Non-Patent Document 1: S. Pornpromlikit, et al., A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS, IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 1, pp. 57-64, Jan. 2010.

[0007] Next, a four - stage stacked power amplifier using a 65nm CMOS process with a standard voltage of 1.2V for the FETs will be used as an example to illustrate the problem. In this example, assuming that each amplification FET operates evenly, it can operate up to a power supply voltage of 4.8V. Although the standard voltage of a lithium - ion battery is 3.7V, for high - output - power operation, it is assumed that the voltage is boosted to 4.8V by a DC - DC converter and operates at an output power of 1W.

[0008] In mobile communication, the output power of a terminal often decreases according to the distance between the base station and the terminal. That is, it frequently switches to the maximum output power when the distance is far and to the low output power when the distance is near. For example, in the case of a city, since the distance between the base station and the terminal is short, the output power of the terminal is often as low as several to several tens of mW. This output power control is achieved by reducing the power supply voltage of the power amplifier. This is because if the high power supply voltage is kept constant and only the input power is reduced to lower the output power, the efficiency of the power amplifier will be significantly reduced.

[0009] However, if the power supply voltage of the stacked power amplifier is reduced from 4.8V to 2.4V, for example, while keeping the load line of the FETs the same and only reducing the power supply voltage, there is a problem that the load line of each stage of the FETs deviates greatly from the optimal state, resulting in not only a decrease in output power but also a significant decrease in efficiency. Summary of the Invention

[0010] The present disclosure is made to solve the above - mentioned problems, and the object is to obtain a power amplifier that can suppress the decrease in efficiency even when the power supply voltage is reduced.

[0011] The power amplifier of the present disclosure includes: a stacked circuit, resistors, capacitors, and a first switch. The stacked circuit has n (n is an integer of 2 or more) FETs. The FETs are numbered from 1 to n, and i is an integer of 2 or more and (n - 1) or less. The gate terminal of the first FET is input with an input signal, the drain terminal is connected to the source terminal of the second FET, and the source terminal is the terminal connected to GND. The drain terminal of the i - th FET is connected to the source terminal of the (i + 1) - th FET, and the drain terminal of the n - th FET outputs an output signal, and the drain terminal is the terminal connected to the power supply. The resistors are respectively connected to the gate terminals of the second to n - th FETs of the stacked circuit, the capacitors are respectively connected to the electrodes on the side opposite to the gate terminals of the resistors, and the first switch is connected in parallel with the resistors respectively.

[0012] According to the present disclosure, a power amplifier that can suppress the decrease in efficiency even when the power supply voltage is reduced can be obtained. Brief Description of the Drawings

[0013] Figure 1 This is a diagram showing the circuit structure of the power amplifier according to Embodiment 1.

[0014] Figure 2 This is a diagram showing the load line of the FET of the power amplifier according to Embodiment 1.

[0015] Figure 3 This is a diagram showing the load line of the FET of the power amplifier according to Embodiment 1.

[0016] Figure 4 This is a diagram showing the circuit structure of the power amplifier according to Embodiment 2.

[0017] Figure 5 This is a diagram showing the circuit structure of the power amplifier according to Embodiment 3. Detailed Embodiments

[0018] Embodiment 1.

[0019] In Figure 1 the circuit structure of the power amplifier 10 according to Embodiment 1 is shown. The 65nm CMOS process is used in the manufacture of the power amplifier 10, and the maximum standard voltage of the FET is 1.2V. Here, the maximum standard voltage refers to the maximum DC voltage that can be applied between the drain-source terminals of the FET having the smallest gate length used in this CMOS process and can obtain the long-term reliability of the FET.

[0020] The gate terminal of the FET 12 is input with an input signal from the input terminal 22, the drain terminal is connected to the source terminal of the FET 14, and the source terminal is the terminal connected to the GND. The drain terminal of the FET 14 is connected to the source terminal of the FET 16. The drain terminal of the FET 16 is connected to the source terminal of the FET 18. The FET 18 outputs an output signal from the drain terminal, and the drain terminal is connected to the power supply (Vdd). The circuit composed of the above four FETs is called the stacked circuit 19. The FETs 12, 14, 16, and 18 are n-type FETs. Although not shown, an input matching circuit is connected to the input terminal 22. An output matching circuit 20 is connected between the output terminal 24 and the drain terminal of the third FET 18.

[0021] The bias terminals 50, 52, and 54 are the gate bias terminals of the FETs 14, 16, and 18 respectively, and are connected to the gate terminals of the FETs 14, 16, and 18 via resistors 38, 40, and 42 of the order of kΩ. The FET switches 32, 34, and 36 are respectively connected in parallel with the resistors 38, 40, and 42. These FET switches function as switches for bypassing the resistors. The FET switches 32, 34, and 36 are turned on and off by the switch terminals 56, 58, and 60 respectively.

[0022] The bias terminals 50, 52, and 54 are the terminals on the side opposite to the gate terminals of the resistors 38, 40, and 42, and capacitors 44, 46, and 48 are respectively connected between them and GND. The capacitors 44, 46, and 48 are variable capacitors.

[0023] In addition, the number of FETs in the stacked circuit is not limited to four. Here, the number of FETs in the stacked circuit is set to n (n is a number of 2 or more) for explanation. The numbers of these FETs are set to 1 to n, and i is an integer of 2 or more and (n - 1) or less. The first FET corresponds to Figure 1 the FET 12 in Figure 1 where an input signal is input to the gate terminal, the drain terminal is connected to the source terminal of the second FET, and the source terminal is the terminal connected to GND. The i-th FET corresponds to Figure 1 the FETs 14 and 16 in

[0024] Returning to the case where the number of FETs in the stacked circuit is four and continuing the explanation. Since the maximum standard voltage of the FET is 1.2V, the power supply voltage of the power amplifier 10 is raised to 4.8V in DC voltage. The wells of each FET are separated, and the back gate is connected to the source. In the case where the FET is a fully depleted type of SOI (Silicon On Insulator), the back gate can also be floating. The control FETs such as the FET switches 32, 34, and 36 also require a breakdown voltage of up to 4.8V, so FETs with a high breakdown voltage of the gate oxide film thickness are used for the control FETs.

[0025] When the power supply voltage is at its maximum of 4.8V, if there is no voltage drop, a voltage of 4.8V is applied to the drain terminal of FET18. In the case of a voltage drop, the applied voltage is correspondingly reduced, but here it is assumed that there is no voltage drop for the purpose of explanation. When the power supply voltage is 4.8V, all of FET switches 32, 34, and 36 are closed, and resistors 38, 40, and 42 are bypassed. As a result, a voltage of 1.2V is applied across the drain-source terminals of FETs 12, 14, 16, and 18, and all of these FETs perform amplification operations.

[0026] Next, consider the case where the power supply voltage is reduced to 3.6V. In this case, FET switch 32 and FET switch 34 are closed, while FET switch 36 is turned off. As a result, resistor 42 becomes effective, and FET18 operates in a switching mode. Here, the switching mode refers to a state where the gate terminal of the FET floats due to the resistor, and the input to the source terminal is output from the drain terminal with almost no loss. The remaining FETs 12 and 14 perform amplification operations. Thus, the voltage drop across the drain-source terminals of FET18 is minimized, and a voltage of approximately 1.2V is applied across the drain-source terminals of FETs 12 and 14 that perform amplification operations, achieving an optimal state in the power amplification operation. That is, the FETs operate in the saturation region so that the voltage amplitude and current amplitude during amplification can be increased sufficiently.

[0027] Next, consider the case where the power supply voltage is reduced to 2.4V. In this case, FET switch 32 is closed, and FET switches 34 and 36 are turned off. As a result, resistors 40 and 42 at the gate terminals of FETs 16 and 18 become effective, and FETs 16 and 18 operate in a switching mode. The remaining FETs 12 and 14 perform amplification operations. Thus, the voltage drop across the drain-source terminals of FETs 16 and 18 is minimized, and a voltage of approximately 1.2V is applied across the drain-source terminals of FETs 12 and 14 that perform amplification operations, enabling sufficient amplification operations.

[0028] Next, consider the case where the power supply voltage is reduced to 1.2V. In this case, all of the FET switches 32, 34, and 36 are turned off. As a result, the resistors 38, 40, and 42 at the gate terminals of the FETs 14, 16, and 18 become effective, and the FETs 14, 16, and 18 operate in the switching mode. The remaining FET 12 performs an amplification operation. Thereby, the voltage drop between the drain-source terminals of the FETs 14, 16, and 18 is suppressed to a minimum, and a voltage of approximately 1.2V is applied between the drain-source terminals of the FET 12 performing the amplification operation, enabling the amplification operation to be sufficiently performed.

[0029] In addition, the order of turning off the FET switches when reducing the power supply voltage does not have to start from the upper-level FET switch 36 as described above.

[0030] Generalize the previous description. Let the number of FETs in the stacked circuit be n (n is an integer of 2 or more), and number the FETs as described above. All of these FETs are closed when, if the maximum standard voltage is Vm, the voltage applied to the drain terminal of the nth FET is Vd, and j is an integer of 1 or more and n or less, then (j - 1)×Vm < Vdd ≤ j×Vm, and the remaining switches are turned off.

[0031] In this way, even when the power supply voltage is reduced, by appropriately turning off the FET switches 32, 34, and 36 according to the level of the reduction in the power supply voltage, a voltage sufficient to cause the FET performing the amplification operation to operate in the saturation region can be applied between the drain-source terminals of the FET.

[0032] The capacitance values of the capacitors can also be set so that the load lines of the respective FETs of the FETs 12, 14, 16, and 18 are equal. Figure 2 Schematically shows the load lines in the case where all of the FETs perform an amplification operation. In order to make the load lines of the respective FETs equal, if the input impedances of the FETs 14, 16, and 18 are Zi (i = 1, 2, 3), and the optimum load resistance of one-stage FETs is Ropt, then Z1 = Ropt, Z2 = 2×Ropt, and Z3 = 3×Ropt. 4×Ropt is equal to the load impedance when viewed from the drain terminal of the FET 18. For example, if the impedance of the output matching circuit 20 is 50Ω, then Ropt is 12.5Ω. Then, the load lines of the FETs 12, 14, 16, and 18 become equal.

[0033] In order to set Zi (i = 1, 2, 3) to the above values, it is sufficient to set the capacitance values of capacitor 44, capacitor 46, and capacitor 48 to specified values using Equation 1 (see Non-Patent Document 1).

[0034] [Equation 1]

[0035]

[0036] Here, Cgs is the gate-source capacitance of FETs 14, 16, and 18, Ci (i = 1, 2, 3) is the capacitance value of capacitor 44, capacitor 46, and capacitor 48, and gm is the transconductance of FETs 14, 16, and 18. Additionally, here the transconductance and gate-source capacitance of FETs 14, 16, and 18 are equal, and the operating frequency is sufficiently lower than the cutoff frequency of these FETs.

[0037] When the power supply voltage is decreased, the load line of each FET changes while remaining in an unchanged state. For example, when the power supply voltage is decreased to 3.6V, FET switch 36 is turned off, and FET 18 operates in the switching mode. In this case, the input impedance Z3 of FET 18 becomes 4 × Ropt. Then, the load line of FET 18 Figure 3 deviates from the optimal load line depicted by the dashed line as shown.

[0038] In order to reduce the change in the load line, the capacitance values of the variable capacitors of capacitor 44 and capacitor 46 can be changed. Specifically, the capacitance value C1 of capacitor 44 is set such that Z1 = 1 / 3 × 4 × Ropt, and the capacitance value C2 of capacitor 46 is set such that Z2 = 2 / 3 × 4 × Ropt. Thereby, the change in the load lines of FETs 12, 14, and 16 can be suppressed.

[0039] Similarly, when the power supply voltage is decreased to 2.4V, FET switch 34 and FET switch 36 are turned off, and FETs 16 and 18 operate in the switching mode, the capacitance value C1 of capacitor 44 is set such that Z1 = 1 / 2 × 4 × Ropt.

[0040] Generalize the previous description. Set the number of FETs in the stacked circuit to n (n is an integer of 2 or more), and number the FETs as described above. Let the load impedance observed from the drain terminal of the nth FET be Z0. Let the number of FETs that perform the amplification operation among the second to nth FETs be m, and number the FETs that perform the amplification operation in order from the smallest number of the FETs in the stacked circuit as 1 to m. If k is an integer of 1 or more and m or less, the input impedance observed from the source terminal of the kth FET that performs the amplification operation may be set within the range from (k - 0.5) / (m + 1)×Z0 to (k + 0.5) / (m + 1)×Z0. It is ideal to set the input impedance to k / (m + 1)×Z0, but it may also have the above-mentioned degree of amplitude.

[0041] In this way, even if the power supply voltage is reduced, by appropriately setting the input impedance of the FET, the load lines of the FETs that perform the amplification operation can be made equal.

[0042] As described above, according to this embodiment, even when the power supply voltage is reduced, a voltage sufficient to cause the FET to operate in the saturation region can be applied between the drain-source terminals of the FETs that perform the amplification operation. Therefore, a decrease in the efficiency of the power amplifier can be suppressed.

[0043] In addition, even when the power supply voltage is reduced, the load lines of the FETs that perform the amplification operation can be made equal. Therefore, a decrease in the efficiency of the power amplifier can be suppressed.

[0044] In addition, since switching by the FET switch is adopted, an additional path such as a high-frequency bypass circuit is not required at the position where the high-frequency signal is transmitted. Therefore, the circuit area can be reduced.

[0045] Embodiment 2.

[0046] In the power amplifier of Embodiment 2, in addition to the capacitors 44, 46, and 48 of the power amplifier 10 of Embodiment 1, additional capacitors that can be connected and disconnected by the FET switch are added.

[0047] Here, the vicinity of only the gate terminal of the FET14 is illustrated for Figure 4 explanation. As Figure 4 such, in addition to the capacitor 44, an FET switch 64 and an additional capacitor 62, and an FET switch 70 and an additional capacitor 68 are added. The additional capacitor 62 can be connected and disconnected through the FET switch 64. The additional capacitor 68 can be connected and disconnected through the FET switch 70.

[0048] Similar to the power amplifier 10 of Embodiment 1, in the power amplifier of this embodiment, four FETs related to amplification are also provided. Therefore, as can be seen from the description of Embodiment 1, the capacitance value of the capacitor connected to the gate terminal of FET 14 can be set to any one of the three values. In this embodiment, by turning on and off FET switch 64 and FET switch 70, switching between the three capacitance values can be performed.

[0049] In addition, the above is not only applicable to FET 14, but also equally applicable to FET 16 and FET 18.

[0050] As described above, in this embodiment, it is possible to digitally change the switching of the capacitance value using a normal FET. Therefore, compared with a capacitator that is variable in an analog manner, the control is simple and the circuit area can also be reduced.

[0051] Embodiment 3.

[0052] The power amplifier 110 of Embodiment 3, as Figure 5 shown, differentiates the circuit structure of the power amplifier 10 of Embodiment 1. Along with this, the input signal also becomes a differential signal, and this differential signal is input to input terminal 122 and input terminal 123. By performing differentiation, it is possible to greatly suppress the influence of gain reduction caused by GND inductance, which is often a problem in single-phase amplifiers mounted on Si-based LSIs. In addition, the power amplifier of Embodiment 2 can also be differentiated.

[0053] In addition, in the power amplifiers of all embodiments, GaAs FETs, InP FETs, etc. can be used instead of CMOS. When using GaAs or InP, the back gate is usually floating.

[0054] Description of Reference Numerals

[0055] 12, 14, 16, 18... FET; 38, 40, 42... Resistor; 44, 46, 48... Capacitator; 32, 34, 36, 64, 70... FET switch; 20... Output matching circuit; 62, 68... Additional capacitance; 19... Stacked circuit.

Claims

1. A power amplifier, characterized in that, it includes: a stacked circuit, a resistor, a capacitor, and a first switch, the stacked circuit has n (n is an integer of 2 or more) FETs, the numbers of the FETs are set to 1 to n, and i is an integer of 2 or more and (n - 1) or less, the gate terminal of the first FET is input with an input signal, the drain terminal is connected to the source terminal of the second FET, and the source terminal is a terminal connected to GND, the drain terminal of the i-th FET is connected to the source terminal of the (i + 1)-th FET, the n-th FET outputs an output signal from the drain terminal, and the drain terminal is a terminal connected to the power supply, the resistors are respectively connected to the gate terminals of the second to n-th FETs of the stacked circuit, the capacitors are respectively connected to the electrodes of the resistors on the side opposite to the gate terminals, the first switch is connected in parallel with the resistors respectively.

2. The power amplifier according to claim 1, characterized in that, the first switch is composed of an FET switch.

3. The power amplifier according to claim 1 or 2, characterized in that, assuming that the maximum standard voltage of the FETs of the stacked circuit is Vm, the voltage applied to the drain terminal of the n-th FET of the stacked circuit is Vd, j is an integer of 1 or more and n or less, when (j - 1)×Vm < Vd ≤ j×Vm, close (j - 1) of the switches and turn off the remaining switches.

4. The power amplifier according to any one of claims 1 to 3, characterized in that, the load impedance observed from the drain terminal of the n-th FET of the stacked circuit is set to Z0, the number of FETs that perform the amplification operation among the second to n-th FETs of the stacked circuit is set to m, where, the numbers of the FETs that perform the amplification operation are set to 1 to m in order starting from the smallest number of the FETs of the stacked circuit, k is an integer of 1 or more and m or less, the input impedance observed from the source terminal of the k-th FET that performs the amplification operation is set within the range from (k - 0.5) / (m + 1)×Z0 to (k + 0.5) / (m + 1)×Z0.

5. The power amplifier according to claim 4, characterized in that, it includes an additional capacitor that is connected in parallel with the capacitor and can be turned on and off by a second switch, and the input impedance is set by turning on and off the second switch.

6. The power amplifier according to claim 5, characterized in that, the second switch is composed of an FET switch.

7. The power amplifier according to any one of claims 1 to 6, characterized in that, the input signal is a differential signal, the circuit structure is differentialized.

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