Direct backside self-aligned contact

Abstract

A semiconductor structure is provided that includes a backside source / drain contact structure that contacts a source / drain region of a transistor and overlaps a portion of a three-layer bottom dielectric isolation structure on a backside of the transistor. The presence of the three-layer bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source / drain contact structure, and thus improves process margin.

Description

BACKGROUND OF THE INVENTION

[0001] This application relates to semiconductor technology, and more particularly to a semiconductor structure including a self-aligned backside source-drain contact structure and a method of forming the same.

[0002] Integrated circuits continue to scale down to smaller feature sizes and higher transistor densities. Three-dimensional (3D) integration increases transistor density by leveraging the Z-dimension, building up in the X and Y dimensions, and building out laterally. Another development for semiconductor devices that can be used in increasingly dense packaging is the use of both frontside and backside connections to establish electrical connections between semiconductor devices. Whether the integrated circuit includes one device layer (or equivalently a "device region") or multiple device layers, the use of backside connections can improve various aspects of semiconductor device configuration and performance, particularly with respect to density constraints. SUMMARY OF THE INVENTION

[0003] A semiconductor structure is provided that includes a backside source / drain contact structure that contacts a source / drain region of a transistor and overlaps a portion of a three-layer bottom dielectric isolation structure located on the backside of the transistor. The backside source / drain contact is self-aligned. The presence of the three-layer bottom dielectric isolation structure prevents a short circuit between the gate structure of the transistor and the backside source / drain contact structure, and thus improves process margin.

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment, the semiconductor structure includes a transistor that includes a gate structure, a first source / drain region located on a first side of the gate structure, and a second source / drain region located on a second side of the gate structure. The structure further includes a three-layer bottom dielectric isolation structure located under the transistor, a backside power rail located under and spaced apart from the three-layer bottom dielectric isolation structure, and a backside source / drain contact structure that connects the backside power rail to the first source / drain region of the transistor. According to the present application, the backside source / drain contact structure overlaps (i.e., vertically) at least a portion of the three-layer bottom dielectric isolation structure. The presence of the three-layer bottom dielectric isolation structure provides a thick dielectric cap that prevents the backside source / drain contact structure from shorting out the gate structure. In the prior art, the bottom isolation structure is a thin structure, typically less than 10 nm, and thus a short circuit between the gate structure and the backside source / drain contact structure may occur.

[0005] In an embodiment of the present application, the triple-bottom dielectric isolation structure includes a first bottom dielectric isolation layer, a second bottom dielectric isolation layer, and a third bottom dielectric isolation layer, where both the first bottom dielectric isolation layer and the third bottom dielectric isolation layer are composed of a first dielectric material, and the second bottom dielectric isolation layer is composed of a second dielectric material different from the composition of the first dielectric material. In the present application, the second bottom dielectric isolation layer is sandwiched between the first and third bottom dielectric isolation layers. The different dielectric materials provide an etching selectivity to the structure, which enables the use of etching to form a backside source / drain contact opening for accommodating the backside source / drain contact structure and stop at the second bottom dielectric isolation layer, thereby preventing the exposure of the gate structure.

[0006] In an embodiment of the present application, the first dielectric material includes a low-k spacer dielectric material (i.e., a dielectric constant less than 5.5), and the second dielectric material includes a high-k gate dielectric material (i.e., a dielectric constant of 4.0 or greater). This provides the above-mentioned etching selectivity.

[0007] In an embodiment of the present application, the structure further includes gate spacers located on the sidewalls of the gate structure, where the gate spacers are composed of the first dielectric material. This aspect of the present application relates to a process in which the gate spacers, the first bottom dielectric isolation layer, and the third bottom dielectric isolation layer are formed simultaneously.

[0008] In an embodiment of the present application, the gate structure includes a gate dielectric material layer, where the gate dielectric material layer is composed of the second dielectric material. This aspect of the present application relates to a process in which the gate dielectric material layer and the second bottom dielectric isolation layer are formed simultaneously.

[0009] In an embodiment of the present application, the backside source / drain contact structure contacts the sidewall of the first bottom dielectric isolation layer, the horizontal surface and the sidewall surface of the second bottom dielectric isolation layer, and the sidewall of the third bottom dielectric isolation layer. This is because different dielectric materials are used in forming the triple-bottom dielectric isolation structure, and thus a short circuit between the gate structure and the backside source / drain contact structure is avoided.

[0010] In an embodiment of the present application, the structure further includes a semiconductor buffer layer on the surface of the first source / drain region, where the semiconductor buffer layer is embedded in a part of the backside source / drain contact structure. The semiconductor buffer layer serves as a growth surface for the source / drain region, which allows the formation of high-quality source / drain regions as defined later in the present application.

[0011] In an embodiment of the present application, the structure further includes a multi-layer backside interlayer dielectric material structure embedded in another part of the backside source / drain contact structure, where the multi-layer backside interlayer dielectric material structure is also embedded in the backside power rail.

[0012] In an embodiment of the present application, the structure further includes a backside power distribution network that contacts the backside power rail. The backside power distribution network distributes power to the transistors.

[0013] In an embodiment of the present application, the structure further includes a frontside source / drain contact structure that contacts the second source / drain region. The presence of the frontside source / drain contact structure allows the transistor to be connected to other electronic components.

[0014] In an embodiment of the present application, the frontside source / drain contact structure is embedded in a first frontside interlayer dielectric material layer and a second frontside interlayer dielectric material layer.

[0015] In an embodiment of the present application, the structure further includes a frontside gate contact structure that is located in the second frontside interlayer dielectric material layer and contacts the gate electrode of the gate structure. The presence of the frontside gate contact structure allows the transistor to be connected to other electronic components.

[0016] In an embodiment of the present application, the structure further includes a frontside back-end-of-line structure located on the second frontside interlayer dielectric material layer, wherein the frontside back-end-of-line structure is electrically connected to the second source / drain region through the frontside source / drain contact structure.

[0017] In an embodiment of the present application, the structure further includes a carrier wafer located on the surface of the frontside back-end-of-line structure.

[0018] In an embodiment of the present application, the transistor is located on one side of a gate cut dielectric pillar. The gate cut dielectric pillar is used to separate one transistor from another transistor.

[0019] In an embodiment of the present application, the transistor is a nanosheet transistor including a nanosheet stack of suspended semiconductor channel material nanosheets. In such an embodiment, the gate structure of the transistor surrounds each of the suspended semiconductor material nanosheets.

[0020] In an embodiment of the present application, the gate structure of the transistor includes a gate electrode located above and laterally adjacent to a three-layer bottom dielectric isolation structure.

[0021] In another aspect of the present application, a method of forming a semiconductor structure is provided. The method of the present application includes forming a three-layer bottom dielectric isolation structure under the gate structure of a transistor, the transistor including a first source / drain region located on one side of the gate structure and a second source / drain region located on a second side of the gate structure. Next, a backside source / drain contact structure that contacts the surface of the first source / drain region is formed, wherein the formation of the backside source / drain contact structure includes partially etching through the three-layer bottom dielectric isolation structure. The method improves the process margin by eliminating a short circuit between the gate structure and the backside source / drain contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a top view of a device layout that can be used to describe a semiconductor structure according to the present application. The device layout includes an X-X cross-section (cut) along a first semiconductor fin structure, a Y1-Y1 cross-section through a gate structure, and a Y2-Y2 cross-section in a source / drain region between two adjacent gate structures.

[0023] Figure 2A 、 2B and 2C are cross-sectional views of exemplary structures that can be employed in the present application through Figure 1 the X-X, Y1-Y1, and Y2-Y2, respectively. The exemplary structure includes at least one semiconductor fin structure on a surface of a semiconductor substrate and at least one sacrificial gate structure on a surface of the at least one semiconductor fin structure. Wherein, the at least one semiconductor fin structure includes a stack of materials of a first sacrificial semiconductor material layer, a second sacrificial semiconductor material layer, a third sacrificial semiconductor material layer, and alternating fourth sacrificial semiconductor material layers and semiconductor channel material layers.

[0024] Figure 3A 、 3B and 3C are cross-sectional views of the exemplary structures shown in Figure 2A 、 2B and 2C, respectively, after removing the first sacrificial semiconductor material layer to form a first gap and removing the third sacrificial semiconductor material layer to form a second gap, wherein the first gap and the second gap are separated by the second sacrificial semiconductor material layer.

[0025] Figure 4A 、 4B and 4C are cross-sectional views of the exemplary structures shown in Figure 3A 、 3B and 3C, respectively, after forming gate dielectric spacer materials along sidewalls of the at least one sacrificial gate structure and in the first and second gaps.

[0026] Figure 5A 、 5B and 5C are, respectively, after patterning the material stack to form a stack of nanosheet layers of alternating fourth sacrificial semiconductor material nanosheets and semiconductor channel material nanosheets, recessing each fourth sacrificial semiconductor material nanosheet of the stack of nanosheet layers, and forming inner spacers laterally adjacent to each recessed fourth semiconductor material nanosheet Figure 4A 、 4B and cross-sectional views of the exemplary structures shown in 4C.

[0027] Figure 6A 、 6B and 6C are, respectively, Figure 5A, 5B and a cross-sectional view of the exemplary structure shown in 5C after performing an etch that physically exposes the surface of the second semiconductor material layer of the semiconductor substrate at and on each side of the footprint of the at least one sacrificial gate structure, forming a semiconductor buffer layer on the physically exposed surface of the second semiconductor material layer of the semiconductor substrate, forming source / drain regions on the semiconductor buffer layer, and forming a front-side interlayer dielectric (ILD) material layer on the source / drain regions.

[0028] Figure 7A , 7B and 7C are cross-sectional views of the exemplary structures shown in Figure 6A , 6B and 6C, respectively, after removing the at least one sacrificial gate structure, the second sacrificial semiconductor material layer, and the fourth semiconductor material nanosheets of each recess, wherein the removal of the second semiconductor material layer forms a third gap between the gate dielectric spacer materials filling the first and second gaps.

[0029] Figure 8A , 8B and 8C are cross-sectional views of the exemplary structures shown in Figure 7A , 7B and 7C, respectively, after forming a high-k gate dielectric material in the third gap and on the physically exposed portions of each semiconductor channel material nanosheet.

[0030] Figure 9A , 9B and 9C are cross-sectional views of the exemplary structures shown in Figure 8A , 8B and 8C, respectively, after forming a gate electrode, forming a gate cut dielectric pillar, forming a second front-side ILD material layer, and forming a front-side contact structure.

[0031] Figure 10A , 10B and 10C are cross-sectional views of the exemplary structures shown in Figure 9A , 9B and 9C, respectively, after forming a front-side back-end-of-line (BEOL) structure and a carrier wafer.

[0032] Figure 11A , 11B and 11C are cross-sectional views of the exemplary structures shown in Figure 10A , 10B and 10C, respectively, after the wafer is flipped to physically expose the back side of the semiconductor substrate and the first semiconductor material layer of the semiconductor substrate is removed to physically expose the etch stop layer of the semiconductor substrate.

[0033] Figure 12A , 12Band 12C are, respectively, cross-sectional views of exemplary structures as shown in Figure 11A , 11B , and 11C after removing an etch stop layer that physically exposes a semiconductor substrate to physically expose a second semiconductor material layer of the semiconductor substrate. Figure 11A , 11B and 11C after removing the second semiconductor material layer and a portion of the semiconductor buffer layer.

[0034] Figure 13A , 13B and 13C are, respectively, cross-sectional views of exemplary structures as shown in Figure 12A , 12B , and 12C after removing the second semiconductor material layer and a portion of the semiconductor buffer layer. Figure 12A , 12B and 12C.

[0035] Figure 14A , 14B and 14C are, respectively, cross-sectional views of exemplary structures as shown in Figure 13A , 13B , and 13C after forming a backside ILD material layer. Figure 13A , 13B and 13C.

[0036] Figure 15A , 15B and 15C are, respectively, Figure 14A , 14B cross-sectional views of exemplary structures as shown in ,

[0037] , and 14C after forming a self-aligned backside source / drain contact structure.

[0037] Figure 16A , 16B and 16C are, respectively, cross-sectional views of exemplary structures as shown in Figure 15A , 15B , and 15C after forming an additional backside ILD material on the backside LID material layer and the self-aligned backside source / drain contact structure, and forming a backside power rail and a backside power distribution network. Figure 15A , 15B and 15C. DETAILED DESCRIPTION

[0038] The present application will now be described in more detail by reference to the following discussion and the accompanying drawings of the present application. Note that the drawings of the present application are for illustrative purposes only and are not drawn to scale. It should also be noted that the same and corresponding elements are denoted by the same reference numerals.

[0039] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, one of ordinary skill in the art will understand that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.

[0040] It should be understood that when an element that is a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element or there can be intervening elements. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "under" or "beneath" another element, it can be directly under or beneath the other element or there can be intervening elements. In contrast, when an element is referred to as being "directly under" or "directly beneath" another element, there are no intervening elements.

[0041] Referring first to Figure 1 , which shows a top view of a device layout that can be used to describe a semiconductor structure in accordance with the present application. Figure 1 The device layout shown in includes three parallel-oriented gate structures GS that span different portions of two semiconductor fin structures (Fin), the fins being parallel to each other and perpendicular to each gate structure. As used herein, a "fin" refers to an adjacent structure that includes one or more semiconductor materials and includes a pair of substantially vertical sidewalls that are parallel to each other. As used herein, a surface is "substantially vertical" if there is a root mean square roughness of the surface deviation from the surface that does not exceed three times the vertical plane. Each fin can have a vertical height ranging from 15 nm to 100 nm and a width ranging from 4 nm to 100 nm. The device layout includes an X-X cross-section along the first semiconductor fin structure, a Y1-Y1 cross-section through the gate structure, and a Y2-Y2 cross-section in the source / drain region between two adjacent gate structures. In the present application, Figure 2A , 3A , each of 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, and 16A is cut by X-X, Figure 2B , 3B , each of 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, and 16B is cut by the Y1-Y1 cross-section, and Figure 2C , 3C , each of 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, and 16C is cut by the Y2-Y2 cross-section.

[0042] Note that although the present application describes and shows transistors that include nanosheets, i.e., transistors in which the gate structure wraps around a plurality of vertically stacked semiconductor channel material nanosheets, the present application is also valid for other types of transistors, such as planar transistors, fin transistors, stacked transistors, or semiconductor nanowire transistors.

[0043] In the present application, the term "transistor" is used to describe a device including a gate structure that contacts a semiconductor channel material structure and has a first source / drain region on a first side of the gate structure and a second source / drain region on a second side of the gate structure, the second side of the gate structure being opposite to the first side of the gate structure.

[0044] In the present application, the term "front side" refers to the side of a structure including a transistor that is above a semiconductor substrate.

[0045] In the present application, the term "back side" refers to the side of a structure that is below a transistor after a semiconductor substrate has been removed.

[0046] Now refer to Figure 2A 、 2B and 2C, which show exemplary structures that can be employed in the present application through X-X, Y1-Y1, and Y2-Y2 of Figure 1 respectively. Figure 2A 、 2B The exemplary structures shown in Figure 2B and 2C include at least one semiconductor fin structure Fin on the surface of a semiconductor substrate 10 / 12 / 14, and at least one sacrificial gate structure 22 (three are shown by way of example) on the surface of the at least one semiconductor fin structure Fin. In Figure 2B and 2C two fins are shown by way of example.

[0047] The semiconductor substrate 10 includes a first semiconductor material layer 10, an etch stop layer 12, and a second semiconductor material layer 14. An optional sacrificial cap 24 may be located on top of each sacrificial gate structure 22, and a shallow trench isolation structure 15 may be located in the upper part of the semiconductor substrate 10 / 12 / 14. In the illustrated embodiment, the shallow trench isolation structure 15 is formed in the second semiconductor material layer 14 and the shallow trench isolation structure 15 contacts the surface of the etch stop layer 12.

[0048] According to the present application, at least one semiconductor fin structure Fin includes a material stack of a first sacrificial semiconductor material layer 16A, a second sacrificial semiconductor material layer 16B, a third sacrificial semiconductor material layer 16C, and alternating fourth sacrificial semiconductor material layers 18 and semiconductor channel material layers 20. As illustrated, each semiconductor fin structure fin is located on top of the second semiconductor material layer 14 of the semiconductor substrate 10 / 12 / 14.

[0049] As described above, the semiconductor substrate includes a first semiconductor material layer 10, an etch stop layer 12, and a second semiconductor material layer 14. The first semiconductor material layer 10 of the semiconductor substrate is composed of a first semiconductor material having semiconductor characteristics. Examples of the first semiconductor material that can be used to provide the first semiconductor material layer 10 include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloy, silicon germanium carbide (SiGeC) alloy, germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors. The second semiconductor material layer 14 of the semiconductor substrate is composed of a second semiconductor material. The second semiconductor material that provides the second semiconductor material layer 14 may be the same as or different from the first semiconductor material that provides the first semiconductor material layer 10 in composition. In some embodiments of the present application, the etch stop layer 12 may be composed of a dielectric material, such as silicon dioxide and / or boron nitride. In other embodiments of the present application, the etch termination layer 12 is composed of a semiconductor material that is different in composition from the semiconductor materials that provide the first semiconductor material layer 10 and the second semiconductor material layer 14. In one example, the first semiconductor material layer 10 is composed of silicon, the etch termination layer 12 is composed of silicon dioxide, and the second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate including silicon / silicon dioxide / silicon may be referred to as a silicon-on-insulator (SOI) substrate. In another example, the first semiconductor material layer 10 is composed of silicon, the etch stop layer 12 is composed of silicon germanium, and the second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate including silicon / silicon germanium / silicon may be referred to as a bulk semiconductor substrate.

[0050] The shallow trench isolation structure 15 is composed of any trench dielectric material, such as silicon oxide. In some embodiments, a trench dielectric material, such as SiN, may be present along the sidewalls and bottom wall of the trench dielectric material. As Figure 2B and 2C shown, the shallow trench isolation structure 15 is located laterally adjacent to the unetched portion of the second semiconductor material layer 14 of the semiconductor substrate.

[0051] The first sacrificial semiconductor material layer 16A and the third sacrificial semiconductor layer 16C are both composed of a third semiconductor material, a fourth semiconductor material, and a fifth semiconductor material. The third semiconductor material is compositionally different from the second semiconductor material of the second semiconductor material layer 14 providing the semiconductor substrate. The fourth semiconductor material provides the second sacrificial semiconductor material layer 16B and each fourth sacrificial semiconductor material layer 18. The fifth semiconductor material provides each semiconductor channel material layer 20. In one example, the third semiconductor material providing the first sacrificial semiconductor material layer 16A and the third sacrificial semiconductor layer 16C is composed of a silicon-germanium alloy with a germanium content of 55 atomic percent. The fourth semiconductor material providing the second sacrificial semiconductor material layer 16B and each fourth sacrificial semiconductor material layer 18 is composed of a silicon-germanium alloy with a germanium content of 30 atomic percent. And the fifth semiconductor material processing each semiconductor channel material layer 20 is composed of silicon. The fifth semiconductor material providing each semiconductor channel material layer 20 may be the same as or different from the second semiconductor material providing the second semiconductor material layer 14 in composition.

[0052] In the present application, the first sacrificial semiconductor material layer 16A and the third sacrificial semiconductor layer 16C may have a thickness ranging from 6 nm to 15 nm, the second sacrificial semiconductor layer 16B may have a thickness ranging from 1 nm to 5 nm, each fourth sacrificial semiconductor material layer 18 may have a thickness ranging from 4 nm to 15 nm (note that the thickness of the second sacrificial semiconductor material layer 16B is less than the thickness of each fourth sacrificial semiconductor material layer 18), and each semiconductor channel material layer 20 may have a thickness ranging from 4 nm to 12 nm. The width and length of each of these layers have been defined above (see the width and length mentioned for the Fin).

[0053] Each sacrificial gate structure 22 includes at least a sacrificial gate material. In some embodiments, each sacrificial gate structure 22 may include a sacrificial gate dielectric material. The sacrificial gate dielectric material may be composed of a dielectric material such as silicon dioxide. The sacrificial gate material may include, but is not limited to, polysilicon, amorphous silicon, amorphous silicon-germanium, or amorphous germanium.

[0054] Each sacrificial cap 24 may be composed of a dielectric hard mask material such as silicon nitride and / or silicon oxynitride. In the illustrated embodiment, each sacrificial cap 24 has a sidewall perpendicularly aligned with the sidewall of one of the sacrificial gate structures 22. In an embodiment, the sacrificial cap 24 may be omitted from the exemplary structure. Note that in Figure 2C the illustrated source / drain cross-section, there is no sacrificial gate structure 22 or sacrificial cap 24.

[0055] Figure 2A - 2CThe exemplary structures shown can be formed using fin formation processing techniques known to those skilled in the art. For example, after providing the semiconductor substrate 10 / 12 / 14, a uniform thickness layer of a third semiconductor material for providing the first sacrificial semiconductor material layer 16A, a uniform thickness layer of a fourth semiconductor material for providing the second sacrificial semiconductor layer 16B, and a uniform thickness layer of a third semiconductor material for providing the third sacrificial semiconductor material layer 16C are formed by one or more deposition processes, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or epitaxial growth. The term "epitaxial growth" or "epitaxy" refers to the growth of a second semiconductor material on the growth surface of a first semiconductor material, where the grown second semiconductor material has the same crystal characteristics as the first semiconductor material. In an epitaxial deposition process, the chemical reactants provided by the source gas are controlled and the system parameters are set such that the deposited atoms reach the growth surface of the first semiconductor material with sufficient energy to move back and forth on the growth surface and orient themselves to the crystal arrangement of the atoms on the growth surface. Examples of various epitaxial growth process equipment that can be used in this application include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature for epitaxial deposition is typically in the range of 550 °C to 900 °C. Although higher temperatures generally result in faster deposition, faster deposition may lead to crystal defects and film cracking.

[0056] Next, an alternating uniform thickness layer stack of a fourth semiconductor material for providing each fourth sacrificial semiconductor material layer 18 and a fifth semiconductor material for providing each semiconductor channel material layer 20 is formed. The blanket material stack can be formed by one or more deposition processes, including (for example) CVD, PECVD, or epitaxial growth. Then, the overlay material stack and the underlying overlay material layer can be patterned by lithography and etching to provide a fin structure including the first sacrificial semiconductor material layer 16A, the second sacrificial semiconductor material layer 16B, the third sacrificial semiconductor material layer 16C, and the alternating fourth sacrificial semiconductor material layers 18 and semiconductor channel material layers 20, as Figure 2A - 2C shown. Next, a shallow trench isolation structure 15 is formed using techniques known to those skilled in the art. Next, a uniform thickness layer of sacrificial gate structure material and a uniform thickness layer of hard mask material are formed by a deposition process, such as CVD, PECVD, physical vapor deposition (PVD), or atomic layer deposition (ALD). Then, the hard mask material and the uniform thickness layer of sacrificial gate structure material are patterned by lithography and etching to provide the sacrificial cap 24 and the sacrificial gate structure 22 described above.

[0057] Now referring toFigure 3A , 3B and 3C, respectively showing the Figure 2A , 2B exemplary structures shown in

[0058] and 2C after removing the first sacrificial semiconductor material layer 16A to form the first gap G1 and removing the third sacrificial semiconductor material layer 16C to form the second gap G2, wherein the first gap G1 and the second gap G2 are separated by the second sacrificial semiconductor material layer 16B. The first sacrificial semiconductor material layer 16A and the third sacrificial semiconductor material layer 16C can be removed using an etching process that is selective in removing the third semiconductor material relative to other semiconductor materials present in the exemplary structure, the third semiconductor material providing the first sacrificial semiconductor material layer 16A and the third sacrificial semiconductor material layer 16C. In one example, and when the third semiconductor material providing both the first sacrificial semiconductor material layer 16A and the third sacrificial semiconductor material layer 16C is composed of a silicon-germanium alloy having a germanium content of 55 atomic percent, vapor phase dry hydrochloric acid (HCl) at an appropriate temperature and pressure can be used to remove both the first sacrificial semiconductor material layer 16A and the third sacrificial semiconductor material layer 16C. Figure 4A , 4B and 4C, respectively showing the Figure 3A , 3B exemplary structures shown in

[0059] The gate dielectric spacer material consists of a dielectric material having a first dielectric constant typically less than 5.5. Examples of gate dielectric spacer materials useful in this application include, but are not limited to, SiN, SiOCN, SiON, SiOC, or SiBCN. The gate dielectric spacer material can be formed by a conformal deposition process, such as CVD, PECVD, or ALD, followed by spacer etching. The conformal deposition and spacer etching provide the above-described gate spacer 30, first bottom dielectric isolation layer 26, and third bottom dielectric isolation layer 28.

[0060] Now refer to Figure 5A , 5B and 5C, which respectively show the exemplary structures shown in Figure 4A , 4B and 4C, after patterning a material stack to form a nanosheet stack of alternating fourth sacrificial semiconductor material nanosheets 18NS and semiconductor channel material nanosheets 20NS, recessing each fourth sacrificial semiconductor material nanosheet 18NS of the nanosheet stack, and forming an inner spacer 32 laterally adjacent to each recessed fourth semiconductor material nanosheet 18NS.

[0061] The material stack is patterned using the gate spacer 30, sacrificial gate structure 22, and (if present) sacrificial cap 24 as a comb-shaped etch mask. The etching converts the material stack into a nanosheet stack as defined above. Note that the fourth sacrificial semiconductor material nanosheets 18NS and semiconductor channel material nanosheets 20NS are unetched portions of the fourth sacrificial semiconductor material layer 18 and semiconductor channel material layer 20. The fourth sacrificial semiconductor material nanosheets 18NS and semiconductor channel material nanosheets 20NS have a width of 10 nm to 100 nm and a length of 20 nm to 150 nm; this length is before forming the inner spacer 32. Then, an inner spacer 32 is formed by selectively etching (i.e., recessing) the ends of each fourth sacrificial semiconductor material nanosheet 18NS relative to each semiconductor channel material nanosheet 20NS. This selective etching (including lateral etching) provides an inner spacer gap adjacent to the recessed fourth sacrificial semiconductor material nanosheets 18NS, and then the recessed fourth sacrificial semiconductor material nanosheets are filled with an inner dielectric spacer material (e.g., SiN, SiBCN, SiOCN, SiON, or SiOC). The filling includes conformal deposition of the inner dielectric spacer material, followed by an isotropic etch-back process. The inner spacer 32 is below the ends of each semiconductor channel material nanosheet 20NS, and the inner spacer 32 has an outermost wall that is vertically aligned with the outermost wall of the gate spacer 30.

[0062] Now refer to Figure 6A , 6B and 6C, which respectively show Figure 5A ,5B After etching the surface of the second semiconductor material layer 14 of the semiconductor substrate that is physically exposed at the occupied area of at least one sacrificial gate structure 22 and on each side thereof, a semiconductor buffer layer 34 is formed on the physically exposed surface of the second semiconductor material layer 14 of the semiconductor substrate, a source / drain region 36 extending outward from each semiconductor channel material nanosheet 20NS is formed on the semiconductor buffer layer 34, and a front-side interlayer dielectric (ILD) material layer 38 is formed on the source / drain region 36.

[0063] The etching that physically exposes the surface of the second semiconductor material layer 14 of the semiconductor substrate removes portions of the third bottom dielectric isolation layer 28, the second sacrificial semiconductor material layer 16B, and the first bottom dielectric isolation layer 26 that are not directly located under the nanosheet layer stack and the gate spacer 30 provided thereon. The etching may include a dry etching process such as reactive ion etching (RIE), ion beam etching (IBE), or plasma etching.

[0064] The semiconductor buffer layer 34 is formed by an epitaxial growth process followed by trench etching. The semiconductor buffer layer 34 includes one of the semiconductor materials described above for the first semiconductor material layer 10; the semiconductor material providing the semiconductor buffer layer 34 is generally different in composition from the fourth semiconductor material providing each of the sacrificial semiconductor material nanosheets 18NS. The semiconductor buffer layer 34 has a top surface that is coplanar with, above, or below the top surface of the third bottom dielectric isolation layer 28 present under each nanosheet stack. The presence of the semiconductor buffer layer 34 provides a semiconductor growth surface on which high-quality source / drain regions 36 can be formed. "High-quality" means that the source / drain regions 36 have few epitaxy-related defects (such as missing epitaxy, stacking faults, dislocations, etc.).

[0065] The source / drain regions 36, which are formed on each side of the nanosheet stack, are composed of a semiconductor material (including one of the semiconductor materials described above for the first semiconductor material layer 10) and a dopant. As used herein, a "source / drain or S / D" region can be a source region or a drain region, depending on subsequent wiring and voltage application during the operation of the transistor. The semiconductor material providing the source / drain regions 36 can be the same as or different from the semiconductor material providing each semiconductor channel material nanosheet 20NS and / or the first semiconductor material layer 10, and the dopant present in the source / drain regions 36 can be a p-type dopant or an n-type dopant. The term "p-type" refers to adding an impurity to an intrinsic semiconductor, which creates a deficiency of valence electrons. In a silicon-containing semiconductor material, examples of p-type dopants, i.e., impurities, include but are not limited to boron, aluminum, gallium, phosphorus, and indium. "N-type" refers to adding an impurity that contributes free electrons to an intrinsic semiconductor. In a silicon-containing semiconductor material, examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic, and phosphorus. In one example, the source / drain region 36 can have a dopant concentration ranging from 4×10²⁰ atoms / cm³ to 3×10²¹ atoms / cm³. The source / drain region 36 can be formed by epitaxial growth, followed by recess etching to reduce the height of the source / drain region 36 to less than the height of the sacrificial gate structure 22.

[0066] The front-side ILD material layer 38 can be composed of a dielectric material, which includes, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" refers to a dielectric material having a dielectric constant less than 4.0. Unless otherwise specified, all dielectric constants mentioned herein are measured in a vacuum. The front-side ILD material layer 38 can be formed by depositing a dielectric material, followed by a planarization process, such as chemical mechanical polishing (CMP). The deposition of the dielectric material can include, for example, CVD, PECVD, ALD, or spin-on coating. The planarization process can remove the sacrificial cap 24 and the upper portions of each gate spacer 30, and the front-side ILD material layer 38 has a top surface coplanar with at least the top surface of the sacrificial gate structure 22.

[0067] Now referring to Figure 7A 、 7B and 7C, respectively, show the Figure 6A 、 6BThe exemplary structures shown in FIGS. 6C, where the removal of the second semiconductor material layer 16B forms a third gap G3 between the first and second gaps filled with gate dielectric spacer material; i.e., between the first bottom dielectric isolation layer 26 and the third bottom dielectric isolation layer 28.

[0068] The removal of the sacrificial gate structure 22 includes an etching process that is selective in removing the material providing the sacrificial gate structure 22. Typically, a single etch is used, but multiple etches may be used depending on the materials present in the sacrificial gate structure 22. The removal of the sacrificial gate structure 22 exposes each nanosheet stack.

[0069] The same selective etching process can be used to remove the second sacrificial semiconductor material layer 16B and each recessed fourth semiconductor material nanosheet 18NS. In addition to creating the third gap G3, this selective etch suspends portions of each semiconductor channel material nanosheet 20NS.

[0070] Now referring to Figure 8A 、 8B and 8C, respectively, show the exemplary structures after forming a high-k gate dielectric material 40L in the third gap and on the physically exposed portions of each semiconductor channel material nanosheet 20Ns (the high-k gate dielectric material 40L is also formed on the physically exposed surface of the shallow trench isolation structure 15, as shown in Figure 7A 、 7B and 7C, and on the top surface of the front-side ILD material layer, as shown in Figure 8B and formed on the top surface of the front-side ILD material layer, as shown in Figure 8A and 8C ). The high-k gate dielectric material 40L has a second dielectric constant greater than the first dielectric constant mentioned above for the gate dielectric spacer material. Thus, the high-k gate dielectric material 40L includes a dielectric material that is compositionally different from the gate dielectric spacer material.

[0071] The high-k gate dielectric material 40L has a dielectric constant of 4.0 or greater. Illustrative examples of high-k gate dielectric materials include metal oxides such as silicon dioxide, hafnium dioxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO 3 ), zirconium dioxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 4 ), zirconium silicon oxynitride (ZrSiO x N y ), tantalum oxide (TaO x ), titanium oxide (TiO), barium strontium titanium oxide (BaO6 SrTi 2 ) barium titanate (BaTiO 3 ) strontium titanate (SrTiO 3 ) ytterbium oxide (Yb 2 O 3 ) aluminum oxide (Al 2 O 3 ) lead scandium tantalum oxide (Pb(Sc,Ta)O 3 ) and / or lead zinc niobium (Pb(Zn,Nb)O). The high-k gate dielectric material 40L may also include dopants such as lanthanum (La), aluminum (Al), and / or magnesium (Mg). The high-k gate dielectric material 40L can be formed using any conformal deposition process, such as CVD, PECVD, or ALD.

[0072] Now refer to Figure 9A and 9B and 9C, which respectively show exemplary structures shown in Figure 8A and 8B and 8C, after forming the gate electrode 42, forming the gate cut dielectric pillar 44, forming the second front ILD material layer 46, and forming the front contact structures 48, 49.

[0073] The WFM layer can be used to set the threshold voltage of the transistor to a desired value. In some embodiments, the WFM layer can be selected to achieve an n-type threshold voltage shift. As used herein, "n-type threshold voltage shift" means the shift of the effective work function of a metal-containing material towards the conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal is 4.1 eV to 4.3 eV. Examples of such materials that can achieve an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM layer can be selected to achieve a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9 eV to 5.2 eV. As used herein, "threshold voltage" is the lowest achievable gate voltage that turns on a semiconductor device (e.g., a transistor) by conducting the channel of the device. As used herein, the term "p-type threshold voltage shift" means the shift of the effective work function of a material containing a work function metal towards the valence band of silicon in a silicon-containing material. Examples of such materials that can achieve a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. The optional conductive metal layer of the gate electrode 42 can be composed of aluminum (Al), tungsten (W), copper (Co), etc.

[0074] The gate 42 can be formed by a deposition process, followed by a planarization process such as CMP. The deposition process includes but is not limited to CVD, PECVD, sputtering, or electroplating. The planarization process removes any WFM layer and, if present, the conductive metal layer present on top of the first ILD material layer 38 and the gate spacer 30. The planarization process also removes the high-k gate dielectric material 40L present on top of the first ILD material layer 38 and the gate spacer 30. The high-k gate dielectric material 40L remains in the third gap G3. Along the physically exposed surface of each semiconductor channel material nanosheet, along the inner sidewall of the gate spacer, along the uppermost surface of the shallow trench isolation structure 15, and along the physically exposed surface of the first bottom dielectric isolation layer 26 and the third bottom dielectric isolation layer 38, the remaining high-k gate dielectric material 40L present in the third gap G3 can be referred to herein as the second bottom dielectric isolation layer 41 of the three-layer bottom dielectric isolation structure. The three-layer bottom dielectric isolation structure further includes the first bottom dielectric isolation layer 26 and the third bottom dielectric isolation layer 28. The second bottom dielectric isolation layer 41 of the three-layer bottom dielectric isolation structure is sandwiched between the first dielectric isolation layer and the third bottom dielectric isolation layer 28 of the three-layer bottom dielectric isolation layer. The high-k gate dielectric material 40L present on the physically exposed portion of the semiconductor channel material nanosheet 20NS, along the inner sidewall of the gate spacer 30, forms the gate dielectric material layer 40 of the gate structure of the transistor; the gate structure further includes a gate electrode 42, which includes a WFM layer and an optional conductive metal layer. The high-k material layer remaining on the physically exposed surfaces of the first and second bottom dielectric isolation layers 26 and 28 also forms the gate dielectric material layer of the gate structure.

[0075] After forming the gate electrode 42, a gate cut dielectric pillar 44 is formed by forming a gate cut trench (not shown) in the gate electrode 42 and then filling the gate cut trench with a gate cut dielectric material (e.g., silicon dioxide or silicon nitride). The gate cut dielectric pillar 44 extends through the gate electrode 42 and a portion of the high-k gate material present on the shallow trench isolation structure 15. The gate cut dielectric pillar 44 has a top surface coplanar with the topmost surface of the gate electrode 42.

[0076] The second front ILD material layer 46 includes one of the dielectric materials described above for the first front ILD material layer 38. The dielectric material providing the second front ILD material layer 46 can be the same as or different in composition from the dielectric material providing the first front ILD material layer 38. The second front ILD material layer 46 can be formed using one of the deposition processes described above for forming the dielectric material providing the first front ILD material layer 38.

[0077] The front contact structures 48, 49 are formed using any conventional metallization process. The front-side contact structure that contacts the source / drain region 36 can be referred to as the front-side source / drain contact structure 48, and the front-side contact structure that contacts the gate electrode 42 can be referred to as the front-side gate contact structure 49. The front contact structures 48, 49 at least include a contact conductor material, such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or an alloy thereof. In an embodiment, the front contact structures 48, 49 may further include a silicide liner such as TiSi, NiSi, NiPtSi, etc., and an adhesion metal liner such as TiN. Each front contact structure 48, 49 can be formed by forming contact openings in various front-side ILD material layers through photolithography and etching. In the case of the front-side gate contact structure 49, the contact opening is formed only through the second front-side ILD material layer 46, while in the case of the front-side source / drain contact structure 48, the contact opening is formed through the first and second front-side ILD material layers 38, 46. In some embodiments (not shown), a metal-semiconductor alloy region may be formed in each contact opening before forming the contact conductor material. The metal-semiconductor alloy region may be composed of a silicide or a germicide. In one or more embodiments of the present application, the metal-semiconductor alloy region can be formed by first depositing a metal layer (not shown) in the trench. The metal layer may include metals such as Ni, Co, Pt, W, Ti, Ta, rare earth metals (such as Er, Yt, La), alloys thereof, or any combination thereof. The metal layer can be deposited by ALD, CVD, PVD, or ALD. The thickness of the metal layer can be from 2 nm to 10 nm, although smaller or larger thicknesses can also be employed. Then, a diffusion barrier layer (not shown), such as TiN or TaN, can be formed on the metal layer. Subsequently, an annealing process can be performed at an elevated temperature to cause a reaction of the semiconductor material in the source / drain region, thereby providing a metal-semiconductor alloy region. Then, the unreacted portion of the metal layer, and if present, the diffusion barrier layer, are removed, for example, by an etching process (or multiple etching processes). In one embodiment, the etching process can be a wet etching that selectively removes the metal in the metal layer relative to the metal-semiconductor alloy in the metal-semiconductor alloy region. Each front contact structure 48, 49 may further include one or more contact pads (not shown). In one or more embodiments, the contact liner (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or laminates thereof, such as Ti / TiN and Ti / WC. The contact liner can be formed using a conformal deposition process including CVD or ALD. The formed contact liner may have a thickness ranging from 1 nm to 5 nm, although smaller or larger thicknesses can also be employed.Each front-side contact structure 48, 49 has a top surface coplanar with the topmost surface of the second front-side ILD material layer 46.

[0078] Now refer to Figure 10A , 10B and 10C, which respectively show the Figure 9A , 9B and exemplary structures shown in 9C after forming the front-side back-end-of-line (BEOL) structure 50 and the carrier wafer 52. The front-side BEOL structure 50 can be formed using BEOL processing techniques known to those skilled in the art. As Figure 10A - 10C shown, the front-side BEOL structure 50 is electrically connected to one of the source / drain regions 36 through the front-side source / drain contact structure 48, and it is also electrically connected to the gate electrode 42 through the front-side gate contact structure 39.

[0079] Now refer to Figure 11A , 11B and 11C, which respectively show the Figure 10A , 10B and exemplary structures shown in 10C after the wafer is flipped to physically expose the back side 10 / 12 / 14 of the semiconductor substrate and the first semiconductor material 10 of the semiconductor substrate is removed to physically expose the etch stop layer 12 of the semiconductor substrate. The flipping will allow back-side processing of the exemplary structure. In this application, the structure is flipped 180°. The flipping of the structure can be performed by hand or by using a mechanical device such as a robotic arm. The removal of the first semiconductor material layer 10 can be performed using a material removal process that is selective in removing the semiconductor material providing the first semiconductor material layer 10.

[0080] Now refer to Figure 12A , 12B and 12C, which respectively show the Figure 11A , 11B and exemplary structures shown in 11C after the physically exposed etch stop layer 12 of the semiconductor substrate is removed to physically expose the second semiconductor material layer 14 of the semiconductor substrate. The removal of the etch stop layer 12 includes a material removal process that is selective in removing the etch stop layer 12.

[0081] Now refer to Figure 13A , 13B and 13C, which respectively show the Figure 12A , 12B and exemplary structures shown in 12C after removing the second semiconductor material layer 14 and a portion of the semiconductor buffer layer 34. The recess etching for removing a portion of the semiconductor buffer layer 34 can be the same or different from the selective etching for removing the second semiconductor material layer 14. A portion of the semiconductor buffer layer 34 remains as Figure 13Abetween the three-layer bottom dielectric isolation structures 26 / 41 / 28 shown and Figure 13C between the gate spacers 30 shown. The remaining semiconductor buffer layer 34 may herein be referred to as the recessed semiconductor buffer layer 34S.

[0082] Now referring to Figure 14A 、 14B and 14C, exemplary structures shown in Figure 13A 、 13B and 13C respectively after the formation of the backside ILD material layer 54 are shown. The backside ILD material layer 54 includes one of the dielectric materials mentioned above for the first frontside ILD material layer 38. The dielectric material providing the backside ILD material layer 54 may be the same as or different from the dielectric material providing the first frontside ILD material layer 38 in composition.

[0083] Now referring to Figure 15A 、 15B and 15C, exemplary structures shown in Figure 14A 、 14B and 14C respectively after the formation of the self-aligned backside source / drain contact structure 56 are shown. When the term "self-aligned" is used with the phrase "backside source / drain contact structure", it means that the backside contact structure is only connected to the source / drain region 36 without shorting to a nearby gate structure even if the contact structure physically overlaps with the gate structure. The self-aligned backside source / drain contact structure 56 is formed into the backside ILD material layer 54 and the recessed semiconductor buffer layer 34S. In the Figure 15A and 15C shown flip-chip structure, the self-aligned backside source / drain contact structure 56 has the bottommost surface in direct physical contact with one of the source / drain regions. As Figure 15A further shown, the self-aligned backside source / drain contact structure 56 overlaps and contacts the three-layer bottom dielectric isolation structure 26 / 41 / 28 of the present application. It is noted that the self-aligned backside source / drain contact structure 56 contacts the sidewall of the first bottom dielectric isolation layer 26, the horizontal and sidewall surfaces of the second bottom dielectric isolation layer (i.e., the high-k dielectric material) 41, and the sidewall surface of the third bottom dielectric isolation layer 28.

[0084] The self-aligned backside source / drain contact structure 56 is formed using a metallization process that includes forming backside contact openings in the backside ILD material layer 54 and the recessed semiconductor buffer layer 34S, and then filling the backside contact openings with at least one of the contact conductor materials used for the frontside contact structures 48, 49. The self-aligned backside source / drain contact structure 56 may also include any of the liners used for the frontside contact structures 48, 49. A three-layer bottom dielectric isolation structure 26 / 41 / 28 forms a protective cap structure over the gate structure such that the self-aligned backside source / drain contact structure 56 remains isolated from the gate structure even in the presence of any corner loss during the etching of the backside ILD material layer 54.

[0085] Now referring Figure 16A , 16B and 16C, respectively show exemplary structures shown in Figure 15A , 15B and 15C. After forming additional backside ILD material over the backside LID material layer 54 and the self-aligned backside source / drain contact structure 56, and forming the backside power rail 58 and the backside power distribution network 60, the additional backside ILD material and the backside ILD material layer 54 together form a multi-layer backside ILD material structure 55. The additional backside material may include one of the dielectric materials used for the frontside ILD material layer 46.

[0086] The backside power rail 58 is composed of any conductive power rail material, including but not limited to tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), platinum (Pt), rhodium (Rh), or palladium (Pd), where a thin metal adhesion layer (such as TiN, TaN) is typically formed before the deposition of the conductive metal; for clarity, the metal adhesion layer is not shown separately in the figures of the present application. The backside power rail 58 can be formed by forming a backside power rail opening in the multi-layer backside ILD material structure 55; the backside power rail opening physically exposes the surface of the self-aligned backside source / drain contact structure 56, and then the backside power rail opening is filled with at least one of the above conductive power rail materials, and a planarization process can follow the filling of the backside power rail opening. The filling may include CVD, PECVD, ALD, sputtering, or electroplating. The resulting backside power rail 58 formed in the backside power rail opening is electrically connected to the source / drain region 36 through the self-aligned backside source / drain contact structure 56.

[0087] The backside power distribution network 60 is formed on top of the multi-layer backside ILD material structure 55 and on top of the backside power rail 58 embedded in the multi-layer backside ILD material structure 55. Thus, the backside power distribution network 60 contacts the backside power rail 58, and the backside power distribution network 60 includes components configured to distribute power to the transistors.

[0088] Note that Figure 16A - 16C shows a semiconductor structure in accordance with an embodiment of the present application. The illustrated structure includes a transistor (i.e., the intermediate structure shown in Figure 16A ), which includes gate structures 40, 42 and a first source / drain region located on a first side of the gate structures 40, 42 (i.e., source / drain region 36 on the right hand side of the intermediate gate structure) and a second source / drain region located on a second side of the gate structures (i.e., source / drain region 36 on the left hand side of the intermediate gate structure). The structure further includes a three-layer bottom dielectric isolation structure 26, 41, 28 located below the transistor, a backside power rail 58 located below and spaced apart from the three-layer bottom dielectric isolation structure 26, 41, 28, and a backside source / drain contact structure 56 that connects the backside power rail 58 to the first source / drain region of the transistor. According to the present application, the backside source / drain contact structure 56 overlaps at least a portion of the three-layer bottom dielectric isolation structure 26, 41, 28 (e.g., see Figure 16A ). The presence of the three-layer bottom dielectric isolation structure 26, 41, 28 provides a thick dielectric capping layer that prevents the backside source / drain contact structure 56 from shorting out the gate structures. In the prior art, the bottom isolation structure is a thin structure, typically less than 10 nm, and thus a short circuit between the gate structure and the backside source / drain contact structure may occur.

[0089] As described above, the three-layer bottom dielectric isolation structure 26, 41, 28 includes a first bottom dielectric isolation layer 26, a second bottom dielectric isolation layer 41, and a third bottom dielectric isolation layer 28. As Figure 16A shown, the backside source / drain contact structure 56 contacts the sidewalls of the first bottom dielectric isolation layer 26, the horizontal and sidewall surfaces of the second bottom dielectric isolation layer 41, and the sidewalls of the third bottom dielectric isolation layer 28. Note that when the structure shown in Figure 16A - 16C is flipped 180°, the gate electrode 42 is located above and laterally adjacent to the three-layer bottom dielectric isolation structure 26, 41, 28.

[0090] Although the present application has been specifically shown and described with reference to preferred embodiments thereof, those skilled in the art will understand that the foregoing and other changes may be made in form and detail without departing from the scope of the present application. Accordingly, the present application should not be limited to the exact forms and details described and shown, but falls within the scope of the appended claims.

Claims

1. A semiconductor structure, comprising: a transistor including a gate structure, a first source / drain region located on a first side of the gate structure, and a second source / drain region located on a second side of the gate structure; a three-layer bottom dielectric isolation structure located below the transistor; a backside power rail located below and spaced apart from the three-layer bottom dielectric isolation structure; and a backside source / drain contact structure connecting the backside power rail to the first source / drain region of the transistor, wherein the backside source / drain contact structure overlaps at least a portion of the three-layer bottom dielectric isolation structure.

2. The semiconductor structure according to claim 1, wherein the three-layer bottom dielectric isolation structure includes a first bottom dielectric isolation layer, a second bottom dielectric isolation layer, and a third bottom dielectric isolation layer, wherein both the first bottom dielectric isolation layer and the third bottom dielectric isolation layer are composed of a first dielectric material, and the second bottom dielectric isolation layer is composed of a second dielectric material different from the first dielectric material.

3. The semiconductor structure according to claim 2, wherein the first dielectric material includes a low-k spacer dielectric material, and the second dielectric material includes a high-k gate dielectric material.

4. The semiconductor structure according to claim 2, further comprising a gate spacer on a sidewall of the gate structure, and wherein the gate spacer is composed of the first dielectric material.

5. The semiconductor structure according to claim 2, wherein the gate structure includes a gate dielectric material layer, and wherein the gate dielectric material layer is composed of the second dielectric material.

6. The semiconductor structure according to claim 2, wherein the backside source / drain contact structure contacts a sidewall of the first bottom dielectric isolation layer, a horizontal surface and a sidewall surface of the second bottom dielectric isolation layer, and a sidewall of the third bottom dielectric isolation layer.

7. The semiconductor structure according to claim 1, further comprising a semiconductor buffer layer on a surface of the first source / drain region, wherein the semiconductor buffer layer is embedded in a portion of the backside source / drain contact structure.

8. The semiconductor structure according to claim 7, further comprising a multi-layer backside interlayer dielectric material structure embedded in another portion of the backside source / drain contact structure, wherein the multi-layer backside interlayer dielectric material structure is also embedded in the backside power rail.

9. The semiconductor structure according to claim 1, further comprising a backside power distribution network contacting the backside power rail.

10. The semiconductor structure according to claim 1, further comprising a frontside source / drain contact structure contacting the second source / drain region.

11. The semiconductor structure according to claim 10, wherein the frontside source / drain contact structure is embedded in a first frontside interlayer dielectric material layer and a second frontside interlayer dielectric material layer.

12. The semiconductor structure according to claim 11 further includes a front-side gate contact structure located in the second front-side interlayer dielectric material layer and contacting the gate electrode of the gate structure.

13. The semiconductor structure according to claim 11 further includes a front-side back-end-of-line structure located on the second front-side interlayer dielectric material layer, wherein the front-side back-end-of-line structure is electrically connected to the second source / drain region through the front-side source / drain contact structure.

14. The semiconductor structure according to claim 13 further includes a carrier wafer located on the surface of the front-side back-end-of-line structure.

15. The semiconductor structure according to claim 1, wherein the transistor is located on one side of a gate cut dielectric pillar.

16. The semiconductor structure according to claim 1, wherein the transistor is a nanosheet transistor including a nanosheet stack of suspended semiconductor channel material nanosheets.

17. The semiconductor structure according to claim 16, wherein the gate structure surrounds each of the suspended semiconductor material nanosheets in the suspended semiconductor material nanosheets.

18. The semiconductor structure according to claim 1, wherein the gate structure includes a gate electrode located above the three-layer bottom dielectric isolation structure and laterally adjacent to the three-layer bottom dielectric isolation structure.

19. A method of forming a semiconductor structure, the method comprising: forming a three-layer bottom dielectric isolation structure under a gate structure of a transistor, the transistor including a first source / drain region located on one side of the gate structure and a second source / drain region located on a second side of the gate structure; and forming a back-side source / drain contact structure in contact with the surface of the first source / drain region, wherein forming the back-side source / drain contact structure includes partially etching through the three-layer bottom dielectric isolation structure.

20. The method according to claim 19, wherein the three-layer bottom dielectric isolation structure includes a first bottom dielectric isolation layer, a second bottom dielectric isolation layer, and a third bottom dielectric isolation layer, wherein both the first bottom dielectric isolation layer and the third bottom dielectric isolation layer are composed of a first dielectric material, and the second bottom dielectric isolation layer is composed of a second dielectric material different from the first dielectric material, and a portion of the first bottom dielectric isolation layer is etched away while stopping on the second bottom dielectric isolation layer.

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