Method and system for realizing high-precision timer based on FPGA (Field Programmable Gate Array)

Abstract

The invention provides a high-precision timer implementation method and system based on an FPGA, and belongs to the technical field of counters, and the working principle is that a phase-locked loop generates a phase dislocation clock signal by adjusting the frequency of a voltage-controlled oscillator and setting the offset through a phase register. And the timer counts the rising edge or the falling edge of the phase dislocation clock signal corresponding to the timer. And the count values of the plurality of timers are added to form one timer. The resolution of the synthesized timer is calculated through the period of the phase-dislocation clock signals and the number of the phase-dislocation clock signals generated by the phase-locked loop in the first step. The device has the advantages of ultrahigh time resolution, simple structure, few called resources and lower design complexity.

Description

Technical Field

[0001] The present invention belongs to the technical field of counters, and in particular, relates to a method and system for realizing a high-precision timer based on FPGA. Background Art

[0002] In modern scientific and technological applications, high-precision time measurement technology has a wide range of application needs in the fields of communication, navigation, industrial control, scientific experiments, etc. For example, in 5G communication systems, time synchronization accuracy is required to reach the nanosecond level; in satellite navigation systems, time measurement accuracy directly affects positioning accuracy; in industrial automation control, high-precision timers are key components for achieving precise control and data acquisition.

[0003] Chinese patent 101498951A relates to a method for processing time values ​​in a computer (10, 20) or a programmable machine. Modern computers (10, 20) come with different timers with different properties such as time resolution, supported time range and time reference. Some are local timers, representing relative time values ​​such as TSC counters (11, 21) that count CPU cycles since the computer was turned on or reset. Some are global timers, representing absolute or real time. There are different timer classes in the computer, and various calculations need to be performed to relate different timers to each other. The idea of ​​the invention is to define a single high-resolution timer structure, in which time values ​​are represented by numbers and a tag clarifies whether the timer is a global timer or a local timer.

[0004] Existing technologies are limited by their clock frequency and software processing delays and are unable to meet the needs of high-precision time measurement. Summary of the invention

[0005] The present invention aims to provide a method and system for realizing a high-precision timer based on FPGA, so as to achieve the technical purpose of improving the accuracy of the timer.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] The present invention provides a high-precision timer implementation method based on FPGA:

[0008] Step 1: A phase-locked loop generates multiple out-of-phase clock signals.

[0009] Step 2: Generate a timer based on each out-of-phase clock signal, and the timer counts respectively.

[0010] Step 3: Add the count values ​​of multiple timers to form a timer.

[0011] In step 1, the phase-locked loop generates phase-shifted clock signals in sequence, and the phase difference of the phase-shifted clock signals is constant.

[0012] In step 1, the phase-locked loop generates a phase-shifted clock signal by adjusting the frequency of the voltage-controlled oscillator and setting the offset through the phase register.

[0013] In step 1, the step of generating a phase-shifted clock signal through a phase-locked loop may also generate multiple phase-shifted clock signals through a digital clock manager.

[0014] The digital clock manager generates multiple out-of-phase clock signals by setting the frequency multiplication factor, the frequency division factor and the phase offset.

[0015] In step 2, the timer counts the rising edge or falling edge of the out-of-phase clock signal corresponding to it.

[0016] In step three, the resolution of the synthesized timer is calculated by the period of the out-of-phase clock signal and the number of out-of-phase clock signals generated by the phase-locked loop in step one.

[0017] The present invention provides a system for realizing a high-precision timer based on FPGA, comprising a staggered clock signal generating module and a timer module, wherein the clock signal generating module is used to generate a staggered clock signal, and the output end of the clock signal generating module is connected to the input end of the timer module.

[0018] The clock signal generating module adopts a phase-locked loop or a digital clock manager.

[0019] The timer module adopts a timer.

[0020] The technical effects of the present invention are:

[0021] (1) The timer of the present invention has ultra-high time resolution. The present invention uses four timers to count the rising edges of their respective clocks, and the resolution of the synthesized timer reaches 2.5ns. Compared with the traditional single clock, the time accuracy is improved by 4 times, which is suitable for scenarios requiring sub-nanosecond accuracy.

[0022] (2) The present invention has a simple structure, requires few resources, and has a low design complexity.

[0023] (3) The present invention can adjust the number and phase difference of the out-of-phase clock signals according to the needs to adapt to different accuracy requirements.

[0024] (4) The phase control flexibility of the present invention can easily generate clock signals with arbitrary phase differences by utilizing the phase offset parameters of a phase-locked loop or a digital clock manager.

[0025] (5) The invention uses a single phase-locked loop or digital clock manager to generate multiple out-of-phase clocks, avoiding the use of multiple independent clock sources and reducing the internal resource usage of the FPGA. Sharing the same reference clock reduces overall power consumption, which is particularly suitable for low-power applications.

[0026] (6) The present invention reduces external dependence and provides an on-chip solution, without the need for an external high-frequency clock source or complex frequency division circuit. Functions are implemented through FPGA internal resources, simplifying system design and improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] This specification includes the following drawings, which show the following contents:

[0028] Figure 1 A flowchart of a method and system for realizing a high-precision timer based on FPGA according to the present invention;

[0029] Figure 2 This is a schematic diagram of a timer synthesis principle of a high-precision timer implementation method and system based on FPGA of the present invention. DETAILED DESCRIPTION

[0030] The specific implementation methods of the present invention are further explained in detail below by describing the embodiments with reference to the accompanying drawings, with the aim of helping those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention and facilitating their implementation.

[0031] The present invention provides a high-precision timer implementation method based on FPGA:

[0032] Step 1: A phase-locked loop generates multiple out-of-phase clock signals.

[0033] Step 2: Generate a timer based on each out-of-phase clock signal, and the timer counts respectively.

[0034] Step 3: Add the count values ​​of multiple timers to form a timer.

[0035] In step 1, the phase-locked loop generates phase-shifted clock signals in sequence, and the phase difference of the phase-shifted clock signals is constant.

[0036] In step 1, the phase-locked loop generates a phase-shifted clock signal by adjusting the frequency of the voltage-controlled oscillator and setting the offset through the phase register.

[0037] In step 1, the step of generating a phase-shifted clock signal through a phase-locked loop may also generate multiple phase-shifted clock signals through a digital clock manager.

[0038] The digital clock manager generates multiple out-of-phase clock signals by setting the frequency multiplication factor, the frequency division factor and the phase offset.

[0039] In step 2, the timer counts the rising edge or falling edge of the out-of-phase clock signal corresponding to it.

[0040] In step three, the resolution of the synthesized timer is calculated by the period of the out-of-phase clock signal and the number of out-of-phase clock signals generated by the phase-locked loop in step one.

[0041] The present invention provides a system for implementing a high-precision timer based on FPGA, comprising a staggered clock signal generating module and a timer module, wherein the clock signal generating module is used to generate a staggered clock signal, and the output end of the clock signal generating module is connected to the input end of the timer module. The clock signal generating module adopts a phase-locked loop or a digital clock manager. The timer module adopts a timer.

[0042] The following describes in detail a method for realizing a high-precision timer based on FPGA of the present invention.

[0043] The phase-locked loop in the FPGA generates multiple out-of-phase clock signals. Specifically, the phase-locked loop generates a clock signal higher than the system clock reference frequency through a voltage-controlled oscillator based on the system clock reference frequency, then divides the output of the voltage-controlled oscillator and adjusts the phase through a phase register.

[0044] The following is a description of the embodiment. The phase-locked loop is based on the reference frequency of the system clock of 100MHz. The reference frequency of 100MHz is multiplied to 400MHz by a voltage-controlled oscillator, and the output of the voltage-controlled oscillator is divided, and the phase is adjusted by a phase register to obtain four phase-shifted clock signals (0°, 90°, 180°, 270°) with a phase difference of 90°. It should be noted that most phase-locked loops now support direct output of multiple fixed-phase clocks, such as Intel / Altera PLL, and use the phase_shift parameter to set the phase offset.

[0045] The above-mentioned generation of the phase-out clock signal through the phase-locked loop can also use a digital clock manager. Specifically, before using the digital clock manager, its parameters are configured according to the design requirements. These parameters include the multiplication factor, the division factor and the phase offset. The multiplication factor is used to increase the clock frequency, the division factor is used to reduce the clock frequency, and the phase offset is used to set the phase difference of the output clock relative to the input clock. In an embodiment of the present invention, the multiplication factor is 4, the division factor is 4, and the phase offset is 90°. The digital clock manager generates 4 phase-out clock signals (0°, 90°, 180°, 270°) with a phase difference of 90°.

[0046] The FPGA generates a timer based on each out-of-phase clock signal, and the timers count respectively. Specifically, each timer counts the rising edge or falling edge of the out-of-phase clock signal corresponding to it. In an embodiment of the present invention, four timers count the rising edges of four out-of-phase clock signals respectively.

[0047] The count values ​​of multiple timers are added together to form a timer. The resolution of the synthesized timer is calculated by the period of the staggered clock signal and the number of staggered clock signals generated by the phase-locked loop in step 1. In an embodiment of the present invention, the count values ​​of the timers corresponding to the four staggered clock signals are added together to form a timer, which can reach The time resolution of the timer in the embodiment of the present invention can reach 2.5ns. Figure 2 As shown, timers CNT1, CNT2, CNT3 and CNT4 respectively collect rising edges of out-of-phase clock signals with phases of 0°, 90°, 180° and 270°, and synthesize them to obtain counter CNT. The present invention can adjust the number and phase difference of out-of-phase clock signals according to requirements to meet different accuracy requirements.

[0048] The present invention is based on FPGA. Field Programmable Gate Array (FPGA) is a programmable logic device with the characteristics of strong parallel processing capability and flexible design, and is very suitable for realizing various timer functions.

[0049] The system of the high-precision timer implementation method based on FPGA of the present invention comprises a clock signal generation module and a timer module, wherein the clock signal generation module adopts a phase-locked loop or a digital clock manager to generate a phase-out clock signal, the output end of the clock signal generation module is connected to the input end of the timer module, and the timer module adopts a timer. The structure of the present invention is simple, the calling resources are small, and the design complexity is low.

[0050] The timer of the present invention has ultra-high time resolution. The present invention uses four timers to count the rising edges of their respective clocks, and the resolution of the synthesized timer reaches 2.5ns. Compared with the traditional single clock, the time accuracy is improved by 4 times, which is suitable for scenarios requiring sub-nanosecond accuracy.

[0051] The phase control flexibility of the present invention can easily generate a clock signal with any phase difference by utilizing the phase offset parameter of a phase-locked loop or a digital clock manager.

[0052] The resource efficient utilization of the present invention generates multiple out-of-phase clocks through a single phase-locked loop or digital clock manager, avoids the use of multiple independent clock sources, reduces the internal resource occupation of FPGA, shares the same reference clock, reduces the overall power consumption, and is particularly suitable for low-power applications.

[0053] The present invention reduces external dependence and provides an on-chip solution without the need for an external high-frequency clock source or a complex frequency division circuit. Functions are implemented through internal resources of the FPGA, thereby simplifying system design and improving reliability.

[0054] The present invention is described above by way of example in conjunction with the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-mentioned methods. As long as various non-substantial improvements are made using the method concept and technical solution of the present invention; or the above concept and technical solution of the present invention are directly applied to other occasions without improvement, they are all within the protection scope of the present invention.

Claims

1. A method for implementing a high-precision timer based on FPGA, characterized in that: Step 1: The phase-locked loop generates multiple out-of-phase clock signals; Step 2: generating a timer based on each out-of-phase clock signal, and the timer counts respectively; Step 3: Add the count values ​​of multiple timers to form a timer.

2. The method for implementing a high-precision timer based on FPGA as claimed in claim 1, characterized in that: In step 1, the phase-locked loop generates phase-shifted clock signals in sequence, and the phase difference of the phase-shifted clock signals is constant.

3. The method for implementing a high-precision timer based on FPGA as claimed in claim 1, characterized in that: In step 1, the phase-locked loop generates a phase-shifted clock signal by adjusting the frequency of the voltage-controlled oscillator and setting the offset through the phase register.

4. The method for implementing a high-precision timer based on FPGA as claimed in claim 1, characterized in that: In step 1, the step of generating a phase-shifted clock signal through a phase-locked loop may also generate multiple phase-shifted clock signals through a digital clock manager.

5. The method for implementing a high-precision timer based on FPGA as claimed in claim 4, characterized in that: The digital clock manager generates multiple out-of-phase clock signals by setting the frequency multiplication factor, the frequency division factor and the phase offset.

6. The method for implementing a high-precision timer based on FPGA as claimed in claim 1, characterized in that: In step 2, the timer counts the rising edge or falling edge of the out-of-phase clock signal corresponding to it.

7. The method for implementing a high-precision timer based on FPGA as claimed in claim 1, characterized in that: In step three, the resolution of the synthesized timer is calculated by the period of the out-of-phase clock signal and the number of out-of-phase clock signals generated by the phase-locked loop in step one.

8. A system for implementing a high-precision timer based on FPGA as claimed in any one of claims 1 to 7, characterized in that: It comprises a phase-shifted clock signal generating module and a timer module. The clock signal generating module is used to generate a phase-shifted clock signal. The output end of the clock signal generating module is connected to the input end of the timer module.

9. The system for implementing a high-precision timer based on FPGA as claimed in claim 8, characterized in that: The clock signal generating module adopts a phase-locked loop or a digital clock manager.

10. The system for implementing a high-precision timer based on FPGA as claimed in claim 8, characterized in that: The timer module adopts a timer.

Images