Data read-write system and data read-write method
By introducing multiple NAND Flash chips and controllers into the SSD system and using the decoder to form a parallel data path, the problem of long SSD data writing time is solved, and a more efficient data writing process is achieved.
Patent Information
- Application Number
- CN202311649137.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-04
- Publication Date
- 2025-06-06
AI Technical Summary
Existing SSD data is written for a long time, resulting in wasted time.
By introducing multiple NAND Flash chips and NAND Flash controllers into the data read and write system, and encoding the data to be written using a decoder, multiple parallel data paths are formed to realize the writing of data into multiple NAND Flash chips at the same time.
It greatly reduces the data writing time, improves the time utilization rate, and avoids wasting time during the data writing process.
Smart Images
Figure CN120104036A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of memory, and in particular to a data reading and writing system and a data reading and writing method. Background Art
[0002] Solid State Disk (SSD) is widely used in electronic devices such as mobile phones, computers, and servers. Its advantages of high performance, low cost, and high reliability have gradually replaced the mechanical hard disk, which was once the mainstream storage device. As the main storage medium in SSD, NAND Flash plays a very important role in the storage market. It has significant read and write speeds, very high storage density, and very stable and reliable data storage capabilities.
[0003] At present, SSD is a data reading and writing system, including a bus, a codec and a NAND Flash. Figure 1 As shown, when writing data to the SSD, the data needs to be transmitted from the host to the ECC encoder through the bus, and the encoded data is transmitted from the encoder to the NAND Flash through the NAND Flash Controller for storage. In this way, the encoder and NAND Flash form a series data path, but in this way, the data writing time is long, which wastes time. Summary of the invention
[0004] In view of this, the purpose of this application is to provide a data reading and writing system and a data reading and writing method, which writes the data to be written into multiple NAND Flash chips, greatly reduces the data writing time, improves the time utilization rate, and avoids wasting time. The specific scheme is as follows:
[0005] On the one hand, the present application provides a data reading and writing system, the system comprising:
[0006] A codec connected to the bus, the codec is used to encode the data to be written to obtain a plurality of coded data; the data to be written includes a plurality of page data, and the plurality of coded data corresponds to the plurality of page data in a one-to-one manner;
[0007] Multiple NAND Flash chips and multiple NAND Flash controllers, one NAND Flash chip is connected to the bus through one NAND Flash controller, and each NAND Flash controller is used to control writing of the encoded data to each NAND Flash chip, so as to write the data to be written into the multiple NAND Flash chips.
[0008] Specifically, the NAND Flash controller is also used to control the acquisition of the to-be-read data from the NAND Flash chip;
[0009] The encoder is also used to perform a decoding operation on the data to be read to obtain decoded data, so as to realize reading the data to be read from the plurality of NAND Flash chips.
[0010] Specifically, the NAND Flash controller includes a main control module, and the main control module includes a read-write state machine and a memory;
[0011] The read / write state machine is used to receive first register configuration information and convert the first register configuration information into write instruction information, the write instruction information is used to control writing of the encoded data into the NAND Flash chip, and the memory is used to store the encoded data.
[0012] Specifically, the read / write state machine is further used to receive second register configuration information and convert the second register configuration information into read instruction information, where the read instruction information is used to control reading of the to-be-read data from the NAND Flash chip.
[0013] Specifically, the system also includes a flash memory converter connected to the bus, and the flash memory converter is used to send first register configuration information to the NAND Flash controller according to a data write instruction, and is also used to send second register configuration information to the NAND Flash controller according to a data read instruction.
[0014] Specifically, the NAND Flash controller also includes an AXI interface module for connecting to the bus.
[0015] Specifically, the codec includes an encoding module, a decoding module and a control logic module, and the control logic module is used to control the encoding module to encode and control the decoding module to decode.
[0016] Specifically, the codec includes an LDPC codec.
[0017] On the other hand, an embodiment of the present application further provides a data reading and writing method, which is applied to a data reading and writing system, wherein the data reading and writing system includes a codec and a plurality of NAND Flash chips, wherein the codec and the plurality of NAND Flash chips are connected in parallel to a bus, and the method includes:
[0018] When receiving a data write instruction, obtaining data to be written; the data to be written includes a first page of data, a plurality of second pages of data, and a plurality of third pages of data;
[0019] Encoding the first page data using the codec to obtain first encoded data;
[0020] In the process of writing the first coded data into the NAND Flash chip, the plurality of second page data are encoded by the encoder until the writing of the first coded data is completed to obtain a plurality of second coded data, and the plurality of second page data and the plurality of second coded data correspond to each other one by one;
[0021] Repeat the step of encoding the plurality of third page data using the encoder to obtain third encoded data in the process of writing the plurality of second encoded data into the plurality of NAND Flash chips at the same time, until the writing of the data to be written is completed; the plurality of second encoded data corresponds one-to-one to the plurality of second NAND Flash chips.
[0022] Specifically, the plurality of NAND Flash chips store data to be read, the data to be read includes a plurality of fourth page data and a plurality of fifth page data, and the method further includes:
[0023] When receiving a read instruction for the data to be read, transmitting a plurality of fourth pages of data from a plurality of the NAND Flash chips to the codec;
[0024] Repeat the steps of decoding the plurality of fourth page data using the encoder in the process of transmitting the plurality of fifth page data from the plurality of NAND Flash chips to the encoder, and obtaining a plurality of decoded data when the transmission is completed, until the reading of the data to be read is completed, and the plurality of decoded data corresponds one-to-one to the plurality of fourth page data.
[0025] The embodiment of the present application provides a data reading and writing system and a data reading and writing method. The data reading and writing system includes a codec connected to a bus, multiple NAND Flash chips and multiple NAND Flash controllers. The codec is used to encode the data to be written to obtain multiple encoded data. Since the NAND Flash chip reads and writes in units of pages, the data to be written may include multiple page data. The multiple encoded data correspond to the multiple page data one by one. A NAND Flash chip is connected to the bus through a NAND Flash controller. In this way, multiple NAND Flash chips and a codec can be connected in parallel. Each NAND Flash controller is used to control the writing of encoded data to each NAND Flash chip, so that data can be written to multiple NAND Flash chips at the same time. A part of the data to be written can be written into each NAND Flash chip, so that the data to be written is written to multiple NAND Flash chips. Compared with writing the data to be written through a serial data path, the present application forms multiple parallel data paths. The multiple data paths can write data simultaneously, which can greatly reduce the data writing time, improve time utilization, and avoid wasting time. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0027] Figure 1 A schematic diagram of a data reading and writing system in the prior art is shown;
[0028] Figure 2 A schematic diagram of a data reading and writing system provided in an embodiment of the present application is shown;
[0029] Figure 3 A schematic diagram of another data reading and writing system provided in an embodiment of the present application is shown;
[0030] Figure 4 A schematic diagram of another data reading and writing system provided in an embodiment of the present application is shown;
[0031] Figure 5 A schematic diagram of the structure of an LDPC encoding module provided in an embodiment of the present application is shown;
[0032] Figure 6 A schematic diagram of the structure of an LDPC decoding module provided in an embodiment of the present application is shown;
[0033] Figure 7 A schematic diagram of a data reading and writing method provided in an embodiment of the present application is shown;
[0034] Figure 8 A schematic diagram of a data writing process provided by an embodiment of the present application is shown;
[0035] Fig. 9 A schematic diagram of a data reading process provided in an embodiment of the present application. DETAILED DESCRIPTION
[0036] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.
[0037] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.
[0038] As described in the background technology, the inventors have discovered through research that the writing process includes an encoding stage and a data transmission stage. In the encoding stage, the codec encodes the first set of data. In the data transmission stage, the encoded data needs to be sent by the codec to the NAND Flash. During data transmission, the codec can encode the second set of data. After sending the first set of encoded data to the NAND Flash, the second set of encoded data can be transmitted. Although the next set of data can be encoded in the data transmission stage to reduce the encoding time, the time required to complete the data writing is still very long, which is not conducive to the realization of an efficient data reading and writing system.
[0039] Based on the above technical problems, an embodiment of the present application provides a data reading and writing system and a data reading and writing method. The data reading and writing system includes a codec connected to a bus, multiple NAND Flash chips and multiple NAND Flash controllers. The codec is used to encode the data to be written to obtain multiple encoded data. Since the NAND Flash chip reads and writes in units of pages, the data to be written may include multiple page data. The multiple encoded data correspond to the multiple page data one by one. A NAND Flash chip is connected to the bus through a NAND Flash controller. In this way, multiple NAND Flash chips and a codec can be connected in parallel. Each NAND Flash controller is used to control the writing of encoded data to each NAND Flash chip, so that data can be written to multiple NAND Flash chips at the same time. A part of the data to be written can be written into each NAND Flash chip, so that the data to be written is written to multiple NAND Flash chips. Compared with writing the data to be written through a serial data path, the present application forms multiple parallel data paths. The multiple data paths can write data simultaneously, which can greatly reduce the data writing time, improve time utilization, and avoid wasting time.
[0040] For ease of understanding, a data reading and writing system and a data reading and writing method provided in an embodiment of the present application are described in detail below with reference to the accompanying drawings.
[0041] refer to Figure 2 , which is a schematic diagram of a data reading and writing system provided in an embodiment of the present application, the data reading and writing system may be an SSD system or other systems capable of realizing data reading and writing. The system may include a codec, multiple NAND Flash chips, and multiple NAND Flash controllers.
[0042] The NAND Flash chip can be a 3D Single-Level Cell (1 bit / cell, SLC) NAND Flash with any number of layers, a 3D Multi-Level Cell (2 bit / cell, MLC) NAND Flash with any number of layers, a 3D Trinary-Level Cell (3 bit / cell, TLC) NAND Flash with any number of layers, or a 3D Quad-Level Cell (4 bit / cell, QLC) NAND Flash with any number of layers.
[0043] The encoder can be connected to a bus, and the bus can be an AMBA bus (Advanced Microcontroller Bus Architecture, advanced microcontroller bus) or the like. When data needs to be written, the encoding module in the encoder can encode the data to be written, and the data to be written can include multiple pages of data. After the encoding is completed, multiple encoded data can be obtained, and the multiple encoded data can correspond to the multiple pages of data one by one. Subsequently, each encoded data can be written into each NAND Flash chip, thereby satisfying the condition that the NAND Flash chip performs read and write operations in units of pages.
[0044] NAND Flash chips can be connected to the bus without going through a codec. In this way, the NAND Flash chip and the codec are no longer connected in series, but in parallel. Specifically, a NAND Flash chip is connected to the bus through a NAND Flash controller. In this way, there is a separate data transmission channel between each NAND Flash chip and the bus, and multiple parallel data transmission channels can be obtained. Each NAND Flash controller can be used to control the writing of encoded data to each NAND Flash chip, so that data can be written to multiple NAND Flash chips at the same time.
[0045] Since the time required for data transmission is several times or even dozens of times the encoding time, multiple pages of data to be transmitted subsequently can be encoded while data is being transmitted. In this way, after the data transmission is completed, multiple parallel data transmission channels can be used to transmit the multiple encoded data. That is, multiple encodings can be performed simultaneously and sequentially during the data transmission process, ensuring that parallel data transmission can be achieved technically and time utilization can be improved.
[0046] In this way, a part of the data to be written can be written into each NAND Flash chip, so that the data to be written can be written into multiple NAND Flash chips. Compared with writing the data to be written through a serial data path, the present application forms multiple parallel data paths, and multiple data paths can write data at the same time, which can greatly reduce the data writing time, improve time utilization, and avoid wasting time. In addition, a combination scheme of a single codec and multiple NAND Flash chips is realized. Compared with the scheme in the prior art where a single codec is connected to a NAND Flash chip, if n NAND Flash chips are required, n codecs are required. In this scheme, data can be read and written to n NAND Flash chips through one codec, and the number of codecs is reduced by n-1, which can reduce the area overhead of the codec, from the area of n codecs to the area of 1 codec, reducing the process manufacturing difficulty and process cost, and making the volume of the data reading and writing system smaller.
[0047] In the embodiments of the present application, not only can the writing time be reduced during the data writing process, but the data reading time can also be reduced, thereby improving the data reading efficiency.
[0048] When reading the data to be read from the NAND Flash chip, the NAND Flash controller can also be used to control the acquisition of the data to be read from the NAND Flash chip. In this way, multiple data to be read can be obtained from multiple NAND Flash chips through their respective data transmission channels, and then the multiple data to be read are sent to the encoder. The encoder is also used to decode the data to be read to obtain decoded data.
[0049] Similarly, while data is being transmitted, the decoding module in the encoder can decode the data to be read that has been transmitted before, so that decoding and data transmission can be performed simultaneously, thereby realizing reading the data to be read from multiple NAND Flash chips. Data transmission is performed simultaneously through multiple parallel channels, which greatly reduces the data transmission time. Encoding and decoding operations can also be performed while data is being transmitted, which reduces the data reading time, completes the data reading operation faster, and improves time utilization.
[0050] In the embodiment of the present application, the NAND Flash controller may receive the encoded data and the first register configuration information from the bus, and the NAND Flash controller may include a main control module (Main Controller Module), referring to Figure 3As shown, the main control module may include a read-write state machine and a memory. When performing a data write operation, the read-write state machine is used to receive the first register configuration information and perform timing conversion on the first register configuration information to obtain write instruction information. The write instruction information can be used to control the writing of encoded data to the NAND Flash chip. The memory is used to store the encoded data. The memory can be a DRAM / RAM (dynamic random access memory / random access memory) memory, thereby realizing the control function of the NAND Flash controller.
[0051] In the embodiment of the present application, when performing a data reading operation, the read / write state machine is also used to receive the second register configuration information and convert the second register configuration information into read instruction information, and the read instruction information is used to control the reading of the to-be-read data from the NAND Flash chip to complete the reading process.
[0052] Specifically, refer to Figure 4 As shown, the system may also include a Flash Translation Layer (FTL) connected to the bus, and the Flash converter is used to send first register configuration information to the NAND Flash controller through the bus according to a data write instruction obtained from the host to provide a physical address for data write, and is also used to send second register configuration information to the NAND Flash controller according to a data read instruction obtained from the host.
[0053] The flash converter may include an address mapping module, a wear leveling module and a garbage collection module. The address mapping module is used to provide a mapping relationship from a logical address to a physical address. The wear leveling module is used to balance data writing to each flash memory block. The garbage collection module is used to move valid data from several flash memory blocks and write them to a new flash memory block, and then erase the previous flash memory blocks to obtain available flash memory blocks.
[0054] That is to say, during the data writing process, a data writing instruction can be obtained from the host, the flash memory converter can generate the first register configuration information according to the data writing instruction, the encoder can obtain the data to be written from the bus, and encode the data to be written to obtain the encoded data, the encoder transmits the encoded data to the NAND Flash controller through the bus, the flash memory converter transmits the first register configuration information to the NAND Flash controller through the bus, the read-write state machine in the NAND Flash controller can convert the first register configuration information into write instruction information, the encoded data is stored in the memory, and under the control of the write instruction information, the encoded data is written to the NAND Flash chip, thereby completing the data writing.
[0055] During the data reading process, a data reading instruction can be obtained from the host, and the flash memory converts and generates the second register configuration information, and transmits it to the NAND Flash controller through the bus. The read-write state machine in the NAND Flash controller can convert the second register configuration information into the reading instruction information, and under the control of the reading instruction, read the data to be read from the NAND Flash chip, and then transmit the data to be read through the bus to the encoder for decoding. Then send the decoded data to the host to complete the data reading operation.
[0056] Specifically, the NAND Flash controller also includes an AXI interface module, which is used to connect to the bus. AXI can achieve better performance with a smaller area and lower power consumption, mainly due to its unidirectional channel architecture, independent address and data channels, and handshake signals. The AXI bus includes three types: AXI Lite, AXI Full, and AXIStream.
[0057] Specifically, the codec may include an encoding module (encoder), a decoding module (decoder) and a control logic (ECC Control Logic) module, wherein the control logic module is used to control the encoding module to encode and the decoding module to decode. The codec may be an LDPC codec or a BCH codec.
[0058] LDPC is the most widely used error correction code in flash memory today. The encoder is essentially a matrix operation. If it is implemented directly, the most convenient way is to store the entire G matrix (for QC-LDPC code, the non-unit sub-matrix of the G matrix can be directly stored) to perform matrix multiplication operations. This method will require a large amount of storage resources when implemented in hardware, so we can start with the construction of LDPC codes. As a system code, QC-LDPC code has good cyclic characteristics. Its generator matrix and check matrix are composed of multiple cyclic shift matrices, which can be implemented using shift register hardware, which can greatly reduce the overhead of hardware implementation.
[0059] refer to Figure 5 As shown, it is a structural schematic diagram of an LDPC encoding module provided in an embodiment of the present application. The parallel encoding unit exchanges area for speed, divides the matrix into layers according to the size of the cyclic shift matrix, and performs parallel encoding in layers. This is also related to the special properties of the generator matrix. It is divided into 8 encoding modules enc1-enc8 in total. Each encoding unit uses a shift register to implement the core operation part of the LDPC encoder. Finally, the check bit output module outputs the results completed by each encoding unit in the parallel encoding unit.
[0060] refer to Figure 6 As shown, it is a structural schematic diagram of an LDPC decoding module provided in an embodiment of the present application, including a check node information RAM unit, an H-based matrix ROM unit, a posterior probability information RAM unit, a variable node information update unit, a check node information update unit, a posterior probability information update unit and a decoding decision module.
[0061] The check node information RAM unit is used to update the check node information, and RAM can be used; the H-based matrix ROM unit is used to store the number of cyclic shifts of each cyclic shift matrix, and ROM can be used; the posterior probability information RAM unit is used to receive the initialization LLR and the subsequent posterior probability update, and RAM can be used.
[0062] The variable node information update unit is used to realize the difference between the posterior probability and the information of the check node, which is specifically implemented as the subtraction of 8-bit signed numbers. In order to simplify the operation of signed numbers, the posterior probability and the check node information are first converted into complement codes, and then subtraction operations are performed (converted to addition of negative numbers), and finally the results are converted into original codes. Since the LLR bit width is 8 bits, considering that overflow may occur in the intermediate variable operation, a limiting operation is performed, and the specific upper and lower limits can be -128 to +127.
[0063] The check node information update unit includes a sign bit calculation circuit, a minimum value and a second minimum value calculation circuit, and a coefficient multiplication circuit. The posterior probability information update unit mainly realizes the sum of the variable node information and the check node information. The specific hardware implementation is the addition of 8-bit signed numbers. In order to simplify the operation of signed numbers, the posterior probability and the check node information are first converted into complement codes, and then the addition operation is performed. Finally, the result is converted into the original code. Since the LLR bit width is 8 bits, considering that the intermediate variable operation will overflow, a limiting operation is performed, and the specific upper and lower limits can be -128 to +127. The decoding decision module determines the end of decoding by the syndrome decision. If all syndromes are 0 or the number of iterations reaches the upper limit, the decoding is determined to be over.
[0064] The embodiment of the present application provides a data reading and writing system, which includes a codec connected to a bus, multiple NAND Flash chips and multiple NAND Flash controllers. The codec is used to encode the data to be written to obtain multiple encoded data. Since the NAND Flash chip reads and writes in units of pages, the data to be written may include multiple page data. The multiple encoded data correspond to the multiple page data one by one. A NAND Flash chip is connected to the bus through a NAND Flash controller. In this way, multiple NAND Flash chips and a codec can be connected in parallel. Each NAND Flash controller is used to control the writing of encoded data to each NAND Flash chip, so that data can be written to multiple NAND Flash chips at the same time. A part of the data to be written can be written into each NAND Flash chip, so that the data to be written is written to multiple NAND Flash chips. Compared with writing the data to be written through a series data path, the present application forms multiple parallel data paths, and the multiple data paths can write data simultaneously, which can greatly reduce the data writing time, improve time utilization, and avoid wasting time.
[0065] Based on the above data reading and writing system, the embodiment of the present application also provides a data reading and writing method, which is applied to the data reading and writing system. The data reading and writing system includes a codec and multiple NAND Flash chips, and the codec and the multiple NAND Flash chips are connected to the bus in parallel. Figure 7 As shown, it is a flow chart of a data reading and writing method provided in an embodiment of the present application, and the method includes the following steps.
[0066] S101, when receiving a data writing instruction, obtaining data to be written; the data to be written includes a first page of data, a plurality of second pages of data and a plurality of third pages of data.
[0067] In an embodiment of the present application, when a data write instruction is received, the data to be written can be obtained from the host through the bus, and the data to be written may include a first page of data, multiple second pages of data, and multiple third pages of data, wherein the first page of data, the second page of data, and the third page of data are determined according to a write order, and the first page of data will be written earlier than the second page of data.
[0068] S102, encoding the first page data using a codec to obtain first encoded data.
[0069] In an embodiment of the present application, the encoder can obtain the data to be written from the bus. When writing page data for the first time, only one page of data can be encoded, and the remaining multiple pages of data can be processed in parallel to improve time utilization.
[0070] Specifically, the encoder can perform an encoding operation on the first page of data to obtain first encoded data corresponding to the first page of data, and then transmit the first encoded data to the NAND Flash chip for storage, thereby completing the writing of the first page of data. Figure 8 As shown, it is a schematic diagram of a data writing process provided by an embodiment of the present application. The time required for encoding can be recorded as tENC, and t0→tENC is used for the first encoding, that is, the encoding process of the first page of data is completed.
[0071] S103, in the process of writing the first coded data into the NAND Flash chip, the plurality of second page data are encoded by using a codec until the writing of the first coded data is completed to obtain a plurality of second coded data, and the plurality of second page data and the plurality of second coded data correspond one to one.
[0072] Specifically, the first encoded data can be transmitted to the NAND Flash chip through the NAND Flash controller. During the data transmission in the channel CH1, the encoding operation can be performed on the data to be written subsequently, that is, the encoding operation can be performed on the second page data. Since the data transmission time is greater than the encoding time, it can be assumed that the data transmission time is k times the encoding time, and the k second pages of data can be encoded in sequence. In this way, when the write operation of the first encoded data is completed, k second encoded data can also be obtained at the same time. In the same period of time, both the data transmission can be completed and multiple pages of data can be encoded, thereby improving time utilization.
[0073] Specifically, refer to Figure 8 In the example, the time required for data transmission is tDATA. During the period of tENC→tENC+tDATA, the codec is used to perform k channel encodings during the data transmission process.
[0074] S104, repeatedly executing the step of encoding the plurality of third page data by using a codec to obtain the third coded data in the process of writing the plurality of second coded data into the plurality of NAND Flash chips at the same time, until the writing of the data to be written is completed; the plurality of second coded data corresponds to the plurality of second NAND Flash chips one by one.
[0075] In an embodiment of the present application, after obtaining multiple second coded data, the multiple second coded data can be written into multiple NAND Flash chips at the same time, and each NAND Flash chip writes one second coded data. In this way, within a data transmission time period, the transmission of k second coded data can be simultaneously achieved through k channels, without the need to transmit k second coded data sequentially, which greatly reduces the data transmission time.
[0076] In addition, in the process of writing multiple second coded data to multiple NAND Flash chips at the same time, the encoding operation can also be continued for the data to be written later, that is, the encoder encodes multiple third pages of data, so that multiple third coded data can be obtained while completing the transmission process of multiple second coded data. Figure 8 In the time period of tENC+tDATA→tENC+2*tDATA, data transmission of multiple channels and encoding of multiple channels can be performed simultaneously.
[0077] This step can be repeated subsequently, with the third encoded data used as the new second encoded data, and the page data to be written subsequently used as the new third page data. In the process of writing multiple second encoded data into multiple NAND Flash chips at the same time, multiple third page data are encoded using a codec to obtain the third encoded data, until all page data are encoded and transmitted to the NAND Flash chip, thereby realizing the write operation on the data to be written.
[0078] It can be seen that this not only can simultaneously transmit data for multiple encoded data, but also can complete the encoding operation during the data transmission process, and write the data to be written into multiple NAND Flash chips, greatly shortening the data writing time.
[0079] In the embodiment of the present application, the time can also be shortened during the data reading process. When reading data, the data to be read is distributed and stored in multiple NAND Flash chips, and the data to be read may include multiple fourth page data and multiple fifth page data. The fourth page data and the fifth page data are determined according to the order of reading, and the reading of the fourth page data is earlier than the reading of the fifth page data. The data reading process may include steps S201 and S202.
[0080] S201, when receiving a read instruction for data to be read, transmitting a plurality of fourth page data from a plurality of NAND Flash chips to a codec.
[0081] Specifically, when a data read instruction for the data to be read is obtained from the host, the multiple NAND Flash controllers can control the corresponding NAND Flash chips to transfer the fourth page data to the codec, thereby realizing the transfer of multiple fourth page data to the codec. Fig. 9 As shown, the time required for decoding is recorded as tDEC, and multiple channels are output simultaneously at t0→tDATA.
[0082] S202, repeatedly executing the step of decoding the multiple fourth page data using the encoder in the process of transmitting the multiple fifth page data from the multiple NAND Flash chips to the encoder, and obtaining multiple decoded data when the transmission is completed, until the reading of the data to be read is completed, and the multiple decoded data correspond to the multiple fourth page data one by one.
[0083] In the embodiment of the present application, after completing the data transmission of multiple fourth-page data, the data transmission channel is idle, and multiple fifth-page data can continue to be transmitted through the data transmission channel to avoid wasting time. In addition, during the data transmission of multiple fifth-page data, the codec can perform decoding processing at the same time, that is, decode multiple fourth-page data. In this way, while completing the transmission of the fifth-page data, multiple decoded data can also be obtained, thereby improving time utilization. Fig. 9 In the process of data transmission, tDATA→2*tDATA, the decoding module is used to decode k channels at the same time, assuming that the data transmission time is k times the decoding time. When decoding k fourth-page data, the time period corresponding to each fourth-page data is tDATA+(m-1)tENC→tDATA+m*tENC, m=1,2,…,k.
[0084] Specifically, the step can be repeatedly performed, and the fifth page data that has completed data transmission is used as the new fourth page data, and the page data to be read subsequently is recorded as the fifth page data. The step of decoding the multiple fourth page data using the encoder during the process of transmitting the multiple fifth page data from the multiple NAND Flash chips to the encoder is repeatedly performed, and a plurality of decoded data are obtained when the transmission is completed, until the data transmission and decoding steps are completed for all the page data to be read, thereby greatly reducing the data reading time and improving the time utilization rate.
[0085] The embodiment of the present application provides a data reading and writing method, which is applied to a data reading and writing system, wherein the data reading and writing system includes a codec and multiple NAND Flash chips, wherein the codec and the multiple NAND Flash chips are connected to a bus in parallel, and upon receiving a data writing instruction, data to be written is obtained; the data to be written includes a first page of data, multiple second pages of data, and multiple third pages of data; the first page of data is encoded using the codec to obtain first encoded data; in the process of writing the first encoded data to the NAND Flash chip, the multiple second pages of data are encoded using the codec until the writing of the first encoded data is completed to obtain multiple second encoded data, and the multiple second pages of data and the multiple second encoded data correspond one to one; repeatedly executing the step of encoding the multiple third pages of data using the codec to obtain third encoded data in the process of writing the multiple second encoded data to the multiple NAND Flash chips at the same time, until the writing of the data to be written is completed; the one-to-one correspondence between the multiple second encoded data and the multiple second NAND Flash chips can realize the simultaneous writing of data to the multiple NAND Flash chips, and a part of the data to be written can be written into each NAND Flash chip, so that the data to be written is written to the multiple NAND Compared with writing the data to be written through a serial data path, the present application forms multiple parallel data paths, and multiple data paths can write data simultaneously, which can greatly reduce the data writing time, improve time utilization, and avoid wasting time.
[0086] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the system embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.
[0087] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.
Claims
1. A data reading and writing system, It is characterized in that The system comprises: A codec connected to the bus, the codec is used to encode the data to be written to obtain a plurality of coded data; the data to be written includes a plurality of page data, and the plurality of coded data corresponds to the plurality of page data in a one-to-one manner; Multiple NAND Flash chips and multiple NAND Flash controllers, one NAND Flash chip is connected to the bus through one NAND Flash controller, and each NAND Flash controller is used to control writing of the encoded data to each NAND Flash chip, so as to write the data to be written into the multiple NAND Flash chips.
2. The system according to claim 1, It is characterized in that The NAND Flash controller is also used to control the acquisition of the to-be-read data from the NAND Flash chip; The encoder is also used to perform a decoding operation on the data to be read to obtain decoded data, so as to realize reading the data to be read from the plurality of NAND Flash chips.
3. The system according to claim 1, It is characterized in that The NAND Flash controller includes a main control module, and the main control module includes a read-write state machine and a memory; The read / write state machine is used to receive first register configuration information and convert the first register configuration information into write instruction information, the write instruction information is used to control writing of the encoded data into the NAND Flash chip, and the memory is used to store the encoded data.
4. The system according to claim 3, It is characterized in that The read / write state machine is further used to receive second register configuration information and convert the second register configuration information into read instruction information, where the read instruction information is used to control reading of the to-be-read data from the NAND Flash chip.
5. The system according to claim 1, It is characterized in that The system also includes a flash memory converter connected to the bus, the flash memory converter is used to send first register configuration information to the NAND Flash controller according to a data write instruction, and is also used to send second register configuration information to the NAND Flash controller according to a data read instruction.
6. The system according to claim 1, It is characterized in that The NAND Flash controller also includes an AXI interface module for connecting to the bus.
7. The system according to claim 1, It is characterized in that The codec includes an encoding module, a decoding module and a control logic module. The control logic module is used to control the encoding module to encode and control the decoding module to decode.
8. The system according to claim 1, It is characterized in that The codec includes an LDPC codec.
9. A method for reading and writing data, It is characterized in that Applied to a data reading and writing system, the data reading and writing system comprises a codec and a plurality of NAND Flash chips, the codec and the plurality of NAND Flash chips are connected in parallel to a bus, the method comprises: When receiving a data write instruction, obtaining data to be written; the data to be written includes a first page of data, a plurality of second pages of data, and a plurality of third pages of data; Encoding the first page data using the codec to obtain first encoded data; In the process of writing the first coded data into the NAND Flash chip, the plurality of second page data are encoded by the encoder until the writing of the first coded data is completed to obtain a plurality of second coded data, and the plurality of second page data and the plurality of second coded data correspond to each other one by one; Repeat the step of encoding the plurality of third page data using the encoder to obtain third encoded data in the process of writing the plurality of second encoded data into the plurality of NAND Flash chips at the same time, until the writing of the data to be written is completed; the plurality of second encoded data corresponds one-to-one to the plurality of second NAND Flash chips.
10. The method according to claim 9, It is characterized in that The plurality of NAND Flash chips store data to be read, the data to be read includes a plurality of fourth page data and a plurality of fifth page data, and the method further includes: When receiving a read instruction for the data to be read, transmitting a plurality of fourth pages of data from a plurality of the NAND Flash chips to the codec; Repeat the steps of decoding the plurality of fourth page data using the encoder in the process of transmitting the plurality of fifth page data from the plurality of NAND Flash chips to the encoder, and obtaining a plurality of decoded data when the transmission is completed, until the reading of the data to be read is completed, and the plurality of decoded data corresponds one-to-one to the plurality of fourth page data.