Storage device control method and storage device

Abstract

The invention provides a control method of a storage device and the storage device, and the control method comprises the following steps: when data reading fails, executing a decoding process on a check bit and an information bit of the read data; in the decoding process, obtaining and recording the number of decoding iterations; a first iteration threshold value is set, when the number of decoding iterations reaches the first iteration threshold value, the reading voltage is replaced and the data is read again while the next decoding iteration is executed, and the reread data is temporarily stored in the storage device; setting a second iteration threshold, if the number of decoding iterations reaches the second iteration threshold, reporting that data reading fails, and executing a decoding process on the temporarily stored reread data; and cycling the decoding process and the rereading process until the data is successfully read out or until the data is still failed to read out until the read voltage is traversed. The invention provides a control method of a storage device and the storage device. The reading efficiency of the storage device and the distribution and utilization efficiency of storage resources can be considered.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a control method for a storage device and a storage device. Background Art

[0002] Due to the change in the amount of stored charge, the data stored in the flash memory is prone to errors, so reading the data from the flash memory requires error correction processing of the data in the flash memory. The error correction process for the data stored in the flash memory involves multiple iterative calculations to obtain the correct data. Multiple iterations will continuously occupy storage resources. When the number of iterations is too high and the correct result is still not obtained, the execution strategy of the iterative calculation decoding of the storage device will be related to the performance of the storage device. How to balance the performance and latency of the storage device is a difficult problem in storage design. Summary of the invention

[0003] The object of the present invention is to provide a control method for a storage device and a storage device, which can take into account both the reading efficiency of the storage device and the allocation and utilization efficiency of storage resources.

[0004] In order to solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention provides a method for controlling a storage device, comprising the following steps: When the data reading fails, a decoding process is performed on the check bits and information bits of the read data; In the decoding process, obtaining and recording the number of decoding iterations; Setting a first iteration threshold, when the number of decoding iterations reaches the first iteration threshold, while executing the next decoding iteration, changing the read voltage and re-reading the data, wherein the re-read data is temporarily stored in the storage device; Setting a second iteration threshold, if the number of decoding iterations reaches the second iteration threshold, reporting a data read failure, and performing a decoding process on the temporarily stored re-read data; and The decoding process and the re-reading process are looped until the data is read out successfully or until the data is still failed to be read out after traversing the read voltage.

[0005] In one embodiment of the present invention, the step of setting the first iteration threshold comprises: When the storage device is idle, obtaining the number of decoding iterations when each storage block is successfully decoded, and obtaining the decoding success rate of each storage block at each number of decoding iterations; Comparing the decoding success rates of two adjacent decoding iterations in sequence, and obtaining a difference in the decoding success rates; and When the difference in the decoding success rates exceeds the allowable range for the first time, the number of decoding iterations corresponding to the larger decoding success rate is used as the first iteration threshold.

[0006] In one embodiment of the present invention, the step of setting the second iteration threshold comprises: When the storage device is idle, obtaining the number of decoding iterations when each storage block is successfully decoded, and obtaining the decoding success rate of each storage block at each number of decoding iterations; and A near-zero threshold is set, and when the decoding success rate is less than the near-zero threshold, the number of decoding iterations corresponding to the decoding success rate is set to the second iteration threshold.

[0007] In one embodiment of the present invention, the steps of the rereading process include: When the number of decoding iterations reaches the first iteration threshold, generating a warning signal; Under the triggering of the warning signal, another read voltage is selected from the read voltage table, and data is read according to the reselected read voltage; and The re-read data is stored in a power-off volatile area of ​​the storage device.

[0008] In one embodiment of the present invention, before executing the decoding iteration process on the reread data, it is determined whether the reread data passes the decoding verification. If it passes the decoding verification, the reread data is directly uploaded to the host computer. If it fails the decoding verification, the decoding iteration process is executed on the reread data.

[0009] In one embodiment of the present invention, the following steps are also included: When the decoding process is successfully decoded, if the storage device is in a busy state, the re-reading process is terminated; When the decoding process is successfully decoded, if the storage device is in a callable state, deleting the re-read data; and When the decoding process is successful, the successfully decoded data is uploaded to the host computer.

[0010] In one embodiment of the present invention, in the step of setting the first iteration threshold and the second iteration threshold, the first iteration threshold and the second iteration threshold are preset data and are stored in a power-off non-volatile area of ​​the storage device.

[0011] In an embodiment of the present invention, in the decoding process, according to the check bits, erroneous bits in the information bits are corrected through LDPC code iterations.

[0012] The present invention provides a storage device, comprising: Flash memory chips; A cache chip, electrically connected to the flash memory chip; A decoding module, used for performing a decoding process on the check bit and information bit of the read data when the read data fails, and in the decoding process, the decoding module obtains and records the number of decoding iterations; A threshold setting module, used to set a first iteration threshold and a second iteration threshold; a readout module, used to read out data from the flash memory chip, and to change a readout voltage and re-read out data while executing the next decoding iteration when the number of decoding iterations reaches the first iteration threshold, wherein the re-read data is temporarily stored in the cache chip; a process control module, configured to report a failure in reading data when the number of decoding iterations reaches the second iteration threshold, and execute a decoding process on temporarily stored re-read data; and The loop control module is used to loop the decoding process and the re-reading process until the data is successfully read out or until the data is still failed to be read out after traversing the read voltage.

[0013] In one embodiment of the present invention, the storage device includes a timing control module, which is connected to the read module and the decoding module, and the timing control module is used to simultaneously output a first timing signal and a second timing signal when the number of decoding iterations reaches the first iteration threshold, wherein the first timing signal is used to trigger the number of decoding iterations to increase by one and trigger a new decoding iteration process, and the second timing signal is used to trigger the reread process.

[0014] As described above, the present invention uses timing control to trigger voltage rereading, combines the dual means of LDPC decoding iteration and voltage adjustment, improves the probability of repairing complex storage errors, and based on the judgment of the decoding success rate tending to zero, avoids invalid calculations, reports uncorrectable errors in a timely manner, and ensures that the system responds quickly to serious faults. In addition, the present invention can improve the rationality of storage resource utilization, only starts rereading when the first threshold is reached, and the reread data is temporarily stored in the power-off volatile area, which can avoid unnecessary data handling. After successful decoding, redundant data is intelligently cleaned according to the device status to reduce storage fragmentation. In addition, the present invention avoids blind iterations and shortens the average decoding time through preset thresholds and real-time success rate analysis, and can make reasonable predictions on the status of the storage device in combination with the service life of the storage device. In addition, the present invention rereads and decodes in parallel, which can improve the decoding efficiency of the storage device, and can also obtain the optimal solution between error correction capability and computational overhead, and can also compensate for charge drift caused by temperature and aging, and extend the life of the storage device.

[0015] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0017] Figure 1 The flowchart of the control method of the storage device in one embodiment of the present invention.

[0018] Figure 2 FIG. 1 is a flow chart of step S300 in an embodiment of the present invention.

[0019] Figure 3 FIG. 1 is a flow chart of step S310 in an embodiment of the present invention.

[0020] Figure 4 FIG. 4 is a flow chart of step S400 in an embodiment of the present invention.

[0021] Figure 5 FIG. 4 is a schematic diagram of the structure of a storage device in an embodiment of the present invention.

[0022] In the figure: 10, main controller; 11, decoding module; 12, threshold setting module; 13, read module; 14, process control module; 15, loop control module; 16, timing control module; 20, cache chip; 30, flash memory chip; 40, memory. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] The control method of the storage device provided by the present invention can be applied to improve the efficiency of reading data from the storage device. The storage medium of the storage device is flash memory. Figure 1 As shown, the present invention provides a storage device control method, including steps S100 to S500.

[0025] Step S100: When the data reading fails, a decoding process is performed on the check bits and information bits of the read data.

[0026] Step S200: In the decoding process, obtain and record the number of decoding iterations.

[0027] Step S300, setting a first iteration threshold. When the number of decoding iterations reaches the first iteration threshold, while executing the next decoding iteration, the read voltage is changed and the data is re-read, wherein the re-read data is temporarily stored in the storage device.

[0028] Step S400: setting a second iteration threshold. If the number of decoding iterations reaches the second iteration threshold, reporting a data read failure, and performing a decoding process on the temporarily stored re-read data.

[0029] Step S500 , looping the decoding process and the re-reading process until the data is successfully read out or until the data is still unsuccessful after traversing the read voltage.

[0030] See also Figure 1 As shown, in one embodiment of the present invention, when writing data to a storage device, the written user data is processed by LDPC code to generate verification data of the user data. The user data is written into the power-off non-lost area of ​​the storage device as the encoded information bit, and the verification data generated after the encoding process is also synchronously written into the power-off non-lost area of ​​the storage device. In this embodiment, the verification bit and the information bit can be written into the same storage page or storage block. The storage block is a physical block (block) of the flash memory, and the storage page is a physical page (page) of the flash memory. When reading data from the storage device, a read voltage is set, and the information bit and the check bit are read under the read voltage. In step S100, when the read data fails, a decoding process is performed on the check bit and the information bit of the read data. In this embodiment, when the decoding iteration number reaches the second iteration threshold, it is still not successfully decoded, and it is determined that the read data failed. It should be noted that in this embodiment, when the data is read out for the first time, the data is checked and processed by error checking and correction (ECC). If the ECC check fails, the first data reading fails, and step S100 is executed. When the read voltage is switched to start rereading the data, that is, when the current data is read out for the second time, if the number of decoding iterations reaches the second iteration threshold and the error correction has not been successful, it is determined that the data reading has failed. In step S100, the decoding process is based on the check bit, and the error bits in the information bits are corrected through LDPC code iterations, and the correct user data is finally restored.

[0031] See also Figure 1As shown, in one embodiment of the present invention, it should be noted that in the decoding process, iterative calculation is used to correct the information bit. It is difficult to solve complex errors by direct one-time calculation, especially when multiple bits are wrong at the same time, and the iterative calculation method can optimize the results step by step. In the decoding process, the number of bits that may be wrong in the information bit is guessed based on the check bit, specifically, for example, part of the "0" or part of the "1" actually undergoes bit flipping. The decoding process will guess which specific "0" and "1" are wrong. Then the algorithm is used to verify whether there are contradictions in the guessed error unit. If there are no contradictions, the guess is correct and the decoding is successful. If there are contradictions, the second guessing of the number of error bits and the algorithm verification process are performed. In this embodiment, each process of proposing a guessed error point and verifying whether the guess is correct is a decoding iteration. Executing the decoding process refers to the process of looping the decoding iteration until the iteration stop condition is reached. Each decoding iteration will make the data of the information bit closer to the correct value, and after several cycles, all contradictions disappear, indicating that the data has been successfully corrected, that is, the decoding is successful. Among them, the selection of the guessed error point is random.

[0032] See also Figure 1 As shown, in one embodiment of the present invention, in step S200, the decoding process includes a plurality of decoding iterations. In this embodiment, each time an error point is guessed, a decoding iteration is started, and the number of decoding iterations is increased by one. In this embodiment, the number of decoding iterations is recorded and stored. The method for obtaining the number of decoding iterations can be to set a counter and a trigger in a stable calculation method, or to count by an algorithm in a way that lowers hardware resource usage.

[0033] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in step S300, a first iteration threshold is used to determine whether to perform parallel decoding and rereading operations. The process of implementing step S300 is based on the simultaneous triggering of timing signals. In this embodiment, a first timing signal and a second timing signal are set. The triggering condition of the first timing signal is that the decoding iteration fails. The first timing signal is used to trigger the number of decoding iterations to increase by one and trigger a new decoding iteration process. The triggering condition of the second timing signal is that the current number of decoding iterations reaches the first iteration threshold. The second timing signal is used to trigger the rereading process. Based on the stable control of the timing signal, the collaborative and parallel work of the two operations can be better coordinated. In other embodiments of the present invention, the coordination of new decoding iterations and rereading processes can also be achieved by setting a task queue and establishing a task sequence. In the present invention, step S300 includes steps S310 to S311. Step S310: Set a first iteration threshold.

[0034] Step S320: When the number of decoding iterations reaches the first iteration threshold, continue to execute the next decoding iteration.

[0035] Step S330 : While executing the next decoding iteration, the read voltage is changed and the data is read again.

[0036] Step S340: When the reread data is read out and the decoding iteration has not been successful, the reread data is stored.

[0037] Step S350: When the decoding iteration is successful before the re-read data is read out, the re-read process is terminated.

[0038] See also Figures 1 to 3 As shown, in one embodiment of the present invention, the first iteration threshold value may be a preset value, or a value obtained by training in an offline state or an idle state of the storage device. The preset value is input by a designer and is a fixed value, which can reduce the algorithm complexity of the storage device. In this embodiment, when the first iteration threshold value is a value obtained by training, step S310 includes steps S311 to S313.

[0039] Step S311: when the storage device is idle, obtain the number of decoding iterations when each storage block is successfully decoded, and obtain the decoding success rate of each storage block at each decoding iteration number.

[0040] Step S312: Compare the decoding success rates of two adjacent decoding iterations in sequence, and obtain the difference in the decoding success rates.

[0041] Step S313: When the difference in decoding success rate exceeds the allowable range for the first time, the number of decoding iterations corresponding to the larger decoding success rate is used as the first iteration threshold.

[0042] See also Figures 1 to 3As shown, in one embodiment of the present invention, in step S311, the storage device is idle, which means that the storage device currently has no host computer tasks to be executed. In this embodiment, the host computer tasks include data writing tasks and data reading tasks. Among them, the data reading tasks also include multiple rounds of data rereading tasks of the rereading process. It should be noted that each time a decoding iteration is performed, it is not certain whether the decoding iteration can be successfully decoded. And as the number of times the storage medium is used increases, the number of decoding iterations will also change after the medium is worn. In this embodiment, when the storage device fails to read data, the decoding information of the storage device is recorded. The decoding information includes the number of rereads of each storage block or each storage page, and the number of decoding iterations in a single rereading process. Among them, each time the read voltage is switched, a rereading process is started, so the number of rereads is equal to the number of times the read voltage is switched, and the number of rereads can be recorded by the number of times the data is reread, or the number of rereads can be obtained by the number of times the read voltage is switched. In this embodiment, the decoding success rate of each storage block at each decoding iteration is counted in units of decoding iterations.

[0043] See also Figures 1 to 3 As shown, in one embodiment of the present invention, in step S311, for example, the total number of times the storage block performs decoding is 50 times, and the number of times the data is read out in the first decoding iteration is 2 times, then the decoding success rate of the first decoding iteration is 1 / 25. For another example, the number of times the fifth decoding iteration reads out data is 10 times, then the decoding success rate of the fifth decoding iteration is 1 / 5. By analogy, the decoding success rate corresponding to each number of decoding iterations is obtained. It should be noted that the example of the present invention is a limited number of times. When the storage device is actually used, the total number of decoding times of the storage device is extremely large, and therefore, a relatively accurate acquisition of the decoding success rate can be achieved through the statistics of big data. In this embodiment, the initial decoding success rate of each decoding iteration can be set. The initial decoding success rate is used as an initial value for the storage device. In the use of the storage device, the decoding success rate of each decoding iteration can be continuously calibrated in an idle state so that the value of the decoding success rate conforms to the actual state of the storage device.

[0044] See also Figures 1 to 3As shown, in one embodiment of the present invention, in step S312, the decoding success rates of two adjacent decoding iterations are compared in sequence, and the difference in decoding success rates is obtained. The maximum value of the decoding iterations is limited by the second iteration threshold. In step S313, the position where the decoding success rate first drops off a cliff is obtained by the difference in success rates of adjacent decoding iterations. In this embodiment, an allowable range can be set to limit the upper limit of the success rate difference, for example, it is set to 35%, that is, the success rate difference exceeds the allowable range, that is, it is determined that the success rate of the decoding iteration drops off a cliff at this time. In this embodiment, the decoding iteration number corresponding to the larger decoding success rate of the two decoding iterations with a cliff-like drop in the decoding success rate is used as the first iteration threshold. For example, when the decoding iteration is executed for the ninth time, the decoding success rate is 52%, when the decoding iteration is executed for the tenth time, the decoding success rate is 50%, and when the decoding iteration is executed for the eleventh time, the decoding success rate is 12%. Then the tenth time is the success rate demarcation position of the decoding iteration, and the first iteration threshold can be set to 10. In this embodiment, the first iteration threshold value may be stored in a power-off non-volatile area of ​​the storage device, and the first iteration threshold value may be called from the storage device each time a judgment is performed.

[0045] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, in step S320 and step S330, the decoding iteration process performed under the current readout voltage is continuously performed and is not limited by the first iteration threshold value. Therefore, even if the number of decoding iterations reaches the first iteration threshold value, if the current decoding is unsuccessful, the next decoding iteration will continue to be performed. The increase in the number of decoding iterations can be used for the calculation of the first iteration threshold value and the second iteration threshold value. In this embodiment, if the current decoding iteration verification fails, it is determined that the current decoding iteration fails, and the first timing signal can be issued. It should be noted that the first timing signal can trigger the number of decoding iterations to increase by one, but due to device delay, the number of decoding iterations actually increases by one when the current round of decoding iterations is determined to fail and the next round of decoding iterations has not yet started, or when the next round of decoding iterations starts and the error point has not yet been guessed. Under the triggering of the first timing signal, the next decoding iteration starts, specifically, a new round of error point guessing starts. In this embodiment, when the number of decoding iterations reaches the first iteration threshold value, the second timing signal is triggered. Under the triggering of the second timing signal, the storage device can establish a reread task and start the reread task. It should be noted that the increase in the number of decoding iterations occurs before the start of the decoding iteration behavior of the current round, so the occurrence of the second timing signal is located before the start of the decoding iteration behavior of the current round. In this embodiment, the reread process and the next decoding iteration process are independent of each other. After the reread task is established, the storage device switches the read voltage and rereads the data. In this embodiment, the switching of the read voltage can select a new read voltage that has not been used from the read voltage table provided by the manufacturer. In another embodiment of the present invention, the switching of the read voltage can also be automatic adjustment of the voltage, for example, adjusting the read voltage in a stepping manner until the read voltage traverses the readable voltage range. For example, the read voltage of the current round is 3V, and the new read voltage can be set to 2.9V or 3.1V according to the step value of 0.1V. Among them, the second timing signal, as a timing signal for starting the reread process, can also be understood as a warning signal.

[0046] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, after the decoding iteration ends, if the decoding iteration is successful, it is determined whether the storage device is in a busy state at this time. If it is in a busy state, the storage device is still executing the reread process at this time, and it can be determined that the reread data has not been completely read out. At this time, step S350 is executed to terminate the reread process, thereby saving storage resources. Then the successfully decoded data is uploaded to the host computer as the read data. If the storage device is not in a busy state at this time, step S340 is executed. At this time, the reread data has been read out, and the reread data is automatically stored in the power-off volatile area of ​​the storage device after being read out, and then the reread data is deleted. In other embodiments of the present invention, it is also possible to use whether the reread data is read out as a judgment basis, for example, after the reread data is read out, the reread data is stored in the power-off volatile area of ​​the storage device, and it is determined whether the decoding has been successful. If the decoding is successful, the data after the successful decoding is directly uploaded, and the reread data is deleted. If the decoding is still unsuccessful, no operation is performed. It should be noted that it is not known at which time the decoding iteration process can be successfully decoded. Therefore, in this embodiment, decoding iteration is used as a benchmark, which can save storage resources, and the judgment method is simple and more efficient.

[0047] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, when the number of decoding iterations of the current data reaches the first iteration threshold, it is determined whether the obtainable read voltages have been traversed before starting the reread process. If the obtainable read voltages have been traversed, the reread process is stopped, that is, although the first iteration threshold is reached, the reread data is not obtained.

[0048] See also Figure 1 and Figure 4 As shown, in one embodiment of the present invention, in step S400, by setting the second iteration threshold, it is possible to avoid too many decoding iterations and occupy too many storage resources. Step S400 includes steps S410 to S430.

[0049] Step S410: Set a second iteration threshold.

[0050] Step S420: If the number of decoding iterations of the data read this time reaches the second iteration threshold, report that the data read fails.

[0051] Step S430: determining whether the obtainable read voltages have been traversed when obtaining the current failed data; if the obtainable read voltages have been traversed, then terminating the data read process.

[0052] Step S440: If the number of decoding iterations of the currently read data reaches the second iteration threshold and the obtainable read voltages have not been traversed, start to perform a decoding iteration process on the re-read data.

[0053] See also Figure 1 , Figure 4 and Figure 5 As shown, in one embodiment of the present invention, step S410 includes steps S411 to S412.

[0054] Step S411: when the storage device is idle, obtain the number of decoding iterations when each storage block is successfully decoded, and obtain the decoding success rate of each storage block at each decoding iteration number.

[0055] Step S412: setting a near-zero threshold. When the decoding success rate is less than the near-zero threshold, setting the number of decoding iterations corresponding to the decoding success rate to a second iteration threshold.

[0056] See also Figure 1 , Figure 4 and Figure 5 As shown, in one embodiment of the present invention, step S411 is the same as step S311 and can be combined into the same step. In another embodiment of the present invention, the second iteration threshold can be a preset value, such as 30 times. In step S412, the near-zero threshold is, for example, 0-5%, and specifically, for example, 5%. When the decoding success rate is less than the near-zero threshold, it means that the possibility of decoding success is already very low, and continuing decoding will only occupy more storage resources. In the case of a large number of sample training, when the number of decoding iterations is greater than the first iteration threshold, as the number of decoding iterations increases, the decoding success rate will also continue to decrease. The second iteration threshold is greater than the first iteration threshold. In step S420, when the number of decoding iterations reaches the second iteration threshold, it is directly determined that the data read out under the current readout voltage fails to be decoded, that is, the data read out failure is reported. Before decoding and iterating the reread data, step S430 is executed to determine whether the data currently failed to be read is the last one of the obtainable readout voltages, that is, whether the readout voltage has been traversed at present. The obtainable read voltage may be the read voltage data stored in the read voltage table, or may be the read voltage data that satisfies the upper software configuration offset voltage range. When all voltages in the read voltage table have been tried, or the read voltage has traversed the preset offset range, the read voltage is in the state of having been traversed. In the case of traversing the read voltage, the reread data is empty, so the result of the unread data can be directly uploaded to the host computer. If the read voltage is still not traversed, the storage device memory 40 stores the reread data at this time, and the reread data can be decoded and iterated.

[0057] See also Figures 1 to 4As shown, in one embodiment of the present invention, in step S500, the decoding process of the reread data is to repeat steps S100 to S400 until the data is successfully read out or the data reading fails to be reported to the host computer. Before executing the decoding iteration process of the reread data, the reread data is decoded to determine whether the data is successfully read out under the new read voltage. If the data is successfully read out, there is no need to execute the decoding iteration process, and the successfully read data can be directly uploaded to the host computer. If the data is not successfully read out, continue to execute the decoding iteration process of the reread data. And so on, loop steps S100 to S400 until the data is successfully read out or it is determined that the data cannot be read out. In this embodiment, after starting the reread process, if the decoding process successfully decodes, the successfully decoded data is uploaded to the host computer.

[0058] See also Figures 1 to 4 As shown, it should be noted that, although the first iteration threshold and the second iteration threshold are to be set in the control method of the present invention, the setting of the first iteration threshold and the second iteration threshold both occur in the idle phase of the storage device. When performing decoding iterations, the step of obtaining the first iteration threshold and the second iteration threshold refers to calling the values ​​directly from the storage device. In this embodiment, the first iteration threshold and the second iteration threshold can be solidified in a non-volatile area of ​​the storage device when power is off, such as a metadata area stored in a flash memory. When the system starts, the first iteration threshold and the second iteration threshold can be loaded into the memory 40 for algorithm call, and can also be configured by the upper-level software during runtime to adapt to different error correction scenarios.

[0059] See also Figures 1 to 5 As shown, the present invention also provides a storage device, wherein the storage device includes a flash memory chip 30, a cache chip 20, a memory 40 and a main controller 10. The cache chip 20 can be a static random access memory (SRAM), and serves as a power-off volatile area of ​​the storage device. The flash memory chip 30 can be a memory using NAND flash memory as a storage medium, and serves as a power-off non-volatile area of ​​the storage device. The cache chip 20 is electrically connected to the flash memory chip 30. The main controller 10 is electrically connected to the flash memory chip 30, the cache chip 20 and the memory 40, respectively. The memory 40 can be a read-only memory (ROM). The control method of the storage device provided by the present invention is stored in the memory 40 in the form of firmware. The main controller 10 can use a microprocessor, such as an ARM processor, as a processing core to call the firmware in the memory 40 to implement the control method of the storage device provided by the present invention.

[0060] See also Figure 1 and Figure 5As shown, in one embodiment of the present invention, the main controller 10 includes a decoding module 11, a threshold setting module 12, a read module 13, a process control module 14 and a loop control module 15. The decoding module 11 is used to perform a decoding process on the check bit and the information bit of the read data when the read data fails, and in the decoding process, the decoding module 11 obtains and records the number of decoding iterations of the decoding module 11. The threshold setting module 12 is used to set the first iteration threshold and the second iteration threshold. The read module 13 is used to read data from the flash memory chip 30, and is used to change the read voltage and re-read the data when the number of decoding iterations reaches the first iteration threshold while executing the next decoding iteration. The re-read data is temporarily stored in the cache chip 20. The process control module 14 is used to report the failure of reading the data when the number of decoding iterations reaches the second iteration threshold, and perform the decoding process on the temporarily stored re-read data. The loop control module 15 is used to loop the decoding process and the re-read process until the data is successfully read or until the data fails to be read after traversing the read voltage.

[0061] See also Figure 1 and Figure 5 As shown, in one embodiment of the present invention, the main controller 10 further includes a timing control module 16. The timing control module 16 is electrically connected to the readout module 13 and the decoding module 11, and the timing control module 16 is used to output a first timing signal and a second timing signal simultaneously when the number of decoding iterations reaches a first iteration threshold, wherein the first timing signal is used to trigger the number of decoding iterations to increase by one and trigger the next decoding process, and the second timing signal is used to trigger the data re-reading process.

[0062] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for controlling a storage device, characterized in that: The following steps are involved: When the data reading fails, a decoding process is performed on the check bits and information bits of the read data; In the decoding process, obtaining and recording the number of decoding iterations; Setting a first iteration threshold, when the number of decoding iterations reaches the first iteration threshold, while executing the next decoding iteration, changing the read voltage and re-reading the data, wherein the re-read data is temporarily stored in the storage device; Setting a second iteration threshold, if the number of decoding iterations reaches the second iteration threshold, reporting a data read failure, and performing a decoding process on the temporarily stored re-read data; as well as The decoding process and the re-reading process are looped until the data is read out successfully or until the data is still failed to be read out after traversing the read voltage.

2. A storage device control method according to claim 1, characterized in that: The step of setting the first iteration threshold comprises: When the storage device is idle, obtaining the number of decoding iterations when each storage block is successfully decoded, and obtaining the decoding success rate of each storage block at each number of decoding iterations; Comparing the decoding success rates of two adjacent decoding iterations in sequence, and obtaining a difference in the decoding success rates; and When the difference in the decoding success rates exceeds the allowable range for the first time, the number of decoding iterations corresponding to the larger decoding success rate is used as the first iteration threshold.

3. The method for controlling a storage device according to claim 1, characterized in that: The step of setting the second iteration threshold comprises: When the storage device is idle, obtaining the number of decoding iterations when each storage block is successfully decoded, and obtaining the decoding success rate of each storage block at each number of decoding iterations; and A near-zero threshold is set, and when the decoding success rate is less than the near-zero threshold, the number of decoding iterations corresponding to the decoding success rate is set to the second iteration threshold.

4. The method for controlling a storage device according to claim 1, characterized in that: The steps of the rereading process include: When the number of decoding iterations reaches the first iteration threshold, generating a warning signal; Under the triggering of the warning signal, another read voltage is selected from the read voltage table, and data is read according to the reselected read voltage; and The re-read data is stored in a power-off volatile area of ​​the storage device.

5. The method for controlling a storage device according to claim 1, characterized in that: Before executing the decoding iteration process on the reread data, determine whether the reread data passes the decoding verification. If it passes the decoding verification, directly upload the reread data to the host computer. If it fails the decoding verification, execute the decoding iteration process on the reread data.

6. The method for controlling a storage device according to claim 1, characterized in that: The following steps are also included: When the decoding process is successfully decoded, if the storage device is in a busy state, the re-reading process is terminated; When the decoding process is successfully decoded, if the storage device is in a callable state, deleting the re-read data; as well as When the decoding process is successful, the successfully decoded data is uploaded to the host computer.

7. The method for controlling a storage device according to claim 1, characterized in that: In the step of setting the first iteration threshold and the second iteration threshold, the first iteration threshold and the second iteration threshold are preset data and are stored in a power-off non-volatile area of ​​the storage device.

8. The method for controlling a storage device according to claim 1, characterized in that: In the decoding process, according to the check bits, erroneous bits in the information bits are corrected through LDPC code iterations.

9. A storage device, characterized in that: include: Flash memory chips; A cache chip, electrically connected to the flash memory chip; A decoding module, used for performing a decoding process on the check bit and information bit of the read data when the read data fails, and in the decoding process, the decoding module obtains and records the number of decoding iterations; A threshold setting module, used to set a first iteration threshold and a second iteration threshold; a readout module, used to read out data from the flash memory chip, and to change a readout voltage and re-read out data while executing the next decoding iteration when the number of decoding iterations reaches the first iteration threshold, wherein the re-read data is temporarily stored in the cache chip; A process control module, configured to report a failure in reading data when the number of decoding iterations reaches the second iteration threshold, and execute a decoding process on temporarily stored re-read data; as well as The loop control module is used to loop the decoding process and the re-reading process until the data is successfully read out or until the data is still failed to be read out after traversing the read voltage.

10. A storage device according to claim 9, characterized in that: The storage device includes a timing control module, which is connected to the read module and the decoding module, and the timing control module is used to simultaneously output a first timing signal and a second timing signal when the number of decoding iterations reaches the first iteration threshold, wherein the first timing signal is used to trigger the number of decoding iterations to increase by one and trigger a new decoding iteration process, and the second timing signal is used to trigger the reread process.

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