Gate-level circuit function safety detection method and system based on graph neural network

Abstract

The invention discloses a gate-level circuit function safety detection method and system based on a graph neural network. The method comprises the following steps: acquiring a circuit characteristic data set; training a GNN model based on the circuit characteristic data set, and predicting and outputting fault injection results of all gate-level netlists and a preliminary key gate node list by using the trained GNN model; and judging the validity of a judgment standard of the key gate nodes in the initial key gate node list, and iteratively optimizing the judgment standard to output a final fault injection result of the gate-level netlist and a final key gate node list conforming to a functional safety standard. According to the method, the logic gate units which are prone to errors in the circuit can be detected in a simulation fault injection mode by using the graph neural network model, the time cost of gate-level fault injection is reduced, and the high precision of an injection result is kept.

Description

Technical Field

[0001] The present invention relates to the field of fault injection technology, and in particular to a gate-level circuit functional safety detection method and system based on graph neural network. Background Art

[0002] Fault injection technology is an important way to detect error-prone modules in circuits and an important part of the verification process in functional safety. Existing fault injection technologies are all simulated fault injections performed at the RTL level. For areas with high reliability requirements, fault injection and analysis at the RTL level cannot reflect the actual structure of the chip, which will lead to inaccurate analysis results and fail to meet high reliability requirements. Performing gate-level simulated fault injection in the gate-level netlist will produce more accurate injection results but will further increase the time cost of injection, making it challenging to balance accuracy and speed.

[0003] The current RTL-level functional safety testing method is to inject simulated faults at the RTL level. Before injection, specify the fault mode, fault injection time, fault injection location and other parameters to generate a fault list. Then, during the operation of the input stimulus, perform detailed fault injection on the Faulty design according to the fault list, compare the results of the Faulty design with the fault injected and the Golden design without the fault injected, and finally export the results, analyze and convert the fault injection results, such as Figure 1 shown.

[0004] At present, the RTL-level simulation fault injection process can only be injected based on HDL, but the HDL model cannot truly reflect the actual circuit structure of the chip, and cannot accurately inject faults into specific single logic gate units, resulting in inaccurate fault injection results and inability to perform fine-grained functional safety analysis and injection result conversion.

[0005] Another major disadvantage of RTL-level simulation fault injection is that it is time-intensive. For large-scale circuit designs, the time cost of fault injection is unacceptable, and most commercial RTL fault injection tools need to simulate faults for all possible situations to obtain accurate fault results. This will cause the fault injection process to consume a lot of time, affecting the subsequent functional safety analysis and verification process and the conversion of injection results. Summary of the invention

[0006] The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

[0007] The present invention proposes a gate-level circuit functional safety detection method based on graph neural network. The gate-level functional safety detection tool based on graph neural network can use the graph neural network model to detect error-prone logic gate units in the circuit by simulating fault injection, thereby reducing the time cost of gate-level fault injection and maintaining the high accuracy of the injection results.

[0008] Another object of the present invention is to propose a gate-level circuit functional safety detection system based on graph neural network.

[0009] To achieve the above objectives, the present invention proposes a gate-level circuit functional safety detection method based on a graph neural network, comprising:

[0010] Acquire a circuit feature data set; the circuit feature data set includes structural features extracted from a gate-level netlist generated based on the circuit to be tested, timing features extracted from an fsdb file by running VCS, and circuit connection information extracted by converting the circuit into a graph;

[0011] Training a GNN model based on the circuit feature data set, and using the trained GNN model to predict and output fault injection results and a preliminary key gate node list of all gate-level netlists;

[0012] The validity of the determination criteria of the key gate nodes in the preliminary key gate node list is judged, and the determination criteria are iteratively optimized to output the final fault injection results of the gate-level netlist and the final key gate node list that meets the functional safety standard.

[0013] The gate-level circuit functional safety detection method based on graph neural network in the embodiment of the present invention may also have the following additional technical features:

[0014] In one embodiment of the present invention, generating a gate-level netlist based on a circuit to be tested and extracting structural features from the gate-level netlist include:

[0015] Input the RTL file of the original circuit into Design Compiler for logic synthesis to convert the high-level hardware description language code into a gate-level netlist; the gate-level netlist is a Verilog file composed of basic logic gate units;

[0016] The script program is used to store the comprehensive library file; wherein the comprehensive library file contains various types of logic gate units and some attributes used in the gate-level netlist, and the script program stores the type of each logic unit in the comprehensive library file;

[0017] The properties of each basic logic unit in the gate-level netlist are recorded according to the stored comprehensive library file, and some features are transformed.

[0018] In one embodiment of the present invention, running VCS and extracting temporal features from the fsdb file includes:

[0019] Write the testbench test case for the corresponding circuit, and use VCS to compile the gate-level netlist and the corresponding testbench to obtain the corresponding FSDB waveform file;

[0020] The operation information of the circuit in the time dimension in the waveform file is extracted through the Python script program and mapped into timing features.

[0021] In one embodiment of the present invention, converting a circuit into a graph and extracting circuit connection information includes:

[0022] Use Python program to parse the gate-level netlist file to identify each logic gate unit and corresponding wire signal in the gate-level netlist file;

[0023] The parsed data is constructed into a graph structure, where each logic gate is represented as a node and the connections between logic gates are represented as edges;

[0024] After completing data collection and graph construction, the constructed graph structure is displayed through the graphical tool of the Python program;

[0025] Output the circuit connection information in the form of an adjacency matrix or an adjacency list.

[0026] In one embodiment of the present invention, training a GNN model based on a circuit feature dataset includes:

[0027] Initialize the weights and bias parameters of the GNN model and determine the aggregation method and aggregation properties to be used;

[0028] The circuit feature data set is used as sample data. In the forward propagation stage, the sample data is read from the input layer and enters the graph neural hidden layer to perform corresponding forward propagation calculations using the read sample features. Each node updates its own feature representation based on the features of its neighboring nodes. After feature propagation, it enters the output layer and applies the activation function to output the prediction results of the sample data.

[0029] The loss function value is calculated based on the trained sample data and the predicted results of the model output, and the weight and bias parameters of each node in the GNN model are updated according to the loss function value through the back propagation algorithm.

[0030] In one embodiment of the present invention, iteratively optimizing the decision criteria includes:

[0031] Obtain circuit characteristic data set and initialize key gate node judgment values;

[0032] The key gate node judgment value is used as the classification basis of the output layer of the GNN model to train the GNN model;

[0033] Obtain a list of key gate nodes based on the model training results, and reinforce the logic units in the key gate list;

[0034] The test calculates the diagnostic coverage of the reinforced circuit. If the diagnostic coverage does not meet the requirements, the key gate node judgment value is replaced according to the diagnostic coverage data; if the diagnostic coverage meets the requirements, the key gate node judgment value and the key gate node list are output.

[0035] To achieve the above-mentioned object, the present invention proposes, on the other hand, a gate-level circuit functional safety detection system based on a graph neural network, comprising:

[0036] A circuit feature data acquisition module is used to acquire a circuit feature data set; the circuit feature data set includes structural features extracted from a gate-level netlist generated based on the circuit to be tested, timing features extracted from an fsdb file by running VCS, and circuit connection information extracted by converting the circuit into a diagram;

[0037] A GNN model training module, used to train a GNN model based on the circuit feature data set, and use the trained GNN model to predict and output fault injection results and a preliminary key gate node list of all gate-level netlists;

[0038] The key gate node output module is used to determine the validity of the judgment criteria of the key gate nodes in the preliminary key gate node list, and iteratively optimize the judgment criteria to output the final fault injection results of the gate-level netlist and the final key gate node list that meets the functional safety standards.

[0039] The gate-level circuit functional safety detection method and system based on graph neural network in the embodiment of the present invention defines the error-prone logic gate units in the circuit as key gate nodes, iteratively tests and verifies the definition and judgment criteria of key gate nodes, and converts the results of gate-level fault injection with high accuracy, so that the circuit reinforced according to the list meets the functional safety standards such as ISO-26262, providing a new solution for the analysis and verification links in functional safety. It solves the high time cost and low precision of gate-level fault analysis and provides high-accuracy data for subsequent circuit reinforcement.

[0040] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0042] Figure 1 It is the existing RTL level fault injection flow chart;

[0043] Figure 2 is a flow chart of a gate-level circuit functional safety detection method based on a graph neural network according to an embodiment of the present invention;

[0044] Figure 3 is a schematic diagram of a gate-level functional safety detection network according to an embodiment of the present invention;

[0045] Figure 4 is a diagram of some structural features and their attributes according to an embodiment of the present invention;

[0046] Figure 5 is a schematic diagram of a structural feature extraction process according to an embodiment of the present invention;

[0047] Figure 6 is a diagram of some temporal characteristics and their attributes according to an embodiment of the present invention;

[0048] Figure 7 is a schematic diagram of a temporal feature extraction process according to an embodiment of the present invention;

[0049] Figure 8 is a schematic diagram of a connection information extraction process according to an embodiment of the present invention;

[0050] Fig. 9 is a schematic diagram of circuit feature data set extraction according to an embodiment of the present invention;

[0051] Fig.10 is a schematic diagram of a GNN training process according to an embodiment of the present invention;

[0052] Fig.11 is a schematic diagram of GNN hyperparameters adjusted according to an embodiment of the present invention;

[0053] Fig.12 is a schematic diagram of iterative optimization of key gate node standards according to an embodiment of the present invention;

[0054] Fig.13 It is an overall working block diagram of a gate-level circuit functional safety detection method based on a graph neural network according to an embodiment of the present invention;

[0055] Fig.14 is a workflow diagram of a gate-level circuit functional safety detection method based on a graph neural network according to an embodiment of the present invention;

[0056] Fig.15 It is a structural diagram of a gate-level circuit functional safety detection system based on a graph neural network according to an embodiment of the present invention. DETAILED DESCRIPTION

[0057] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0058] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0059] The following describes a gate-level circuit functional safety detection method and system based on graph neural network proposed according to an embodiment of the present invention with reference to the accompanying drawings.

[0060] The following is a list of technical abbreviations that may be used in the present invention:

[0061] RTL: Register Transfer Level

[0062] GNN: Graph Neural Network

[0063] VCS: Verilog Compile Simulator

[0064] FSDB:Fast Serial Data Base

[0065] VCD: Value Change Dump

[0066] GCN:Graph Convolutional Network

[0067] GAT: Graph Attention Network

[0068] Figure 2 is a flow chart of a gate-level circuit functional safety detection method based on a graph neural network according to an embodiment of the present invention. Figure 2 As shown, the method includes:

[0069] S1, obtaining a circuit feature data set; the circuit feature data set includes generating a gate-level netlist based on the circuit to be tested and extracting structural features from the gate-level netlist, running VCS and extracting timing features from the fsdb file, and converting the circuit into a graph to extract circuit connection information;

[0070] S2, training a GNN model based on the circuit feature data set, and using the trained GNN model to predict and output fault injection results and a preliminary key gate node list of all gate-level netlists;

[0071] S3, judging the validity of the determination criteria of the key gate nodes in the preliminary key gate node list, and iteratively optimizing the determination criteria to output the final fault injection results of the gate-level netlist and the final key gate node list that meets the functional safety standards.

[0072] The gate-level functional safety detection tool based on graph neural network proposed in the present invention can use a small amount of gate-level simulation fault injection results to train the GNN model, use the trained GNN model to quickly obtain high-precision results of all gate-level fault injections and a list of key gate nodes of the circuit, and determine the validity of the key gate nodes. Finally, a high-accuracy list of key gate nodes is obtained, and the circuit reinforced according to the list meets the specific index requirements of the functional safety standard ISO 26262. The key gate node is an effective transformation of the fault injection results, which finds the error-prone logical units in the circuit and provides data for subsequent reinforcement and verification analysis. It solves the problems of high time cost and low precision of simulation fault injection, and provides a new solution for gate-level functional safety analysis and verification.

[0073] The overall process of the present invention can be divided into three parts: circuit data set construction, GNN model training and key gate node result determination. Figure 3 As shown:

[0074] The construction of circuit dataset can be divided into three parts: structural feature extraction, timing feature extraction and circuit connection information extraction.

[0075] like Figure 5 As shown in the figure, for the structural feature extraction of the circuit, the RTL file of the original circuit needs to be input into Design Compiler for logic synthesis. The synthesis process can be roughly divided into three steps: translation, optimization and mapping. In the synthesis stage, the high-level hardware description language code is converted into a gate-level netlist and optimized to meet the requirements of performance, power consumption and area. The gate-level netlist is a Verilog file composed of basic logic gate units, which can reflect the real structure of the circuit. Then, the script program such as python and shell is used to store the synthesis library file. The synthesis library file contains various types of logic gate units used in the gate-level netlist and their partial properties. The script program stores the type, name and other properties of each logic unit in the library file. Finally, the properties of each basic logic unit in the gate-level netlist are recorded according to the stored synthesis library file, and some features are converted. Figure 4 It is a description of some structural features and their specific contents.

[0076] like Figure 7 As shown, for the extraction of the timing characteristics of the circuit, it is first necessary to write the testbench test case of the corresponding circuit. The result of the gate-level simulation fault injection is not only related to the structural composition of the gate-level netlist but also related to the testbench used for the test. The logic gate unit in the same gate-level netlist may eventually lead to different injection results due to the difference in the testbench, which ultimately affects the prediction and judgment of the key gate nodes. The present invention uses VCS to compile the gate-level netlist and the corresponding testbench generated by DesignCompiler in the previous step to obtain the corresponding FSDB waveform file. The FSDB file is a special data format used by Verdi, similar to VCD, but it only proposes useful information of the signal during the simulation process, and removes the information redundancy in VCD, just like performing a Huffman encoding on the VCD data. Therefore, the FSDB data volume is small, and the simulation speed will be improved. The present invention extracts the operation information of the circuit in the time dimension in the waveform file through a python script program and maps it to the timing characteristics. Figure 6 It is a partial temporal feature and its attributes.

[0077] like Figure 8 As shown, for the connection information extraction of the circuit, the present invention needs to convert the gate-level netlist generated by Design Compiler into a graphical representation. This process involves converting the information such as logic gates (cells), connections (nets) and hierarchical structures in the netlist into graphical elements, such as nodes and edges. Such a graphical representation helps to understand and analyze the structure of the circuit design and extract the connection information of the circuit therefrom.

[0078] Specifically, the conversion process includes the following steps:

[0079] 1. Parsing the netlist: The present invention needs to parse the gate-level netlist file output by Design Compiler to identify the logic gates, connections, and hierarchical structures. This process will be performed using a python program, which will identify each logic gate unit and the corresponding wire signal in the gate-level netlist file.

[0080] 2. Build a graph structure: This step builds the parsed data into a graph structure, where each logic gate is represented as a node, and the connection between logic gates is represented as an edge.

[0081] 3. Graphical display: After completing data collection and graph construction, the constructed graph structure is displayed through the graphical tools of the Python program.

[0082] 4. Export connection information: The connection information of the circuit will be exported in the form of an adjacency matrix or adjacency list and input into the graph neural network model as part of the circuit feature dataset.

[0083] Finally, the present invention integrates the features of the above three parts into a characteristic data set of the circuit. Fig. 9 Block diagram for circuit feature extraction.

[0084] The graph neural network model is a machine learning method used by the present invention to detect key gate nodes in gate-level circuits. It takes a circuit feature data set as input and outputs the detection results of key gate nodes in the circuit. The model training process of the graph neural network in the present invention is as follows: Fig.10 shown.

[0085] Graph Neural Networks (GNN) include a variety of algorithms, such as GCN, GAT, etc., and are very sensitive to hyperparameters, and there are many adjustable hyperparameters. GNN models with the same hyperparameters may have huge differences in prediction accuracy due to different hyperparameters. Therefore, hyperparameter adjustment of GNN is a key step in optimizing model performance. The following are some GNN hyperparameters that the present invention involves adjusting, such as Fig.11 shown.

[0086] The training process of the GNN model is as follows: First, you need to initialize the GNN's weights, biases and other parameters and determine the aggregation method, aggregation attributes and other hyperparameters to be used. Then in the forward propagation stage, the model reads the sample data from the input layer, enters the graph neural hidden layer and uses the read-in sample features to perform corresponding forward propagation calculations. Each node updates its own feature representation based on the features of its neighboring nodes. After feature propagation, it enters the output layer and applies the activation function to output the prediction results of the sample. Subsequently, the loss function value is calculated based on the trained sample data and the model output to measure the prediction accuracy of the model. Through the back-propagation algorithm, the weights and biases of each node in the GNN are updated according to the value of the loss function. In the model optimization stage, the model performance is continuously optimized by adjusting the hyperparameters and the selection of the optimization algorithm.

[0087] The purpose of the present invention is to use the GNN model to predict and find the key gate nodes in the circuit shown in the gate-level netlist. The key gate node is a definition obtained by the present invention based on the analysis of the gate-level fault injection results, which is intended to define the logic unit in the original circuit that is susceptible to faults and thus causes errors. The key gate node can be used in the safety verification stage of functional safety to evaluate the error tolerance of the system and the parts that need to be reinforced. In the present invention, the list of key gate nodes of the overall circuit obtained by GNN model detection is an important basis for subsequent functional safety reinforcement. Compared with traditional reinforcement methods, strengthening the weak points in the original circuit according to the list of key gate nodes saves hardware resource consumption and increases the reliability of the circuit. Therefore, the judgment criteria of the key gate nodes directly determine the overall quality of the system. The judgment criteria of the key gate nodes of the present invention will be associated with the existing functional safety standard ISO-26262.

[0088] Based on the key gate node data and the functional safety analysis and verification data of the circuit after strengthening the key gate nodes, the appropriate key gate node judgment standard is selected so that the strengthened circuit meets the requirements of the relevant indicators of ISO 26262. Fig.12 As shown in Figure 2, the iterative optimization process of the key gate node judgment criteria is as follows:

[0089] 1) Obtain the circuit characteristic data set and initialize the key gate node judgment value.

[0090] 2) Use the judgment value as the classification basis of the GNN output layer to train the GNN model

[0091] 3) Obtain a list of key gate nodes and strengthen the logic units in the key gate list

[0092] 4) Test and calculate the diagnostic coverage of the reinforced circuit. If the diagnostic coverage does not meet the requirements, replace the judgment value according to the diagnostic coverage data and return to 2); if the diagnostic coverage meets the requirements, output the key gate node judgment value and key gate node list.

[0093] After meeting ISO 26262, the system outputs the fault injection results of the gate-level netlist and a list of critical gate nodes.

[0094] Fig.13 The workflow of the entire solution includes the extraction of circuit feature data sets, GNN model training, and iteration of key gate node judgment criteria. Users only need to provide the Verilog file and the corresponding testbench file and specify the initialization values ​​of the GNN model and key gate judgment criteria. The script will generate a gate-level netlist, perform gate-level fault injection on some logic units, and train the GNN model and iterate the key gate nodes.

[0095] The Verilog file is the HDL code file of the circuit to be tested, and the library file provides standard logic units for the logic synthesis stage. The logic synthesis module uses the Verilog file and the library file to perform logic synthesis on the circuit to be tested at the RTL level in Design Compiler, and generates a gate-level netlist file composed of standard logic units. The structural feature extraction module runs the corresponding python script program to extract structural features using the gate-level netlist file and the library file. The testbench file contains the test cases used to test the gate-level netlist. The timing feature extraction module uses the gate-level netlist file and the Testbench to perform logic simulation in VCS, and the results are handed over to the python and shell script programs in the module for timing feature extraction. The connection information extraction module uses the python program to extract the connection information of the circuit. The results of the above three modules are combined to form a circuit feature data set. The GNN model training module accepts the circuit feature data set for GNN model training, and hands the resulting preliminary key gate node list to the key gate node judgment module, which will verify the validity of the key gate node judgment and iteratively optimize the judgment criteria, and finally output the key gate node list that meets the functional safety standards.

[0096] Fig.14 This is the fault injection workflow diagram after the entire solution starts working, which includes a total of 6 steps: 1. Generate a gate-level netlist by synthesizing the circuit to be tested; 2. Extract structural features from the gate-level netlist; 3. Run VCS to extract timing features from the fsdb file; 4. Convert the circuit into a graph and extract circuit connection information; 5. Train the GNN model to detect key gate nodes; 6. Verify whether the key gate node judgment criteria are valid.

[0097] According to the gate-level circuit functional safety detection method based on graph neural network in the embodiment of the present invention, critical gate node detection can be performed on any logic unit in the gate-level circuit. Compared with the traditional gate-level simulation fault injection analysis process, which requires fault injection and analysis of all logic units in the gate-level circuit, only less than 50% of the gate-level logic units need to be fault injected, which greatly reduces the key gate node detection time of large-scale circuit design. The gate-level functional safety detection tool proposed by the present invention has high accuracy. Compared with the traditional RTL-level simulation fault injection process, it can directly reflect the real structure of the circuit, perform simulation fault injection on the gate-level logic units that specifically constitute the circuit, and derive injection results with finer granularity and higher accuracy. And by proposing the critical gate node as the evaluation criterion, the injection results are converted with high accuracy, providing effective data for subsequent verification and reinforcement, meeting the requirements of ISO 26262 standard.

[0098] In summary, the beneficial effects of the present invention are:

[0099] This solution detects the key gate nodes in the gate-level circuit without completing the simulation fault injection process for all gate-level nodes, greatly reducing the time cost of gate-level fault injection, with high detection accuracy, and proposes the definition of key gate nodes and verifies their standards, effectively transforming the injection results. It speeds up the gate-level fault injection process and provides a new method for functional safety verification and analysis.

[0100] In order to implement the above embodiment, Fig.15 As shown, this embodiment also provides a gate-level circuit functional safety detection system 10 based on a graph neural network, including:

[0101] The circuit characteristic data acquisition module 100 is used to acquire a circuit characteristic data set; the circuit characteristic data set includes structural features extracted from a gate-level netlist generated based on the circuit to be tested, timing features extracted from an fsdb file by running VCS, and circuit connection information extracted by converting the circuit into a diagram;

[0102] A GNN model training module 200 is used to train a GNN model based on the circuit feature data set, and use the trained GNN model to predict and output fault injection results and a preliminary key gate node list of all gate-level netlists;

[0103] The key gate node output module 300 is used to determine the validity of the judgment criteria of the key gate nodes in the preliminary key gate node list, and iteratively optimize the judgment criteria to output the final fault injection results of the gate-level netlist and the final key gate node list that meets the functional safety standards.

[0104] Further, a gate-level netlist is generated based on the circuit to be tested and structural features are extracted from the gate-level netlist, including:

[0105] Input the RTL file of the original circuit into Design Compiler for logic synthesis to convert the high-level hardware description language code into a gate-level netlist; the gate-level netlist is a Verilog file composed of basic logic gate units;

[0106] The script program is used to store the comprehensive library file; wherein the comprehensive library file contains various types of logic gate units and some attributes used in the gate-level netlist, and the script program stores the type of each logic unit in the comprehensive library file;

[0107] The properties of each basic logic unit in the gate-level netlist are recorded according to the stored comprehensive library file, and some features are transformed.

[0108] Furthermore, VCS is run to extract timing features from the fsdb file, including:

[0109] Write the testbench test case for the corresponding circuit, and use VCS to compile the gate-level netlist and the corresponding testbench to obtain the corresponding FSDB waveform file;

[0110] The operation information of the circuit in the time dimension in the waveform file is extracted through the Python script program and mapped into timing features.

[0111] Furthermore, the circuit is converted into a graph to extract the circuit connection information, including:

[0112] Use Python program to parse the gate-level netlist file to identify each logic gate unit and corresponding wire signal in the gate-level netlist file;

[0113] The parsed data is constructed into a graph structure, where each logic gate is represented as a node and the connections between logic gates are represented as edges;

[0114] After completing data collection and graph construction, the constructed graph structure is displayed through the graphical tool of the Python program;

[0115] Output the circuit connection information in the form of an adjacency matrix or an adjacency list.

[0116] According to the gate-level circuit functional safety detection system based on graph neural network according to the embodiment of the present invention, critical gate node detection can be performed on any logic unit in the gate-level circuit. Compared with the traditional gate-level simulation fault injection analysis process, which requires fault injection and analysis of all logic units in the gate-level circuit, only less than 50% of the gate-level logic units need to be fault injected, which greatly reduces the key gate node detection time of large-scale circuit design. The gate-level functional safety detection tool proposed by the present invention has high accuracy. Compared with the traditional RTL-level simulation fault injection process, it can directly reflect the real structure of the circuit, perform simulation fault injection on the gate-level logic units that specifically constitute the circuit, and derive injection results with finer granularity and higher accuracy. And by proposing the critical gate node as the evaluation criterion, the injection results are converted with high accuracy, providing effective data for subsequent verification and reinforcement, meeting the requirements of ISO 26262 standard.

[0117] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0118] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Claims

1. A gate-level circuit functional safety detection method based on graph neural network, characterized in that: include: Acquire a circuit feature data set; the circuit feature data set includes structural features extracted from a gate-level netlist generated based on the circuit to be tested, timing features extracted from an fsdb file by running VCS, and circuit connection information extracted by converting the circuit into a graph; Training a GNN model based on the circuit feature data set, and using the trained GNN model to predict and output fault injection results and a preliminary key gate node list of all gate-level netlists; The validity of the determination criteria of the key gate nodes in the preliminary key gate node list is judged, and the determination criteria are iteratively optimized to output the final fault injection results of the gate-level netlist and the final key gate node list that meets the functional safety standard.

2. The method according to claim 1, characterized in that Generate a gate-level netlist based on the circuit under test and extract structural features from the gate-level netlist, including: Input the RTL file of the original circuit into Design Compiler for logic synthesis to convert the high-level hardware description language code into a gate-level netlist; the gate-level netlist is a Verilog file composed of basic logic gate units; The script program is used to store the comprehensive library file; wherein the comprehensive library file contains various types of logic gate units and some attributes used in the gate-level netlist, and the script program stores the type of each logic unit in the comprehensive library file; The properties of each basic logic unit in the gate-level netlist are recorded according to the stored comprehensive library file, and some features are transformed.

3. The method according to claim 1, characterized in that Run VCS and extract timing features from the fsdb file, including: Write the testbench test case for the corresponding circuit, and use VCS to compile the gate-level netlist and the corresponding testbench to obtain the corresponding FSDB waveform file; The operation information of the circuit in the time dimension in the waveform file is extracted through the Python script program and mapped into timing features.

4. The method according to claim 1, characterized in that: Convert the circuit into a diagram to extract circuit connection information, including: Use Python program to parse the gate-level netlist file to identify each logic gate unit and corresponding wire signal in the gate-level netlist file; The parsed data is constructed into a graph structure, where each logic gate is represented as a node and the connections between logic gates are represented as edges; After completing data collection and graph construction, the constructed graph structure is displayed through the graphical tool of the Python program; Output the circuit connection information in the form of an adjacency matrix or an adjacency list.

5. The method according to claim 1, characterized in that The GNN model is trained based on the circuit feature dataset, including: Initialize the weights and bias parameters of the GNN model and determine the aggregation method and aggregation properties to be used; The circuit feature data set is used as sample data. In the forward propagation stage, the sample data is read from the input layer and enters the graph neural hidden layer to perform corresponding forward propagation calculations using the read sample features. Each node updates its own feature representation based on the features of its neighboring nodes. After feature propagation, it enters the output layer and applies the activation function to output the prediction results of the sample data. The loss function value is calculated based on the trained sample data and the predicted results of the model output, and the weight and bias parameters of each node in the GNN model are updated according to the loss function value through the back propagation algorithm.

6. The method according to claim 1, characterized in that Iterative optimization judgment criteria include: Obtain circuit characteristic data set and initialize key gate node judgment values; The key gate node judgment value is used as the classification basis of the output layer of the GNN model to train the GNN model; Obtain a list of key gate nodes based on the model training results, and reinforce the logic units in the key gate list; The test calculates the diagnostic coverage of the reinforced circuit. If the diagnostic coverage does not meet the requirements, the key gate node judgment value is replaced according to the diagnostic coverage data; if the diagnostic coverage meets the requirements, the key gate node judgment value and the key gate node list are output.

7. A gate-level circuit functional safety detection system based on graph neural network, characterized in that: include: A circuit feature data acquisition module is used to acquire a circuit feature data set; the circuit feature data set includes structural features extracted from a gate-level netlist generated based on the circuit to be tested, timing features extracted from an fsdb file by running VCS, and circuit connection information extracted by converting the circuit into a diagram; A GNN model training module, used to train a GNN model based on the circuit feature data set, and use the trained GNN model to predict and output fault injection results and a preliminary key gate node list of all gate-level netlists; The key gate node output module is used to determine the validity of the judgment criteria of the key gate nodes in the preliminary key gate node list, and iteratively optimize the judgment criteria to output the final fault injection results of the gate-level netlist and the final key gate node list that meets the functional safety standards.

8. The system according to claim 7, characterized in that Generate a gate-level netlist based on the circuit under test and extract structural features from the gate-level netlist, including: Input the RTL file of the original circuit into Design Compiler for logic synthesis to convert the high-level hardware description language code into a gate-level netlist; the gate-level netlist is a Verilog file composed of basic logic gate units; The script program is used to store the comprehensive library file; wherein the comprehensive library file contains various types of logic gate units and some attributes used in the gate-level netlist, and the script program stores the type of each logic unit in the comprehensive library file; The properties of each basic logic unit in the gate-level netlist are recorded according to the stored comprehensive library file, and some features are transformed.

9. The system according to claim 7, characterized in that Run VCS and extract timing features from the fsdb file, including: Write the testbench test case for the corresponding circuit, and use VCS to compile the gate-level netlist and the corresponding testbench to obtain the corresponding FSDB waveform file; The operation information of the circuit in the time dimension in the waveform file is extracted through the Python script program and mapped into timing features.

10. The system according to claim 7, characterized in that Convert the circuit into a diagram to extract the circuit connection information, including: Use Python program to parse the gate-level netlist file to identify each logic gate unit and corresponding wire signal in the gate-level netlist file; The parsed data is constructed into a graph structure, where each logic gate is represented as a node and the connections between logic gates are represented as edges; After completing data collection and graph construction, the constructed graph structure is displayed through the graphical tool of the Python program; Output the circuit connection information in the form of an adjacency matrix or an adjacency list.

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