Display driving apparatus and display apparatus including the same

Abstract

Disclosed herein are a display driving apparatus and a display apparatus including the same, which are capable of recovering a communication abnormality state to a normal state when a communication abnormality occurs due to an unexpected variable during communication between a timing controller and a plurality of source drivers. The display apparatus may include: a timing controller configured to transmit a communication signal; a first source driver connected to the timing controller through a first communication link and configured to receive the communication signal; and a second source driver connected to the timing controller through a second communication link and configured to receive the communication signal. The first source driver and the second source driver may receive a resume command from the timing controller in a communication abnormal state, and execute a configuration mode in which an option for resuming a communication state is set according to configuration data received after the resume command.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a divisional application of the invention patent application with application number 202010610705.0.

[0003] This application claims priority to and the benefit of Korean Patent Application No. 2019-0174231, filed on December 24, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] The present invention relates to a display device, and more particularly, to a display driving device capable of restoring a communication abnormal state to a communication normal state and a display device including the display driving device. Background Art

[0005] Typically, a display device includes a display panel, a source driver, a timing controller, and the like.

[0006] The source driver converts the digital image data provided from the timing controller into a data voltage and provides the data voltage to the display panel. The source driver may be integrated into an integrated circuit chip (IC chip) and may be configured as a plurality of IC chips in consideration of the size and resolution of the display panel.

[0007] Meanwhile, in the display device, when a communication abnormality occurs due to an unexpected variable during communication between the timing controller and the source driver, a situation in which communication states differ from each other may occur.

[0008] A problem with the display device according to the related art is that communication states between the timing controller and some source drivers are different from each other due to communication abnormality, so that a display operation cannot be normally performed. Summary of the invention

[0009] The present disclosure aims to provide a display driving device capable of restoring an abnormal communication state between a timing controller and a source driver to a normal state, and a display device including the display driving device.

[0010] According to one aspect of the present disclosure, a display device is provided, comprising: a timing controller configured to send a communication signal; a first source driver connected to the timing controller via a first communication link and configured to receive the communication signal; and a second source driver connected to the timing controller via a second communication link and configured to receive the communication signal. The first source driver may be connected to the second source driver via a locking link, and the second source driver may be connected to the timing controller via a feedback link. The second source driver may provide a locking signal indicating a communication state to the timing controller via the feedback link, and the first source driver and the second source driver may receive a recovery command from the timing controller in a communication abnormal state, and execute a configuration mode according to configuration data received after the recovery command, in which an option for recovering the communication state is set.

[0011] According to another aspect of the present disclosure, a display driver device is provided, comprising: a first source driver connected to a timing controller via a first communication link; and a second source driver connected to the timing controller via a second communication link. The first source driver may be connected to the second source driver via a locking link, and the second source driver may be connected to the timing controller via a feedback link. The second source driver may provide a locking signal indicating a communication state to the timing controller via the feedback link, and when a recovery command is received from the timing controller, the first source driver and the second source driver may execute a configuration mode in which at least one of the following is set: an Internet Protocol (IP) option of the first communication link and the second communication link, an option of a clock data recovery circuit, an option for pre-clock training, and an equalizer option. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0013] Figure 1 is a block diagram of a display device according to an embodiment;

[0014] Figure 2 is a diagram for describing a recovery protocol of a display device according to one embodiment;

[0015] Figure 3 is a diagram for describing a recovery protocol of a display device according to another embodiment; and

[0016] Figure 4 is a diagram for describing a configuration protocol of a display device according to an embodiment. DETAILED DESCRIPTION

[0017] The embodiment discloses a display driving device and a display device including the same, and when a communication abnormality occurs due to an unexpected variable during communication between a timing controller and a source driver, the communication abnormal state can be restored to a normal state.

[0018] The embodiment discloses a display driving device and a display device including the same, which allows reducing the time of a configuration mode for operating at a low frequency by defining the length of a variable data packet in a packet header, thereby supporting high-speed data communication.

[0019] In an embodiment, the recovery protocol or the recovery mode may be defined as a protocol or a mode that makes the communication status between the timing controller and the source driver in the same state.

[0020] In an embodiment, a configuration protocol, a configuration mode, or a configuration cycle may be defined as a protocol, mode, or cycle for setting options for an Internet Protocol (IP) of a communication link for high-speed operation in a display mode, options for a clock data recovery circuit of a source driver, options for pre-clock training, and equalizer options.

[0021] In an embodiment, a display mode or a display cycle may be defined as a mode or a cycle for processing configuration data and image data of a source driver.

[0022] In an embodiment, the pre-clock training or bandwidth setting period may be defined as a mode or period for searching and setting an optimal frequency bandwidth for a communication link operating at high speed in a display mode.

[0023] In an embodiment, equalizer training or equalizer cycle may be defined as a pattern or cycle for setting equalizer gain levels to improve the characteristics of a communication link operating at high speed in display mode.

[0024] In an embodiment, the terms "first", "second", etc. may be used for the purpose of distinguishing a plurality of elements from one another. Here, the terms "first", "second", etc. are not intended to limit the elements.

[0025] Figure 1 is a block diagram of a display device according to an embodiment.

[0026] Reference Figure 1 , the display device may include a timing controller TCON, first to fifth plurality of source drivers SDIC1 to SDIC5 , and a display panel.

[0027] The timing controller TCON may be connected to the first to fifth plurality of source drivers SDIC1 to SDIC5 in a point-to-point manner through first to fifth communication links CL1 to CL5 .

[0028] As an example, the timing controller TCON may be connected to the first source driver SDIC1 through the first communication link CL1, and the timing controller TCON may be connected to the second source driver SDIC2 through the second communication link CL2. The timing controller TCON may be connected to the third source driver SDIC3 through the third communication link CL3, and the timing controller TCON may be connected to the fourth source driver SDIC4 through the fourth communication link CL4. The timing controller TCON may be connected to the fifth source driver SDIC5 through the fifth communication link CL5. In addition, each of the first to fifth communication links CL1 to CL5 may be configured as a pair of differential signal channels.

[0029] The timing controller TCON may provide communication signals CEDS GEN2 + / − to the source drivers SDIC1 to SDIC5 through the first to fifth communication links CL1 to CL5 , respectively.

[0030] In addition, the first to fifth source drivers SDIC1 to SDIC5 may be connected to each other in a cascade manner through the first to fifth locking links LL1 to LL5 .

[0031] As an example, the power supply voltage terminal VCC may be connected to the first source driver SDIC1 through the first locking link LL1. The first source driver SDIC1 may be connected to the second source driver SDIC2 through the second locking link LL2, and the second source driver SDIC2 may be connected to the third source driver SDIC3 through the third locking link LL3. The third source driver SDIC3 may be connected to the fourth source driver SDIC4 through the fourth locking link LL4, and the fourth source driver SDIC4 may be connected to the fifth source driver SDIC5 through the fifth locking link LL5. In addition, the fifth source driver SDIC5, which is the last one, may be connected to the timing controller TCON through the feedback link FL.

[0032] The first source driver SDIC1 may send a first locking signal LOCK1 to the second source driver SDIC2 through the second locking link LL2, and the second source driver SDIC2 may send a second locking signal LOCK2 to the third source driver SDIC3 through the third locking link LL3. The third source driver SDIC3 may send a third locking signal LOCK3 to the fourth source driver SDIC4 through the fourth locking link LL4, and the fourth source driver SDIC4 may send a fourth locking signal LOCK4 to the fifth source driver SDIC5 through the fifth locking link LL5. In addition, the fifth source driver SDIC5 may send a fifth locking signal RX_LOCK to the timing controller TCON through the feedback link FL. Here, the fifth locking signal RX_LOCK may indicate a communication state of at least one of the first to fifth source drivers SDIC1 to SDIC5. When a locking failure occurs in at least one of the first to fifth source drivers SDIC1 to SDIC5, the fifth locking signal RX_LOCK may be switched to have a value indicating a communication abnormal state.

[0033] Figure 2 is a diagram for describing a recovery protocol of a display device according to one embodiment.

[0034] Reference Figure 2 , when a communication abnormal state occurs due to external noise such as electrostatic discharge (ESD) while executing the display mode, the display device may switch from the display mode to the configuration mode.

[0035] As an example, when a lock failure occurs in at least one of the first to fifth source drivers SDIC1 to SDIC5 , the fifth source driver SDIC5 may switch the level of the fifth lock signal RX_LOCK from a high level to a low level and provide the fifth lock signal RX_LOCK to the timing controller TCON.

[0036] When a lock failure occurs, the timing controller TCON may include a recovery command SYNC_RST for recovering the communication state in the communication signal CEDS GEN2+ / − and transmit the communication signal CEDS GEN2+ / − to the first to fifth source drivers SDIC1 to SDIC5 through the first to fifth communication links CL1 to CL5 .

[0037] As an example, the timing controller TCON may transmit the resume command SYNC_RST having a predetermined level within a predetermined time period. In addition, the timing controller TCON may transmit the configuration data packet RX CFG to the first to fifth source drivers SDIC1 to SDIC5 after transmitting the resume command SYNC_RST having a predetermined level within a predetermined time period.

[0038] The first to fifth source drivers SDIC1 to SDIC5 may receive the resume command SYNC_RST and the configuration packet RXCFG and may execute a configuration mode according to the configuration packet RXCFG. Here, the configuration mode may be defined as a mode for setting IP options of the first to fifth communication links CL1 to CL5 operating at high speed in the display mode.

[0039] Additionally, the configuration mode may be set to operate in a lower frequency band compared to the display mode.

[0040] In addition, the timing controller TCON may transmit configuration completion data CFG DONE to the first to fifth source drivers SDIC1 to SDIC5 after transmitting the entire configuration data packet RX CFG.

[0041] As an example, the timing controller TCON may transmit the configuration completion data CFG DONE having a value that continuously switches between 0 and 1 within a predetermined time period to the first to fifth source drivers SDIC1 to SDIC5 .

[0042] In addition, when the first to fifth source drivers SDIC1 to SDIC5 receive the configuration completion data CFG DONE from the timing controller TCON, the first to fifth source drivers SDIC1 to SDIC5 may switch from the configuration mode to the display mode.

[0043] The first to fifth source drivers SDIC1 to SDIC5 may recover a phase locked loop (PLL) clock of an internal clock data recovery circuit (not shown) by performing clock training in a display period.

[0044] Next, after the clock training in the display period, the first to fifth source drivers SDIC1 to SDIC5 may lock the symbol boundary detection and the symbol clock by performing link training.

[0045] Next, after the link training in the display period, the first to fifth source drivers SDIC1 to SDIC5 may receive the frame data transmitted from the timing controller TCON, convert the row data included in the frame data into data voltages, and provide the data voltages to the display panel.

[0046] Figure 3 is a diagram for describing a recovery protocol of a display device according to another embodiment. Figure 3 When, with reference Figure 2 The description of the embodiment described is repeated by Figure 2 Description instead.

[0047] Reference Figure 3, when a communication abnormal state occurs due to external noise, the timing controller TCON may transmit a restoration command SYNC_RST having a predetermined level to the first to fifth source drivers SDIC1 to SDIC5 within a predetermined time period.

[0048] Next, after sending the resume command SYNC_RST within a predetermined time period, the timing controller TCON may send the configuration data packet RX CFG to the first to fifth source drivers SDIC1 to SDIC5 .

[0049] As an example, when transmitting the configuration data packet RX CFG to the first to fifth source drivers SDIC1 to SDIC5 , the timing controller TCON may cause the pre-clock training option and the equalizer training option to be included in the configuration data packet RX CFG.

[0050] Next, after completing the configuration mode, the first to fifth source drivers SDIC1 to SDIC5 may perform pre-clock training to set optimal frequency bandwidths of the first to fifth communication links CL1 to CL5 operating at a high speed in the display mode.

[0051] Next, after the pre-clock training is completed, the first to fifth source drivers SDIC1 to SDIC5 may perform equalizer training, thereby setting an equalizer gain level that may improve the characteristics of a communication link operating at a high speed in a display mode.

[0052] As an example, the timing controller TCON may repeat the pattern of sending the equalizer clock training and the equalizer link training during the equalizer cycle for the number of times set in the previous configuration mode.

[0053] The first to fifth source drivers SDIC1 to SDIC5 may change the level of the equalizer gain level by the value set in the previous configuration mode.

[0054] In addition, each of the first to fifth source drivers SDIC1 to SDIC5 may check the lock, symbol lock, and the number of errors of the clock data recovery circuit according to its equalizer gain level.

[0055] In addition, the first to fifth source drivers SDIC1 to SDIC5 can compare the lock, symbol lock and error numbers of the clock data recovery circuits according to the equalizer gain level to select the most effective equalizer gain level and set the first to fifth communication links CL1 to CL5 accordingly.

[0056] Here, the pre-clock training and the equalizer training may be set to operate at a high frequency band compared to the configuration mode.

[0057] In addition, after the equalizer training is completed, the first to fifth source drivers SDIC1 to SDIC5 may be switched to the display mode.

[0058] The first to fifth source drivers SDIC1 to SDIC5 may recover the PLL clock by performing clock training in the display mode, and may lock the symbol boundary detection and the symbol clock by performing link training.

[0059] In addition, the first to fifth source drivers SDIC1 to SDIC5 may convert row data transmitted from the timing controller TCON into data voltages and provide the data voltages to the display panel.

[0060] As described above, according to the embodiment, when a communication abnormality occurs between a timing controller and a source driver due to an unexpected variable, the communication abnormal state can be restored to a normal state at a desired time, thereby preventing a communication failure.

[0061] Reference Figure 4 , the source driver can receive a communication signal having a format of leading data PREAMBLE, start data START, configuration data CFG_DATA, end data END and configuration completion data CFG_DONE from the timing controller TCON in the configuration mode. The configuration data CFG_DATA can include a header CFG [7:0] defining the length of the data packets DATA1 to DATAN.

[0062] The configuration data CFG_DATA may have the following format: a packet header CFG [7:0], data packets DATA1 to DATAN, and a checksum CHECK_SUM [7:0].

[0063] The packet header CFG [7:0] can define the data packet DATA currently being exchanged 1 To DATA N In addition, the header CFG[7:0] may define the total number of the configuration data CFG_DATA sequence CFG_DATA[1] to CFG_DATA[N]. In addition, the header CFG[7:0] may define whether the checksum CHECK_SUM[7:0] is activated.

[0064] As an example, the packet header CFG[7:0] may include 8 bits, and the [0] bit of the packet header CFG[7:0] may be used for synchronization, and the [3:1] bits of the packet header CFG[7:0] may be used to define the data packet DATA currently being exchanged. 1 To DATA NThe [6:4] bits of the header CFG [7:0] can be used to define the total number of the configuration data CFG_DATA sequence CFG_DATA [1] to CFG_DATA [N]. In addition, the [7] bit of the header CFG [7:0] can define whether the checksum CHECK_SUM [7:0] is activated.

[0065] First, in the configuration mode, the source driver may receive preamble data PREAMBLE that continuously switches between a 0 level and a 1 level.

[0066] Next, when the source driver continuously receives the leading data PREAMBLE within a predetermined time period, the source driver may send a lock signal RX_LOCK indicating that the source driver is ready to receive the configuration data CFG_DATA to the timing controller TCON. As an example, the source driver may provide the lock signal RX_LOCK by switching from a low level to a high level.

[0067] Next, the timing controller TCON may transmit start data START, configuration data CFG_DATA, end data END, and configuration completion data CFG_DONE to the source driver in response to the lock signal RX_LOCK. Here, the start data START may be set to a level "0011", and the end data END may be set to a level "1100".

[0068] Next, after receiving the end data END '1100', the source driver may receive the configuration completion data CFG_DONE which continuously switches between a 0 level and a 1 level.

[0069] Next, when the source driver receives the configuration completion data CFG_DONE within a predetermined time period, the source driver may perform a pre-clock training, an equalizer training, or a display mode according to the configuration data CFG_DATA.

[0070] As described above, according to the embodiment, when a communication abnormality occurs between a timing controller and a source driver due to an unexpected variable, the communication abnormal state can be restored to a normal state at a desired time, thereby preventing a communication failure.

Claims

1. A display device, include: a timing controller configured to send a communication signal; a first source driver connected via the timing controller and the first communication link and configured to receive the communication signal; as well as a second source driver connected via the timing controller and the second communication link and configured to receive the communication signal, The first source driver and the second source driver switch from a display mode to a configuration mode in a communication abnormality state, and when a recovery command is received from the timing controller, set an option for recovering the communication state according to configuration data received after receiving the recovery command.

2. The display device according to claim 1, in, The timing controller is configured to send the restore command having a predetermined level within a predetermined time period.

3. The display device according to claim 2, in, After sending the recovery command within the predetermined time period, the timing controller includes a configuration data packet in the communication signal and sends it.

4. The display device according to claim 3, in, The first source driver and the second source driver receive the resume command and the configuration data packet, and execute the configuration mode according to the configuration data packet.

5. The display device according to claim 4, in, The configuration mode is set to operate in a low frequency band compared to the frequency band of the display mode.

6. The display device according to claim 3, in, When the sending of the configuration data packet is completed, the timing controller sends configuration completion data to the first source driver and the second source driver.

7. The display device according to claim 6, in, The timing controller sends the configuration completion data that switches continuously between a 0 level and a 1 level.

8. The display device according to claim 3, in, The timing controller includes an option for pre-clock training and an option for equalizer training in the configuration data packet and transmits the configuration data packet.

9. The display device according to claim 8, in, After completing the configuration mode, the first source driver and the second source driver perform pre-clock training to set a frequency bandwidth.

10. The display device according to claim 8, in, After completing the pre-clock training, the first source driver and the second source driver perform the equalizer training to set an equalizer gain level.

11. The display device according to claim 10, in, The pre-clock training and the equalizer training are configured to operate in a high frequency band compared to a frequency band of the configuration mode.

12. A display driver device, include: a first source driver connected to the timing controller via a first communication link; as well as a second source driver connected to the timing controller via a second communication link, The first source driver and the second source driver switch from a display mode to a configuration mode in a communication abnormality state, and When a recovery command is received from the timing controller, at least one of the following is set in the configuration mode: Internet Protocol IP options for the first communication link and the second communication link, options for a clock data recovery circuit, options for pre-clock training, and equalizer options.

13. The display driving device according to claim 12, in, The first source driver and the second source driver are configured to receive the resume command having a predetermined level from the timing controller within a predetermined time period.

14. The display driving device according to claim 13, in, After receiving the resume command within the predetermined time period, the first source driver and the second source driver receive a configuration data packet from the timing controller.

15. The display driving device according to claim 14, in, The first source driver and the second source driver execute the configuration mode according to the configuration data packet, and The configuration mode is set to operate in a low frequency band compared to the frequency band of the display mode.

16. The display driving device according to claim 14, in, The first source driver and the second source driver receive an option for pre-clock training and an option for equalizer training included in the configuration data packet.

17. The display driving device according to claim 16, in, After completing the configuration mode, the first source driver and the second source driver perform the pre-clock training to set a frequency bandwidth.

18. The display driving device according to claim 17, in, After completing the pre-clock training, the first source driver and the second source driver perform the equalizer training to set an equalizer gain level.

19. The display driving device according to claim 18, in, The pre-clock training and the equalizer training are configured to operate in a high frequency band compared to a frequency band of the configuration mode.

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