Display panel and display device

Abstract

The invention relates to the technical field of display, and provides a display panel and a display device.The display panel comprises a substrate, a plurality of pixel driving circuits and a plurality of data lines, and the pixel driving circuits comprise the first pixel driving circuit and the second pixel driving circuit; the data lines comprise first data lines, and the same first data line is connected with a part of the first pixel driving circuit and a part of the second pixel driving circuit; the pixel driving circuit comprises a driving transistor and a second transistor; the display panel further comprises a third bridging part and a first grid line. The third bridging part is connected between the first electrode of the second transistor and the grid electrode of the driving transistor. The partial structure of the first grid line is used for forming the grid electrode of the second transistor, and the overlapping area of the orthographic projection of the third bridging part in the first pixel driving circuit and the orthographic projection of the first grid line on the substrate is not equal to the overlapping area of the orthographic projection of the third bridging part in the second pixel driving circuit and the orthographic projection of the first grid line on the substrate. The display panel has a relatively high display effect.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, there is a large difference between the RC loading of the data lines near the center of the display panel and the RC loading of the data lines far from the center, which results in color shift on both sides of the display panel far from the center.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes:

[0005] substrate substrate;

[0006] A plurality of pixel driving circuits, wherein the orthographic projections of the plurality of pixel driving circuits on the substrate are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect, and the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit, wherein the first pixel driving circuit and the second pixel driving circuit are used to respectively drive light-emitting units of different colors;

[0007] A plurality of data lines connected to the pixel driving circuit, the data lines being used to provide data signals to the pixel driving circuit connected thereto, the plurality of data lines comprising a first data line, the same first data line connecting part of the first pixel driving circuit and part of the second pixel driving circuit;

[0008] Wherein, the pixel driving circuit comprises a driving transistor and a second transistor, a first electrode of the second transistor is connected to a gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor;

[0009] The display panel further includes:

[0010] a third bridge portion, the third bridge portion being connected between the first electrode of the second transistor and the gate of the driving transistor;

[0011] A first gate line, whose orthographic projection on the substrate extends along the first direction, a partial structure of the first gate line is used to form a gate of the second transistor, and an overlapping area of ​​an orthographic projection of a third bridge portion in the first pixel driving circuit on the substrate and an orthographic projection of the first gate line on the substrate is not equal to an overlapping area of ​​an orthographic projection of the third bridge portion in the second pixel driving circuit on the substrate and an orthographic projection of the first gate line on the substrate.

[0012] In an exemplary embodiment of the present disclosure, the first pixel driving circuit is used to drive a first color light emitting unit, and the second pixel driving circuit is used to drive a second color light emitting unit;

[0013] The driving transistor and the second transistor are P-type transistors, and the gate voltage required by the driving transistor to light up the first color light-emitting unit is smaller than the gate voltage required by the driving transistor to light up the second color light-emitting unit;

[0014] An overlapping area of ​​an orthographic projection of the third bridge portion on the substrate and an orthographic projection of the first gate line on the substrate in the first pixel driving circuit is smaller than an overlapping area of ​​an orthographic projection of the third bridge portion on the substrate and an orthographic projection of the first gate line on the substrate in the second pixel driving circuit.

[0015] In an exemplary embodiment of the present disclosure, the first pixel driving circuit is used to drive a first color light emitting unit, and the second pixel driving circuit is used to drive a second color light emitting unit;

[0016] The driving transistor is a P-type transistor, the second transistor is an N-type transistor, and the gate voltage required by the driving transistor to light up the first color light-emitting unit is less than the gate voltage required by the driving transistor to light up the second color light-emitting unit;

[0017] An overlapping area of ​​an orthographic projection of the third bridge portion on the substrate and an orthographic projection of the first gate line on the substrate in the first pixel driving circuit is greater than an overlapping area of ​​an orthographic projection of the third bridge portion on the substrate and an orthographic projection of the first gate line on the substrate in the second pixel driving circuit.

[0018] In an exemplary embodiment of the present disclosure, an overlapping area of ​​an orthographic projection of the third bridge portion in the first pixel driving circuit on the substrate and an orthographic projection of the first gate line on the substrate is S1, an overlapping area of ​​an orthographic projection of the third bridge portion in the second pixel driving circuit on the substrate and an orthographic projection of the first gate line on the substrate is S2, and S1 / S2 is 1-3.5.

[0019] In an exemplary embodiment of the present disclosure, the orthographic projection of the third bridging portion on the substrate extends along the second direction, the third bridging portion includes a first extension segment and a second extension segment, the orthographic projection of the first extension segment on the substrate overlaps with the orthographic projection of the first gate line on the substrate, and the orthographic projection of the second extension segment on the substrate does not overlap with the orthographic projection of the first gate line on the substrate;

[0020] Wherein, in the first pixel driving circuit, the size of the orthographic projection of the first extending section on the base substrate in the first direction is equal to the size of the orthographic projection of the second extending section on the base substrate in the first direction;

[0021] In the second pixel driving circuit, a size of an orthographic projection of the first extending section on the base substrate in the first direction is larger than a size of an orthographic projection of the second extending section on the base substrate in the first direction.

[0022] In an exemplary embodiment of the present disclosure, the orthographic projection of the third bridge portion on the substrate extends along the second direction, the third bridge portion includes a first extension segment, and the orthographic projection of the first extension segment on the substrate overlaps with the orthographic projection of the first gate line on the substrate;

[0023] The dimension of the orthographic projection of the first extension section on the substrate in the first pixel driving circuit in the first direction is smaller than the dimension of the orthographic projection of the first extension section on the substrate in the second pixel driving circuit in the first direction.

[0024] In an exemplary embodiment of the present disclosure, the first pixel driving circuit is used to drive a first color light emitting unit, the second pixel driving circuit is used to drive a second color light emitting unit, and the gate voltage required by the driving transistor to light up the first color light emitting unit is less than the gate voltage required by the driving transistor to light up the second color light emitting unit;

[0025] The pixel driving circuit further includes a capacitor, the capacitor includes a first electrode and a second electrode, the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the first power line;

[0026] An overlapping area of ​​orthographic projections of the first electrode and the second electrode of the capacitor in the first pixel driving circuit on the base substrate is larger than an overlapping area of ​​orthographic projections of the first electrode and the second electrode of the capacitor in the second pixel driving circuit on the base substrate.

[0027] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0028] A first gate layer, located on one side of the base substrate, the first gate layer comprises a first conductive portion, and the first conductive portion is used to form a gate of the driving transistor and a first electrode of a capacitor;

[0029] a second gate layer, located on a side of the first gate layer away from the base substrate, the second gate layer comprising a second conductive portion, an orthographic projection of the second conductive portion on the base substrate overlaps with an orthographic projection of the first conductive portion on the base substrate, the second conductive portion is used to form a second electrode of the capacitor, an opening is formed on the second conductive portion, and the third bridge portion is connected to the first conductive portion through a via hole penetrating the opening;

[0030] Wherein, the area of ​​the orthographic projection of the opening on the second conductive part in the first pixel driving circuit on the substrate is smaller than the area of ​​the orthographic projection of the opening on the second conductive part in the second pixel driving circuit on the substrate;

[0031] And / or, an area of ​​an orthographic projection of the first conductive portion in the first pixel driving circuit on the base substrate is larger than an area of ​​an orthographic projection of the first conductive portion in the second pixel driving circuit on the base substrate.

[0032] In an exemplary embodiment of the present disclosure, the overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the first pixel driving circuit on the substrate is S3, and the overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the second pixel driving circuit on the substrate is S4, and S3 / S4 is 1-1.8.

[0033] In an exemplary embodiment of the present disclosure, the first pixel driving circuit is used to drive a first color light emitting unit, the second pixel driving circuit is used to drive a second color light emitting unit, and the gate voltage required by the driving transistor to light up the first color light emitting unit is less than the gate voltage required by the driving transistor to light up the second color light emitting unit;

[0034] The width-to-length ratio of the channel region of the driving transistor in the first pixel driving circuit is greater than the width-to-length ratio of the channel region of the driving transistor in the second pixel driving circuit.

[0035] In an exemplary embodiment of the present disclosure, in the first pixel driving circuit, the channel region of the driving transistor extends linearly along the first direction;

[0036] In the second pixel driving circuit, the channel region of the driving transistor is bent and extended along the first direction.

[0037] In an exemplary embodiment of the present disclosure, the width of the channel region of the driving transistor in the first pixel driving circuit is greater than the width of the channel region of the driving transistor in the second pixel driving circuit;

[0038] And / or, the length of the channel region of the driving transistor in the first pixel driving circuit is smaller than the length of the channel region of the driving transistor in the second pixel driving circuit.

[0039] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a seventh transistor, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode of the seventh transistor is connected to the light emitting unit;

[0040] The display panel further includes:

[0041] The first source-drain layer is located on one side of the base substrate, the third bridge portion and the second initial signal line are located on the first source-drain layer, and the orthographic projection of the second initial signal line on the base substrate extends along the first direction.

[0042] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, a first electrode of the first transistor is connected to the first initial signal line, and a second electrode is connected to the gate of the driving transistor;

[0043] The display panel further includes:

[0044] an active layer, located between the base substrate and the first source-drain layer, the active layer comprising a first active portion and a fifteenth active portion, the first active portion comprising a first sub-active portion and a second sub-active portion, the first sub-active portion and the second sub-active portion are respectively used to form a channel region of the first transistor, and the fifteenth active portion is connected between the first sub-active portion and the second sub-active portion;

[0045] A second gate layer is located between the active layer and the first source and drain layer, the second gate layer includes a third conductive portion, the orthographic projection of the third conductive portion on the base substrate and the orthographic projection of the fifteenth active portion on the base substrate at least partially overlap, and the second initial signal line is connected to the third conductive portion through a via.

[0046] In an exemplary embodiment of the present disclosure, the plurality of pixel driving circuits further include a third pixel driving circuit, and the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit respectively drive light-emitting units of different colors;

[0047] The plurality of data lines further include a second data line, and the second data line is connected to the third pixel driving circuit;

[0048] An overlapping area of ​​an orthographic projection of the third bridge portion in the second pixel driving circuit on the substrate and an orthographic projection of the first gate line on the substrate is equal to an overlapping area of ​​an orthographic projection of the third bridge portion in the third pixel driving circuit on the substrate and an orthographic projection of the first gate line on the substrate.

[0049] In an exemplary embodiment of the present disclosure, the plurality of pixel driving circuits further include a third pixel driving circuit, and the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit respectively drive light-emitting units of different colors;

[0050] The plurality of data lines further include a second data line, and the second data line is connected to the third pixel driving circuit;

[0051] The overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the second pixel driving circuit on the substrate is equal to the overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the third pixel driving circuit on the substrate.

[0052] In an exemplary embodiment of the present disclosure, the first pixel driving circuit is used to drive a blue light emitting unit, the second pixel driving circuit is used to drive a red light emitting unit, and the third pixel driving circuit is used to drive a green light emitting unit.

[0053] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor and a fifth transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode is connected to a gate of the driving transistor, and a first electrode of the fifth transistor is connected to a power line, and a second electrode is connected to a first electrode of the driving transistor;

[0054] The display panel comprises a plurality of pixel driving circuit groups, the orthographic projections of the plurality of pixel driving circuit groups on the substrate are arranged in an array along the first direction and the second direction, the pixel driving circuit group comprises two pixel driving circuits arranged in the first direction, and the two pixel driving circuits in the same pixel driving circuit group are at least partially arranged in a mirror-symmetrical manner;

[0055] The display panel further includes:

[0056] an active layer, the active layer comprising a first active portion and a fifth active portion, the first active portion being used to form a channel region of the first transistor, and the fifth active portion being used to form a channel region of the fifth transistor;

[0057] In the same pixel driving circuit group, two adjacent first active portions are connected in the same layer, and two adjacent fifth active portions are connected in the same layer.

[0058] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes:

[0059] A first transistor, a first electrode connected to a first initial signal line, a second electrode connected to a gate of the driving transistor, and a gate connected to a first reset signal line;

[0060] a fourth transistor, a first electrode connected to the data line, a second electrode connected to the first electrode of the driving transistor, and a gate connected to the first gate line;

[0061] a fifth transistor, a first electrode connected to a power line, a second electrode connected to the first electrode of the driving transistor, and a gate connected to an enable signal line;

[0062] a sixth transistor, wherein a first electrode is connected to the second electrode of the driving transistor, a second electrode is connected to the light emitting unit, and a gate is connected to the enable signal line;

[0063] The seventh transistor has a first electrode connected to the second initial signal line, a second electrode connected to the second electrode of the sixth transistor, and a gate connected to the second reset signal line.

[0064] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0065] an active layer, located on one side of the substrate, wherein at least a portion of the structure of the active layer is used to form channel regions of the driving transistor, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor;

[0066] A first gate layer is located on a side of the active layer away from the base substrate, the first gate layer comprises a first conductive portion, a first reset signal line, a first gate line, an enable signal line, and a second reset signal line, and the orthographic projections of the first reset signal line, the first gate line, the enable signal line, and the second reset signal line on the base substrate extend along the first direction;

[0067] wherein at least a portion of the structure of the first reset signal line is used to form the gate of the first transistor, at least a portion of the structure of the second reset signal line is used to form the gate of the seventh transistor, at least a portion of the structure of the first gate line is used to form the gates of the second transistor and the fourth transistor, at least a portion of the structure of the enable signal line is used to form the gates of the fifth transistor and the sixth transistor, and the first conductive portion is used to form the gate of the drive transistor;

[0068] In the same pixel driving circuit, the orthographic projections of the first reset signal line, the first gate line, the enable signal line, and the second reset signal line on the base substrate are spaced apart in sequence along the second direction, and the orthographic projection of the first conductive portion on the base substrate is located between the orthographic projection of the first gate line on the base substrate and the orthographic projection of the enable signal line on the base substrate.

[0069] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0070] A gating circuit is provided, wherein the gating circuit is connected to the output end of the source driver chip and a plurality of data lines, and is used for responding to signals on different gating signal lines respectively to connect the output end of the source driver chip and different data lines in a time-sharing manner.

[0071] According to one aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned display panel.

[0072] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0074] Figure 1 A schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0075] Figure 2 A timing diagram of each node in a driving method of a display panel disclosed in the present invention;

[0076] Figure 3 for Figure 1 The overall structural diagram of the display panel is shown;

[0077] Figure 4 It is a structural schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel disclosed in the present invention;

[0078] Figure 5 A structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0079] Figure 6 for Figure 5 The structural layout of the active layer in the display panel shown;

[0080] Figure 7 for Figure 5 The structural layout of the first gate layer in the display panel is shown;

[0081] Figure 8 for Figure 5 The structural layout of the second gate layer in the display panel shown;

[0082] Fig. 9 for Figure 5 The structural layout of the first source and drain layer in the display panel is shown;

[0083] Fig.10 for Figure 5 The structural layout of the second source and drain layer in the display panel is shown;

[0084] Fig.11 for Figure 5 The structural layout of the electrode layer in the display panel is shown;

[0085] Fig.12 for Figure 5 The structure layout of the active layer and the first gate layer in the display panel shown;

[0086] Fig.13 for Figure 5 The structure layout of the active layer, the first gate layer and the second gate layer in the display panel shown;

[0087] Fig.14 for Figure 5 The structure layout of the active layer, the first gate layer, the second gate layer, and the first source and drain layer in the display panel shown;

[0088] Fig.15 for Figure 5 The structure layout of the active layer, the first gate layer, the second gate layer, the first source and drain layer, and the second source and drain layer in the display panel shown;

[0089] Fig.16 is a schematic structural diagram of an active layer in another exemplary embodiment of a display panel disclosed herein;

[0090] Fig.17 It is a structural schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel disclosed in the present invention;

[0091] Fig.18 A structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0092] Fig.19 for Fig.18 The structural layout of the active layer in the display panel shown;

[0093] Fig. 20 for Fig.18 The structural layout of the first gate layer in the display panel is shown;

[0094] Fig.21 for Fig.18 The structural layout of the second gate layer in the display panel shown;

[0095] Fig. 22 for Fig.18 The structural layout of the first source and drain layer in the display panel is shown;

[0096] Fig.23 for Fig.18 The structure layout of the active layer and the first gate layer in the display panel shown;

[0097] Fig.24 for Fig.18 The structure layout of the active layer, the first gate layer and the second gate layer in the display panel shown;

[0098] Fig.25 for Figure 5 The display panel is shown in a partial cross-sectional view taken along the dotted line CC. DETAILED DESCRIPTION

[0099] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0100] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0101] In the description of the present disclosure, unless otherwise clearly specified and limited, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance; the term "plurality" refers to two or more; the term "and / or" includes any and all combinations of one or more associated listed items. In particular, reference to "the / the" object or "an" object is also intended to indicate one of a possible plurality of such objects.

[0102] Unless otherwise specified or explained, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0103] Further, in the description of the present disclosure, it should be understood that the directional words such as "upper", "lower", "inner", "outer" and the like described in the exemplary embodiments of the present disclosure are described at the angles shown in the accompanying drawings and should not be understood as limitations on the exemplary embodiments of the present disclosure. It should also be understood that, in the context, when it is mentioned that an element or feature is connected to one or more "upper", "lower", or "inner", "outer" of another element, it can not only be directly connected to the "upper", "lower", "inner", "outer" of another element or elements, but can also be indirectly connected to the "upper", "lower", "inner", "outer" of another element or elements through an intermediate element.

[0104] like Figure 1 As shown, it is a schematic diagram of the structure of an exemplary embodiment of the display panel of the present disclosure. The display panel may include a gating circuit MUX, which is connected between the output terminal Dac of the source driver chip and the data line Da, and the gating circuit MUX is used to input the signal of the output terminal Dac of the source driver chip to the data line Da in a time-sharing manner. For example, the gating circuit MUX includes a plurality of transistors, and the plurality of transistors are controlled by the gating signal terminals Mux1 and Mux2 to input the signal of the output terminal Dac of the source driver chip to different data lines Da in a time-sharing manner. Among them, the gating circuit MUX can be located in the border area BB, and the pixel driving circuit Pix is ​​located in the display area CC. The display panel can reduce the number of source driver chips.

[0105] like Figure 1As shown, the plurality of pixel driving circuits Pix may be distributed in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y intersect, for example, the first direction X may be a row direction, and the second direction Y may be a column direction. The plurality of pixel driving circuits Pix may include a first pixel driving circuit Pix1, a second pixel driving circuit Pix2, and a third pixel driving circuit Pix3, wherein the first pixel driving circuit Pix1, the second pixel driving circuit Pix2, and the third pixel driving circuit Pix3 are used to drive light-emitting units of different colors, respectively, for example, the first pixel driving circuit Pix1 is used to drive a blue light-emitting unit, the second pixel driving circuit Pix2 is used to drive a red light-emitting unit, and the third pixel driving circuit Pix3 is used to drive a green light-emitting unit. The plurality of data lines Da include a first data line Da1 and a second data line Da2. The first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 can be distributed alternately in the second direction Y, and the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 distributed alternately in the second direction Y can be connected to the same first data line Da1, and multiple third pixel driving circuits Pix3 are distributed in the second direction Y, and the multiple third pixel driving circuits Pix3 distributed in the second direction Y are connected to the same second data line Da2.

[0106] like Figure 2 As shown, it is a timing diagram of each node in a driving method of the display panel disclosed in the present invention. Among them, Mux1 is a timing diagram of the strobe signal terminal Mux1, Mux2 is a timing diagram of the strobe signal terminal Mux2, Dac is a timing diagram of the output terminal of the source driver chip, Da1 is a timing diagram of the first data line, and Da2 is a timing diagram of the second data line. In the first time period t1, the strobe signal terminal Mux1 turns on the transistor connected thereto, and the output terminal Dac of the source driver chip provides a data signal to the first data line Da1 through the turned-on transistor, so that the first data line drives the first pixel driving circuit; in the second time period t2, the strobe signal terminal Mux2 turns on the transistor connected thereto, and the output terminal Dac of the source driver chip provides a data signal to the second data line Da2 through the turned-on transistor, so that the second data line drives the third pixel driving circuit; in the third time period t3, the strobe signal terminal Mux1 turns on the transistor connected thereto, and the output terminal Dac of the source driver chip provides a data signal to the first data line through the turned-on transistor, so that the first data line drives the second pixel driving circuit.

[0107] like Figure 3 As shown, Figure 1The overall structural diagram of the display panel is shown. The display panel may also include a gate drive circuit GOA, which is located on both sides of the display area CC in the first direction X. Compared with the red light-emitting unit and the green light-emitting unit, the gate voltage of the driving transistor required to turn on the blue light-emitting unit is smaller, and the data Range (voltage range of the data signal) corresponding to the blue light-emitting unit is different from the data Range corresponding to the red light-emitting unit. At the same time, since the first pixel drive circuit and the second pixel drive circuit are connected to the same data line Da, when the display panel displays a pure color picture, the data signal on the data line needs to jump. The speed of the voltage jump is related to the RC loading of the first data line Da1. As shown in FIG. Figure 3 As shown, the plurality of data lines Da include a central data line Daz near the center position and an edge data line Dab far from the center position. There is a large difference between the RC loading of the central data line Daz and the RC loading of the edge data line Dab, and the RC loading of the data line far from the center position is greater than the RC loading of the data line near the center position. The difference in RC loading between the central data line Daz and the edge data line Dab will cause the data signal voltages on the central data line Daz and the edge data line Dab to be different after the gating circuit is turned off, thereby causing the output currents of the pixel driving circuits connected to the central data line Daz and the edge data line Dab to be different, wherein the output current of the first pixel driving circuit connected to the edge data line Dab is less than the output current of the first pixel driving circuit connected to the central data line Daz, and the output current of the second pixel driving circuit connected to the edge data line Dab is greater than the output current of the second pixel driving circuit connected to the central data line Daz. This results in poor uniformity of the reddening on both sides of the display panel. In particular, in a display panel provided with a gating circuit, the above-mentioned color unevenness is more serious due to the short time of inputting the data signal to the first data line Da1. The voltage difference formula of the data signal input from the edge data line Dab to the second pixel driving circuit and the data signal input from the center data line Daz to the second pixel driving circuit is:

[0108]

[0109] Where Δdata_R is the voltage difference, Rdata b is the voltage of the data signal input to the second pixel driving circuit along the edge data line Dab, Rdata z is the voltage of the data signal input from the center data line Daz to the second pixel driving circuit, Rdata is the voltage of the data signal input from the first data line to the second pixel driving circuit, Bdata is the voltage of the data signal input from the first data line to the first pixel driving circuit, R z is the resistance of the center data line Daz, Cz is the capacitance of the center data line Daz, R b is the resistance of the edge data line Dab, C b is the capacitance of the edge data line Dab, and t is the time. According to the above formula, reducing the amplitude of the voltage jump on the first data line Da1 can improve the above poor uniformity.

[0110] It should be understood that in other exemplary embodiments, the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit may also be distributed in other ways, and the data line Da may connect multiple pixel driving circuits located in the same column, or may connect multiple pixel driving circuits located in different columns. As long as the same data line is connected to the first pixel driving circuit and the second pixel driving circuit, the display panel has the above-mentioned technical problems.

[0111] like Figure 4 FIG. 1 is a schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first electrode of the second transistor T2 is connected to the node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, the gate is connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to the node N, the first electrode is connected to the first initial signal terminal Vinit1, and the gate is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to the node N, and the second electrode is connected to the first power supply terminal VDD. The pixel driving circuit can be connected to a light emitting unit OLED, and the pixel driving circuit is used to drive the light emitting unit OLED to emit light, and the light emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. Among them, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors.

[0112] The pixel driving circuit driving method may include a reset phase, a data writing phase, and a light emitting phase. In the reset phase, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs a first initial signal to the node N. In the data writing phase, the first gate drive signal terminal G1 outputs a low-level signal, the second reset signal terminal Re2 outputs a low-level signal, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light emitting unit, and the data signal terminal Da outputs a data signal to write a compensation voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3. Light emitting phase: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C. The output current I of the driving transistor in the pixel driving circuit of the present disclosure is (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Wherein, I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.

[0113] This exemplary embodiment also provides a display panel, which may include a base substrate, an active layer, a first gate layer, a second gate layer, a first source drain layer, a second source drain layer, and an electrode layer stacked in sequence. An insulating layer may be provided between the adjacent layers. Figure 5-15 As shown, Figure 5 is a structural diagram of an exemplary embodiment of a display panel disclosed in the present invention, Figure 6 for Figure 5 The structure layout of the active layer in the display panel is shown. Figure 7 for Figure 5 The structure layout of the first gate layer in the display panel is shown. Figure 8 for Figure 5 The structure layout of the second gate layer in the display panel is shown. Fig. 9 for Figure 5 The structure layout of the first source and drain layer in the display panel is shown. Fig.10 for Figure 5 The structure layout of the second source and drain layer in the display panel is shown. Fig.11 for Figure 5 The structure layout of the electrode layer in the display panel is shown. Fig.12 for Figure 5The structure layout of the active layer and the first gate layer in the display panel is shown. Fig.13 for Figure 5 The structure layout of the active layer, the first gate layer, and the second gate layer in the display panel shown. Fig.14 for Figure 5 The structure layout of the active layer, the first gate layer, the second gate layer, and the first source and drain layer in the display panel shown. Fig.15 for Figure 5 The structure layout of the display panel shown includes an active layer, a first gate layer, a second gate layer, a first source and drain layer, and a second source and drain layer.

[0114] in, Figure 5 The display panel shown includes a plurality of pixel driving circuit groups Pz distributed along a first direction X and a second direction Y. The pixel driving circuit group Pz includes two pixel driving circuits Pix distributed in the first direction X, and the orthographic projections of the two pixel driving circuits Pix in the same pixel driving circuit group Pz on the substrate are at least partially mirror-symmetrically arranged. In the same pixel driving circuit group Pz, the channel regions of the same transistors in the two pixel driving circuits Pix are mirror-symmetrically arranged. For example, the channel regions of the two first transistors in the same pixel driving circuit group Pz are mirror-symmetrically arranged. The structure of the pixel driving circuit Pix can be as follows: Figure 4 shown.

[0115] like Figure 5 , 6, 12, the active layer may include: a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, and a seventeenth active portion 717. The first active portion 71 is used to form the channel region of the first transistor T1, wherein the first active portion 71 includes a first sub-active portion 711 and a second sub-active portion 732; the second active portion 72 is used to form the channel region of the second transistor T2, wherein the second active portion 72 includes a third sub-active portion 723 and a fourth sub-active portion 724; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 is connected to the eighth active portion 79; the eighth active portion 79 is connected to the eighth active portion 710; the eighth active portion 711 is connected to the eighth active portion 712; the eighth active portion 713 is connected to the eighth active portion 714; the eighth active portion 714 is connected to the eighth active portion 715; the eighth active portion 716 is connected to the eighth active portion 717; the eighth active portion 718 is connected to the eighth active portion 719; the eighth active portion 719 is connected to the eighth active portion 710; the eighth active portion 711 is connected to the eighth active portion 712; the eighth active portion 714 is connected to the eighth active portion 715; the eighth active portion 716 is connected to the eighth active portion 717; the eighth active portion 718 is connected to the eighth active portion 719; the eighth active portion 719 is connected to the eighth active portion 71 The ninth active portion 79 is connected between the first active portion 71 and the second active portion 72; the tenth active portion 710 is connected to the end of the seventh active portion 77 away from the sixth active portion 76; the thirteenth active portion 713 is connected between the seventh active portion 77 and the sixth active portion 76; the fourteenth active portion 714 is connected between the third sub-active portion 723 and the fourth sub-active portion 724; the fifteenth active portion 715 is connected between the first sub-active portion 711 and the second sub-active portion 732; the sixteenth active portion 716 is connected to the end of the fourth active portion 74 away from the third active portion 73; the seventeenth active portion 717 is connected to the end of the first active portion 71 away from the second active portion 72. In this exemplary embodiment, the active layer may be formed of polysilicon material, and accordingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polysilicon thin film transistors. The first transistor and the second transistor each have two channel regions spaced apart, and accordingly, the first transistor T1 and the second transistor T2 each have two gates, that is, the first transistor T1 and the second transistor T2 are dual-gate structures, and the transistors of the dual-gate structure have a smaller off leakage current, and this setting can reduce the leakage current of the driving transistor gate through the first transistor T1 and the second transistor T2, thereby improving the voltage stability of the driving transistor gate.

[0116] like Figure 5 , 6 As shown in FIGS. 1 and 12 , in the same pixel driving circuit group Pz, the seventeenth active portion 717 is connected between two adjacent first active portions 71 , and the eighth active portion 78 is connected between two adjacent fifth active portions 75 .

[0117] like Figure 5 , 7 As shown in FIG. 12 , the first gate layer may include: a first conductive portion 11, a first gate line G1, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The first gate line G1 may be used to provide Figure 4 The first gate drive signal terminal; the enable signal line EM can be used to provide Figure 4 The first reset signal line Re1 can be used to provide Figure 4 The first reset signal terminal in; the second reset signal line Re2 can be used to provide Figure 4 The second reset signal terminal in. The orthographic projection of the first gate line G1 on the substrate, the orthographic projection of the enable signal line EM on the substrate, the orthographic projection of the first reset signal line Re1 on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can all extend along the first direction X. The orthographic projection of the first gate line G1 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate and the orthographic projection of the second active portion 72 on the substrate. A partial structure of the first gate line G1 is used to form the gate of the fourth transistor T4, and a partial structure of the first gate line G1 is used to form the gate of the second transistor T2. The orthographic projection of the enable signal line EM on the substrate covers the orthographic projection of the fifth active portion 75 on the substrate and the orthographic projection of the sixth active portion 76 on the substrate. A partial structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate can cover the orthographic projection of the first active portion 71 on the substrate. A partial structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 77 on the substrate, and a partial structure of the first reset signal line Re1 can be used to form the gate of the seventh transistor T7. Among them, the second reset signal line Re2 corresponding to the pixel driving circuit of this row can be reused as the first reset signal line in the adjacent next row of pixel driving circuits. The orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 73 on the substrate, and the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to perform conductor processing on the active layer, that is, the area covered by the first gate layer in the active layer can form the channel region of the transistor, and the area not covered by the first gate layer in the active layer forms a conductor structure.

[0118] like Figure 5 , 8As shown in FIG. 13 , the second gate layer may include: a second conductive portion 22, a first connecting portion 23, a first initial signal line Vinit1, and a second initial signal line Vinit2. The orthographic projection of the first initial signal line Vinit1 on the substrate and the orthographic projection of the second initial signal line Vinit2 on the substrate may extend along the first direction X. The first initial signal line Vinit1 is used to provide Figure 4 The first initial signal terminal in the second initial signal line Vinit2 is used to provide Figure 4 The orthographic projection of the second conductive portion 22 on the substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate, and the second conductive portion 22 is used to form a second electrode of the capacitor C. The first connecting portion 23 is connected between two adjacent second conductive portions 22 in the same pixel driving circuit group Pz.

[0119] like Figure 5 , 9 As shown in Figures 14, the first source-drain layer may include a first bridge portion 41, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, a tenth bridge portion 410, and a first fan-out line FIPH. The first bridge portion 41 is connected to the second initial signal line Vinit2 and the tenth active portion 710 through vias to connect the second initial signal terminal and the first electrode of the seventh transistor; the third bridge portion 43 may be connected to the first conductive portion 11 and the ninth active portion 79 through vias to connect the gate of the driving transistor T3 and the second electrode of the first transistor T1 and the first electrode of the second transistor T2, wherein an opening 221 is formed on the second conductive portion 22, and a via connected between the first conductive portion 11 and the third bridge portion 43 may be provided through the opening 221. The fourth bridge portion 44 can be connected to the thirteenth active portion 713 through a via hole to connect the second electrode of the sixth transistor and the second electrode of the seventh transistor; the fifth bridge portion 45 can be connected to the sixteenth active portion 716 through a via hole to connect the first electrode of the fourth transistor; the sixth bridge portion 46 can be connected to the seventeenth active portion 717 and the first initial signal line Vinit1 through via holes to connect the first electrode and the first initial signal end of the first transistor T1; the seventh bridge portion 47 can be connected to the first connection portion 23 and the eighth active portion 78 through via holes to connect the first electrode of the fifth transistor T5 and the second electrode of the capacitor C. The tenth bridge portion 410 is connected between two second conductive portions 22 located in different pixel driving circuit groups Pz and adjacent in the first direction X. The orthographic projection of the first fan-out line FIPH on the substrate can extend along the first direction X, and the first fan-out line FIPH can be used as a row fan-out line connecting the data line in FIP (Fanout In Pixel, fan-out area in pixel).

[0120] like Figure 5, 10 As shown in FIG. 15 , the second source-drain layer may include a data line Da, a power line VDD, a second fan-out line FIPV, and a ninth bridge portion 59. The orthographic projections of the data line Da, the power line VDD, and the second fan-out line FIPV on the substrate all extend along the second direction Y. The data line Da is used to provide Figure 4 The data line Da can be connected to the fifth bridge portion 45 through a via hole to connect the data signal terminal and the first electrode of the fourth transistor T4. The power line VDD can be used to provide Figure 4 The power line VDD can be connected to the tenth bridge portion 410 through a via hole to connect the first power terminal and the first electrode of the fifth transistor T5 and the second electrode of the capacitor C. The ninth bridge portion 59 is connected to the fourth bridge portion 44 through a via hole. The second fan-out line FIPV can be used as a column-direction fan-out line connecting the data line in the FIP (Fanout In Pixel, fan-out area in pixel).

[0121] like Figure 5 , 11 As shown, the electrode layer may include a plurality of electrode portions: the plurality of electrode portions include a first electrode portion R, a second electrode portion B, and a third electrode portion G, and each electrode portion may be connected to the eighth bridge portion 58 through a via to connect the second electrode of the sixth transistor. Among the plurality of electrode portions connected to the same row of pixel driving circuits, the first electrode portion R, the third electrode portion G, the second electrode portion B, and the third electrode portion G are alternately distributed in sequence in the first direction; in two adjacent columns of pixel driving circuits, a plurality of first electrode portions R and a plurality of second electrode portions B are connected to the same column of pixel driving circuits, and the first electrode portion R and the second electrode portion B connected to the same column of pixel driving circuits are alternately distributed in sequence in the second direction, and a plurality of third electrode portions G are connected to another column of pixel driving circuits. The third electrode portion G may be used as the first electrode of a green light-emitting unit, the first electrode portion R may be used as the first electrode of a red light-emitting unit, and the second electrode portion B may be used as the first electrode of a blue light-emitting unit.

[0122] In this exemplary embodiment, Figure 5-15 As shown, the second gate layer may further include a first protruding portion 26 connected to one side of the first initial signal line in the second direction Y, and an overlapping area of ​​an orthographic projection of the first fan-out line FIPH on the substrate and an orthographic projection of the thirteenth active portion 713 on the substrate at least partially overlaps with the orthographic projection of the first protruding portion 26 on the substrate. The first protruding portion 26 may shield the voltage influence of the first fan-out line FIPH on the thirteenth active portion 713.

[0123] In this exemplary embodiment, Figure 5-15As shown, the second gate layer may further include: a second protruding portion 27, the second protruding portion 27 is connected to one side of the first initial signal line in the second direction, and the orthographic projection of the second protruding portion 27 on the base substrate at least partially overlaps with the orthographic projection of the fifteenth active portion 715 on the base substrate. The second protruding portion 27 may stabilize the fifteenth active portion 715 to reduce leakage current from the fifteenth active portion 715 to the source and drain of the first transistor.

[0124] In this exemplary embodiment, Figure 5-15 As shown, the second gate layer may further include a third protrusion 29, the third protrusion 29 being connected to one side of the second initial signal line in the second direction; the orthographic projection of the third protrusion 29 on the base substrate is located between the orthographic projection of the data line Da on the base substrate and the orthographic projection of the ninth active portion 79 on the base substrate. The third protrusion 29 may shield the signal interference of the data line Da on the ninth active portion 79.

[0125] In this exemplary embodiment, Figure 5-15 As shown, the second gate layer may further include a fourth protruding portion 28, the fourth protruding portion 28 being connected to one side of the second initial signal line in the second direction; wherein the orthographic projection of the fourth protruding portion 28 on the substrate substrate at least partially overlaps the orthographic projection of the fourteenth active portion 714 on the substrate substrate. The fourth protruding portion 28 may stabilize the fourteenth active portion 714 to reduce leakage current from the fourteenth active portion 714 to the source and drain of the second transistor.

[0126] In this exemplary embodiment, Figure 5-15 As shown, the orthographic projection of the first gate line G1 on the substrate overlaps with the orthographic projection of the third bridge portion 43 on the substrate, and a parasitic capacitor is formed between the first gate line G1 and the third bridge portion 43. After the threshold compensation stage is completed, the voltage of the first gate line G1 changes from a low level to a high level, and under the action of the parasitic capacitor between the first gate line G1 and the third bridge portion 43, the third bridge portion 43 is pulled high, thereby driving the gate of the transistor T3 to be pulled high.

[0127] In this exemplary embodiment, Figure 5-15As shown, the overlapping area of ​​the orthographic projection of the third bridge portion 43 on the substrate substrate and the orthographic projection of the first gate line G1 on the substrate substrate in the first pixel driving circuit is smaller than the overlapping area of ​​the orthographic projection of the third bridge portion 43 on the substrate substrate and the orthographic projection of the first gate line G1 on the substrate substrate in the second pixel driving circuit. The first gate line G1 has a stronger pulling effect on the gate of the driving transistor in the second pixel driving circuit than the first gate line G1 has on the gate of the driving transistor in the first pixel driving circuit. Therefore, under the same gray scale, this setting can reduce the voltage of the data signal written by the first data line Da1 to the second pixel driving circuit, that is, this setting can reduce the jump amplitude of the voltage on the first data line, and thus can improve the above-mentioned poor uniformity.

[0128] In this exemplary embodiment, the overlapping area of ​​the orthographic projection of the third bridge portion in the first pixel driving circuit on the substrate and the orthographic projection of the first gate line on the substrate is S1, and the overlapping area of ​​the orthographic projection of the third bridge portion in the second pixel driving circuit on the substrate and the orthographic projection of the first gate line on the substrate is S2, and S1 / S2 is 1-3.5. For example, S1 / S2 can be equal to 1, 1.5, 2, 2.5, 3, 3.5, etc.

[0129] In this exemplary embodiment, Figure 5-15 As shown, the orthographic projection of the third bridge portion 43 on the substrate extends along the second direction Y, and the third bridge portion 43 includes a first extension segment 431 and a second extension segment 432, the orthographic projection of the first extension segment 431 on the substrate overlaps with the orthographic projection of the first gate line G1 on the substrate, and the orthographic projection of the second extension segment 432 on the substrate does not overlap with the orthographic projection of the first gate line G1 on the substrate; wherein, in the first pixel driving circuit Pix1, the size of the orthographic projection of the first extension segment 431 on the substrate in the first direction X is equal to the size of the orthographic projection of the second extension segment 432 on the substrate in the first direction X; in the second pixel driving circuit Pix2, the size of the orthographic projection of the first extension segment 431 on the substrate in the first direction X is greater than the size of the orthographic projection of the second extension segment 432 on the substrate in the first direction X. That is, in this exemplary embodiment, the overlapping area of ​​the third bridge portion 43 and the first gate line G1 in the second pixel driving circuit can be increased by increasing the width of the first extension segment 431.

[0130] In this exemplary embodiment, Figure 5-15As shown, the size of the orthogonal projection of the first extension section 431 on the substrate in the first pixel driving circuit in the first direction X is smaller than the size of the orthogonal projection of the first extension section 431 on the substrate in the second pixel driving circuit in the first direction.

[0131] In this exemplary embodiment, Figure 5-15 As shown, the overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the first pixel driving circuit on the substrate is greater than the overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the second pixel driving circuit on the substrate. That is, the overlapping area of ​​the orthographic projections of the first conductive portion 11 and the second conductive portion 22 in the first pixel driving circuit on the substrate is greater than the overlapping area of ​​the orthographic projections of the first conductive portion 11 and the second conductive portion 22 in the second pixel driving circuit on the substrate. This exemplary embodiment increases the capacity of the capacitor C in the first pixel driving circuit, and the voltage of the data signal required for the first data line to write the same voltage to the gate of the driving transistor in the first pixel driving circuit is greater than the voltage of the data signal required for the first data line to write the same voltage to the gate of the driving transistor in the second pixel driving circuit, so that this setting can also reduce the jump amplitude of the voltage on the first data line, and thus can improve the above-mentioned poor uniformity.

[0132] In this exemplary embodiment, Figure 5-15 As shown, the area of ​​the orthographic projection of the opening 221 on the second conductive portion 22 in the first pixel driving circuit on the substrate is smaller than the area of ​​the orthographic projection of the opening 221 on the second conductive portion 22 in the second pixel driving circuit on the substrate; and / or the area of ​​the orthographic projection of the first conductive portion 11 in the first pixel driving circuit on the substrate is larger than the area of ​​the orthographic projection of the first conductive portion 11 in the second pixel driving circuit on the substrate.

[0133] In this exemplary embodiment, Figure 5-15 As shown, the overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the first pixel driving circuit on the substrate is S3, and the overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the second pixel driving circuit on the substrate is S4, and S3 / S4 is 1-1.8. For example, S3 / S4 can be equal to 1, 1.2, 1.4, 1.6, 1.8, etc.

[0134] In this exemplary embodiment, the driving transistor T3 is a P-type transistor. The smaller the gate-source voltage difference of the driving transistor T3 is, the greater the output current thereof is.

[0135] like Fig.16As shown, it is a schematic diagram of the structure of the active layer in another exemplary embodiment of the display panel of the present disclosure. The width-to-length ratio of the driving transistor channel region 73 in the first pixel driving circuit Pix1 is greater than the width-to-length ratio of the driving transistor channel region 73 in the second pixel driving circuit Pix2. The first pixel driving circuit Pix1 has a stronger driving capability than the second pixel driving circuit Pix2. Compared with the second pixel driving circuit Pix2, the driving transistor in the first pixel driving circuit Pix1 can output the same driving current with a larger gate-source voltage difference, that is, compared with the second pixel driving circuit Pix2, when outputting the same driving current, the first pixel driving circuit Pix1 requires a larger data signal, so that this setting can also reduce the jump amplitude of the voltage on the first data line, and thus can improve the above-mentioned poor uniformity.

[0136] In this exemplary embodiment, Fig.16 As shown, in the first pixel driving circuit Pix1, the channel region 73 of the driving transistor may extend linearly along the first direction X; in the second pixel driving circuit Pix2, the channel region 73 of the driving transistor may extend along the first direction X in a bent manner.

[0137] In this exemplary embodiment, Fig.16 As shown, the width of the driving transistor channel region 73 in the first pixel driving circuit Pix1 is greater than the width of the driving transistor channel region 73 in the second pixel driving circuit Pix2; and / or, the length of the driving transistor channel region 73 in the first pixel driving circuit Pix1 is less than the length of the driving transistor channel region 73 in the second pixel driving circuit Pix2.

[0138] In this exemplary embodiment, Figure 5-16 As shown, the overlapping area of ​​the orthographic projection of the third bridge portion 43 on the substrate in the second pixel driving circuit Pix2 and the orthographic projection of the first gate line G1 on the substrate can be equal to the overlapping area of ​​the orthographic projection of the third bridge portion 43 on the substrate in the third pixel driving circuit Pix3 and the orthographic projection of the first gate line G1 on the substrate.

[0139] In this exemplary embodiment, Figure 5-16 As shown, the overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the second pixel driving circuit Pix2 on the substrate is equal to the overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the third pixel driving circuit Pix3 on the substrate.

[0140] This exemplary embodiment proposes three ways to reduce the signal jump amplitude on the first data line: 1. Increase the overlapping area of ​​the third bridge portion and the first gate line in the second pixel driving circuit; 2. Increase the capacity of the capacitor in the first pixel driving circuit; 3. Increase the width-to-length ratio of the channel region of the driving transistor in the first pixel driving circuit. The display panel can apply one or more of the three ways.

[0141] like Fig.17 FIG. 1 is a schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel disclosed herein. Figure 4 Compared with the pixel driving circuit shown in Fig.17 In the pixel driving circuit shown, the gate of the fourth transistor is connected to the second reset signal terminal Re2.

[0142] This exemplary embodiment also provides another display panel, which includes Fig.17 The pixel driving circuit shown in FIG. Figure 18-24 As shown, Fig.18 is a structural diagram of an exemplary embodiment of a display panel disclosed in the present invention, Fig.19 for Fig.18 The structure layout of the active layer in the display panel is shown. Fig. 20 for Fig.18 The structure layout of the first gate layer in the display panel is shown. Fig.21 for Fig.18 The structural layout of the second gate layer in the display panel is shown. Fig. 22 for Fig.18 The structure layout of the first source and drain layer in the display panel is shown. Fig.23 for Fig.18 The structure layout of the active layer and the first gate layer in the display panel is shown. Fig.24 for Fig.18 The structure layout of the active layer, the first gate layer and the second gate layer in the display panel is shown.

[0143] like Fig.18 , 1923, the active layer may include: a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717, an eighteenth active portion 718, and a nineteenth active portion 719. The first active portion 71 is used to form the channel region of the first transistor T1, wherein the first active portion 71 includes a first sub-active portion 711 and a second sub-active portion 732; the second active portion 72 is used to form the channel region of the second transistor T2, wherein the second active portion 72 includes a third sub-active portion 723 and a fourth sub-active portion 724; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 is connected to the fifth active portion 75 away from the third active portion one end of 73; the ninth active portion 79 is connected between the first active portion 71 and the second active portion 72; the tenth active portion 710 is connected to one end of the seventh active portion 77 away from the sixth active portion 76; the thirteenth active portion 713 is connected between the seventh active portion 77 and the sixth active portion 76; the fourteenth active portion 714 is connected between the third sub-active portion 723 and the fourth sub-active portion 724; the fifteenth active portion 715 is connected between the first sub-active portion 711 and the second sub-active portion 732; the sixteenth active portion 716 and the eighteenth active portion 718 are connected to both sides of the fourth active portion 74; the seventeenth active portion 717 is connected to one end of the first active portion 71 away from the second active portion 72; the nineteenth active portion 719 is connected to one end of the third active portion 73 away from the sixth active portion 76. In this exemplary embodiment, the active layer may be formed of polysilicon material, and accordingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polysilicon thin film transistors.

[0144] like Fig.18 , 20 As shown in FIG. 23 , the first gate layer may include: a first conductive portion 11, a first gate line G1, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The first gate line G1 may be used to provide Fig.17 The first gate drive signal terminal; the enable signal line EM can be used to provide Fig.17 The first reset signal line Re1 can be used to provide Fig.17The first reset signal terminal in; the second reset signal line Re2 can be used to provide Fig.17 The orthographic projection of the first gate line G1 on the substrate, the orthographic projection of the enable signal line EM on the substrate, the orthographic projection of the first reset signal line Re1 on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can all extend along the first direction X. The orthographic projection of the first gate line G1 on the substrate covers the orthographic projection of the second active portion 72 on the substrate, and a partial structure of the first gate line G1 is used to form the gate of the fourth transistor T4. The orthographic projection of the enable signal line EM on the substrate covers the orthographic projection of the fifth active portion 75 on the substrate, and the orthographic projection of the sixth active portion 76 on the substrate, and a partial structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate can cover the orthographic projection of the first active portion 71 on the substrate, and a partial structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 77 on the substrate and the orthographic projection of the second active portion 72 on the substrate, and a partial structure of the first reset signal line Re1 can be used to form the gate of the seventh transistor T7 and the second transistor T2. The orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 73 on the substrate, and the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to perform conductor processing on the active layer, that is, the area of ​​the active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first gate layer forms a conductor structure.

[0145] like Fig.18 , 21 As shown in FIG. 24 , the second gate layer may include: a second conductive portion 22, a first connecting portion 23, and a first initial signal line Vinit1. The orthographic projection of the first initial signal line Vinit1 on the substrate may extend along the first direction X. The first initial signal line Vinit1 is used to provide Fig.17 The orthographic projection of the second conductive portion 22 on the substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate, and the second conductive portion 22 is used to form a second electrode of the capacitor C. The first connecting portion 23 is connected between two adjacent second conductive portions 22.

[0146] like Fig.18 , 22As shown, the first source-drain layer may include a first bridge portion 41, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a tenth bridge portion 410, a second initial signal line Vinit2, and a first fan-out line FIPH. The first bridge portion 41 is connected to the eighteenth active portion 718 and the nineteenth active portion 719 through vias, respectively, to connect the second electrode of the fourth transistor and the first electrode of the driving transistor. The third bridge portion 43 may be connected to the first conductive portion 11 and the ninth active portion 79 through vias, respectively, to connect the gate of the driving transistor T3 and the second electrode of the first transistor T1 and the first electrode of the second transistor T2, wherein an opening 221 is formed on the second conductive portion 22, and a via connected between the first conductive portion 11 and the third bridge portion 43 may be provided through the opening 221. The fourth bridge portion 44 may be connected to the thirteenth active portion 713 through a via hole to connect the second electrode of the sixth transistor and the second electrode of the seventh transistor; the fifth bridge portion 45 may be connected to the sixteenth active portion 716 through a via hole to connect the first electrode of the fourth transistor; the sixth bridge portion 46 may be connected to the seventeenth active portion 717 and the first initial signal line Vinit1 through via holes to connect the first electrode of the first transistor T1 and the first initial signal terminal; the tenth bridge portion 410 may be connected to the second conductive portion 22 and the eighth active portion 78 through via holes to connect the first electrode of the fifth transistor T5 and the second electrode of the capacitor C. The second initial signal line Vinit2 is connected to the tenth active portion 710 through via holes to connect the second initial signal terminal and the first electrode of the seventh transistor. The second initial signal line Vinit2 can also be connected to the third conductive part 24 through a via, and the orthographic projection of the third conductive part 24 on the substrate can overlap with the orthographic projection of the fifteenth active part 715 on the substrate, and the third conductive part 24 can stabilize the fifteenth active part 715, thereby reducing the leakage current of the fifteenth active part 715 to the source and drain of the first transistor T1. The orthographic projection of the first fan-out line FIPH on the substrate can extend along the first direction X, and the first fan-out line FIPH can be used as a row fan-out line connecting the data line in FIP (Fanout In Pixel, fan-out area in pixel).

[0147] like Fig.18 , 22 As shown, in this exemplary embodiment, the second initial signal line is arranged in the first source-drain layer, and the square resistance of the first source-drain layer is smaller than the square resistance of the second gate layer. This arrangement can improve the uniformity of the display panel.

[0148] In this exemplary embodiment, the second transistor T2 is a P-type transistor, and after the threshold compensation stage ends, the voltage of the first gate line jumps from a low level to a high level, and the first gate line has a pull-up effect on the third bridge portion. It should be understood that in other exemplary embodiments, the second transistor T2 may also be an N-type transistor, and after the threshold compensation stage ends, the voltage of the first gate line jumps from a high level to a low level, and the first gate line has a pull-down effect on the third bridge portion. In order to reduce the amplitude of the signal voltage jump on the first data line, the overlap area of ​​the positive projection of the third bridge portion on the substrate substrate and the positive projection of the first gate line on the substrate substrate in the first pixel driving circuit may be greater than the overlap area of ​​the positive projection of the third bridge portion on the substrate substrate and the positive projection of the first gate line on the substrate substrate in the second pixel driving circuit.

[0149] like Fig.25 As shown, Figure 5 The display panel is shown in a partial cross-sectional view taken along the dotted line CC. The display panel may also include a first insulating layer 101, a second insulating layer 102, a dielectric layer 103, a passivation layer 104, a first flat layer 105, and a second flat layer 106. Among them, the base substrate 100, the active layer, the first insulating layer 101, the first gate layer, the second insulating layer 102, the second gate layer, the dielectric layer 103, the first source and drain layer, the passivation layer 104, the first flat layer 105, the second source and drain layer, the second flat layer 106, and the electrode layer are stacked in sequence. The first insulating layer 101 and the second insulating layer 102 may be a single-layer structure or a multi-layer structure, and the materials of the first insulating layer 101 and the second insulating layer 102 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer 103 may be a silicon nitride layer; the materials of the first flat layer 105 and the second flat layer 106 may be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG) and the like. The passivation layer 104 may be a silicon oxide layer. The substrate 100 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material. The materials of the first gate layer and the second gate layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum / titanium alloy or a stacked conductive layer. The material of the first source-drain layer and the second source-drain layer may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum / titanium alloy or a stack, or a conductive layer such as a titanium / aluminum / titanium stack. The square resistance of any one of the first source-drain layer and the second source-drain layer may be less than the square resistance of any one of the first gate layer and the second gate layer.

[0150] It should be noted that if Figure 5-24As shown, the black squares drawn on the side of the first source and drain layer away from the substrate substrate represent the vias of the first source and drain layer connected to the other layers facing the substrate substrate; the chamfered black circles drawn on the side of the second source and drain layer away from the substrate substrate represent the vias of the second source and drain layer connected to the other layers facing the substrate substrate; the rounded rectangles drawn on the side of the electrode layer away from the substrate substrate represent the vias of the electrode layer connected to the other layers facing the substrate substrate, and vias at different positions can pass through different insulating layers.

[0151] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the numbers shown in the figure. The drawings described in this disclosure are only structural schematic diagrams. In addition, qualifiers such as first and second are only used to limit different structural names, and they do not have a specific order of meaning. The same structural layer can be formed by the same composition process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate substrate extends in a certain direction, which can be understood as the orthographic projection of the structure on the substrate substrate extending in a straight line or bending along this direction.

[0152] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a display device such as a mobile phone, a tablet computer, a television, etc.

[0153] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0154] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel comprises: substrate substrate; A plurality of pixel driving circuits, wherein the orthographic projections of the plurality of pixel driving circuits on the substrate are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect, and the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit, wherein the first pixel driving circuit and the second pixel driving circuit are used to respectively drive light-emitting units of different colors; A plurality of data lines connected to the pixel driving circuit, the data lines being used to provide data signals to the pixel driving circuit connected thereto, the plurality of data lines comprising a first data line, the same first data line connecting part of the first pixel driving circuit and part of the second pixel driving circuit; Wherein, the pixel driving circuit comprises a driving transistor and a second transistor, a first electrode of the second transistor is connected to a gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; The display panel further includes: a third bridge portion, the third bridge portion being connected between the first electrode of the second transistor and the gate of the driving transistor; A first gate line, whose orthographic projection on the substrate extends along the first direction, a partial structure of the first gate line is used to form a gate of the second transistor, and an overlapping area of ​​an orthographic projection of a third bridge portion in the first pixel driving circuit on the substrate and an orthographic projection of the first gate line on the substrate is not equal to an overlapping area of ​​an orthographic projection of the third bridge portion in the second pixel driving circuit on the substrate and an orthographic projection of the first gate line on the substrate.

2. The display panel according to claim 1, wherein: The first pixel driving circuit is used to drive a first color light emitting unit, and the second pixel driving circuit is used to drive a second color light emitting unit; The driving transistor and the second transistor are P-type transistors, and the gate voltage required by the driving transistor to light up the first color light-emitting unit is smaller than the gate voltage required by the driving transistor to light up the second color light-emitting unit; An overlapping area of ​​an orthographic projection of the third bridge portion on the substrate and an orthographic projection of the first gate line on the substrate in the first pixel driving circuit is smaller than an overlapping area of ​​an orthographic projection of the third bridge portion on the substrate and an orthographic projection of the first gate line on the substrate in the second pixel driving circuit.

3. The display panel according to claim 1, wherein: The first pixel driving circuit is used to drive a first color light emitting unit, and the second pixel driving circuit is used to drive a second color light emitting unit; The driving transistor is a P-type transistor, the second transistor is an N-type transistor, and the gate voltage required by the driving transistor to light up the first color light-emitting unit is less than the gate voltage required by the driving transistor to light up the second color light-emitting unit; An overlapping area of ​​an orthographic projection of the third bridge portion on the substrate and an orthographic projection of the first gate line on the substrate in the first pixel driving circuit is greater than an overlapping area of ​​an orthographic projection of the third bridge portion on the substrate and an orthographic projection of the first gate line on the substrate in the second pixel driving circuit.

4. The display panel according to claim 2, wherein: The overlapping area of ​​the orthographic projection of the third bridge portion in the first pixel driving circuit on the substrate and the orthographic projection of the first gate line on the substrate is S1, and the overlapping area of ​​the orthographic projection of the third bridge portion in the second pixel driving circuit on the substrate and the orthographic projection of the first gate line on the substrate is S2, and S1 / S2 is 1-3.

5.

5. The display panel according to claim 2, wherein: The orthographic projection of the third bridge portion on the substrate extends along the second direction, the third bridge portion comprises a first extension segment and a second extension segment, the orthographic projection of the first extension segment on the substrate overlaps with the orthographic projection of the first gate line on the substrate, and the orthographic projection of the second extension segment on the substrate does not overlap with the orthographic projection of the first gate line on the substrate; Wherein, in the first pixel driving circuit, the size of the orthographic projection of the first extending section on the base substrate in the first direction is equal to the size of the orthographic projection of the second extending section on the base substrate in the first direction; In the second pixel driving circuit, a size of an orthographic projection of the first extending section on the base substrate in the first direction is larger than a size of an orthographic projection of the second extending section on the base substrate in the first direction.

6. The display panel according to claim 2, wherein: The orthographic projection of the third bridge portion on the base substrate extends along the second direction, the third bridge portion comprises a first extension segment, and the orthographic projection of the first extension segment on the base substrate overlaps with the orthographic projection of the first gate line on the base substrate; The dimension of the orthographic projection of the first extension section on the substrate in the first pixel driving circuit in the first direction is smaller than the dimension of the orthographic projection of the first extension section on the substrate in the second pixel driving circuit in the first direction.

7. The display panel according to claim 1, wherein: The pixel driving circuit further includes a capacitor, the capacitor includes a first electrode and a second electrode, the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the first power line; The first pixel driving circuit is used to drive a first color light emitting unit, the second pixel driving circuit is used to drive a second color light emitting unit, and the gate voltage required by the driving transistor to light up the first color light emitting unit is less than the gate voltage required by the driving transistor to light up the second color light emitting unit; An overlapping area of ​​orthographic projections of the first electrode and the second electrode of the capacitor in the first pixel driving circuit on the base substrate is larger than an overlapping area of ​​orthographic projections of the first electrode and the second electrode of the capacitor in the second pixel driving circuit on the base substrate.

8. The display panel according to claim 7, wherein: The display panel further includes: A first gate layer, located on one side of the base substrate, the first gate layer comprises a first conductive portion, and the first conductive portion is used to form a gate of the driving transistor and a first electrode of a capacitor; a second gate layer, located on a side of the first gate layer away from the base substrate, the second gate layer comprising a second conductive portion, an orthographic projection of the second conductive portion on the base substrate overlaps with an orthographic projection of the first conductive portion on the base substrate, the second conductive portion is used to form a second electrode of the capacitor, an opening is formed on the second conductive portion, and the third bridge portion is connected to the first conductive portion through a via hole penetrating the opening; Wherein, the area of ​​the orthographic projection of the opening on the second conductive part in the first pixel driving circuit on the substrate is smaller than the area of ​​the orthographic projection of the opening on the second conductive part in the second pixel driving circuit on the substrate; And / or, an area of ​​an orthographic projection of the first conductive portion in the first pixel driving circuit on the base substrate is larger than an area of ​​an orthographic projection of the first conductive portion in the second pixel driving circuit on the base substrate.

9. The display panel according to claim 7, wherein: The overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the first pixel driving circuit on the substrate is S3, and the overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the second pixel driving circuit on the substrate is S4, and S3 / S4 is 1-1.

8.

10. The display panel according to claim 1, wherein: The first pixel driving circuit is used to drive a first color light emitting unit, the second pixel driving circuit is used to drive a second color light emitting unit, and the gate voltage required by the driving transistor to light up the first color light emitting unit is less than the gate voltage required by the driving transistor to light up the second color light emitting unit; The width-to-length ratio of the channel region of the driving transistor in the first pixel driving circuit is greater than the width-to-length ratio of the channel region of the driving transistor in the second pixel driving circuit.

11. The display panel according to claim 10, wherein: In the first pixel driving circuit, the channel region of the driving transistor extends linearly along the first direction; In the second pixel driving circuit, the channel region of the driving transistor is bent and extended along the first direction.

12. The display panel according to claim 10, wherein: The width of the channel region of the driving transistor in the first pixel driving circuit is greater than the width of the channel region of the driving transistor in the second pixel driving circuit; And / or, the length of the channel region of the driving transistor in the first pixel driving circuit is smaller than the length of the channel region of the driving transistor in the second pixel driving circuit.

13. The display panel according to claim 1, wherein: The pixel driving circuit further includes a seventh transistor, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode of the seventh transistor is connected to the light emitting unit; The display panel further includes: The first source-drain layer is located on one side of the base substrate, the third bridge portion and the second initial signal line are located on the first source-drain layer, and the orthographic projection of the second initial signal line on the base substrate extends along the first direction.

14. The display panel according to claim 13, wherein: The pixel driving circuit further comprises a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a gate of the driving transistor; The display panel further includes: an active layer, located between the base substrate and the first source-drain layer, the active layer comprising a first active portion and a fifteenth active portion, the first active portion comprising a first sub-active portion and a second sub-active portion, the first sub-active portion and the second sub-active portion are respectively used to form a channel region of the first transistor, and the fifteenth active portion is connected between the first sub-active portion and the second sub-active portion; A second gate layer is located between the active layer and the first source and drain layer, the second gate layer includes a third conductive portion, the orthographic projection of the third conductive portion on the base substrate and the orthographic projection of the fifteenth active portion on the base substrate at least partially overlap, and the second initial signal line is connected to the third conductive portion through a via.

15. The display panel according to claim 1, wherein: The plurality of pixel driving circuits further include a third pixel driving circuit, and the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit respectively drive light-emitting units of different colors; The plurality of data lines further include a second data line, and the second data line is connected to the third pixel driving circuit; An overlapping area of ​​an orthographic projection of the third bridge portion in the second pixel driving circuit on the substrate and an orthographic projection of the first gate line on the substrate is equal to an overlapping area of ​​an orthographic projection of the third bridge portion in the third pixel driving circuit on the substrate and an orthographic projection of the first gate line on the substrate.

16. The display panel according to claim 7, wherein: The plurality of pixel driving circuits further include a third pixel driving circuit, and the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit respectively drive light-emitting units of different colors; The plurality of data lines further include a second data line, and the second data line is connected to the third pixel driving circuit; The overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the second pixel driving circuit on the substrate is equal to the overlapping area of ​​the orthographic projections of the first electrode and the second electrode of the capacitor in the third pixel driving circuit on the substrate.

17. The display panel according to claim 15 or 16, wherein: The first pixel driving circuit is used to drive the blue light emitting unit, the second pixel driving circuit is used to drive the red light emitting unit, and the third pixel driving circuit is used to drive the green light emitting unit.

18. The display panel according to any one of claims 1 to 16, wherein: The pixel driving circuit further includes a first transistor and a fifth transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode is connected to a gate of the driving transistor, and a first electrode of the fifth transistor is connected to a power line, and a second electrode is connected to a first electrode of the driving transistor; The display panel comprises a plurality of pixel driving circuit groups, the orthographic projections of the plurality of pixel driving circuit groups on the substrate are arranged in an array along the first direction and the second direction, the pixel driving circuit group comprises two pixel driving circuits arranged in the first direction, and the two pixel driving circuits in the same pixel driving circuit group are at least partially arranged in a mirror-symmetrical manner; The display panel further includes: an active layer, the active layer comprising a first active portion and a fifth active portion, the first active portion being used to form a channel region of the first transistor, and the fifth active portion being used to form a channel region of the fifth transistor; In the same pixel driving circuit group, two adjacent first active portions are connected in the same layer, and two adjacent fifth active portions are connected in the same layer.

19. The display panel according to any one of claims 1 to 16, wherein: The pixel driving circuit further includes: A first transistor, a first electrode connected to a first initial signal line, a second electrode connected to a gate of the driving transistor, and a gate connected to a first reset signal line; a fourth transistor, a first electrode connected to the data line, a second electrode connected to the first electrode of the driving transistor, and a gate connected to the first gate line; a fifth transistor, a first electrode connected to a power line, a second electrode connected to the first electrode of the driving transistor, and a gate connected to an enable signal line; a sixth transistor, wherein a first electrode is connected to the second electrode of the driving transistor, a second electrode is connected to the light emitting unit, and a gate is connected to the enable signal line; The seventh transistor has a first electrode connected to the second initial signal line, a second electrode connected to the second electrode of the sixth transistor, and a gate connected to the second reset signal line.

20. The display panel according to claim 19, wherein: The display panel further includes: an active layer, located on one side of the substrate, wherein at least a portion of the structure of the active layer is used to form channel regions of the driving transistor, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor; A first gate layer is located on a side of the active layer away from the base substrate, the first gate layer comprises a first conductive portion, a first reset signal line, a first gate line, an enable signal line, and a second reset signal line, and the orthographic projections of the first reset signal line, the first gate line, the enable signal line, and the second reset signal line on the base substrate extend along the first direction; wherein at least a portion of the structure of the first reset signal line is used to form the gate of the first transistor, at least a portion of the structure of the second reset signal line is used to form the gate of the seventh transistor, at least a portion of the structure of the first gate line is used to form the gates of the second transistor and the fourth transistor, at least a portion of the structure of the enable signal line is used to form the gates of the fifth transistor and the sixth transistor, and the first conductive portion is used to form the gate of the drive transistor; In the same pixel driving circuit, the orthographic projections of the first reset signal line, the first gate line, the enable signal line, and the second reset signal line on the base substrate are spaced apart in sequence along the second direction, and the orthographic projection of the first conductive portion on the base substrate is located between the orthographic projection of the first gate line on the base substrate and the orthographic projection of the enable signal line on the base substrate.

21. The display panel according to claim 1, wherein: The display panel further includes: A gating circuit is provided, wherein the gating circuit is connected to the output end of the source driver chip and a plurality of data lines, and is used for responding to signals on different gating signal lines respectively to connect the output end of the source driver chip and different data lines in a time-sharing manner.

22. A display device, wherein: The display device comprises the display panel according to any one of claims 1-21.

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