Fine-adjustable reference unit circuit of MRAM (Magnetic Random Access Memory) chip

Abstract

The invention provides a fine-tuning reference unit circuit of an MRAM (Magnetic Random Access Memory) chip. The fine-tuning reference unit circuit comprises an initial reference unit sub-circuit, a coarse tuning unit sub-circuit, a fine tuning unit sub-circuit and a fine tuning control sub-circuit, wherein the initial reference unit sub-circuit is composed of MTJs in a high resistance state RAP and a low resistance state RP, the coarse adjustment unit sub-circuit and the fine adjustment unit sub-circuit comprise a plurality of resistor units and NMOS used for control, the resistor unit of the coarse adjustment unit sub-circuit is composed of the MTJs in the RAP and the RP states, the resistor unit of the fine adjustment unit sub-circuit is composed of the MTJs in the RP states, and the NMOS used for control is composed of the MTJs in the RP states. The fine tuning control sub-circuit controls the grid electrodes of the NMOS tubes corresponding to all the resistor units. The circuit is suitable for the reference end of the MRAM sensing amplifier, is used for providing reference current, can carry out high-precision resistance fine tuning within a certain range, and is simple in circuit structure, small in number of used MOSFETs, small in occupied chip area, high in circuit stability, good in process compatibility, wide in fine tuning range and high in precision.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit design, and more particularly to a reference end circuit of a sensing amplifier in a magnetic random access memory (MRAM) chip reading circuit. Background Art

[0002] Magnetic Random Access Memory (MRAM) does not require standby power consumption and is usually called non-volatile memory. This memory uses a magnetic tunnel junction (MTJ) as a storage unit. When storing data, the MTJ has two resistance states: a high resistance state R AP and low resistance state R P , the high resistance state corresponds to the storage data "1", and the low resistance state corresponds to the storage data "0", R AP Represents the resistance of the MTJ in the antiparallel state (AP), R P Indicates the resistance of the MTJ in the parallel state (P).

[0003] The read operation in the MRAM chip is realized by combining the sense amplifier. First, a fixed voltage is applied to the storage cell and the reference cell. Due to the different resistance values ​​of the storage cell and the reference cell, different currents will be generated. The sense amplifier reads the generated current, compares the magnitude of the two currents, and outputs the logic value "0" and "1" according to the difference in magnitude, thereby realizing the reading of the information stored in the storage cell of the MRAM chip. Usually, the reference resistor R ref Fixed at (R AP +R P ) / 2, so that the sensing margin when the sense amplifier reads "1" and reads "0" is the same as much as possible to improve the reading and writing accuracy.

[0004] However, process fluctuations cause changes in the resistance of the MTJ, and the process deviation of the sensing amplifier itself will also cause the amplifier to have a certain offset voltage, affecting the size of the sensing margin, making the reading results prone to errors and resulting in a decrease in the reading accuracy. Summary of the invention

[0005] In view of the above background, the present invention proposes a fine-tunable reference unit circuit for a sense amplifier reference terminal in an MRAM chip reading circuit and capable of fine-tuning the reference terminal input current value according to the output result value of the sense amplifier, and the structural features thereof are:

[0006] The fine-tunable reference unit circuit is composed of an initial reference unit subcircuit, a coarse adjustment unit subcircuit for reducing the total resistance of the fine-tunable reference unit circuit by coarsely adjusting the resistance of the fine-tunable reference unit circuit downward, a fine adjustment unit subcircuit for increasing the total resistance of the fine-tunable reference unit circuit by finely adjusting the resistance of the fine-tunable reference unit circuit upward, and a fine adjustment control subcircuit for controlling the resistor units connected to the coarse adjustment unit subcircuit and the fine adjustment unit subcircuit according to the output result of the external sensing amplifier to fine-tune the total resistance of the fine-tunable reference unit circuit, thereby realizing the function of improving the reading accuracy of the external sensing amplifier. The fine-tuning control subcircuit is composed of four subcircuits; and the fine-tuning reference unit circuit outputs signals to the outside through the initial reference unit subcircuit; and the fine-tuning reference unit circuit receives external sensing amplifier signals through the fine-tuning control subcircuit for signal input;

[0007] The initial reference unit subcircuit is composed of two branches connected in parallel, and each branch has a high resistance state (R AP ) and a low resistance state (R P ) of a magnetic tunnel junction (MTJ); the initial resistance value of the initial reference unit sub-circuit is the low resistance state resistance value (R P ) and high resistance state resistance (R AP )’s average value;

[0008] The coarse adjustment unit subcircuit is composed of m mutually independent resistor units with different resistance values ​​and m NMOS tubes with the same performance and interconnected drain electrodes. The branches formed by the nth NMOS tube among the m mutually independent resistor units with the same performance and the nth resistor unit among the m mutually independent resistor units with different resistance values ​​are connected in series with the initial reference unit (n=1, 2, ...., m), and the resistance of the nth resistor unit among the m mutually independent resistor units with different resistance values ​​is 2^(n-2) times that of the initial reference unit (n=1, 2, ...., m);

[0009] The fine adjustment unit subcircuit is composed of k resistor units with different resistance values ​​connected in series in sequence and k NMOS tubes with the same performance and the source and drain of which are interconnected in sequence. The first resistor unit among the k resistor units with different resistance values ​​connected in series in sequence and the drain of the first NMOS among the k NMOS tubes with the same performance and the source and drain of which are interconnected in sequence are both connected to the initial reference unit subcircuit. The first resistor unit among the k resistor units with different resistance values ​​connected in series in sequence is an R P The MTJ of the state and the nth resistance unit is 2^(n-1) R PThe MTJs of the k states are connected in parallel (n=2, 3, ...., k), the source of the kth NMOS tube among the k NMOS tubes with the same performance and the source and drain are sequentially interconnected is grounded, and the nth NMOS tube among the k NMOS tubes with the same performance and the source and drain are sequentially interconnected is connected in parallel with the nth resistance unit among the k resistance units with different resistance values ​​and sequentially connected in series (n=1, 2, ...., k);

[0010] The fine-tuning control subcircuit is composed of a data storage area and a digital logic circuit, and has a signal input terminal connected to the output signal of an external sensing amplifier and a signal output terminal connected to the coarse adjustment unit subcircuit and the fine adjustment unit subcircuit; the fine-tuning control subcircuit controls the coarse adjustment unit subcircuit and the fine adjustment unit subcircuit according to the signal input from the external sensing amplifier, adjusts the overall resistance value of the fine-tunable reference unit circuit to a resistance value when the external sensing amplifier reaches the highest reading accuracy, and saves the control signal of the output terminal of the fine-tuning control subcircuit corresponding to the resistance value in the internal data storage area.

[0011] The following are additional explanations for the above content:

[0012] The total resistance of the fine-tunable reference unit circuit is the total resistance R of the initial reference unit subcircuit (hereinafter referred to as the initial reference unit), the fine adjustment unit subcircuit, and the coarse adjustment unit subcircuit. ref .

[0013] The fine-tuning unit subcircuit selects the resistance unit connected to the circuit by controlling the NMOS tube connected in parallel with the resistance unit. When the NMOS tube is turned on, the corresponding resistance unit is short-circuited, and the resistance unit is not connected to the circuit, and the overall resistance value of the fine-tuning reference unit circuit remains unchanged. When the NMOS tube is turned off, the corresponding resistance unit is connected to the circuit, and the overall resistance value of the fine-tuning reference unit circuit increases.

[0014] The first resistor unit in the fine-tuning unit subcircuit is 1 R P The nth resistor unit is 2^(n-1) R P The MTJs of the state are connected in parallel (n=2, ...., k), the resistance value of the nth resistance unit is half of the resistance value of the n-1 resistance unit (n=2, ...., k), and the resistance value of the fine-tuning unit sub-circuit can be between 0 and Range The precision of the reference unit circuit is increased from 0 to

[0015] The coarse adjustment unit sub-circuit selects the resistance unit connected to the circuit by controlling the NMOS tube connected in series with the resistance unit. When the NMOS tube is turned on, the corresponding resistance unit is connected to the circuit, and the overall resistance value of the fine-tuning reference unit circuit is reduced. When the NMOS tube is turned off, the corresponding resistance unit is not connected to the circuit, and the overall resistance value of the fine-tuning reference unit circuit remains unchanged.

[0016] The resistance unit in the coarse adjustment unit subcircuit is a series-parallel structure of multiple initial reference units, wherein the first resistance unit is a parallel structure of two initial reference units, and the resistance value is half of the resistance value of the initial reference unit, and the resistance value of the nth resistance unit is twice the resistance value of the n-1 resistance unit (n=2,....,m), and the resistance value of the nth resistance unit is 2^(n-2) times the initial reference unit (n=1,....,m), so that the total resistance value of the coarse adjustment unit subcircuit and the initial reference unit is to R ref0 The specific value depends on the connected resistance unit. By simply controlling the on / off of the first resistance unit and the second resistance reference unit, the total resistance of the coarse adjustment unit subcircuit and the initial reference unit can be reduced to R ref0 / 4, R ref0 / 3, R ref0 / 2.

[0017] The number of resistor units connected to the circuit in the fine adjustment unit subcircuit and the coarse adjustment unit subcircuit is controlled by the fine adjustment control subcircuit, so that the adjustable ranges of the fine adjustment unit subcircuit and the coarse adjustment unit subcircuit overlap each other, so as to achieve ref0 Large range and high precision fine adjustment on both sides to select the appropriate total resistance R ref .

[0018] Each block area of ​​the memory array may be provided with a separate fine-tunable reference unit circuit, so that the fine-tunable reference unit can fully reflect the resistance of the memory cells in the block area.

[0019] In the initial state, no resistor unit is connected to the fine adjustment unit subcircuit and the coarse adjustment unit subcircuit. At this time, the total resistance value R of the reference unit circuit can be fine-tuned. ref is the initial resistance R ref0 .

[0020] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0021] The fine-tunable reference unit circuit proposed by the present invention can be set at an initial resistance value R ref0 Left To the right In the range of The precision is fine-tuned, and all resistance units only use MTJs in AP and P states. The process compatibility is good, the number of MOSFETs used is small, the chip area is small, the fine-tuning range is wide, the adjustment accuracy is high, and the resistance units connected to the coarse adjustment unit sub-circuit and the fine adjustment unit sub-circuit are controlled by the fine-tuning control sub-circuit to solve the influence of the parasitic resistance in the circuit and the offset voltage of the sensing amplifier on the reading accuracy.

[0022] The fine-tunable reference unit circuit proposed in the present invention only uses MTJ to form a resistance unit. Among all the resistance units, MTJs in P state account for the majority. MTJs in P state are less affected by temperature changes, and the circuit stability is higher. The space occupied by using MTJs is smaller than that of using polysilicon resistors. With the optimization of MTJ size, the occupied space can be further reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The figure is a schematic diagram of the internal structure of the fine-tunable reference unit circuit of the MRAM chip of the present invention.

[0024] Figure 2 The first resistor unit of the MRAM chip of the present invention is 2R ref0 Schematic diagram of the coarse adjustment unit sub-circuit structure.

[0025] Figure 3 This is a schematic diagram of the MRAM chip reading circuit structure of the present invention. DETAILED DESCRIPTION

[0026] The present invention is described below in conjunction with specific embodiments.

[0027] In MRAM, the MTJ in the memory cell has a high resistance state R AP (storing data “1”) and low resistance state R P The MTJ has two states (storage data "0"), and the MTJ can maintain the original state after power failure. This property of the MTJ is used to store data information. The process of reading the storage cell data is to compare the storage cell and the reference cell resistance values. Different currents are generated by applying the same voltage. The sense amplifier determines the value stored in the storage cell according to the magnitude of the two currents. How to select a suitable reference cell resistance value and improve the reading reliability of MRAM has always been a problem to be solved. The present invention provides a fine-tunable reference cell circuit of an MRAM chip and a related reading circuit structure, which can fine-tune the reference cell resistance value according to the output result value of the sense amplifier to improve the reading reliability. The following is a description of the embodiment:

[0028] Embodiment 1 of the present invention provides a fine-tunable reference unit circuit, such as Figure 1As shown, the fine-tuning reference unit circuit includes four parts: an initial reference unit subcircuit 11 for providing an initial resistance value, a coarse-tuning unit subcircuit 12 for realizing downward adjustment of the resistance, a fine-tuning unit subcircuit 13 for realizing upward adjustment of the resistance, and a fine-tuning control subcircuit 14 for adjusting and controlling the coarse-tuning unit subcircuit 12 and the fine-tuning unit subcircuit 13.

[0029] The initial reference unit subcircuit 11 is composed of two pairs of AP and P state MTJs connected in series, wherein the magnetization direction arrows in the P state MTJs are in the same direction, and the magnetization direction arrows in the AP state MTJs are in opposite directions. The two pairs of MTJs are connected in parallel to form an initial resistance value R ref0 =(R AP +R P ) / 2, the initial resistance value can be selected at R AP and R P The middle position is convenient for subsequent fine-tuning.

[0030] The coarse adjustment unit subcircuit 12 controls the connected parallel resistance unit branch by controlling the on-off of the NMOS. When there are m resistance units, the total resistance of the coarse adjustment unit subcircuit 12 and the initial reference unit subcircuit 11 can be made within a range of to R ref0 The overall resistance value R of the reference unit circuit can be fine-tuned ref Decrease downward.

[0031] In the coarse adjustment unit subcircuit 12, the total resistance of the coarse adjustment unit subcircuit and the initial reference unit subcircuit can be reduced to R by simply controlling the on / off of the first resistance unit 121 and the second resistance unit 122. ref0 / 4, R ref0 / 3, R ref0 / 2, the number m of the resistor units in the coarse adjustment unit subcircuit 12 can also make the total resistance value of the coarse adjustment unit subcircuit 12 and the initial reference unit subcircuit 11 to R ref0 There are finer values ​​within the range. Usually, the number m of resistance units in the coarse adjustment unit sub-circuit 12 will not take a too large value. The larger the value of m, the more resistance units there are and the higher the adjustable accuracy. However, the actual adjustment range shows a phenomenon of diminishing marginal returns, and the circuit area occupied also increases accordingly. Finer adjustments can be completed by the fine adjustment unit sub-circuit 13. Therefore, in the actual implementation process, the coarse adjustment unit sub-circuit 12 needs to reasonably determine the value of the number m of resistance units based on actual conditions.

[0032] The fine-tuning unit subcircuit 13 controls the connected resistance unit by controlling the on-off of the NMOS. When there are k resistance units, the total resistance value is calculated based on the difference of the connected resistance units. The step size increases from 0 to To achieve fine-tuning operation, the more resistance units there are, the smaller the step size is, and the more accurate the fine-tuning is. When k resistance units are used, the resistance value has 2 k Combinations, covering from 0 to

[0033] The coarse adjustment unit sub-circuit 12 and the fine adjustment unit sub-circuit 13 are used in combination, so that the R ref0 The initial resistance value can be stepped both below and above the Fine-tuning for R ref0 For the fine adjustment below, the coarse adjustment unit subcircuit 12 is required to control the connected resistor unit so that the overall resistance value of the fine-tunable reference unit circuit decreases, and then the fine adjustment unit subcircuit 13 is used to control the connected resistor unit so that the overall resistance value of the fine-tunable reference unit circuit increases; for R ref0 The fine adjustment above only requires fine-tuning the unit sub-circuit 13 so that the overall reference unit resistance R ref Increase, and you can complete the R ref0 Fine-tuning above.

[0034] By controlling the fine adjustment unit subcircuit 13 and the coarse adjustment unit subcircuit 12, the adjustable ranges of the fine adjustment unit subcircuit 13 and the coarse adjustment unit subcircuit 12 overlap each other, so as to realize ref0 The high-precision fine-tuning on both sides greatly reduces the number of NMOS used, and can achieve high-precision fine-tuning in a large range while using less NMOS, which can reduce the R in the storage unit caused by the MTJ process. AP and R P The influence of resistance fluctuation on the reading result, select the appropriate R of the reference unit circuit that can be fine-tuned ref This improves the reading accuracy, reduces the influence of parasitic resistance in the circuit, and offsets the sense amplifier 33 ( Figure 3 The offset voltage is shown in Figure 1.

[0035] Figure 1 The first resistor unit 121 of the coarse adjustment unit subcircuit 12 is R ref0 / 2, the second resistance unit 122 is R ref0 The total resistance adjustment range of the coarse adjustment unit subcircuit 12 and the initial reference unit subcircuit 11 is to R ref0 , only the first resistance unit 121 and the second resistance unit 122 can be used to realize that the total resistance of the coarse adjustment unit subcircuit 12 and the initial reference unit subcircuit 11 becomes R ref0 / 4, R ref0 / 3, R ref0 / 2 adjustment.

[0036] like Figure 1All resistance units in the fine-tunable reference unit circuit shown can be implemented using MTJs. Compared with the solution using polysilicon resistors as resistors, the resistance units formed by MTJs occupy less space in the chip. When k=7 of the fine-tuning unit sub-circuit 13, the 7th resistance unit is composed of 64 MTJs in parallel. This resistance unit is the resistance unit that uses the most MTJs. When the diameter of an MTJ is 30nm and the thickness is 20nm, the two MTJs are spaced 10nm apart, and the total occupied area is approximately 310nm×310nm with a thickness of 20nm. A polysilicon resistor usually occupies an area of ​​approximately 10μm×10μm with a thickness of approximately 200nm. In comparison, the fine-tunable reference unit circuit using MTJs to form resistance units occupies less space, and as the size of the MTJ is optimized, the occupied space will be further reduced.

[0037] Embodiment 2 of the present invention provides a first resistor unit having a 2R ref0 The coarse adjustment unit subcircuit 22, such as Figure 2 As shown, the first resistor unit 221 in the coarse adjustment unit sub-circuit 22 is R ref0 / 2, a total of m resistance units, at this time the total resistance of the coarse adjustment unit sub-circuit 22 and the initial reference unit sub-circuit 21 can be to R ref0 The value is within the range, and the leftmost side of the range is close to R ref0 / 2, and Figure 1 The coarse adjustment unit sub-circuit 12 in the embodiment of the present invention achieves the following result by only adding the resistor unit 121 and the resistor unit 122. to R ref0 The adjustment range is Figure 2 The coarse adjustment unit subcircuit 22 in is larger.

[0038] Embodiment 3 of the present invention provides an MRAM read circuit structure using a fine-tunable reference unit circuit, such as Figure 3 As shown, the circuit structure includes three parts: a block storage matrix 31, a fine-tunable reference unit circuit array 32, and a sense amplifier array 33.

[0039] For ease of explanation, in this embodiment, the first fine-tunable reference unit circuit 321 (including the internal fine-tunable reference unit 3211 and the fine-tuning control subcircuit 3212) in the fine-tunable reference unit circuit array 32 and the first sense amplifier 331 in the sense amplifier array 33 are described in detail as examples. The fine-tunable reference unit circuit 321 and the sense amplifier 331 in the description will not be limited to the partition 1 of the corresponding block storage matrix 31. It should be clearly pointed out that these descriptions are also applicable to all fine-tunable reference unit circuits in the fine-tunable reference unit circuit array 32 and all sense amplifiers in the sense amplifier array 33.

[0040] The fine-tunable reference unit circuit array 32 includes a plurality of fine-tunable reference unit circuits 321. The fine-tunable reference unit circuit 321 includes a fine-tunable reference unit 3211 and a fine-tuning control subcircuit 3212. The fine-tunable reference unit 3211 is composed of Figure 1 The initial reference unit subcircuit 11, the coarse adjustment unit subcircuit 12 and the fine adjustment unit subcircuit 13 are composed of each fine-tunable reference unit circuit 321 corresponding to a block area in the block storage matrix 31.

[0041] The sense amplifier 331 is a current-type sense amplifier that compares the data current I transmitted from the data unit. data and the reference current I transmitted from the trimmable reference unit circuit 321 ref , determine the value of the data unit, each sense amplifier 331 in the sense amplifier array 33 outputs the data of different partitions in the block storage matrix 31, and the output data is DQ <1> To DQ <n>, N is the bit width of the MRAM chip.

[0042] The sense amplifier 331 in the sense amplifier array 33 performs sense amplification on the memory cell and the adjustable reference cell circuit 321, and compares the data current I data and the reference current I of the fine-tunable reference unit circuit 321 ref , when I data Greater than I ref When the storage unit is judged to store data "0", the DQ terminal of the sense amplifier 331 outputs logic "0". data Less than I ref When the storage unit stores data "1", the DQ terminal of the sense amplifier array 33 outputs logic "1", thereby realizing the read operation.

[0043] The resistance values ​​of the MTJs storing data "0" and data "1" in the block storage matrix 31 are easily affected by the process and fluctuate, and the resistance values ​​of some MTJs in AP state and some MTJs in P state are close to R ref0 By adjusting the overall resistance of the corresponding fine-tunable reference unit circuit 321, the read errors of such storage cells can be reduced during reading.

[0044] The fine-tuning control sub-circuit 3212 writes all "0" and "1" to one of the partitions of the storage array 31 through the control circuit, and then reads the storage array through the sensing amplifier circuit 331. The fine-tuning control sub-circuit 3212 controls the fine-tunable reference unit 3211 in the fine-tunable reference unit circuit 321. During the fine-tuning process, the number of errors in reading "0" and reading "1" is counted, so that the fine-tunable reference unit circuit 321 is fine-tuned to the number of "0" and "1" errors in reading the corresponding partition data is 0 or the minimum. The output control signals of the SP and SS signals corresponding to the optimal resistance value of the fine-tunable reference unit 3211 are stored in the internal storage space of the fine-tuning control sub-circuit 3212, and the SP is stored in the internal storage space of the fine-tuning control sub-circuit 3212. 1 -SP N and SS 1 -SS N The signal is used to separately set the fine-tunable reference unit circuit 321 corresponding to each block area of ​​the storage array, so that the corresponding fine-tunable reference unit circuit 321 can fully reflect the resistance of the storage unit in the block area, thereby improving the overall reading accuracy.

[0045] The following is a feasible fine-tuning scheme implementation example: the first step is to write "0" to all the storage cells in one partition of the storage matrix 31, fine-tune the resistance of the fine-tunable reference cell circuit 321 corresponding to the partition, and read all the storage cells in the partition through the sensing amplifier circuit 321 until the fine-tuning causes an error when reading the storage cell, and determine the maximum reference cell resistance when the error occurs. At this time, the resistance of the reference cell is the minimum reference value. The second step is to write "1" to all the storage cells in the storage matrix, fine-tune the reference cell resistance, and read all the storage cells at the same time until the fine-tuning causes an error when reading the storage cell, and determine the minimum reference cell resistance when the error occurs. At this time, the resistance of the reference cell is the maximum reference value. All values ​​between the minimum reference value and the maximum reference value can correctly read all the storage cells. The third step is to select the median of the minimum reference value and the maximum reference value, and determine it as the optimal resistance of the reference cell after fine-tuning.

[0046] From the above fine-tuning process, we can see that Figure 1 The fine-tuning unit subcircuit 13 in the circuit uses n resistance units for fine-tuning during the upward fine-tuning process. Each resistance unit from the 2nd to the nth bit is half of the resistance of the previous bit, which is equivalent to an n-bit binary number. This binary number method provides a simple and effective way to perform fine-tuning. Compared with the equal-step fine-tuning method, this method uses fewer resistance units to achieve higher fine-tuning accuracy and more adjustment combinations, while reducing the number of NMOS used and the area within the chip.

[0047] The following is another parameter design scheme embodiment, the scheme is as follows: MRAM storage array 31 ( Figure 3 The bit width N is 16; refer to Figure 1 , the number of resistor units in the coarse adjustment unit subcircuit 12 is m=4, and the number of resistor units in the fine adjustment unit subcircuit 13 is k=7; R AP =5KΩ, R P =2KΩ; initial reference unit subcircuit 11 resistance R ref0 =(R AP +R P ) / 2=3.5KΩ; the fine adjustment unit subcircuit 13 has an upward adjustment range of 0-3.97KΩ, and a minimum adjustment step of 31.25Ω, which is the same as R ref0 The ratio is 0.89%, and the adjustment has 128 combinations; the coarse adjustment unit subcircuit 12 has a downward adjustment range of 0-2.76KΩ, and the adjustment has 16 combinations; the coarse adjustment unit subcircuit 12 and the fine adjustment unit subcircuit 13 are combined, and the adjustment has 2048 combinations, which can be realized in R ref0 Fine trimming from 2.76KΩ on the left to 3.97KΩ on the right (-78.9% to +113%).

[0048] According to the actual MTJ R AP and R P According to the resistance value and distribution, the corresponding circuit parameter scheme can be set to determine the appropriate fine-tuning accuracy and appropriate fine-tuning range, save circuit area, save power consumption, and adapt to various practical application scenarios.

[0049] The MRAM fine-tunable reference unit circuit provided in the embodiment of the present invention has a simple circuit structure, uses a small number of MOSFETs, occupies a small chip area, has good process compatibility, good temperature stability, a wide fine-tuning range, and high precision, and can solve the influence of the parasitic resistance in the circuit and the offset voltage of the sense amplifier on the reading accuracy.

[0050] The above-mentioned embodiments only express certain implementation methods of the present invention, and the description is relatively specific, but it cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be based on the attached claims.< / n>

Claims

1. A fine-tunable reference unit circuit for a sense amplifier reference terminal in an MRAM chip reading circuit and capable of fine-tuning the reference terminal input current value according to the output result value of the sense amplifier, wherein the structural features are: The fine-tunable reference unit circuit is composed of an initial reference unit subcircuit, a coarse-tuning unit subcircuit for reducing the total resistance of the fine-tunable reference unit circuit by coarsely adjusting the resistance of the fine-tunable reference unit circuit downward, a fine-tuning unit subcircuit for increasing the total resistance of the fine-tunable reference unit circuit by fine-tuning the resistance of the fine-tunable reference unit circuit upward, and a fine-tuning control subcircuit for controlling the resistor units connected to the coarse-tuning unit subcircuit and the fine-tuning unit subcircuit according to the output result of the external sensing amplifier to fine-tune the total resistance of the fine-tunable reference unit circuit, thereby improving the reading accuracy of the external sensing amplifier. The fine-tuning reference unit circuit outputs signals to the outside through the initial reference unit subcircuit; and the fine-tuning reference unit circuit receives external sensing amplifier signals through the fine-tuning control subcircuit for signal input; The initial reference unit subcircuit is composed of two branches connected in parallel, and each branch has a high resistance state (R AP ) and a low resistance state (R P ) of a magnetic tunnel junction (MTJ); the initial resistance value of the initial reference unit sub-circuit is the low resistance state resistance value (R P ) and high resistance state resistance (R AP )’s average value; The coarse adjustment unit subcircuit is composed of m mutually independent resistor units with different resistance values ​​and m NMOS tubes with the same performance and interconnected drain electrodes. The branches formed by the nth NMOS tube among the m mutually independent resistor units with the same performance and the nth resistor unit among the m mutually independent resistor units with different resistance values ​​are connected in series with the initial reference unit (n=1, 2, ...., m), and the resistance of the nth resistor unit among the m mutually independent resistor units with different resistance values ​​is 2^(n-2) times that of the initial reference unit (n=1, 2, ...., m); The fine adjustment unit subcircuit is composed of k resistor units with different resistance values ​​connected in series in sequence and k NMOS tubes with the same performance and the source and drain of which are interconnected in sequence. The first resistor unit among the k resistor units with different resistance values ​​connected in series in sequence and the drain of the first NMOS among the k NMOS tubes with the same performance and the source and drain of which are interconnected in sequence are both connected to the initial reference unit subcircuit. The first resistor unit among the k resistor units with different resistance values ​​connected in series in sequence is an R P The MTJ of the state and the nth resistance unit is 2^(n-1) R P The MTJs of the k states are connected in parallel (n=2, 3, ...., k), the source of the kth NMOS tube among the k NMOS tubes with the same performance and the source and drain are sequentially interconnected is grounded, and the nth NMOS tube among the k NMOS tubes with the same performance and the source and drain are sequentially interconnected is connected in parallel with the nth resistance unit among the k resistance units with different resistance values ​​and sequentially connected in series (n=1, 2, ...., k); The fine-tuning control subcircuit is composed of a data storage area and a digital logic circuit, and has a signal input terminal connected to the output signal of an external sensing amplifier and a signal output terminal connected to the coarse adjustment unit subcircuit and the fine adjustment unit subcircuit; the fine-tuning control subcircuit controls the coarse adjustment unit subcircuit and the fine adjustment unit subcircuit according to the signal input from the external sensing amplifier, adjusts the overall resistance value of the fine-tunable reference unit circuit to a resistance value when the external sensing amplifier reaches the highest reading accuracy, and saves the control signal of the output terminal of the fine-tuning control subcircuit corresponding to the resistance value in the internal data storage area.

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