Wafer cutting method
By forming a mask layer and a guide layer on the wafer surface, combined with plasma and wet etching technology, efficient SiC wafer cutting is achieved, solving the problems of high cost and performance impact of traditional cutting solutions.
Patent Information
- Application Number
- CN202311657180.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-05
- Publication Date
- 2025-06-06
AI Technical Summary
Traditional semiconductor cutting solutions can easily lead to high cutting costs, and debris and microcracks generated during diamond wire saw cutting will affect device performance.
A mask layer is formed on the first surface of the wafer to be cut, and a guide layer is formed on the second surface, and a plasma etching is etched to a predetermined depth, combined with wet etching until the through-wafer is achieved, efficient wafer cutting is achieved.
Reduces cutting costs, reduces cutting losses, improves device performance, and simplifies process flow.
Smart Images
Figure CN120109091A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a wafer cutting method. Background Art
[0002] As the third generation wide bandgap semiconductor material, semiconductor materials such as SiC (silicon carbide) have a series of advantages such as large bandgap width, high thermal conductivity, large breakdown electric field strength, large saturated electron drift velocity and the ability to withstand extreme environmental changes. Currently, they are mainly used in the preparation of electronic devices. Field effect transistor is a typical electronic device that can realize signal amplification, switching and other functions, and is widely used in microwave communications, power grids and other fields.
[0003] After completing the front and back processes such as groove etching, ion implantation, electrode interconnection, and dielectric layer patterning, the devices made of SiC wafers must be cut into discrete chips (also called wafer units) before they can be used for subsequent connection and packaging. Usually, a diamond wire saw is used to perform the segmentation step along the cutting path on the wafer. However, due to the high hardness of SiC materials, the Mohs hardness among non-artificial materials is second only to diamond, requiring the diamond wire saw to be at least greater than a lower size limit. Secondly, in addition to the wafer width removed by the diamond wire saw itself, the debris and microcracks generated near the cutting path during mechanical cutting will have a serious impact on the performance of the device. In order to avoid this effect, the cutting path width needs to leave a certain margin on the basis of the lower limit of the diamond wire saw size. Usually, the cutting path spacing of the wafer unit needs to be at least 70 to 100um, combining these two. The area of SiC wafer units is sometimes as small as hundreds of microns, and the cutting loss caused by diamond wire cutting will seriously affect production efficiency.
[0004] Some solutions use plasma cutting solutions to cut semiconductors such as SiC. Such cutting solutions often require the installation of auxiliary components such as supports in the process chamber, which easily leads to high cutting costs. Summary of the invention
[0005] In view of this, the present application provides a wafer cutting method to solve the problem that traditional semiconductor cutting solutions easily lead to high cutting costs.
[0006] The present application provides a wafer cutting method, comprising:
[0007] forming a mask layer having a cutting line pattern on a first surface of the wafer to be cut;
[0008] forming a guide layer on a second surface of the wafer to be cut, the second surface being opposite to the first surface, the guide layer being used to guide etching of the wafer to be cut in a direction perpendicular to the first surface;
[0009] Performing a first etching on the first surface of the wafer to be cut exposed by the mask layer to a predetermined depth, wherein the predetermined depth is less than the thickness of the wafer to be cut;
[0010] The guide layer is used to perform a second etching on the remaining thickness of the wafer to be cut until the wafer to be cut is penetrated.
[0011] Optionally, the first etching is plasma etching, and the difference between the thickness of the wafer to be cut and the predetermined depth is in the range of 10 to 100 μm.
[0012] Optionally, in the plasma etching step, the temperature range of the wafer stage includes -10 to 450°C.
[0013] Optionally, the second etching is anisotropic wet etching, and an etching rate of the second etching in a direction perpendicular to the first surface is greater than an etching rate in a direction parallel to the first surface.
[0014] Optionally, the mask layer includes at least one sub-mask layer, and at least one of the at least one sub-mask layer includes the same material as the guide layer.
[0015] Optionally, the guide layer is used to perform a second etching on the remaining thickness of the wafer to be cut until the wafer to be cut is penetrated, including: immersing the remaining thickness of the wafer to be cut in a chemical etching solution; irradiating the first surface of the wafer to be cut with light of a predetermined wavelength, and / or connecting an energy source between the mask layer and the guide layer.
[0016] Optionally, the predetermined wavelength range includes 180-400nm, and the power range of the ultraviolet lamp includes 1000-6000W.
[0017] Optionally, the chemical etching solution comprises a mixed solution of hydrogen peroxide solution, hydrofluoric acid solution and water; the volume ratio of the hydrogen peroxide solution, the hydrofluoric acid solution and the water is in the range of (13-29):(1-11):(2-8).
[0018] Optionally, after using the guide layer to perform a second etching on the remaining thickness of the wafer to be cut until the wafer to be cut is penetrated, the wafer cutting method further includes: removing the mask layer and the guide layer.
[0019] Optionally, the material of the guide layer includes at least one of Pt, Au and Pd.
[0020] The above-mentioned wafer cutting method of the present application forms a mask layer on the first surface of the wafer to be cut to provide a mask function in each etching process. In the first etching process, only etching is performed to a predetermined depth, and the remaining thickness is not cut, so that the wafer to be cut 101 with this partial thickness can support the entire wafer to be cut in the first etching process. In this way, there is no need to rely on other frame structures or supporting workpieces to support the wafer to be cut, which can reduce the cost in the first etching process. A guide layer is formed on the second surface of the wafer to be cut to guide the etching direction in the second etching process. The mask layer on the first surface of the wafer to be cut can also be used to protect the wafer to be cut and improve the etching effect.
[0021] Furthermore, the second etching includes chemical etching such as wet etching, so that part of the mask layer can be directly removed by the chemical etching solution at this stage, without considering the removal of this part of the mask layer, which can simplify the corresponding process flow. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0023] Figure 1 A schematic diagram of a wafer cutting method according to an embodiment of the present application;
[0024] Figure 2a , Figure 2b and Figure 2c This is a schematic diagram of the structure obtained by the relevant steps in an embodiment of the present application;
[0025] Figure 3 Schematic diagram of a chemical etching environment according to an embodiment of the present application. DETAILED DESCRIPTION
[0026] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.
[0027] The first aspect of the present application provides a wafer cutting method, which can be used to cut SiC wafers with high hardness and thin thickness. Figure 1 As shown, the above-mentioned wafer cutting method includes steps S310 to S340.
[0028] S310, reference Figure 2a As shown, a mask layer 111 having a scribe line pattern 105 is formed on a first surface of a wafer 101 to be diced.
[0029] The first surface may be the front side of the wafer 101 to be cut, and the second surface opposite to the first surface may be the back side of the wafer 101 to be cut.
[0030] Optionally, the mask layer may include at least one sub-mask layer, and at least one of the at least one sub-mask layer includes the same material as the guide layer. Optionally, each sub-mask layer may provide a corresponding mask function in each etching process; for example, the mask layer 111 may include a first sub-mask layer 104 and a second sub-mask layer 103.
[0031] Optionally, the first sub-mask layer 104 may be formed by a PECVD deposition (plasma enhanced chemical vapor deposition) process, or may be formed by other deposition processes. The first sub-mask layer 104 may include an oxide layer such as a SiOx (silicon oxide) layer, or may include other dielectric material layers such as BPSG (boron phospho-silicate glass) or TEOS (tetraethyl silicate). Optionally, the thickness of the first sub-mask layer 104 may be between 4um and 10um.
[0032] Optionally, the width of the cutting line pattern 105 is between 1um and 100um. Preferably, the width of the cutting line pattern 105 is between 5um and 10um, so as to reduce the loss of the wafer 101 to be cut during the cutting process as much as possible.
[0033] S320, such as Figure 2a As shown, a guide layer 102 is formed on the second surface of the wafer to be cut 101, the second surface is opposite to the first surface, and the guide layer is used to guide the etching direction of the wafer to be cut to be perpendicular to the first surface. The guide layer 102 is used to make the etching rate along the cutting pattern 105 direction (i.e., the direction perpendicular to the first surface) greater than the etching rate in other directions during the subsequent second etching process.
[0034] S330, reference Figure 2b As shown, the first surface of the wafer 101 to be cut exposed by the mask layer 111 is first etched to a predetermined depth, and the predetermined depth is less than the thickness of the wafer to be cut. For example, the difference between the thickness of the wafer to be cut and the predetermined depth can be R, so that a portion of the wafer 101 to be cut and the guide layer 102 can be reserved to provide a support function together during the first etching process. The first sub-mask layer 104 can provide a masking function during the first etching process, and the formation process and material characteristics of the first sub-mask layer 104 can be determined according to the first etching.
[0035] Specifically, the first etching is plasma etching. In the above step S330, if the thickness of the wafer 101 to be cut is H, the predetermined depth of the plasma cutting the wafer 101 to be cut along each cutting path pattern 105 is (HR), and here the bottom of the wafer 101 to be cut is not cut during the first etching process, but the remaining thickness R is not cut, so that the wafer 101 to be cut with the thickness R can support the entire wafer 101 to be cut during the first etching process, so that there is no need to rely on other frame structures or support workpieces to support the wafer 101 to be cut, which can reduce the cost during the first etching process.
[0036] Optionally, after the first etching, the range of the remaining thickness R of the wafer to be cut includes 10um to 100um, for example, R can be 10um, 20um, 80um or 100um. Preferably, the range of the value of the remaining thickness R includes 30um to 80um, for example, R can be 30um, 40um, 60um or 70um, so as to ensure the self-supporting ability of the wafer to be cut with the remaining thickness R on the basis of etching the wafer to be cut 101 as much as possible during the first etching process, so that the wafer to be cut with the remaining thickness R can be combined with the wafer to be cut 101 to effectively support itself.
[0037] S340, reference Figure 2c As shown, the guide layer 102 is used to perform a second etching on the remaining thickness of the wafer 101 to be cut until the wafer 101 to be cut is penetrated, so that the wafer 101 to be etched is cut into multiple parts. The second sub-mask layer 103 can provide a masking function in the second etching process, and the formation process and material characteristics of the second sub-mask layer 103 can be determined according to the second etching.
[0038] Optionally, the second etching is anisotropic wet etching, and the etching rate of the second etching in the direction perpendicular to the first surface is greater than the etching rate in the direction parallel to the first surface. In the etching process, the guide layer 102 can affect the charge distribution in the chemical etching solution, and the chemical etching is adjusted by adjusting the charge to a certain position or a certain direction, so that the etching rate along the cutting path pattern 105 in the second etching process is greater than the etching rate in other directions. In addition, the second etching adopts chemical etching, so that part of the mask layer 111 (such as the first sub-mask layer 104, etc.) can be directly removed by the chemical etching solution at this stage, and there is no need to consider the removal of this part of the mask layer 111, which can simplify the corresponding process flow.
[0039] In the above-mentioned wafer cutting method, a mask layer 111 is formed on the first surface of the wafer 101 to be cut to provide a mask function in each etching process. In the first etching process, only a predetermined depth is etched, and the remaining thickness R is not cut, so that the wafer 101 to be cut with a thickness R can support the entire wafer 101 to be cut in the first etching process. In this way, there is no need to rely on other frame structures or supporting workpieces to support the wafer 101 to be cut, which can reduce the cost in the first etching process. A guide layer 102 is formed on the second surface of the wafer 101 to be cut to guide the etching direction in the second etching process. The mask layer 111 on the first surface of the wafer 101 to be cut can also be combined with the mask layer 111 on the first surface of the wafer 101 to be cut to protect the wafer 101 to be cut and improve the etching effect.
[0040] In one embodiment, the first etching to a predetermined depth is performed on the front side of the wafer 101 to be cut exposed by the mask layer 111, including: using plasma to first etch the front side of the wafer 101 to be cut exposed by the mask layer to a predetermined depth, so that the unetched portion of the back side of the wafer 101 to be cut and the guide layer 102 can self-support the wafer 101 to be cut. In this way, there is no need to set auxiliary elements such as supports in the plasma process chamber, which can simplify the structure of the corresponding process chamber and reduce the corresponding plasma etching cost.
[0041] Optionally, in the plasma etching process, the temperature range of the wafer stage can be -10°C to 450°C. Specifically, it can include 150°C to 300°C. In this temperature range, the plasma etching process has a more suitable etching rate, which can improve the selectivity of SiC to the mask and reduce the thickness of the required mask layer. Preferably, the temperature range of the wafer stage is 250°C to 280°C. For example, in the plasma etching process, the temperature of the wafer stage can be 250°C, 260°C, 270°C or 280°C, etc.
[0042] In one example, the plasma etching process may include an inductively coupled plasma (ICP) etching process, a capacitively coupled plasma (CCP) etching process, or an electromagnet high frequency plasma (ECR) etching process.
[0043] Specifically, referring to Table 1, when inductively coupled plasma etching is used, the etching gas includes at least one of the following gases: Ar (argon), He (helium), O 2 (oxygen), N 2 (nitrogen), SF 6 (sulfur hexafluoride), NF 3 (nitrogen trifluoride), SiF 4 (Silicon tetrafluoride), BCl 3 (boron trichloride), Cl 2 (Chlorine), SiCl 4(tetrachlorosilane), CF 4 (carbon tetrafluoride), CHF 3 (Trifluoromethane) and C 4 F 8 (octafluorocyclobutane); preferably, the etching gas includes at least one of the following gases: Ar, O 2 , SF 6 and BCl 3 . The coil power includes 100W to 5000W; preferably, the coil power includes 1500W to 3500W. The electrode plate power includes 100W to 1500W; preferably, the electrode plate power includes 450W to 600W. The pressure in the process chamber includes 3mT to 150mT; preferably, the pressure in the process chamber includes 9mT to 98mT. The wafer stage temperature includes -10℃ to 450℃; preferably, the wafer stage temperature includes 150℃ to 300℃.
[0044] Table 1 Inductively coupled plasma etching process conditions
[0045]
[0046] Specifically, as shown in Table 2, when capacitively coupled plasma etching is used, the etching gas includes at least one of the following gases: Ar, He, O 2 、N 2 , SF 6 NF 3 、SiF 4 , BCl 3 , Cl 2 、SiCl 4 CF 4 , CHF 3 and C 4 F 8 Preferably, the etching gas includes at least one of the following gases: Ar, O 2 , SF 6 and BCl 3 The power of the electrode plate is 100W to 5000W; preferably, the power of the electrode plate is 1000W to 2500W. The pressure in the process chamber is 30mT to 800mT; preferably, the power of the electrode plate is 100mT to 400mT. The temperature of the wafer stage is -10°C to 450°C; preferably, the temperature of the wafer stage is 150°C to 300°C.
[0047] Table 2 Capacitively coupled plasma etching process conditions
[0048]
[0049] In one embodiment, the mask layer 111 includes at least one sub-mask layer, and at least one of the at least one sub-mask layer includes the same material as the guide layer 102. For example, when the first surface is the front surface, the bottom sub-mask layer is the same material as the guide layer 102, so that the sub-mask layer and the guide layer 102 can adjust the charge distribution in the chemical etching solution during the chemical etching process, thereby adjusting the etching rate in a specific direction during the chemical etching process. For example, when the mask layer includes the first sub-mask layer 104 and the second sub-mask layer 103, the second sub-mask layer 103 can provide a masking function during the second etching process; the second sub-mask layer 103 can also adjust the charge distribution in the chemical etching solution together with the guide layer 102 to adjust the etching rate in a specific direction during the chemical etching process; the second sub-mask layer 103 and the guide layer 102 can be formed of the same material, for example, both are metal layers or both are conductive layers, so as to respectively gather charges on the front and back of the wafer to be cut, so that the etching rate in the direction perpendicular to the surface of the guide layer 102 is relatively high.
[0050] Optionally, the material of the guide layer 102 includes at least one of Pt (platinum), Au (gold) and Pd (palladium), and correspondingly, the material of the corresponding sub-mask layer in the mask layer 111 of the second sub-mask layer 103 includes at least one of Pt (platinum), Au (gold) and Pd (palladium); both can be one of Pt, Au, Pd or a binary or ternary alloy thereof. The thickness of the guide layer 102 and the corresponding sub-mask layer can be between 10 and 500 nm, respectively, so as to adjust the charge distribution in the subsequent chemical etching process and effectively protect the wafer 101 to be cut.
[0051] In one example, the step of performing a second etching on the remaining thickness of the wafer 101 to be cut by using the guide layer 102 until the wafer 101 to be cut is penetrated includes:
[0052] The remaining thickness of the wafer 101 to be cut is immersed in a chemical etching solution for a second etching, so that the second sub-mask layer 103 and the guide layer 102 respectively gather the charges in the chemical etching solution, thereby increasing the etching rate in the direction perpendicular to the surface of the guide layer 102, and realizing anisotropic electrochemical etching; in this example, when the second etching penetrates the wafer 101 to be cut, the wafer 101 to be cut can be removed from the chemical etching solution to complete the second etching process.
[0053] Optionally, the chemical etching solution comprises a mixed solution of hydrogen peroxide solution, hydrofluoric acid solution and water (e.g., deionized water). Specifically, the volume ratio of hydrogen peroxide solution, hydrofluoric acid solution and deionized water is in the range of (13-29):(1-11):(2-8). Preferably, the volume ratio of hydrogen peroxide solution, hydrofluoric acid solution and deionized water is in the range of (18-27):(6-9):(3-6) to ensure stability during chemical etching.
[0054] In one example, after immersing the remaining thickness of the wafer 101 to be cut into a chemical etching solution, the use of the guide layer 102 to perform a second etching on the remaining thickness of the wafer 101 to be cut until the wafer 101 to be cut is penetrated also includes at least one of the following items: using ultraviolet light to irradiate the front side of the wafer 101 to be cut to increase the chemical etching rate in the direction of ultraviolet light irradiation; connecting an energy source between the second sub-mask layer 103 and the guide layer 102 to increase the charge accumulation ability of the second sub-mask layer 103 and the guide layer 102, thereby further increasing the chemical etching rate in the direction perpendicular to the surface of the guide layer 102.
[0055] Specifically, the ultraviolet light is emitted by an ultraviolet lamp or an ultraviolet laser. For example, the ultraviolet lamp can irradiate the first surface (front side) of the wafer 101 to be etched to emit ultraviolet light in the corresponding direction. The ultraviolet laser can emit ultraviolet light by surface scanning or line scanning, etc. Optionally, the power range of the ultraviolet lamp includes 1000W to 6000W. Preferably, the power range of the ultraviolet lamp includes 2000W to 5000W. For example, the power of the ultraviolet lamp can be 2000W, 3000W, 4000W or 5000W. Optionally, the wavelength range of the ultraviolet light is 180nm to 400nm. Preferably, the wavelength range of the ultraviolet light can be 193nm to 293nm, so that the rate of chemical etching along the direction of ultraviolet light irradiation is significantly higher than the rate of chemical etching in other directions.
[0056] Specifically, the energy source may include a DC power supply, the positive electrode of which may be connected to the second sub-mask layer 103 , and the negative electrode of which may be connected to the guide layer 102 , so as to enhance the charge gathering capabilities of the second sub-mask layer 103 and the guide layer 102 , respectively.
[0057] Optionally, after the guide layer 102 is used to perform a second etching on the remaining thickness of the wafer 101 to be cut until the wafer 101 to be cut is penetrated, the wafer cutting method further includes: removing the second sub-mask layer 103 and the guide layer 102 to obtain discrete partial wafer units. Optionally, the second sub-mask layer 103 and the guide layer 102 can be removed by laser ablation or other methods.
[0058] In one example, reference Figure 3 As shown, the chemical etching process is described by taking the ultraviolet lamp as an example. The semiconductor structure 202 after the first etching (for example, a structure including the wafer 101 to be etched, the second sub-mask layer 103 and the guide layer 102) is sent to the container 201 where the chemical etching occurs. In the container 201, the support structure 203 is used to support the semiconductor structure 202. The chemical etching solution 204 includes a mixed solution of hydrogen peroxide stock solution, hydrofluoric acid stock solution and deionized water. The ultraviolet lamp 205 is arranged above the container 201 to irradiate the front of the semiconductor structure 202. In the chemical etching process, the photochemical wet etching occurring under the irradiation of the ultraviolet light 205 is not isotropic, but anisotropic. The rate in the direction perpendicular to the front of the semiconductor structure 202 (i.e., the longitudinal direction) will be faster, reaching 3 to 4. When R is etched in the longitudinal direction, the size etched on both sides in the lateral direction is about R / 3. During the chemical cutting process, each surface of the wafer 101 to be etched is covered with a metal layer for protection, and the R / 3 etched on the lateral sides is located in the substrate layer of the wafer 101 to be etched (rather than the device structure layer located on the surface of the wafer 101 to be etched), so the impact on the device is very small. It can be seen that in the above-mentioned chemical etching process, on the basis of effectively cutting the wafer 101 to be etched, it is also possible to avoid affecting other structures of the wafer 101 to be etched.
[0059] In the above wafer cutting method, a mask layer 111 is formed on the first surface of the wafer 101 to be cut to provide a mask function in each etching process. In the first etching process, only a predetermined depth is etched, and the remaining thickness R is not cut, so that the wafer 101 to be cut with a thickness R can support the entire wafer 101 to be cut in the first etching process. In this way, there is no need to rely on other frame structures or support workpieces to support the wafer 101 to be cut, which can reduce the cost in the first etching process. A guide layer 102 is formed on the second surface of the wafer 101 to be cut to guide the etching direction in the second etching process, and the mask layer 111 on the first surface of the wafer 101 to be cut can also be combined to protect the wafer 101 to be cut, thereby improving the etching effect. The second etching includes chemical etching such as wet etching, which can make part of the mask layer 111 directly removed by the chemical etching solution at this stage, without considering the removal of this part of the mask layer 111, and can simplify the corresponding process flow.
[0060] The above is a detailed introduction to a wafer cutting method provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. It should be noted that in the present application, the descriptions of various embodiments have different emphases. For parts that are not described or recorded in detail in a particular embodiment, please refer to the relevant descriptions of other embodiments.
[0061] Although the present application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on reading and understanding of this specification and the accompanying drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (e.g., it is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the functions in the exemplary implementation of this specification shown herein.
[0062] That is, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.
[0063] In addition, although the terms first, second, etc. may be used to describe various information in this article, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. The terms "first" and "second" should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0064] In this application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or more advantageous than other embodiments. In order to enable any technician in the field to implement and use the present application, the present application provides the above description. In the above description, various details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.
Claims
1. A wafer cutting method, It is characterized in that include forming a mask layer having a cutting line pattern on a first surface of the wafer to be cut; forming a guide layer on a second surface of the wafer to be cut, the second surface being opposite to the first surface, the guide layer being used to guide etching of the wafer to be cut in a direction perpendicular to the first surface; Performing a first etching on the first surface of the wafer to be cut exposed by the mask layer to a predetermined depth, wherein the predetermined depth is less than the thickness of the wafer to be cut; The guide layer is used to perform a second etching on the remaining thickness of the wafer to be cut until the wafer to be cut is penetrated.
2. The wafer cutting method according to claim 1, It is characterized in that The first etching is plasma etching, and the difference between the thickness of the wafer to be cut and the predetermined depth is in the range of 10 to 100 μm.
3. The wafer cutting method according to claim 2, It is characterized in that In the plasma etching step, the temperature of the wafer stage ranges from -10 to 450°C.
4. The wafer cutting method according to any one of claims 1 to 3, wherein the second etching is anisotropic wet etching, and an etching rate of the second etching in a direction perpendicular to the first surface is greater than an etching rate in a direction parallel to the first surface. 5 . The wafer cutting method according to claim 4 , wherein the mask layer comprises at least one sub-mask layer, and at least one of the at least one sub-mask layer comprises the same material as the guide layer.
6. The wafer cutting method according to claim 5, It is characterized in that The method of using the guide layer to perform a second etching on the remaining thickness of the wafer to be cut until the wafer to be cut is penetrated includes: Immersing the remaining thickness of the wafer to be cut into a chemical etching solution; The first surface of the wafer to be cut is irradiated with light of a predetermined wavelength, and / or an energy source is connected between the mask layer and the guide layer.
7. The wafer cutting method according to claim 6, It is characterized in that The predetermined wavelength range includes 180-400nm, and the power range of the ultraviolet lamp includes 1000-6000W.
8. The wafer cutting method according to claim 6, It is characterized in that The chemical etching solution comprises a mixed solution of hydrogen peroxide solution, hydrofluoric acid solution and water; the volume ratio of the hydrogen peroxide solution, the hydrofluoric acid solution and the water is in the range of (13-29):(1-11):(2-8).
9. The wafer cutting method according to claim 6, It is characterized in that After using the guide layer to perform a second etching on the remaining thickness of the wafer to be cut until the wafer to be cut is penetrated, the wafer cutting method further includes: The mask layer and the guide layer are removed.
10. The wafer cutting method according to claim 1, It is characterized in that The material of the guide layer includes at least one of Pt, Au and Pd.