Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method of manufacturing a semiconductor package are provided, in which a height and a two-dimensional area of the semiconductor package may be reduced. The semiconductor package includes: a package substrate; a chip stacking structure including at least two semiconductor chips aligned with each other in a vertical direction and stacked on the package substrate, each of the at least two semiconductor chips including a chip pad exposed at a side surface of the semiconductor chip; an anisotropic conductive film (ACF) covering a side surface of the chip stack structure; and a conductive pattern film covering the ACF and including a conductive pattern connecting the chip pad to the base pad of the package substrate.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0173442 filed on December 4, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor package and a method of manufacturing the semiconductor package, and more particularly, to a semiconductor package having a chip stack structure and a method of manufacturing the semiconductor package having the chip stack structure. Background Art

[0003] With the rapid development of the electronics industry and the growth of user demand, electronic devices are becoming further miniaturized and becoming more multifunctional. As electronic devices become miniaturized and lightweight, semiconductor packages are becoming miniaturized and lightweight. In addition, semiconductor packages require high performance, large capacity, and high reliability. With the implementation of semiconductor packages with high performance and large capacity, the power consumption (power consumption) of semiconductor packages is increasing. Therefore, the importance of the structure of semiconductor packages corresponding to the size / performance of semiconductor packages and used to stably supply power to semiconductor packages is increasing. Summary of the invention

[0004] Some embodiments according to the present disclosure provide a semiconductor package and a method of manufacturing the same, wherein a height and a two-dimensional area of ​​the semiconductor package may be reduced.

[0005] The advantages are not limited to the foregoing, and other advantages will be clearly understood by those of ordinary skill in the art from the following description.

[0006] According to some embodiments, a semiconductor package includes: a packaging substrate; a chip stacking structure, including at least two semiconductor chips aligned with each other in a vertical direction and stacked on the packaging substrate, each of the at least two semiconductor chips including a chip pad exposed at a side surface of the semiconductor chip; an anisotropic conductive film (ACF) covering the side surface of the chip stacking structure; and a conductive pattern film covering the ACF and including a conductive pattern, the conductive pattern connecting the chip pad to a base pad of the packaging substrate.

[0007] According to some embodiments, a semiconductor package includes: a packaging substrate, including a substrate pad arranged on an upper surface of an outer portion of the packaging substrate; a chip stacking structure, including at least two semiconductor chips aligned with each other in a vertical direction and stacked on a central portion of the packaging substrate, each of the at least two semiconductor chips including a main body layer at a lower portion of the semiconductor chip, an active layer at an upper portion of the semiconductor chip, and a chip pad exposed at a side surface of the active layer; an anisotropic conductive film (ACF), covering the side surface of the chip stacking structure and the substrate pad on the packaging substrate, and including an adhesive resin and conductive particles; and a conductive pattern film, including a polymer film and a conductive pattern on the polymer film, and covering the ACF so that the chip pad is connected to the substrate pad through the conductive pattern.

[0008] According to some embodiments, a semiconductor package includes: a packaging substrate; a chip stacking structure, including at least two semiconductor chips aligned with each other in a vertical direction and stacked on the packaging substrate, each of the at least two semiconductor chips including a chip pad exposed at four side surfaces of the semiconductor chip; an anisotropic conductive film (ACF) covering a portion of an upper surface of the packaging substrate and four side surfaces of the chip stacking structure; a conductive pattern film covering the ACF and including a conductive pattern, the conductive pattern connecting the chip pad to a base pad of the packaging substrate; and a sealant covering the side surfaces and upper surface of the chip stacking structure on the packaging substrate.

[0009] According to some embodiments, a method for manufacturing a semiconductor package includes: preparing a plurality of semiconductor chips, each semiconductor chip including a main body layer at a lower portion of the semiconductor chip and an active layer at an upper portion of the semiconductor chip, and each semiconductor chip has a structure in which a chip pad is exposed at a side surface of the active layer; stacking a first semiconductor chip among the plurality of semiconductor chips on a packaging substrate by using an adhesive layer; stacking at least one second semiconductor chip among the plurality of semiconductor chips on the first semiconductor chip to be aligned in a vertical direction to form a chip stacking structure including the first semiconductor chip and the at least one second semiconductor chip; attaching an anisotropic conductive film (ACF) on at least one side surface of the chip stacking structure and on a portion of an upper surface of the packaging substrate; attaching a conductive pattern film on the ACF, the conductive pattern film including a conductive pattern; and forming a sealant covering the side surface and upper surface of the chip stacking structure on the packaging substrate, wherein the step of attaching the conductive pattern film on the ACF includes connecting the chip pad to a substrate pad of the packaging substrate by using the conductive pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1is a perspective view of a semiconductor package according to some embodiments.

[0012] Figure 2A is a cross-sectional view of a semiconductor package according to some embodiments.

[0013] Figure 2B and Figure 2C is a perspective view of a semiconductor package according to some embodiments.

[0014] Figure 2D is a plan view of a semiconductor package according to some embodiments.

[0015] Figure 3A is a perspective view of a semiconductor package according to some embodiments.

[0016] Figure 3B is a plan view of a semiconductor package according to some embodiments.

[0017] Figure 4A is a perspective view of a semiconductor package according to some embodiments.

[0018] Figure 4B is a plan view of a semiconductor package according to some embodiments.

[0019] Figure 5A and Figure 5B is a perspective view of a semiconductor package according to some embodiments.

[0020] FIG. 6A to FIG. 6E is a perspective view illustrating a process of manufacturing a semiconductor package according to some embodiments.

[0021] Fig. 7A and Figure 7B is a plan view illustrating a process of attaching a conductive pattern film according to some embodiments.

[0022] FIG. 8A to FIG. 8H is a cross-sectional view illustrating a process of preparing a semiconductor chip according to some embodiments.

[0023] 9A to 9C is a diagram illustrating a process of forming oxide bonding in a process of stacking semiconductor chips according to some embodiments. DETAILED DESCRIPTION

[0024] Hereinafter, examples will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals denote the same elements, and their repeated descriptions are omitted.

[0025] Figure 1 is a perspective view of a semiconductor package according to some embodiments, and FIG. 2A to FIG. 2D They are Figure 1 sectional views, perspective views, and plan views of a semiconductor package. Figure 2A yes Figure 1 A cross-sectional view of a semiconductor package taken along line II'. For illustration purposes, Figure 2B 1 shows a semiconductor package in which the anisotropic conductive film, the conductive pattern film, and the sealant are removed. For illustration purposes, Figure 2C A semiconductor package is shown in which an encapsulant is removed from the semiconductor package. Figure 2D It is shown Figure 1 A plan view of an upper surface of a chip stacking structure portion in a semiconductor package.

[0026] Reference Figures 1 to 2D , a semiconductor package 1000 according to some embodiments may include a package substrate 100 , a chip stack structure CSS, an anisotropic conductive film (ACF) 300 , a conductive pattern film 400 , and a sealant 500 .

[0027] The package substrate 100 may be disposed under the chip stack structure CSS and may support the chip stack structure CSS. The package substrate 100 may include a substrate body, a multi-wiring layer, and a solder resist (SR) layer.

[0028] The substrate body may include, for example, resin and glass fiber such as flame retardant 4 (FR-4). However, the material of the substrate body is not limited thereto. For example, the substrate body may include bismaleimide triazine (BT) resin, polycarbonate (PC) resin, build-up film (such as Ajinomoto build-up film (ABF)) or laminating resin.

[0029] A multi-wiring layer may be provided in the substrate body. The multi-wiring layer may include several or dozens of wiring layers. The number of layers of the multi-wiring layer is not limited to the above numerical range. The wiring of other layers may be connected to each other through vias. The wiring and the via may include metal, such as copper (Cu). However, the material of the wiring and the via is not limited to copper. The SR layer may be a layer that protects the substrate body and the multi-wiring layer from external physical or chemical damage. The SR layer may be provided on the upper surface and the lower surface of the substrate body.

[0030] In the semiconductor package 1000 , the package substrate 100 may be, for example, a printed circuit board (PCB). However, the package substrate 100 is not limited to the PCB. For example, the package substrate 100 may include a ceramic substrate, a glass substrate, an interposer substrate, or a redistribution substrate.

[0031] like Figure 2A and Figure 2BAs shown in , the chip stacking structure CSS may include a plurality of semiconductor chips 200 stacked in a vertical direction on a package substrate 100. The semiconductor chips 200 may be semiconductor chips of the same kind. For example, the semiconductor chips 200 may include volatile memory devices such as dynamic random access memory (RAM) (DRAM) and static RAM (SRAM) or non-volatile memory devices such as flash memory.

[0032] The semiconductor chip 200 may include a body layer 210, an active layer 220, and a chip pad 230. The body layer 210 may form a body of the semiconductor chip 200 and may include silicon (Si). However, the material of the body layer 210 is not limited to Si.

[0033] The active layer 220 may include an integrated circuit layer and a wiring layer. The integrated circuit layer may be formed by using an impurity region of an upper portion of the body layer 210. For example, the integrated circuit layer may include transistors, each transistor including a gate electrode and an impurity region such as a source / drain region. However, the elements included in the integrated circuit layer are not limited to transistors. The wiring layer may be disposed on the integrated circuit layer and may include a plurality of wirings. The plurality of wirings may be electrically connected to the integrated circuit layer through contacts. In addition, in the wiring layer, wirings of different layers may be connected to each other through vertical vias.

[0034] In addition, the upper surface of the active layer 220 may correspond to the active surface, and the lower surface of the body layer 210 opposite to the active surface may correspond to the inactive surface. A passivation layer such as an oxide film, a nitride film, or a nitride oxide film for protecting the semiconductor chip 200 may be provided on the upper surface of the active layer 220.

[0035] The chip pad 230 may be exposed at the side surface of the semiconductor chip 200. For example, the chip pad 230 may be disposed on the active layer 220 of the semiconductor chip 200. Figure 2A and Figure 2C As shown in , the chip pad 230 may be disposed to be exposed at the side surface of the active layer 220. In the semiconductor package 1000, the chip pad 230 may be disposed to be exposed at all four side surfaces of the active layer 220. As described above, the passivation layer may be disposed on the upper surface of the active layer 220, and therefore, the chip pad 230 may not be exposed at the upper surface of the active layer 220. However, according to some embodiments, the chip pad 230 may be exposed on the upper surface of the active layer 220 in a structure that passes through the passivation layer.

[0036] The chip pad 230 may be formed to have a thickness corresponding to a partial thickness of an upper portion of the active layer 220. Figure 2A, the chip pad 230 is illustrated as having a thickness corresponding to the total thickness of the active layer 220, in order to facilitate illustrating a structure in which the chip pad 230 is exposed at a side surface of the active layer 220. In some embodiments, the chip pad 230 may be formed on a side surface of the active layer 220 to have a thickness corresponding to the total thickness of the active layer 220, in order to facilitate expanding a contact area with the conductive pattern 410 of the conductive pattern film 400.

[0037] In the semiconductor package 1000, the chip stacking structure CSS may include four semiconductor chips 200. For example, the chip stacking structure CSS may include first to fourth semiconductor chips 200-1 to 200-4. However, the number of semiconductor chips 200 included in the chip stacking structure CSS is not limited to four. For example, the chip stacking structure CSS may include two, three, or five or more semiconductor chips 200.

[0038] In the chip stacking structure CSS, the bottommost first semiconductor chip 200-1 may be bonded to the package substrate 100 by an adhesive layer 250. The adhesive layer 250 may be, for example, a die attach film (DAF). However, the adhesive layer 250 is not limited to the DAF. The second semiconductor chip 200-2 may be bonded to the first semiconductor chip 200-1 by oxide bonding. In addition, the third semiconductor chip 200-3 may be bonded to the second semiconductor chip 200-2 by oxide bonding, and the fourth semiconductor chip 200-4 may be bonded to the third semiconductor chip 200-3 by oxide bonding.

[0039] The oxide bonding may be an interface bonding between a lower semiconductor chip (e.g., a passivation layer on the upper surface of the first semiconductor chip 200-1) and an upper semiconductor chip (e.g., an oxide film on the lower surface of the second semiconductor chip 200-2). For example, the passivation layer may be a SiCN layer or a SiN layer, and the oxide film may be a SiO 2 However, the material of the passivation layer and the material of the oxide film are not limited to the above materials. 9A to 9C The oxide bonding between the semiconductor chips 200 is described in more detail.

[0040] In the semiconductor package 1000, the semiconductor chips 200 of the chip stacking structure CSS may be aligned with each other in the vertical direction (e.g., z direction) of the package substrate 100 and stacked. Here, alignment may mean alignment of the side surfaces of the semiconductor chips 200 with each other. For example, the side surfaces of the semiconductor chips 200 may be aligned with each other in the vertical direction. In addition, in the case where the side surfaces of the semiconductor chips 200 are aligned with each other very accurately in the vertical direction, the side surfaces of the semiconductor chips 200 may form a substantially identical common flat surface.

[0041] The ACF 300 may cover the four side surfaces of the chip stacking structure CSS and a portion of the upper surface of the package substrate 100. For example, the ACF 300 may extend in the z-direction at each of the four side surfaces of the chip stacking structure CSS. In addition, the ACF 300 may be bent or bent by about 90 degrees at a joining portion between the chip stacking structure CSS and the package substrate 100, and may extend in the x-direction and / or y-direction on the upper surface of the package substrate 100. For example, the ACF 300 may extend in the z-direction, and may be bent by about 90 degrees at a joining portion at two side surfaces of the chip stacking structure CSS in the x-direction, and in addition, the ACF 300 may extend in the x-direction on the upper surface of the package substrate 100. In addition, the ACF 300 may extend in the z-direction, and may be bent by about 90 degrees at a joining portion at two side surfaces of the chip stacking structure CSS in the y-direction, and in addition, the ACF 300 may extend in the y-direction on the upper surface of the package substrate 100. In addition, as Figure 2A As shown in , the ACF 300 may cover the base pad 120 of the package substrate 100. For example, the ACF 300 may extend from the bonding portion on the upper surface of the package substrate 100 to a portion beyond the base pad 120 of the package substrate 100. For reference, the ACF 300 may be an ACF that allows current to flow in only one direction, and may include fine conductive particles 310 and an adhesive resin 320 (such as Figure 2D ). For example, the ACF 300 may be an ACF formed in a film state by combining the conductive particles 310 with the adhesive resin 320 having adhesive properties and insulating properties.

[0042] The conductive pattern film 400 may cover the ACF 300. Similar to the ACF 300, the conductive pattern film 400 may cover the four side surfaces of the chip stacking structure CSS and a portion of the upper surface of the package substrate 100. For example, the conductive pattern film 400 may extend in the z direction on the ACF 300 at each of the four side surfaces of the chip stacking structure CSS. In addition, the conductive pattern film 400 may be bent about 90 degrees at the bonding portion between the chip stacking structure CSS and the package substrate 100, and may extend in the x direction and / or y direction on the ACF 300 on the upper surface of the package substrate 100. For example, the conductive pattern film 400 may extend in the z direction, and may be bent about 90 degrees at the bonding portion on the ACF 300 on both side surfaces of the chip stacking structure CSS in the x direction, and in addition, the conductive pattern film 400 may extend in the x direction on the ACF 300 on the upper surface of the package substrate 100. In addition, the conductive pattern film 400 may extend in the z direction and may be bent about 90 degrees at the bonding portion on the ACF 300 on both side surfaces of the chip stack structure CSS in the y direction, and further, the conductive pattern film 400 may extend in the y direction on the ACF 300 on the upper surface of the package substrate 100. Figure 2A As shown in , similar to the ACF 300 , the conductive pattern film 400 may extend from a bonding portion on the ACF 300 on the upper surface of the package substrate 100 until a portion beyond the substrate pad 120 of the package substrate 100 .

[0043] The conductive pattern film 400 may include a conductive pattern 410 and a polymer film 420. The conductive pattern 410 may include a conductive material. For example, the conductive pattern 410 may include a metal such as Cu, aluminum (Al), nickel (Ni), tin (Sn), silver (Ag), or gold (Au). In some embodiments, the conductive pattern 410 may include polysilicon, a conductive oxide film, or a conductive nitride film. In the semiconductor package 1000, the conductive pattern 410 may include, for example, Cu. However, the material of the conductive pattern 410 is not limited to the above materials. The polymer film 420 may include, for example, polyimide (PI). However, the material of the polymer film 420 is not limited to PI.

[0044] The conductive pattern 410 may be disposed on the polymer film 420. For example, the conductive pattern 410 may extend on the polymer film 420 in a direction (e.g., z direction) along which the polymer film 420 extends, and further, a plurality of conductive patterns 410 may be arranged spaced apart from each other on the polymer film 420 in a direction (e.g., x direction or y direction) perpendicular to the extending direction.

[0045] To describe the four side surfaces of the chip stacking structure CSS in more detail, the conductive pattern 410 may extend in the z direction on the ACF 300 on each of the four side surfaces of the chip stacking structure CSS. In addition, the conductive pattern 410 may be bent about 90 degrees at the bonding portion between the chip stacking structure CSS and the package substrate 100, and may extend in the x direction or the y direction on the ACF 300 on the upper surface of the package substrate 100. In the case where the polymer film 420 extends in the x direction on the upper surface of the package substrate 100 (for example, for the side surface where the polymer film 420 extends in the x direction on the upper surface of the package substrate 100), the conductive patterns 410 on the polymer film 420 may be arranged spaced apart from each other in the y direction on the corresponding side surfaces of the chip stacking structure CSS. In addition, in the case where the polymer film 420 extends in the y direction on the upper surface of the package substrate 100, the conductive patterns 410 on the polymer film 420 may be arranged spaced apart from each other in the x direction on the corresponding side surfaces of the chip stacking structure CSS.

[0046] The conductive pattern 410 may connect the corresponding chip pads 230 of the semiconductor chips 200 of the chip stack structure CSS to each other. In addition, the conductive pattern 410 may connect the chip pads 230 of the semiconductor chips 200 to the corresponding substrate pads 120 of the package substrate 100. As a result, the semiconductor chips 200 of the chip stack structure CSS may be electrically connected to the package substrate 100 through the conductive pattern 410. Figure 2D As shown in , in a plan view (top view), the separation intervals between the conductive patterns 410 may be substantially the same as the separation intervals between the chip pads 230 of the semiconductor chip 200. For example, at both side surfaces of the semiconductor chip 200 in the x direction, the separation intervals between the conductive patterns 410 in the y direction may be substantially the same as the separation intervals between the chip pads 230 of the semiconductor chip 200 in the y direction. In addition, at both side surfaces of the semiconductor chip 200 in the y direction, the separation intervals between the conductive patterns 410 in the x direction may be substantially the same as the separation intervals between the chip pads 230 of the semiconductor chip 200 in the x direction.

[0047] In some embodiments, at least some of the conductive patterns 410 may extend in the x direction, the y direction, the xz direction, the yz direction, and the z direction at the side surface of the semiconductor chip 200 of the chip stack structure CSS. In the case where the conductive patterns 410 extend in the x direction, the y direction, or the oblique (xz or yz) direction, the conductive patterns 410 may overlap each other, and in this case, an insulating layer may be provided between the overlapped conductive patterns 410. In addition, as Figure 2DAs shown in FIG. 4 , the conductive pattern 410 may be electrically connected to the corresponding chip pad 230 of the semiconductor chip 200 of the chip stack structure CSS through the conductive particles 310 of the ACF 300. For example, a conductive path may be formed between the conductive pattern 410 and the corresponding chip pad 230 by using the conductive particles 310. In some embodiments, the conductive pattern 410 may be directly connected to the chip pad 230.

[0048] The sealant 500 may seal the chip stack structure CSS on the package substrate 100. The sealant 500 may include an insulating material (e.g., a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide). The sealant 500 may include a resin (e.g., ABR, FR-4, or BT resin), wherein a stiffener such as an inorganic filler is added to the thermosetting resin or the thermoplastic resin. In addition, a photosensitive material such as a photoimageable encapsulant (PIE) or a molding material such as an epoxy molding compound (EMC) may be used in the sealant 500. In the semiconductor package 1000, the sealant 500 may include, for example, EMC. However, the material of the sealant 500 is not limited to the above materials.

[0049] In the semiconductor package 1000, in some embodiments, the lowermost first semiconductor chip 200-1 may be bonded to the package substrate 100 by using an adhesive layer 250 (such as DAF), and the upper semiconductor chip 200 may be interface-bonded to the lower semiconductor chip 200 by oxide bonding. Therefore, the total height of the package may be reduced by the thickness of the adhesive layer 250 (e.g., by reducing the thickness of the adhesive layer 250 that would otherwise be used for bonding), and the material cost of the adhesive layer 250 (such as DAF) may be reduced. In addition, in the semiconductor package 1000, in some embodiments, the electrical connection between the semiconductor chip 200 and the package substrate 100 may be implemented by using a conductive pattern film 400 and a chip pad 230 exposed at a side surface, and therefore, the semiconductor chip 200 may be stacked on the package substrate 100 in a vertical form rather than a stepped form. As a result, the planar area of ​​the package may be greatly reduced compared to a package structure stacked in a stepped form. In addition, in the semiconductor package 1000, in some embodiments, the semiconductor chip 200 can be electrically connected to the package substrate 100 through the conductive pattern film 400 instead of the wire, and therefore, the height of the package can be additionally reduced by the height of the wire loop. For reference, in the semiconductor package 1000, in some embodiments, the ACF 300 on the four side surfaces of the chip stack structure CSS can compensate for the horizontal bonding force between the semiconductor chips 200 based on the vertical combined force, which can be weakened by the removal of the adhesive layer 250.

[0050] Figure 3A and Figure 4Ais a perspective view of an example of a semiconductor package in which an encapsulant is omitted for illustration purposes, and Figure 3B and Figure 4B It is shown Figure 3A and Figure 4A A plan view of the upper surface of a chip stacking structure portion in a semiconductor package. Figures 1 to 2D The same or similar descriptions are briefly given or omitted and can be equally applied to FIG. 3A to FIG. 4B of the package, unless the context indicates otherwise or suggests otherwise.

[0051] Reference Figure 3A and Figure 3B According to some embodiments, the semiconductor package 1000a may be Figure 1 The semiconductor package 1000 of the present invention is different. The semiconductor package 1000a includes a semiconductor chip 200a and a structure of a chip stacking structure CSSa based on the semiconductor chip 200a, an ACF 300a, and a structure of a conductive pattern film 400a. In the semiconductor package 1000a according to some embodiments, the semiconductor chip 200a may include a body layer 210, an active layer 220, and a chip pad 230a. In addition, in the semiconductor chip 200a, the chip pad 230a may be configured to be exposed at one of the four side surfaces of the semiconductor chip 200a (for example, one of the two side surfaces extending in the x direction). In addition, the four semiconductor chips 200a constituting the chip stacking structure CSSa may have substantially the same structure. For example, in the chip stacking structure CSSa, the chip pad 230a may be configured to be exposed at the same one side surface in each of the four semiconductor chips 200a.

[0052] In addition, when the chip pad 230a is exposed only at one side surface of the corresponding semiconductor chip 200a, the ACF 300a and the conductive pattern film 400a may extend in the z direction at one side surface of the chip stacking structure CSSa, and may extend on a portion of the upper surface of the package substrate 100 corresponding to the one side surface of the chip stacking structure CSSa. Figure 2A The substrate pad 120 may be disposed on the upper surface of the package substrate 100 , and the substrate pad 120 may be covered by the ACF 300 a and the conductive pattern film 400 a both extending on the upper surface of the package substrate 100 .

[0053] For example, in the semiconductor package 1000a, the chip pad 230a may be disposed along the x direction at the upper side surface of the semiconductor chip 200a in the y direction. In addition, the ACF 300a and the conductive pattern film 400a may be disposed at the upper side surface of the chip stack structure CSSa in the y direction and extend in the z direction, and may be bent about 90 degrees at the joint portion to extend in the y direction on the upper surface of the package substrate 100. The ACF 300a and the conductive pattern film 400a, both extending in the y direction on the upper surface of the package substrate 100, may cover the base pad 120 on the upper surface of the package substrate 100.

[0054] Reference Figure 4A and Figure 4B According to some embodiments, the semiconductor package 1000b may be Figure 1 The semiconductor package 1000 of the present invention is different. The semiconductor package 1000b includes a semiconductor chip 200b and a chip stacking structure CSSb based on the semiconductor chip 200b, an ACF 300b, and a conductive pattern film 400b. In the semiconductor package 1000b according to some embodiments, the semiconductor chip 200b may include a body layer 210, an active layer 220, and a chip pad 230b. In addition, in the semiconductor chip 200b, the chip pad 230b may be configured to be exposed at two side surfaces (e.g., two side surfaces extending in the x direction) opposite to each other among the four side surfaces of the semiconductor chip 200b. In addition, the four semiconductor chips 200b constituting the chip stacking structure CSSb may have substantially the same structure. For example, in the chip stacking structure CSSb, the chip pad 230b may be configured to be exposed at two side surfaces opposite to each other in each of the four semiconductor chips 200b.

[0055] When the chip pad 230b is exposed at two side surfaces of the corresponding semiconductor chip 200b opposite to each other, the ACF 300b and the conductive pattern film 400b may extend in the z direction on two side surfaces of the chip stack structure CSSb opposite to each other, and may extend on a portion of the upper surface of the package substrate 100 corresponding to the side surface of the chip stack structure CSSb. The substrate pad 120 may be disposed on the upper surface of the package substrate 100, and the substrate pad 120 may be covered by the ACF 300b and the conductive pattern film 400b both extending on the upper surface of the package substrate 100.

[0056] For example, in the semiconductor package 1000b according to some embodiments, the chip pad 230b may be disposed at both side surfaces of the semiconductor chip 200b in the y direction along the x direction. In addition, the ACF 300b and the conductive pattern film 400b may be disposed at both side surfaces of the chip stack structure CSSb in the y direction and extend in the z direction, and may be bent about 90 degrees at the joint portion to extend in the y direction on the upper surface of the package substrate 100. The ACF 300b and the conductive pattern film 400b, both extending in the y direction on the upper surface of the package substrate 100, may cover the base pad 120 on the upper surface of the package substrate 100.

[0057] Above, structures have been described in which the chip pad 230a is exposed at one side surface of the semiconductor chip 200a, the chip pad 230b is exposed at two opposite side surfaces of the semiconductor chip 200b, and accordingly, the ACF 300a and the conductive pattern film 400a cover one side surface of the chip stacking structure CSSa and extend onto the package substrate 100, and the ACF 300b and the conductive pattern film 400b cover two side surfaces of the chip stacking structure CSSb and extend onto the package substrate 100. However, the structure of the semiconductor package within the scope of the present disclosure is not limited thereto. For example, the chip pad may be configured to be exposed at three side surfaces of the semiconductor chip, or exposed at two adjacent side surfaces of the semiconductor chip. In addition, the ACF and the conductive pattern film may cover any side surface of the chip stacking structure that exposes the chip pad, and may extend on the upper surface of the package substrate.

[0058] Figure 5A and Figure 5B is a perspective view of a semiconductor package according to some embodiments. For illustration purposes, Figure 5A and Figure 5B Only the package substrate and the chip stacking structure are shown, and the sealant, ACF, and conductive pattern film that may be included in the semiconductor package are omitted. Figures 1 to 4B The same or similar descriptions are briefly given or omitted and can be equally applied to FIG. 5A to FIG. 5B of the package, unless the context indicates otherwise or suggests otherwise.

[0059] Reference Figure 5A According to some embodiments, the semiconductor package 1000c may be Figure 1 In the semiconductor package 1000c, the semiconductor chip 200 may be Figure 1 The semiconductor chip 200 of the semiconductor package 1000 is substantially the same. In addition, the ACF and the conductive pattern film may be Figure 1 The ACF 300 and the conductive pattern film 400 of the semiconductor package 1000 are substantially the same.

[0060] In the semiconductor package 1000c according to some embodiments, the stacking structure of the semiconductor chips 200 of the chip stack structure CSSc may be Figure 1 The stacking structure of the semiconductor chip 200 of the chip stacking structure CSS of the semiconductor package 1000 is different. For example, in the semiconductor package 1000c, the semiconductor chip 200 of the chip stacking structure CSSc can be bonded to the package substrate 100 or the semiconductor chip 200 below by using an adhesive layer 250 (such as DAF), and can be stacked. For example, bonding between adjacent semiconductor chips 200 by oxide bonding may not be implemented. For example, the first semiconductor chip 200-1 can be bonded to the package substrate 100 by the adhesive layer 250, and the second semiconductor chip 200-2 can be bonded to the first semiconductor chip 200-1 by the adhesive layer 250. In addition, the third semiconductor chip 200-3 can be bonded to the second semiconductor chip 200-2 by the adhesive layer 250, and the fourth semiconductor chip 200-4 can be bonded to the third semiconductor chip 200-3 by the adhesive layer 250.

[0061] Reference Figure 5B According to some embodiments, the semiconductor package 1000d may be configured in a chip stack structure CSSd. Figure 5A For example, in the semiconductor package 1000d, the semiconductor chip 200 may be Figure 5A The semiconductor chip 200 of the semiconductor package 1000c is substantially the same as that of the semiconductor package 1000c. In addition, the ACF and the conductive pattern film may be Figure 5A The ACF and the conductive pattern film of the semiconductor package 1000 c are substantially the same.

[0062] However, in the semiconductor package 1000d according to some embodiments, the stacking structure of the semiconductor chips 200 of the chip stack structure CSSd may be different from Figure 5A The stacking structure of the semiconductor chips 200 of the chip stacking structure CSSc is different. For example, in the semiconductor package 1000d, the second semiconductor chip 200-2 to the fourth semiconductor chip 200-4 of the semiconductor chip 200 of the chip stacking structure CSSd can be bonded to the lower semiconductor chip 200 by using the polymer adhesive layer 250a, and can be stacked. For example, the second semiconductor chip 200-2 can be bonded to the first semiconductor chip 200-1 by the polymer adhesive layer 250a. In addition, the third semiconductor chip 200-3 can be bonded to the second semiconductor chip 200-2 by the polymer adhesive layer 250a, and the fourth semiconductor chip 200-4 can be bonded to the third semiconductor chip 200-3 by the polymer adhesive layer 250a.

[0063] In addition, bonding by oxide bonding based on the polymer bonding layer 250a can be implemented between adjacent semiconductor chips 200. For oxide bonding based on the polymer bonding layer 250a, when surface treatment is performed on the bonding interface by plasma treatment and deionized (DI) water cleaning, bonding based on hydrogen bonding can be implemented in a C-stage at room temperature. Subsequently, covalent bond-based oxide bonding can be completed by high-temperature annealing. For example, the polymer bonding layer 250a can be thinly coated on the semiconductor chip 200 in a liquid state (e.g., a thickness of about 1 μm or less), and then can be cured and attached to the semiconductor chip 200. Plasma treatment and DI water cleaning can be performed on the cured polymer bonding layer 250a.

[0064] FIG. 6A to FIG. 6E is a perspective view showing a process of manufacturing a semiconductor package according to some embodiments, and Fig. 7A and Figure 7B is shown in more detail, for example Fig. 6E The process of attaching the conductive pattern film is shown in FIG. Figures 1 to 2D describe FIG. 6A to FIG. 6E , Fig. 7A and Figure 7B , and briefly give or omit Figures 1 to 5B It will be understood that the same or similar description as described above can be applied. FIG. 6A to FIG. 6B , Fig. 7A and Figure 7B Process or part thereof to form Figures 1 to 5B semiconductor packages.

[0065] Reference Fig. 6A The process may include preparing a plurality of semiconductor chips 200. Each of the semiconductor chips 200 may include a body layer 210, an active layer 220, and a chip pad 230. The chip pad 230 may be exposed at a side surface of the active layer 220. The structure or material of the semiconductor chip 200 may be described in detail. Figure 1 The semiconductor chip 200 may be manufactured in a Si wafer by various semiconductor processes. FIG. 8A to FIG. 8H The process of preparing or manufacturing the semiconductor chip 200 is described in more detail.

[0066] Reference Figure 6B , a semiconductor chip 200 may be prepared, and then one semiconductor chip 200 may be stacked on the package substrate 100. The semiconductor chip 200 may be bonded to and stacked on a central portion of an upper surface of the package substrate 100 by using an adhesive layer 250 such as DAF. Hereinafter, the lowermost semiconductor chip 200 stacked on the upper surface of the package substrate 100 may be referred to as a first semiconductor chip 200-1.

[0067] The package substrate 100 may include a substrate body, a multi-wiring layer, and an SR layer. The package substrate 100 may be, for example, a PCB. Figure 6B As shown in FIG. 1 , a substrate pad 120 may be provided at an outer portion of an upper surface of the package substrate 100. The structure or material of the package substrate 100 may be described with reference to FIG. Figure 1 The description of the semiconductor package 1000 is the same as above.

[0068] Reference Figure 6C , a first semiconductor chip 200-1 may be stacked, and then a chip stacking structure CSS may be formed by stacking a plurality of semiconductor chips 200 on the first semiconductor chip 200-1. For example, a second semiconductor chip 200-2 may be stacked on the first semiconductor chip 200-1, a third semiconductor chip 200-3 may be stacked on the second semiconductor chip 200-2, and a fourth semiconductor chip 200-4 may be stacked on the third semiconductor chip 200-3. In addition, the semiconductor chips 200 may be aligned with each other in a vertical direction (e.g., z direction) and stacked. For example, in the chip stacking structure CSS, the side surfaces of the semiconductor chips 200 may be aligned with each other in a vertical direction.

[0069] In addition, in the method of manufacturing a semiconductor package, according to some embodiments, the second semiconductor chip 200-2 to the fourth semiconductor chip 200-4 may be bonded to the lower semiconductor chip 200 by oxide bonding. For example, the second semiconductor chip 200-2 may be bonded to the first semiconductor chip 200-1 by oxide bonding, the third semiconductor chip 200-3 may be bonded to the second semiconductor chip 200-2 by oxide bonding, and the fourth semiconductor chip 200-4 may be bonded to the third semiconductor chip 200-3 by oxide bonding. 9A to 9C The oxide bonding between the semiconductor chips 200 is described in more detail.

[0070] In the method of manufacturing a semiconductor package according to some embodiments, the bonding process between the semiconductor chips 200 is not limited to oxide bonding. For example, the bonding process may be performed by an adhesive layer (such as DAF) (for example, as described in relation to Figure 5B The bonding is performed between the semiconductor chips 200 by the polymer adhesive layer described above. In the case where the bonding is performed between the semiconductor chips 200 by the adhesive layer, as a result of the process, Figure 5B Semiconductor package 1000d.

[0071] Reference Fig.6D, a chip stacking structure CSS may be formed, and then, the ACF 300 may be attached to a portion of the upper surface of the package substrate 100 and four side surfaces of the chip stacking structure CSS. The ACF 300 may include conductive particles 310 and an insulating adhesive resin 320. The ACF 300 may extend in a vertical direction (e.g., z-direction) at each of the side surfaces of the chip stacking structure CSS, may be bent by about 90 degrees at a joint portion between the chip stacking structure CSS and the package substrate 100, and may extend in an x-direction or a y-direction on the upper surface of the package substrate 100 to cover the corresponding substrate pad 120. For example, the ACF 300 may extend in the z-direction, and may be bent by about 90 degrees at a joint portion at both side surfaces of the chip stacking structure CSS in the x-direction, and further, the ACF 300 may extend in the x-direction on the upper surface of the package substrate 100. Furthermore, the ACF 300 may extend in the z direction and may be bent about 90 degrees at a bonding portion at both side surfaces of the chip stack structure CSS in the y direction and may extend in the y direction on the upper surface of the package substrate 100 .

[0072] The substrate pad 120 may be arranged in the y direction on the upper surface of the package substrate 100 to correspond to both side surfaces of the chip stack structure CSS in the x direction, and the substrate pad 120 may be covered by the ACF 300 extending in the x direction on the upper surface of the package substrate 100. In addition, the substrate pad 120 may be arranged in the x direction on the upper surface of the package substrate 100 to correspond to both side surfaces of the chip stack structure CSS in the y direction, and the substrate pad 120 may be covered by the ACF 300 extending in the y direction on the upper surface of the package substrate 100.

[0073] Reference Fig. 6E , the ACF 300 may be attached, and then the conductive pattern film 400 may be attached to the ACF 300. The conductive pattern film 400 may include a conductive pattern 410 and a polymer film 420. The conductive pattern 410 may extend in one direction on the polymer film 420, and may be arranged spaced apart from each other in a direction perpendicular to the extending direction. Fig. 7A As shown in , in the conductive pattern film 400 attached to the ACF 300 on both side surfaces of the chip stack structure CSS in the y direction, the conductive patterns 410 may extend in the z direction and may be arranged spaced apart from each other in the x direction. In addition, the position of the conductive pattern 410 in the x direction may be substantially the same as the x-direction position of the chip pad 230 exposed at the side surface of the corresponding semiconductor chip 200. In addition, as Fig. 6EAs shown in FIG. 4 , in the conductive pattern film 400 attached to the ACF 300 on both side surfaces of the chip stack structure CSS in the x direction, the conductive patterns 410 may extend in the z direction and may be arranged spaced apart from each other in the y direction. In addition, the position of the conductive pattern 410 in the y direction may be substantially the same as the y-direction position of the chip pad 230 exposed at the side surface of the corresponding semiconductor chip 200.

[0074] In some embodiments, at least some of the conductive patterns 410 of the conductive pattern film 400 may extend in the x-direction, the y-direction, or an oblique direction (such as the xz direction or the yz direction) and the z-direction at the polymer film 420. In the case where the conductive patterns 410 extend in the x-direction, the y-direction, or the oblique direction, the conductive patterns 410 may overlap each other, and, for example, an insulating layer may be provided between the overlapped conductive patterns 410.

[0075] For reference Fig. 7A and Figure 7B Describing in detail the process of attaching the conductive pattern film 400 on the ACF 300, first, the conductive pattern film 400 may be aligned on the corresponding side surface of the chip stack structure CSS so that the position of the conductive pattern 410 corresponds to the position of the chip pad 230 of the semiconductor chip 200. Subsequently, the conductive pattern film 400 may be attached to the ACF 300 at the corresponding side surface of the chip stack structure CSS by applying heat and pressure HP. Based on the heat and pressure HP, the adhesive resin 320 of the ACF 300 may have fluidity, and thus, the conductive pattern 410 of the conductive pattern film 400 may be inserted into the adhesive resin 320 of the ACF 300. In addition, the conductive particles 310 of the ACF 300 may be concentrated between the conductive pattern 410 and the chip pad 230, and thus, a conductive path may be formed between the conductive pattern 410 and the chip pad 230 by using the conductive particles 310. Furthermore, the same process may be performed on the ACF 300 on the package substrate 100 , and thus a conductive path (a local conductive path based on the presence of the conductive pattern 410 ) may be formed between the conductive pattern 410 of the conductive pattern film 400 and the base pad 120 by using the conductive particles 310 .

[0076] exist Fig. 7A and Figure 7B , a process of attaching the ACF 300 and the conductive pattern film 400 on one side surface of the chip stack structure CSS is shown, but the same process may be performed on one or more other side surfaces of the chip stack structure CSS. Fig. 6E As shown in , the ACF 300 and the conductive pattern film 400 may be attached on four side surfaces of the chip stack structure CSS and an upper surface of the package substrate 100 .

[0077] In addition, Fig.6D and Fig. 6E In the embodiment, the ACF 300 may be attached to all of the four side surfaces of the chip stack structure CSS, and then the conductive pattern film 400 may be attached to the ACF 300. However, in some embodiments, the ACF 300 and / or the conductive pattern film 400 may be individually attached to individual side surfaces of the chip stack structure CSS. For example, the ACF 300 and the conductive pattern film 400 may be attached to each other at a first side surface of the chip stack structure CSS, and then the ACF 300 and the conductive pattern film 400 may be attached to each other at a second side surface of the chip stack structure CSS.

[0078] Furthermore, in the case where the ACF 300 and the conductive pattern film 400 are attached to each other only at one side surface of the chip stack structure CSS, as a result of the process, it is possible to manufacture Figure 3A In addition, in the case where the ACF 300 and the conductive pattern film 400 are attached to each other at both side surfaces of the chip stack structure CSS, as a result of the process, a semiconductor package 1000a can be manufactured. Figure 4A Semiconductor package 1000b.

[0079] After the conductive pattern film 400 is attached to the ACF 300, the sealant 500 may seal the chip stack structure CSS on the package substrate 100 through a molding process, thereby Figure 1 The semiconductor package 1000 may be manufactured.

[0080] FIG. 8A to FIG. 8H FIG. 1 is a diagram showing a method of preparing a semiconductor chip (eg, Fig. 6A A cross-sectional view of the process of manufacturing a semiconductor chip. Figures 1 to 2D The same or similar descriptions are briefly given or omitted and can be equally applied to FIG. 8A to FIG. 8H elements unless the context indicates otherwise or suggests otherwise.

[0081] Reference Fig. 8A In the method of manufacturing a semiconductor package according to some embodiments, an active layer 220W and a chip pad 230W may be first formed at an upper portion of a wafer 210W. The wafer 210W may include Si. However, the material of the wafer 210W is not limited to Si. Here, the active layer 220W may include an integrated circuit layer and a wiring layer. The description of the integrated circuit layer and the wiring layer may be the same as Figure 1 The description of the semiconductor package 1000 is the same as above.

[0082] A scribe lane 240 may be provided at an upper portion of the wafer 210W. The scribe lane 240 may correspond to a boundary portion by which a plurality of semiconductor chips on the wafer 210W are distinguished from each other. In addition, by removing the scribe lane 240 in the wafer 210W later, the semiconductor chips may be individualized / separated. A chip pad 230W may be formed to contact the scribe lane 240. The chip pad 230W may be provided to contact the scribe lane 240, and then, by removing the scribe lane 240, the chip pad 230W may be exposed at a side surface of the semiconductor chip (e.g., a side surface of the active layer 220W).

[0083] exist Fig. 8A , the chip pad 230W may be disposed in contact with one side surface of the scribe line 240. As described above, in the case where the chip pad 230W is disposed in contact with one side surface of the scribe line 240, when the semiconductor chips are later individualized, the chip pad 230W may be exposed only at the side surface of the semiconductor chip corresponding to the corresponding scribe line 240. However, by arranging the chip pad 230W to be in contact with all scribe lines surrounding the semiconductor chip, when the wafer 210W is later individualized into semiconductor chips, the chip pad 230W may be exposed at all of the four side surfaces of the semiconductor chip.

[0084] Reference Figure 8B , after forming the active layer 220W and the chip pad 230W in the wafer 210W, the wafer 210W may be turned over, and the exposed surface of the active layer 220W may be attached to the support tape 600. For illustration purposes, only the support tape 600 is shown, but the support tape 600 may be disposed on a carrier wafer, and the wafer 210W may be disposed on the carrier wafer and supported by the carrier wafer through the support tape 600.

[0085] Reference Figure 8C , then, the wafer 210W may be thinned by removing the back side portion of the wafer 210W through the back grinding process BG. For example, in the back grinding process BG, the back side portion of the wafer 210W up to a portion of the scribe line 240 may be removed. The portion of the wafer 210W after the back grinding process BG may constitute a body layer of the semiconductor chip. For reference, in the wafer 210W, a surface of the active layer 220W may correspond to a front side surface, and a surface opposite thereto may correspond to a back side surface.

[0086] Reference Fig.8D, then, the wafer 210W may be separated from the support tape 600, and the wafer 210W may be attached to a dicing tape 720 of a ring mount apparatus 700. The backside surface of the wafer 210W may be attached to the dicing tape 720. For reference, the ring mount apparatus 700 may be an apparatus for individualizing the wafer 210W into semiconductor chips, and may include a ring mount frame 710 and a dicing tape 720. In addition, the ring mount frame 710 may have a circular ring shape, and may have a structure in which the dicing tape 720 is attached to the lower side and the lower side is plugged by the dicing tape 720.

[0087] Reference Fig. 8E , the wafer 210W may be attached to the dicing tape 720 of the ring-shaped mounting device 700, and then the protective tape 800 may be attached to the upper surface of the wafer 210W. The protective tape 800 may be referred to as a protective layer coating (PLC). The protective tape 800 may prevent the active layer 220W and the chip pad 230W from being contaminated or damaged in the process of removing the scribe line 240.

[0088] Reference Figure 8F , a protective tape 800 may be attached to the wafer 210W, and then the scribe line 240 may be removed by a laser grooving process LG. Laser grooving may be referred to as laser sawing. Figure 8F As shown in FIG. 1 , the scribe line 240 may not be completely removed by the laser grooving process LG. Figure 8G The plasma cutting process PD is used to completely remove the scribe line 240 .

[0089] In some embodiments, when preparing a semiconductor chip, a laser grooving process LG may be used to remove scribe line 240, but the process of removing scribe line 240 is not limited to the laser grooving process LG. For example, scribe line 240 may be removed by a mechanical sawing process such as blade sawing.

[0090] Reference Figure 8G After the scribe line 240 is removed by the laser grooving process LG, the remaining scribe line 240 may be completely removed by the plasma cutting process PD. Based on the complete removal of the scribe line 240, the chip pad 230W may be exposed at the side surface of the corresponding semiconductor chip 200.

[0091] For reference, the plasma dicing process PD may refer to a process of placing the ring-shaped mounting device 700 including the wafer 210W in a plasma chamber and removing the scribe line 240 through a plasma process. Figure 8G , a portion surrounding the ring-shaped mounting device 700 including the wafer 210W may correspond to a portion of the plasma chamber filled with plasma.

[0092] Reference Figure 8H , then, by removing the protective tape 800 on the upper surface of the wafer 210W, the wafer 210W may be individualized into semiconductor chips 200. Each of the semiconductor chips 200 may include a body layer 210, an active layer 220, and a chip pad 230. In some embodiments, even after removing the protective tape 800, the semiconductor chips 200 may be kept attached to the dicing tape 720 of the ring mounting device 700. Therefore, then, the semiconductor chips 200 may be separated from the dicing tape 720 by a die separation process to become separated from each other, and may be mounted on a package substrate.

[0093] 9A to 9C is shown in stacked semiconductor chips (e.g., Figure 6C FIG. 1 is a diagram of an example of a process for forming an oxide bond in a process for forming a semiconductor chip 200 or other semiconductor chips 200 that are oxide-bonded to each other as described herein. Figures 1 to 2D The same or similar descriptions are briefly given or omitted and can be equally applied to 9A to 9C elements unless the context indicates otherwise or suggests otherwise.

[0094] Reference Fig.9A The process of forming an oxide bond between the semiconductor chips 200 may include performing a plasma treatment and then performing a deionized (DI) water cleaning on the semiconductor chip 200 to form OH dangling bonds on the semiconductor chip 200. For example, the semiconductor chip 200 may include SiO formed on the lower surface of the body layer 210. 2 The oxide film 260 and the passivation layer 235 of SiCN or SiN formed on the upper surface of the active layer 220. When the plasma treatment is performed on the semiconductor chip 200, as shown in FIG. Fig.9A As shown in FIG. 2 , OH dangling bonds may be formed in the oxide film 260 and the passivation layer 235. SiO 2 The oxide film 260 may correspond to a natural oxide film. In addition, in some embodiments, a polymer adhesive layer (e.g., Figure 5B 250a) is attached to the upper surface or the lower surface of the semiconductor chip 200. In this case, the polymer adhesive layer 250a may be subjected to plasma treatment and subsequent DI water cleaning. The plasma treatment and subsequent DI water cleaning may be performed on each of the semiconductor chips 200, or the plasma treatment and subsequent DI water cleaning may be performed on all semiconductor chips in the semiconductor chips 200 in units of wafers. In addition, the plasma treatment and DI water cleaning of the semiconductor chip 200 may be performed on both the oxide film 260 and the passivation layer 235, or the plasma treatment and DI water cleaning of the semiconductor chip 200 may be performed on one of the oxide film 260 and the passivation layer 235.

[0095] Reference Fig. 9B After forming OH dangling bonds in the semiconductor chip 200, the upper semiconductor chip may be stacked on the lower semiconductor chip. For example, the lower surface (i.e., oxide film 260) of the second semiconductor chip 200-2 may be stacked to contact the upper surface (i.e., passivation layer 235) of the first semiconductor chip 200-1. In the process of stacking the second semiconductor chip 200-2 on the first semiconductor chip 200-1, as shown in FIG. Fig. 9B As shown in , the OH dangling bonds may form hydrogen bonding HD based on hydrogen bonding. The hydrogen bonding HD may have a relatively low bonding force. Therefore, the hydrogen bonding HD may have a bonding force that enables the second semiconductor chip 200 - 2 to be held on the first semiconductor chip 200 - 1 .

[0096] Reference Fig. 9C After forming the hydrogen bond HD by stacking the second semiconductor chip 200-2 on the first semiconductor chip 200-1, high temperature annealing may be performed. Based on the high temperature annealing, the hydrogen bond HD may be changed to the oxide bond OD. For example, in the case of simply expressing it as a chemical formula, based on the high temperature annealing, the hydrogen bond HD may be changed to “-OH+-OH→O+H 2 Here, the process temperature of the high temperature annealing may be about 150° C. or higher. However, the high temperature annealing is not limited to this temperature range. The oxide bonding OD may have a higher bonding force than the hydrogen bonding HD. Therefore, the second semiconductor chip 200-2 may be firmly held on the first semiconductor chip 200-1 with a high bonding force.

[0097] Above, examples have been described in the drawings and the specification. It will be appreciated by those skilled in the art that various modifications may be implemented without departing from the scope of the present disclosure.

[0098] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of what may be claimed. Certain features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, one or more features from a combination may be deleted from the combination in some cases, and the combination may involve sub-combinations or variations of sub-combinations.

[0099] While examples have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: Package substrate; A chip stacking structure, comprising at least two semiconductor chips aligned with each other in a vertical direction and stacked on a package substrate, each of the at least two semiconductor chips having a side surface and comprising a chip pad arranged at the side surface; An anisotropic conductive film covering the side surface of the chip stacking structure; as well as The conductive pattern film covers the anisotropic conductive film and includes a conductive pattern, and the conductive pattern electrically connects the chip pad to the substrate pad of the package substrate.

2. The semiconductor package according to claim 1, wherein: The chip pad is arranged at one or more side surfaces of the four side surfaces of the at least two semiconductor chips, and The anisotropic conductive film and the conductive pattern film cover one or more side surfaces of the chip stack structure corresponding to the one or more side surfaces on which the chip pads are arranged among the four side surfaces of the at least two semiconductor chips.

3. The semiconductor package according to claim 1, wherein: Chip pads are arranged at four side surfaces of the at least two semiconductor chips, and The anisotropic conductive film and the conductive pattern film cover the four side surfaces of the chip stacking structure.

4. The semiconductor package according to claim 3, wherein: The anisotropic conductive film and the conductive pattern film extend in a vertical direction on each of the four side surfaces of the chip stacking structure, are bent 90 degrees at the position where the chip stacking structure is joined to the packaging substrate, and extend in a first horizontal direction or a second horizontal direction on the packaging substrate, wherein the second horizontal direction is perpendicular to the first horizontal direction.

5. The semiconductor package according to claim 4, wherein: The conductive pattern extends on each of the four side surfaces of the chip stacking structure to electrically connect the corresponding chip pads of the at least two semiconductor chips to each other, and extends in a first horizontal direction or a second horizontal direction on the package substrate to electrically connect the chip pads of the at least two semiconductor chips to the substrate pad.

6. The semiconductor package according to claim 4, wherein: At a first side of the chip stacking structure, the conductive pattern film extends in a first horizontal direction on the package substrate, and the conductive pattern of the conductive pattern film includes a first plurality of conductive patterns spaced apart from each other on corresponding side surfaces of the chip stacking structure in a second horizontal direction, and At a second side of the chip stack structure, the conductive pattern film extends in a second horizontal direction on the package substrate, and the conductive pattern of the conductive pattern film includes a second plurality of conductive patterns spaced apart from each other on corresponding side surfaces of the chip stack structure in the first horizontal direction.

7. The semiconductor package according to claim 1, wherein: The at least two semiconductor chips include a first semiconductor chip located at the bottom and a second semiconductor chip on the first semiconductor chip, The first semiconductor chip is bonded to the package substrate via an adhesive layer, and The second semiconductor chip is bonded to the first semiconductor chip by oxide bonding.

8. The semiconductor package according to claim 1, wherein: The at least two semiconductor chips include a first semiconductor chip located at the bottom and a second semiconductor chip on the first semiconductor chip, The first semiconductor chip is bonded to the package substrate via a first adhesive layer, and The second semiconductor chip is bonded to the first semiconductor chip via the second adhesive layer.

9. A semiconductor package, comprising: a package substrate including a substrate pad disposed on an upper surface of an outer portion of the package substrate; A chip stacking structure, comprising at least two semiconductor chips aligned with each other in a vertical direction and stacked on a central portion of a package substrate, wherein each of the at least two semiconductor chips comprises a body layer at a lower portion of the semiconductor chip, an active layer at an upper portion of the semiconductor chip and having a side surface, and a chip pad arranged at the side surface of the active layer; an anisotropic conductive film covering the side surface of the chip stacking structure and the substrate pad on the package substrate, the anisotropic conductive film comprising an adhesive resin and conductive particles; and The conductive pattern film comprises a polymer film and a conductive pattern on the polymer film, wherein the conductive pattern film covers the anisotropic conductive film so that the chip pad is electrically connected to the substrate pad through the conductive pattern.

10. The semiconductor package according to claim 9, wherein: The chip pads are arranged at four side surfaces of the active layer of each of the at least two semiconductor chips, Among them, the anisotropic conductive film and the conductive pattern film cover the four side surfaces of the chip stacking structure, and Among them, the anisotropic conductive film and the conductive pattern film extend in a vertical direction on each of the four side surfaces of the chip stacking structure, are bent 90 degrees at the position where the chip stacking structure is joined to the packaging substrate, and extend in a first horizontal direction or a second horizontal direction on the packaging substrate, wherein the second horizontal direction is perpendicular to the first horizontal direction.

11. The semiconductor package according to claim 10, wherein: The conductive pattern is electrically connected to the chip pad or substrate pad through the conductive particles. wherein the conductive pattern extends on each of the four side surfaces of the chip stack structure to electrically connect the corresponding chip pads of the at least two semiconductor chips to each other, and extends in a first horizontal direction or a second horizontal direction on the package substrate to electrically connect the chip pads of the at least two semiconductor chips to the substrate pad, and The conductive pattern includes a plurality of conductive patterns spaced apart from each other in the first horizontal direction or the second horizontal direction on each of the four side surfaces of the chip stack structure.

12. The semiconductor package according to claim 9, wherein: A first semiconductor chip located at the bottom of the at least two semiconductor chips is bonded to the package substrate through an adhesive layer, and The second semiconductor chip of the at least two semiconductor chips is bonded to the first semiconductor chip through oxide bonding or a second adhesive layer.

13. A semiconductor package, comprising: Package substrate; A chip stacking structure, comprising at least two semiconductor chips aligned with each other in a vertical direction and stacked on a package substrate, each of the at least two semiconductor chips having four side surfaces and comprising chip pads arranged at the four side surfaces; an anisotropic conductive film covering a portion of the upper surface of the package substrate and four side surfaces of the chip stacking structure; a conductive pattern film covering the anisotropic conductive film and including a conductive pattern, the conductive pattern electrically connecting the chip pad to the substrate pad of the package substrate; as well as The sealant covers the side surfaces and the upper surface of the chip stacking structure.

14. The semiconductor package according to claim 13, wherein: The anisotropic conductive film and the conductive pattern film extend in a vertical direction on each of the four side surfaces of the chip stacking structure, are bent 90 degrees at the position where the chip stacking structure is joined to the packaging substrate, and extend in a first horizontal direction or a second horizontal direction on the packaging substrate, wherein the second horizontal direction is perpendicular to the first horizontal direction.

15. The semiconductor package according to claim 13, wherein: The at least two semiconductor chips include a first semiconductor chip located at the bottom and a second semiconductor chip on the first semiconductor chip, The first semiconductor chip is bonded to the package substrate via an adhesive layer, and The second semiconductor chip is bonded to the first semiconductor chip by oxide bonding.

16. A method for manufacturing a semiconductor package, the method comprising: providing a plurality of semiconductor chips, each semiconductor chip including a body layer at a lower portion of the semiconductor chip and an active layer at an upper portion of the semiconductor chip, the active layer having a side surface, and each semiconductor chip having a structure in which a chip pad is arranged at the side surface of the active layer; stacking a first semiconductor chip of the plurality of semiconductor chips on a package substrate using an adhesive layer; stacking at least one second semiconductor chip of the plurality of semiconductor chips on the first semiconductor chip to be aligned with the first semiconductor chip in a vertical direction to form a chip stack structure including the first semiconductor chip and the at least one second semiconductor chip; attaching an anisotropic conductive film on at least one side surface of the chip stack structure and a portion of an upper surface of a package substrate; attaching a conductive pattern film on the anisotropic conductive film, the conductive pattern film including a conductive pattern; and forming a sealant covering the side surfaces and the upper surface of the chip stack structure, The step of attaching the conductive pattern film to the anisotropic conductive film includes electrically connecting the chip pad to the substrate pad of the package substrate using the conductive pattern.

17. The method according to claim 16, wherein: The step of providing the plurality of semiconductor chips comprises: forming the plurality of semiconductor chips in a wafer in which scribe lines are arranged to contact chip pads; grinding the backside surface of the wafer; attaching the backside surface of the wafer to a dicing tape of a ring mounting apparatus; coating the upper surface of the wafer with a protective film; Remove the scribe line with a laser or a blade; removing the remaining portion of the scribe line using plasma cutting; and Remove the protective film.

18. The method according to claim 16, wherein: The step of stacking the at least one second semiconductor chip on the first semiconductor chip includes bonding the second semiconductor chip of the at least one second semiconductor chip to the first semiconductor chip by oxide bonding.

19. The method according to claim 18, wherein: The step of bonding the second semiconductor chip to the first semiconductor chip by oxide bonding includes: forming OH dangling bonds by performing plasma treatment and deionized water cleaning on at least one of the second semiconductor chip and the first semiconductor chip; forming a hydrogen bond by stacking a second semiconductor chip on the first semiconductor chip; and An oxide bond is formed between the first semiconductor chip and the second semiconductor chip using high temperature annealing.

20. The method according to claim 16, wherein: The step of attaching the conductive pattern film on the anisotropic conductive film is performed using heat and pressure, and The conductive pattern is electrically connected to the chip pad using conductive particles of an anisotropic conductive film.

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