A tunable laser driver circuit

Abstract

The application discloses a driving circuit of an adjustable laser, which comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a tenth resistor, a first operational amplifier, a second operational amplifier, a third digital potentiometer, a fourth operational amplifier, a first triode and a first stabilized voltage diode; one end of the first resistor, one end of the fourth resistor and a power supply are connected; the other end of the first resistor, the cathode of the first stabilized voltage diode and the non-inverting terminal of the second operational amplifier are connected; the inverting terminal of the second operational amplifier and one end of the second resistor and one end of the third resistor are connected; the output terminal of the second operational amplifier and the other end of the second resistor and the inverting terminal of the first operational amplifier are connected; the output terminal of the first operational amplifier and one end of the tenth resistor and the second pin of the third digital potentiometer are connected; and the seventh pin of the third digital potentiometer and one end of the fifth resistor are connected.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of laser, in particular to a kind of adjustable laser drive circuit. BACKGROUND

[0002] Publication No.: CN117650425A discloses a kind of adjustable laser drive circuit and laser, can generate MOS tube multiple drive signals by FPGA, input the current controlled by superposition module into laser, but due to the inside of laser is composed of photosensitive element, element is exported by photo-coupler between, its element is very high to the stability requirement of current and voltage of power supply, and the output deviation caused by the floating voltage of switch tube power supply in drive signal cannot be avoided, the existing processing mode is to realize stability by capacitor filtering, when capacitor voltage balance, still voltage appears floating in certain range when the AC (pulsating component) ripple of direct current power supply appears, and when laser is blocked, laser is in the state of waiting to excite by bias signal, since the cut-off interval range of element is narrowed, it is also more susceptible to voltage floating, and misfire occurs. SUMMARY

[0003] The application aims at providing a driving circuit of an adjustable laser, which comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a tenth resistor R10, a first operational amplifier U1, a second operational amplifier U2, a third digital potentiometer U3, a fourth operational amplifier U4, a first triode Q1, and a first stabilized diode D1, wherein one end of the first resistor R1, one end of the fourth resistor R4, and a power supply are connected, the other end of the first resistor R1, the cathode of the first stabilized diode D1, and the non-inverting terminal of the second operational amplifier U2 are connected, the inverting terminal of the second operational amplifier U2 and one end of the second resistor R2, one end of the third resistor R3 are connected, the output terminal of the second operational amplifier U2 and the other end of the second resistor R2, the inverting terminal of the first operational amplifier U1 are connected, the output terminal of the first operational amplifier U1 and one end of the tenth resistor R10, the second pin of the third digital potentiometer U3 are connected, the seventh pin of the third digital potentiometer U3 and one end of the fifth resistor R5 are connected, the non-inverting terminal of the first operational amplifier U1, the collector of the first triode Q1, and the third pin of the third digital potentiometer U3 are connected, the emitter of the first triode Q1, one end of the sixth resistor R6, and a driving current signal Out_1 are connected, the base of the first triode Q1, the output terminal of the fourth operational amplifier U4, one end of the seventh resistor R7, and a pulse driving current amplification signal VIN_1 are connected, the inverting terminal of the fourth operational amplifier U4 and the other end of the seventh resistor R7 are connected, the non-inverting terminal of the fourth operational amplifier U4 and a bias signal VIN_2 are connected, the other end of the third resistor R3, the other end of the fifth resistor R5, the other end of the sixth resistor R6, the other end of the tenth resistor R10, the anode of the first stabilized diode D1, the fifth pin of the third digital potentiometer U3, the sixth pin of the third digital potentiometer U3, and a ground terminal are connected.

[0004] Further, it further includes the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, the fifth operational amplifier U5, the sixth operational amplifier U6, the seventh operational amplifier U7, the eighth flip-flop U8, the second MOS tube Q2, the third MOS tube Q3, the fourth transistor Q4, the second thyristor D2, the third thyristor D3, the fourth diode D4, the fifth diode D5, the sixth diode D6, the first solid state relay S1, the one end of the eleventh resistor R11, the source of the third MOS tube Q3, the first pin of the eighth flip-flop U8 and the power supply are connected, the one end of the first solid state relay S1 and the bias signal VIN_2 are connected, the other end of the first solid state relay S1 and the base of the fourth transistor Q4, the cathode of the fourth diode D4, the same phase end of the fourth operational amplifier U4 are connected, the input end of the first solid state relay S1 and the second pin of the eighth flip-flop U8, the sixth pin of the eighth flip-flop U8, the anode of the fifth diode D5 are connected, the cathode of the fifth diode D5 and the one end of the twelfth resistor R12, the fourth pin of the eighth flip-flop U8 are connected, the third pin of the eighth flip-flop U8 and the cathode of the sixth diode D6 are connected, the anode of the sixth diode D6 and the source of the second MOS tube Q2 are connected, the gate of the second MOS tube Q2 and the output end of the seventh operational amplifier U7 are connected, the drain of the second MOS tube Q2 and the output end of the sixth operational amplifier U6 are connected, the inverting end of the sixth operational amplifier U6 and the inverting end of the seventh operational amplifier U7 are connected, the same phase end of the sixth operational amplifier U6 and the one end of the fifteenth resistor R15, the cathode of the third thyristor D3 are connected, the control electrode of the third thyristor D3 and the one end of the thirteenth resistor R13, the drain of the third MOS tube Q3 are connected, the gate of the third MOS tube Q3 and the control electrode of the second thyristor D2, the second pin of the third digital potentiometer U3 are connected, the cathode of the second thyristor D2 and the one end of the fourteenth resistor R14, the same phase end of the seventh operational amplifier U7 are connected, the anode of the second thyristor D2 and the anode of the third thyristor D3, the emitter of the fourth transistor Q4 are connected, the collector of the fourth transistor Q4 and the other end of the eleventh resistor R11 are connected, the anode of the fourth diode D4 and the seventh pin of the third digital potentiometer U3, the output end of the fifth operational amplifier U5 are connected, the same phase end of the fifth operational amplifier U5 and the emitter of the first transistor Q1 are connected, the other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15, the output end of the first solid state relay S1 and the ground are connected.

[0005] Further, the nineteenth resistor R19, the twentieth resistor R20, the twenty-first resistor R21, the twenty-second resistor R22, the ninth operational amplifier U9, the tenth operational amplifier U10, the fifth transistor Q5, the seventh diode D7, the eighth diode D8, the first capacitor C1, the second solid state relay S2 are further included. The fifth transistor Q5 collector electrode is connected with the power supply, the fifth transistor Q5 base electrode is connected with the first transistor Q1 collector electrode, the fifth transistor Q5 emitter electrode is connected with the twentieth resistor R20 one end and the first capacitor C1 one end, the first capacitor C1 other end is connected with the nineteenth resistor R19 one end and the ninth operational amplifier U9 non-inverting terminal, the ninth operational amplifier U9 output terminal is connected with the twenty-first resistor R21 one end, the ninth operational amplifier U9 inverting terminal is connected with the twenty-first resistor R21 other end, the twenty-second resistor R22 one end and the tenth operational amplifier U10 inverting terminal, the tenth operational amplifier U10 output terminal is connected with the second solid state relay S2 one end, the second solid state relay S2 other end is connected with the seventh diode D7 anode and the eighth diode D8 anode, the seventh diode D7 cathode is connected with the sixth diode D6 cathode, the eighth diode D8 cathode is connected with the fifth diode D5 cathode, the second solid state relay S2 input terminal is connected with the eighth flip-flop U8 fifth pin, the nineteenth resistor R19 other end, the twentieth resistor R20 other end, the twenty-second resistor R22 other end, the second solid state relay S2 output terminal and the ground terminal are connected.

[0006] Further, the eighth resistor R8, the ninth resistor R9, the sixteenth resistor R16, the seventeenth resistor R17 are further included. The ninth resistor R9 one end and the seventeenth resistor R17 one end are connected with the power supply, the ninth resistor R9 other end is connected with the eighth resistor R8 one end and the fifth operational amplifier U5 inverting terminal, the seventeenth resistor R17 other end is connected with the sixteenth resistor R16 one end and the sixth operational amplifier U6 inverting terminal, the eighth resistor R8 other end and the sixteenth resistor R16 other end are connected with the ground terminal.

[0007] Further, the eighteenth resistor R18 is further included. The eighteenth resistor R18 one end is connected with the seventh operational amplifier U7 output terminal, the eighteenth resistor R18 other end is connected with the ground terminal.

[0008] Further, the twenty-third resistor R23, the twenty-fourth resistor R24 are further included. The twenty-third resistor R23 one end is connected with the power supply, the twenty-third resistor R23 other end is connected with the twenty-fourth resistor R24 one end and the tenth operational amplifier U10 non-inverting terminal, the twenty-fourth resistor R24 other end is connected with the ground terminal.

[0009] Further, the second resistor R2 is an adjustable resistor. The second resistor R2 tap terminal is connected with the second operational amplifier U2 inverting terminal.

[0010] The present application has the following advantages compared with the prior art:

[0011] The present application can avoid the floating of the filtered power supply voltage when the AC ripple appears, and can prevent the mis-triggering problem caused by the voltage floating range exceeding the cutoff interval of the element when the static working point of the laser is changed by the bias signal and the cutoff interval range of the element is narrowed after the laser quickly enters the excited state. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the prior art and the drawings needed to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0013] Figure 1 The circuit structure schematic diagram provided by the present application. DETAILED DESCRIPTION

[0014] In order to make the objects and advantages of the present application more clear, the present application will be specifically described below in combination with the embodiments. It should be understood that the following description is only used to describe one or several specific embodiments of the present application, and does not strictly limit the protection scope of the present application.

[0015] The application discloses a kind of adjustable laser driving circuit, including first resistance R1, second resistance R2, third resistance R3, fourth resistance R4, fifth resistance R5, sixth resistance R6, seventh resistance R7, tenth resistance R10, first operational amplifier U1, second operational amplifier U2, third digital potentiometer U3, fourth operational amplifier U4, first triode Q1, first stabilizing diode D1, the first resistance R1 one end, fourth resistance R4 one end and power supply are connected, first resistance R1 other end and first stabilizing diode D1 cathode, second operational amplifier U2 same phase terminal are connected, second operational amplifier U2 opposite phase terminal and second resistance R2 one end, third resistance R3 one end are connected, second operational amplifier U2 output and second resistance R2 other end, first operational amplifier U1 opposite phase terminal are connected, first operational amplifier U1 output and tenth resistance R10 one end, third digital potentiometer U3 second pin are connected, third digital potentiometer U3 seventh pin and fifth resistance R5 one end are connected, first operational amplifier U1 same phase terminal and fourth resistance R4 other end, first triode Q1 collector, third digital potentiometer U3 third pin are connected, first triode Q1 emitter, sixth resistance R6 one end and drive current signal Out_1 are connected, first triode Q1 base, fourth operational amplifier U4 output, seventh resistance R7 one end and pulse drive current amplification signal VIN_1 are connected, fourth operational amplifier U4 opposite phase terminal and seventh resistance R7 other end are connected, fourth operational amplifier U4 same phase terminal and bias signal VIN_2 are connected, third resistance R3 other end, fifth resistance R5 other end, sixth resistance R6 other end, tenth resistance R10 other end, first stabilizing diode D1 anode, third digital potentiometer U3 fifth pin, third digital potentiometer U3 sixth pin and ground terminal are connected.

[0016] Specifically, it further includes the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, the fifth operational amplifier U5, the sixth operational amplifier U6, the seventh operational amplifier U7, the eighth flip-flop U8, the second MOS tube Q2, the third MOS tube Q3, the fourth transistor Q4, the second thyristor D2, the third thyristor D3, the fourth diode D4, the fifth diode D5, the sixth diode D6, the first solid state relay S1, one end of the eleventh resistor R11, the source electrode of the third MOS tube Q3, the first pin of the eighth flip-flop U8 and the power supply are connected, one end of the first solid state relay S1 and the bias signal VIN_2 are connected, the other end of the first solid state relay S1 and the base electrode of the fourth transistor Q4, the cathode of the fourth diode D4, the non-inverting terminal of the fourth operational amplifier U4 are connected, the input end of the first solid state relay S1 and the second pin of the eighth flip-flop U8, the sixth pin of the eighth flip-flop U8, the anode of the fifth diode D5 are connected, the cathode of the fifth diode D5 and one end of the twelfth resistor R12, the fourth pin of the eighth flip-flop U8 are connected, the third pin of the eighth flip-flop U8 and the cathode of the sixth diode D6 are connected, the anode of the sixth diode D6 and the source electrode of the second MOS tube Q2 are connected, the gate electrode of the second MOS tube Q2 and the output end of the seventh operational amplifier U7 are connected, the drain electrode of the second MOS tube Q2 and the output end of the sixth operational amplifier U6 are connected, the non-inverting terminal of the sixth operational amplifier U6 and the inverting terminal of the seventh operational amplifier U7 are connected, the inverting terminal of the sixth operational amplifier U6 and one end of the fifteenth resistor R15, the cathode of the third thyristor D3 are connected, the control electrode of the third thyristor D3 and one end of the thirteenth resistor R13, the drain electrode of the third MOS tube Q3 are connected, the gate electrode of the third MOS tube Q3 and the control electrode of the second thyristor D2, the second pin of the third digital potentiometer U3 are connected, the cathode of the second thyristor D2 and one end of the fourteenth resistor R14, the non-inverting terminal of the seventh operational amplifier U7 are connected, the anode of the second thyristor D2 and the anode of the third thyristor D3, the emitter electrode of the fourth transistor Q4 are connected, the collector electrode of the fourth transistor Q4 and the other end of the eleventh resistor R11 are connected, the anode of the fourth diode D4 and the seventh pin of the third digital potentiometer U3, the output end of the fifth operational amplifier U5 are connected, the non-inverting terminal of the fifth operational amplifier U5 and the emitter electrode of the first transistor Q1 are connected, the other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15, the output end of the first solid state relay S1 and the ground are connected.

[0017] Specifically, it further includes the nineteenth resistance R19, the twentieth resistance R20, the twenty-first resistance R21, the twenty-second resistance R22, the ninth operational amplifier U9, the tenth operational amplifier U10, the fifth transistor Q5, the seventh diode D7, the eighth diode D8, the first capacitor C1, the second solid state relay S2, the fifth transistor Q5 collector and power supply are connected, the fifth transistor Q5 base and the first transistor Q1 collector are connected, the fifth transistor Q5 emitter and the twentieth resistance R20 one end, the first capacitor C1 one end are connected, the first capacitor C1 other end and the nineteenth resistance R19 one end, the ninth operational amplifier U9 non-inverting terminal are connected, the ninth operational amplifier U9 output and the twenty-first resistance R21 one end are connected, the ninth operational amplifier U9 inverting terminal and the twenty-first resistance R21 other end, the twenty-second resistance R22 one end, the tenth operational amplifier U10 inverting terminal are connected, the tenth operational amplifier U10 output and the second solid state relay S2 one end are connected, the second solid state relay S2 other end and the seventh diode D7 anode, the eighth diode D8 anode are connected, the seventh diode D7 cathode and the sixth diode D6 cathode are connected, the eighth diode D8 cathode and the fifth diode D5 cathode are connected, the second solid state relay S2 input and the eighth flip-flop U8 fifth pin are connected, the nineteenth resistance R19 other end, the twentieth resistance R20 other end, the twenty-second resistance R22 other end, the second solid state relay S2 output and the ground are connected.

[0018] Specifically, it further includes the eighth resistance R8, the ninth resistance R9, the sixteenth resistance R16, the seventeenth resistance R17, the ninth resistance R9 one end, the seventeenth resistance R17 one end and the power supply are connected, the ninth resistance R9 other end and the eighth resistance R8 one end, the fifth operational amplifier U5 inverting terminal are connected, the seventeenth resistance R17 other end and the sixteenth resistance R16 one end, the sixth operational amplifier U6 inverting terminal are connected, the eighth resistance R8 other end, the sixteenth resistance R16 other end and the ground are connected.

[0019] Specifically, it further includes the eighteenth resistance R18, the eighteenth resistance R18 one end and the seventh operational amplifier U7 output are connected, the eighteenth resistance R18 other end and the ground are connected.

[0020] Specifically, it further includes the twenty-third resistance R23, the twenty-fourth resistance R24, the twenty-third resistance R23 one end and the power supply are connected, the twenty-third resistance R23 other end and the twenty-fourth resistance R24 one end, the tenth operational amplifier U10 non-inverting terminal are connected, the twenty-fourth resistance R24 other end and the ground are connected.

[0021] Specifically, the second resistance R2 is an adjustable resistance, and the tap end and the second operational amplifier U2 inverting terminal are connected.

[0022] Considering the power supply filter provides a power supply voltage after filtering the point voltage balance, but the AC ripple in the power supply when it appears, the voltage will still appear ripple float, so the power supply after filtering through the first resistor R1, the first voltage regulator diode D1 voltage input to the second operational amplifier U2 in-phase terminal, the second operational amplifier U2 inverting terminal and the third resistor R3, the second resistor R2 negative feedback amplification input to the first operational amplifier U1 to provide a reference voltage, while the power supply through the fourth resistor R4, the third digital potentiometer U3 to the first transistor Q1 power supply, the first transistor Q1 base input pulse drive current signal amplification signal VIN_1, Out_1 in the output drive current signal to the laser, change the duty cycle of the VIN_1 signal input to control the current Out_1 output to the laser, when the AC ripple appears voltage jump, the first operational amplifier U1 compared to the reference voltage and the supply voltage and output signal to the third digital potentiometer U3 second pin, control the third digital potentiometer U3 adjustment state, change the fourth resistor R4 and the third digital potentiometer U3 voltage division coefficient, change the supply voltage to offset the floating deviation voltage, prevent the pulse drive current signal amplification signal VIN_1 input, Out_1 output drive current signal and preset does not conform to, when the laser is in the blocking state, VIN_2 input bias signal, and through the fourth operational amplifier U4 and the seventh resistor R7 followed by input to the first transistor Q1, the third digital potentiometer U3 initial state third pin in this embodiment through the fifth resistor R5 loop.

[0023] Considering that the bias signal is changed when the laser is blocked, the static working voltage of the laser is in the standby state, although it can make the laser quickly enter the excited state, but the cutoff interval range of the element is also narrowed, which is more susceptible to voltage floating, and mis-triggering occurs. Therefore, on the basis of the above, when the pulse driving current signal amplification signal VIN_1 is input, the fifth operational amplifier U5 is used to detect whether the laser is in the emission state. The signal output by the fifth operational amplifier U5 is fed back to the seventh pin of the third digital potentiometer U3, which closes the third digital potentiometer U3 adjustment. Another way is input to the fourth transistor Q4 base through the fourth diode D4. At the same time, the output of the first operational amplifier U1 is also connected to the gate of the third MOS tube Q3 and the control electrode of the second thyristor D2. When the third digital potentiometer U3 is closed and the power supply appears floating, the second thyristor D2 or the third MOS tube Q3 is turned on at this time. When the first operational amplifier U1 outputs, the signal is fed back to the control electrode of the second thyristor D2 through the fourteenth resistor R14 loop, and the second thyristor D2 is turned on. The other way is fed back to the gate of the third MOS tube Q3, and the third MOS tube Q3 is cut off. After the eleventh resistor R11 power supply is connected through the fourth transistor Q4 collector, emitter, anode and cathode of the second thyristor D2, the fourteenth resistor R14, the ground terminal loop, the voltage at the fourteenth resistor R14 end is fed back to the same phase end of the seventh operational amplifier U7, and the output of the seventh operational amplifier U7 is obtained. In this embodiment, the bias signal input by VIN_2 is input through the first solid-state relay S1, instead of being directly input to the same phase end of the fourth operational amplifier U4. When the first operational amplifier U1 is cut off, the third MOS tube Q3 is turned on. After the eleventh resistor R11 power supply is connected through the fourth transistor Q4 collector, emitter, drain of the third MOS tube Q3, source of the third MOS tube Q3, thirteenth resistor R13 loop, the voltage at the thirteenth resistor R13 end is connected through the control electrode of the third thyristor D3 and the fifteenth resistor R15, and the voltage at the fifteenth resistor R15 end is fed back to the same phase end of the sixth operational amplifier U6. The output signal of the sixth operational amplifier U6 is input to the source of the second MOS tube Q2, and the output signal of the seventh operational amplifier U7 is input to the gate of the second MOS tube Q2. The second MOS tube Q2 is turned on, and the source signal is input to the third pin of the eighth flip-flop U8 through the drain and the sixth diode D6. The sixth pin of the eighth flip-flop U8 is cut off, the fifth pin is output, the first solid-state relay S1 is disconnected, the fourth pin of the eighth flip-flop U8 is pulled down through the twelfth resistor R12, and the VIN_2 input bias signal is locked and cut off to prevent the bias signal from being input to the base of the first transistor Q1 after the voltage floating, and the driving current signal output by Out_1 exceeds the cutoff interval range of the laser to trigger.

[0024] Considering the uncertainty of floating, the control by fixed time reset is not accurate, therefore, on the basis of the above-mentioned circuit, the output of the fifth operational amplifier U5 is also fed back to the second solid-state relay S2, the voltage at the third pin of the third digital potentiometer U3 is fed back to the fifth transistor Q5, when the pulse driving current signal amplification signal VIN_1 is output, if there is no floating, the first capacitor C1 is decoupled through the twentieth resistor R20, and the input signal of the fifth transistor Q5 is isolated, the ninth operational amplifier U9 has no output, and the tenth operational amplifier U10 outputs a signal, when floating occurs, the first capacitor C1 couples the floating signal to the ninth operational amplifier U9, the voltage at the same phase end of the ninth operational amplifier U9 changes, is amplified through the twenty-first resistor R21 and the twenty-second resistor R22, and is then input to the opposite phase end of the tenth operational amplifier U10, the tenth operational amplifier U10 is cut off after comparing the reference signal at the same phase end, at the same time, the fifth pin output of the eighth flip-flop U8 makes the second solid-state relay S2 conduct, and the first capacitor C1 has a time lag for the floating occurring in the same time period, when there is no floating, after the coupling signal of the first capacitor C1 is discharged through the nineteenth resistor R19, the ninth operational amplifier U9 is cut off, the output signal of the tenth operational amplifier U10 is input to the third pin of the eighth flip-flop U8 through the second solid-state relay S2 and the seventh diode D7, and is input to the fourth pin of the eighth flip-flop U8 through the eighth diode D8, the sixth pin output of the eighth flip-flop U8 is cut off, and the fifth pin is reset, completing the reset. The reference voltage at the same phase end of the tenth operational amplifier U10, the opposite phase end of the fifth operational amplifier U5, the opposite phase end of the sixth operational amplifier U6 and the opposite phase end of the seventh operational amplifier U7 can be set through the voltage dividing resistor in addition to the input through the power supply, wherein the opposite phase end of the fifth operational amplifier U5 and the opposite phase end of the sixth operational amplifier U6 are connected in parallel, and the eighteenth resistor R18 is used for the internal parasitic capacitor loop of the second MOS transistor Q2.

[0025] It is apparent for those skilled in the art that the present application is not limited to the details of the above-mentioned exemplary embodiments, but can be implemented in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and not restrictive, the scope of the present application being defined by the appended claims rather than the above-mentioned description, and it is intended to embrace all changes and modifications that fall within the meaning and scope of equivalents of the claims. Any reference signs in the claims should not be construed as limiting the claims to which they belong.

Claims

1. A driving circuit of a tunable laser, characterized by, The first resistance, the second resistance, the third resistance, the fourth resistance, the fifth resistance, the sixth resistance, the seventh resistance, the tenth resistance, the first operational amplifier, the second operational amplifier, the third digital potentiometer, the fourth operational amplifier, the first triode, the first stabilized diode, the eleventh resistance, the twelfth resistance, the thirteenth resistance, the fourteenth resistance, the fifteenth resistance, the fifth operational amplifier, the sixth operational amplifier, the seventh operational amplifier, the eighth flip-flop, the second MOS tube, the third MOS tube, the fourth triode, the second thyristor, the third thyristor, the fourth diode, the fifth diode, the sixth diode, the first solid-state relay; One end of the first resistor and one end of the fourth resistor are connected to the power supply, the other end of the first resistor is connected to the cathode of the first voltage stabilizing diode and the non-inverting end of the second operational amplifier, the inverting end of the second operational amplifier is connected to one end of the second resistor and one end of the third resistor, the output end of the second operational amplifier is connected to the other end of the second resistor and the inverting end of the first operational amplifier, the output end of the first operational amplifier is connected to one end of the tenth resistor and the second pin of the third digital potentiometer, the seventh pin of the third digital potentiometer is connected to one end of the fifth resistor, the non-inverting end of the first operational amplifier is connected to the other end of the fourth resistor, the collector of the first transistor, and the third pin of the third digital potentiometer, the emitter of the first transistor, one end of the sixth resistor and the drive current signal Ou t_1 is connected, the base of the first transistor, the output terminal of the fourth operational amplifier, one end of the seventh resistor and the pulse drive current amplification signal VIN_1 are connected, the inverting terminal of the fourth operational amplifier and the other end of the seventh resistor are connected, the non-inverting terminal of the fourth operational amplifier and the bias signal VIN_2 are connected, the other end of the third resistor, the other end of the fifth resistor, the other end of the sixth resistor, the other end of the tenth resistor, the anode of the first voltage regulator diode, the fifth pin of the third digital potentiometer, the sixth pin of the third digital potentiometer and the ground terminal are connected, the first pin of the eighth trigger is connected to the power supply, one end of the first solid-state relay is connected to the bias signal VIN_2, the other end of the first solid-state relay and the base of the fourth transistor, the cathode of the fourth diode, the The non-inverting terminal of the fourth operational amplifier is connected, the input terminal of the first solid-state relay is connected to the second pin of the eighth trigger, the sixth pin of the eighth trigger, and the anode of the fifth diode are connected, the cathode of the fifth diode is connected to one end of the twelfth resistor and the fourth pin of the eighth trigger, the third pin of the eighth trigger is connected to the cathode of the sixth diode, the anode of the sixth diode is connected to the source of the second MOS tube, the gate of the second MOS tube is connected to the output terminal of the seventh operational amplifier, the drain of the second MOS tube is connected to the output terminal of the sixth operational amplifier, the inverting terminal of the sixth operational amplifier is connected to the inverting terminal of the seventh operational amplifier, the non-inverting terminal of the sixth operational amplifier is connected to one end of the fifteenth resistor and the cathode of the third thyristor, the control electrode of the third thyristor is connected to the thirteenth resistor The first terminal of the first transistor is connected to the first MOSFET, the second terminal of the second MOSFET is connected to the first transistor, the second terminal of the first transistor is connected to the second MOSFET, the first terminal of the second MOSFET is connected to the first transistor, and the first MOSFET is connected to the second transistor. The first terminal of the first transistor is connected to the first MOSFET, and the first MOSFET is connected to the second transistor. The first terminal of the first transistor is connected to the first MOSFET, and the first MOSFET is connected to the first transistor. The first terminal of the first transistor is connected to the first MOSFET, and the first MOSFET is connected to the first transistor. The first terminal of the first transistor is connected to the first MOSFET, and the first MOSFET is connected to the first transistor.

2. The driving circuit of a tunable laser according to claim 1, wherein, The ninth resistor, the tenth resistor, the twenty-first resistor, the twenty-second resistor, the ninth operational amplifier, the tenth operational amplifier, the fifth transistor, the seventh diode, the eighth diode, the first capacitor, the second solid state relay, the fifth transistor collector and the power supply are connected, the fifth transistor base and the first transistor collector are connected, the fifth transistor emitter and one end of the twentieth resistor and one end of the first capacitor are connected, the other end of the first capacitor and one end of the nineteenth resistor and the non-inverting terminal of the ninth operational amplifier are connected, the output terminal of the ninth operational amplifier and one end of the twenty-first resistor are connected, the inverting terminal of the ninth operational amplifier and the other end of the twenty-first resistor, one end of the twenty-second resistor and the inverting terminal of the tenth operational amplifier are connected, the output terminal of the tenth operational amplifier and one end of the second solid state relay are connected, the other end of the second solid state relay and the anode of the seventh diode and the anode of the eighth diode are connected, the cathode of the seventh diode and the cathode of the sixth diode are connected, the cathode of the eighth diode and the cathode of the fifth diode are connected, the input terminal of the second solid state relay and the fifth pin of the eighth flip-flop are connected, and the other end of the nineteenth resistor, the other end of the twentieth resistor, the other end of the twenty-second resistor, the output terminal of the second solid state relay and the ground terminal are connected.

3. The driving circuit of a tunable laser according to claim 1, wherein, The eighth resistor, the ninth resistor, the sixteenth resistor, the seventeenth resistor, one end of the ninth resistor and one end of the seventeenth resistor and the power supply are connected, the other end of the ninth resistor and one end of the eighth resistor and the inverting terminal of the fifth operational amplifier are connected, the other end of the seventeenth resistor and one end of the sixteenth resistor and the inverting terminal of the sixth operational amplifier are connected, and the other end of the eighth resistor, the other end of the sixteenth resistor and the ground terminal are connected.

4. The driving circuit of a tunable laser according to claim 1, wherein, The eighteenth resistor, one end of the eighteenth resistor and the output terminal of the seventh operational amplifier are connected, and the other end of the eighteenth resistor and the ground terminal are connected.

5. The driving circuit of a tunable laser according to claim 2, wherein, The twenty-third resistor, the twenty-fourth resistor, one end of the twenty-third resistor and the power supply are connected, the other end of the twenty-third resistor and one end of the twenty-fourth resistor and the non-inverting terminal of the tenth operational amplifier are connected, and the other end of the twenty-fourth resistor and the ground terminal are connected.

6. The driving circuit of a tunable laser according to claim 1, wherein, The second resistor is an adjustable resistor, and the tap terminal of the second resistor and the inverting terminal of the second operational amplifier are connected.

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