A chip for self-calibrating operational amplifier offset voltage and offset voltage temperature drift

Abstract

The present application relates to a chip for self-calibrating the offset voltage and offset voltage temperature drift of an operational amplifier. The chip includes an operational amplifier, an on-chip heater, a calibration module, a control module, a first determination module, and a second determination module. The control module controls the connection between the operational amplifier and the calibration module, and the calibration module outputs a first calibration current to perform a first calibration on the offset voltage of the operational amplifier at room temperature. After the first determination module determines that the first calibration is complete, the control module turns on the on-chip heater to heat the chip. After the second determination module determines that the chip is heated to a preset temperature, the calibration module outputs a second calibration current to perform a second calibration on the offset voltage of the operational amplifier at the preset temperature, thereby calibrating the offset voltage temperature drift of the operational amplifier. The chip of the present application can conveniently and quickly calibrate the offset voltage and offset voltage temperature drift of the operational amplifier and is applicable to operational amplifiers of various structures.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular to a chip for self-calibrating operational amplifier offset voltage and offset voltage temperature drift. Background Art

[0002] The function of an operational amplifier (AMP) is to amplify the input voltage and output it. Op amps are the foundation of analog circuits, and most applications involving analog circuits cannot do without them. For an ideal op amp, its positive and negative input voltage amplification components should be completely symmetrical. If the positive and negative input terminals are short-circuited, the output voltage should be zero. However, due to the randomness of the actual manufacturing process, the symmetry between the positive and negative input terminals of an op amp is not perfect. When the positive and negative input terminals are short-circuited, the output voltage is not zero. The equivalent input voltage obtained by dividing the output voltage by the op amp gain is called the input offset voltage (Vos). The ratio of the change in Vos with temperature, ΔV, to the temperature change, ΔT, is called the temperature drift of input offset voltage (TCVos). Operational amplifiers that use metal-oxide-semiconductor field-effect transistors (MOS) as input transistors have particularly large offset voltages and offset voltage temperature drift. When designing high-precision operational amplifiers, this non-ideality must be addressed and the offset voltage and offset voltage temperature drift must be calibrated. Summary of the Invention

[0003] In view of this, the present application proposes a chip for self-calibrating the offset voltage and offset voltage temperature drift of an operational amplifier and a self-calibration method for the offset voltage and offset voltage temperature drift of an operational amplifier, which can conveniently and quickly automatically calibrate the offset voltage and offset voltage temperature drift of the operational amplifier.

[0004] According to one aspect of the present application, a chip for self-calibrating offset voltage and offset voltage temperature drift of an operational amplifier is provided, the chip comprising an operational amplifier, an on-chip heater, a calibration module, a control module, a first determination module, and a second determination module; the control module is used to control the connection between the positive input terminal and the negative input terminal of the operational amplifier, or to input the same voltage to the positive input terminal and the negative input terminal of the operational amplifier; and to control the connection between the operational amplifier and the calibration module; the calibration module is used to output a first calibration current to the operational amplifier in response to the connection between the operational amplifier and the calibration module, so as to perform a first calibration of the offset voltage of the operational amplifier; the first determination module module, for outputting a first determination signal to the control module when determining that the first calibration is completed; the control module is further configured to, in response to the first determination signal, turn on the on-chip heater to heat the chip; the second determination module is configured to output a second determination signal to the control module and the calibration module when determining that the chip is heated to a preset temperature; the control module is further configured to turn off the on-chip heater in response to the second determination signal; the calibration module is further configured to output a second calibration current to the operational amplifier in response to the second determination signal to perform a second calibration of the offset voltage of the operational amplifier, thereby achieving calibration of the offset voltage temperature drift of the operational amplifier.

[0005] In a possible implementation, the on-chip heater includes a serpentine metal on-chip heater made using a top metal layer of the chip.

[0006] In one possible implementation, the calibration module includes a comparison submodule, a successive approximation logic submodule, and a current conversion submodule; a first input terminal of the comparison submodule is connected to the positive output terminal of the operational amplifier; a second input terminal of the comparison submodule is connected to the negative output terminal of the operational amplifier; an output terminal of the comparison submodule is connected to the input terminal of the successive approximation logic submodule; an output terminal of the successive approximation logic submodule is connected to the input terminal of the current conversion submodule; and an output terminal of the current conversion submodule is connected to the operational amplifier; wherein, controlling the connection between the operational amplifier and the calibration module includes: controlling the connection between the positive output terminal of the operational amplifier and the first input terminal of the comparison submodule, and controlling the connection between the negative output terminal of the operational amplifier and the second input terminal of the comparison submodule.

[0007] In one possible implementation, the current conversion submodule includes a first current-type digital-to-analog converter, a second current-type digital-to-analog converter, a first switch, and a second switch; the first end of the first switch is connected to the first end of the second switch, constituting the input end of the current conversion submodule; the output end of the first current-type digital-to-analog converter is connected to the output end of the second current-type digital-to-analog converter, constituting the output end of the current conversion submodule; the second end of the first switch is connected to the input end of the first current-type digital-to-analog converter; the second end of the second switch is connected to the input end of the second current-type digital-to-analog converter; wherein, controlling the connection between the operational amplifier and the calibration module also includes: controlling the first switch to close and the second switch to open; the control module is also used to control the second switch to close in response to the second determination signal.

[0008] In a possible implementation, the output current of the first current-mode digital-to-analog converter does not change with temperature; and the output current of the second current-mode digital-to-analog converter is proportional to the absolute temperature.

[0009] In one possible implementation, the first current-type digital-to-analog converter is an N-bit current-type digital-to-analog converter; N≥2; the comparison submodule is used to compare the positive output voltage output by the positive output terminal of the operational amplifier received by the first input terminal and the negative output voltage output by the negative output terminal of the operational amplifier received by the second input terminal N times in response to the connection between the operational amplifier and the calibration module, and output a first comparison signal based on the comparison result; the successive approximation logic submodule is used to generate a first current control signal based on successive approximation logic according to the first comparison signal; the first current control signal includes an N-bit binary code; the first current-type digital-to-analog converter is used to generate the first calibration current according to the first current control signal, and output the first calibration current to the operational amplifier.

[0010] In a possible implementation, the first determination module includes a counter; the counter is used to count the number of comparisons of the comparison submodule; the first determination module is further used to determine that the first calibration is completed when the counter counts the number of comparisons to N times.

[0011] In one possible implementation, the second current-type digital-to-analog converter is an N-bit current-type digital-to-analog converter; the comparison submodule is further used to compare the positive output voltage and the negative output voltage N times in response to the second determination signal, and output a second comparison signal based on the comparison result; the successive approximation logic submodule is further used to generate a second current control signal based on successive approximation logic according to the second comparison signal; the second current control signal includes an N-bit binary code; the second current-type digital-to-analog converter is used to generate the second calibration current according to the second current control signal, and output the second calibration current to the operational amplifier.

[0012] In one possible implementation, the second determination module includes a timer: the timer is used to time the heating time of the chip heated by the on-chip heater; the second determination module is also used to determine that the chip is heated to the preset temperature when it is determined based on the timing of the timer that the heating time reaches the preset heating time; or, the second determination module includes a temperature sensor: the temperature sensor is used to detect the temperature of the chip and send the detected chip temperature to the second determination module; the second determination module is also used to determine that the chip is heated to the preset temperature when it is determined that the chip temperature reaches the preset temperature.

[0013] According to another aspect of the present application, a self-calibration method for the offset voltage and offset voltage temperature drift of an operational amplifier is provided, which is applied to the above-mentioned chip; the method includes: controlling the connection between the positive input terminal and the negative input terminal of the operational amplifier, or inputting the same voltage to the positive input terminal and the negative input terminal of the operational amplifier; and controlling the connection between the operational amplifier and the calibration module; when it is determined that the connection between the operational amplifier and the calibration module is connected, inputting a first calibration current into the operational amplifier to perform a first calibration of the offset voltage of the operational amplifier; when it is determined that the first calibration is completed, turning on the on-chip heater to heat the chip; when it is determined that the chip is heated to a preset temperature, turning off the on-chip heater and inputting a second calibration current into the operational amplifier to perform a second calibration of the offset voltage of the operational amplifier, thereby achieving calibration of the offset voltage temperature drift of the operational amplifier.

[0014] The chip of the present application can quickly and conveniently automatically calibrate the offset voltage and offset voltage temperature drift of an operational amplifier with the help of an on-chip heater. By calibrating the offset voltage of the operational amplifier twice, when the chip is at room temperature (i.e., the temperature before the chip is heated) and at a preset temperature, the offset voltage and offset voltage temperature drift of the operational amplifier can be maintained at a low level over a large temperature range. The chip is applicable to operational amplifiers of various structures and has a wider range of applications.

[0015] Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the application and, together with the description, serve to explain the principles of the application.

[0017] Figure 1 A schematic structural diagram of a chip for self-calibrating offset voltage and offset voltage temperature drift of an operational amplifier according to an embodiment of the present application is shown.

[0018] Figure 2 A schematic diagram illustrating an on-chip heater according to an embodiment of the present application is shown.

[0019] Figure 3 A schematic structural diagram of a calibration module according to an embodiment of the present application is shown.

[0020] Figure 4 A flow chart of a method for self-calibrating offset voltage and offset voltage temperature drift of an operational amplifier according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] Various exemplary embodiments, features, and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0022] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0023] In addition, numerous specific details are provided in the detailed description below to better illustrate the present application. Those skilled in the art will appreciate that the present application can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present application.

[0024] Current calibration methods for op amp input offset voltage and input offset voltage temperature drift can be categorized into two types: dynamic calibration and static calibration. Dynamic calibration methods utilize clocks and switches to shift low-frequency offset voltages to high frequencies for calibration. Static calibration methods do not utilize dynamic modules such as clocks and switches. For op amps integrated on a chip, most existing static calibration methods require the use of off-chip heating equipment (such as a furnace) to heat the chip to be calibrated to a high temperature in order to calibrate the offset voltage temperature drift. Currently, static calibration methods that do not utilize off-chip heating equipment are only applicable to certain specialized amplifier structures and can only calibrate off two-thirds of the offset voltage temperature drift, resulting in a narrow application range and poor calibration results.

[0025] In view of this, the present application proposes a chip for self-calibrating the offset voltage and offset voltage temperature drift of an operational amplifier and a self-calibration method for the offset voltage and offset voltage temperature drift of an operational amplifier. The offset voltage and offset voltage temperature drift of the operational amplifier can be calibrated by using an on-chip heater instead of an off-chip heating device. The chip is suitable for various operational amplifier structures, has a wider range of applications and better calibration effects.

[0026] Figure 1 FIG. 1 shows a schematic structural diagram of a chip for self-calibrating offset voltage and offset voltage temperature drift of an operational amplifier according to an embodiment of the present application. Figure 1 As shown, the chip 100 may include an operational amplifier 101 , an on-chip heater 102 , a calibration module 103 , a control module 104 , a first determination module 105 , and a second determination module 106 .

[0027] The control module 104 is used to control the positive input terminal (ie Figure 1 Vi+) and the negative input terminal (i.e. Figure 1 The connection between the positive input terminal and the negative input terminal of the operational amplifier 101 is turned on, or the same voltage is input to the positive input terminal and the negative input terminal of the operational amplifier 101; and the connection between the operational amplifier 101 and the calibration module 103 is turned on;

[0028] The calibration module 103 is configured to output a first calibration current to the operational amplifier 101 in response to the connection between the operational amplifier 101 and the calibration module 103 being turned on, so as to perform a first calibration on the offset voltage of the operational amplifier 101;

[0029] A first determination module 105 is configured to output a first determination signal to the control module 104 when determining that the first calibration is completed;

[0030] The control module 104 is further configured to, in response to the first determination signal, turn on the on-chip heater 102 to heat the chip 100 ;

[0031] The second determination module 106 is configured to output a second determination signal to the control module 104 and the calibration module 103 when determining that the chip 100 is heated to a preset temperature;

[0032] The control module 104 is further configured to turn off the on-chip heater 102 in response to the second determination signal;

[0033] The calibration module 103 is further configured to output a second calibration current to the operational amplifier 101 in response to the second determination signal, so as to perform a second calibration on the offset voltage of the operational amplifier 101 , thereby calibrating the offset voltage temperature drift of the operational amplifier 101 .

[0034] The on-chip heater is a micro heating element integrated on a chip. For example, the on-chip heater 102 may include a metal on-chip heater made of a top metal layer of the chip and may be designed in a serpentine shape.

[0035] Figure 2 A schematic diagram of an on-chip heater according to an embodiment of the present application is shown. Figure 2 As shown, the gray part represents the chip, and the red part is a serpentine metal on-chip heater made of the top metal of the chip. The sizes of the chip and the on-chip heater can be set according to actual needs. For example, the size of the chip can be 700μm×700μm, and the size of the on-chip heater can be 250μm×250μm. The serpentine metal on-chip heater of the embodiment of the present application can be regarded as a metal wire designed as a serpentine trace. A heating voltage can be connected at both ends of the on-chip heater (i.e., both ends of the metal wire) to generate Joule heat to heat the chip. The heating voltage can be set according to actual needs. For example, one end of the on-chip heater can be connected to 1.8V and the other end to the ground voltage (Ground Voltage, GND). Since heating on the chip requires a large power, if the impedance of the on-chip heater is large, a higher heating voltage is required. In order to avoid using a higher heating voltage and to achieve a larger heating power, the impedance of the on-chip heater needs to be smaller. Since the top metal layer of the chip is thicker and has lower impedance, the embodiment of the present application uses the top metal layer of the chip to make a metal wire as an on-chip heater. The impedance per unit length is small, so that a larger heating power can be achieved at a lower heating voltage. In addition, the metal wire is designed as a serpentine route to heat the chip more evenly.

[0036] For example, the preset temperature can be determined by those skilled in the art according to actual needs. The higher the preset temperature, the better the calibration effect of the offset voltage temperature drift. As an example, the preset temperature can be 50° C. or above.

[0037] The chip of the embodiment of the present application first completes the first calibration of the operational amplifier offset voltage using the calibration module at room temperature (i.e., the temperature before the chip is heated), then turns on the on-chip heater to heat the chip to a preset temperature, and then uses the calibration module to complete the second calibration of the operational amplifier offset voltage at the preset temperature, thereby achieving the calibration of the operational amplifier offset voltage temperature drift. Since the offset voltage is a linear function of temperature, by calibrating the chip twice at low and high temperatures, the offset voltage and offset voltage temperature drift of the operational amplifier can be maintained at a low level within a larger temperature range. Experiments have shown that after calibration, the offset voltage and offset voltage temperature drift of the operational amplifier are significantly reduced within the range of -40°C to 125°C, and the higher the preset temperature (i.e., the higher the temperature to which the chip is heated), the greater the decrease in the operational amplifier offset voltage and offset voltage temperature drift, and the better the calibration effect.

[0038] Existing methods for calibrating operational amplifier chips using off-chip heating equipment can only be performed in the factory, making it difficult for users to return the chips to the factory for calibration after a period of use. The chip of the present embodiment uses an on-chip heater to achieve self-calibration of the operational amplifier offset voltage and offset voltage temperature drift. Users can calibrate the chip themselves after a period of use, making calibration more convenient, faster, and less costly. Furthermore, the chip of the present embodiment is applicable to operational amplifiers of various structures, thus having a wider range of applications.

[0039] In one possible implementation, the calibration module 103 may include a comparison submodule, a successive approximation logic submodule, and a current conversion submodule; the first input terminal of the comparison submodule is connected to the positive output terminal of the operational amplifier 101; the second input terminal of the comparison submodule is connected to the negative output terminal of the operational amplifier 101; the output terminal of the comparison submodule is connected to the input terminal of the successive approximation logic submodule; the output terminal of the successive approximation logic submodule is connected to the input terminal of the current conversion submodule; and the output terminal of the current conversion submodule is connected to the operational amplifier 101.

[0040] Among them, controlling the connection between the operational amplifier 101 and the calibration module 103 may include: controlling the connection between the positive output terminal of the operational amplifier 101 and the first input terminal of the comparison submodule, and controlling the connection between the negative output terminal of the operational amplifier 101 and the second input terminal of the comparison submodule.

[0041] For example, the comparison submodule can be implemented using a comparator (CMP). The two input terminals of the comparator are respectively connected to the positive and negative output terminals of the operational amplifier 101. The comparator can output the positive output voltage Vo of the positive output terminal of the operational amplifier 101. +Compare the magnitude relationship between the positive output voltage Vo+ and the negative output voltage Vo- output from the negative output terminal, and output a comparison signal according to the comparison result. The comparison signal can include a high level (i.e., 1) and a low level (i.e., 0).

[0042] As an example, when Vo + >Vo-, the comparison signal is at a high level, that is, the comparator output is 1; when Vo + <Vo-, the comparison signal is at a low level, that is, the comparator output is 0.

[0043] It should be noted that the comparison sub-module can be implemented using comparators of various structures, and this application does not limit this, as long as the requirements are met.

[0044] Successive Approximation Register (SAR) logic is a logic that achieves successive approximation through binary comparison. Exemplarily, the successive approximation logic sub-module can be implemented using a binary successive approximation logic (SAR Logic) digital circuit, and the specific implementation method can refer to related technologies. The SAR Logic circuit can generate a current control signal based on the successive approximation logic according to the comparison signal output by the comparator, and the current control signal includes multiple-bit binary codes.

[0045] Exemplarily, the current conversion sub-module can be implemented using a Current Digital - Analog Converter (IDAC). The IDAC can generate a calibration current according to the current control signal output by the SAR Logic circuit and inject the calibration current into the operational amplifier 101 to calibrate the offset voltage of the operational amplifier 101. It should be noted that the specific position where the calibration current output by the IDAC is injected into the operational amplifier can be determined according to the structure of the operational amplifier, and this application does not limit this, as long as the offset voltage calibration can be achieved.

[0046] Before calibrating the offset voltage, when the positive and negative input terminals of the operational amplifier are short - circuited or the same voltage is input to the positive and negative input terminals, the positive output voltage Vo + and the negative output voltage Vo- can be compared. If Vo + >Vo-, it indicates that the operational amplifier has a positive offset voltage; if Vo + <Vo-, it indicates that the operational amplifier has a negative offset voltage. Assuming that the calibration current is injected into point A of the operational amplifier, when the operational amplifier has a positive offset voltage, the direction of the injected calibration current is opposite to the current direction at point A of the operational amplifier; when the operational amplifier has a negative offset voltage, the direction of the injected calibration current is the same as the current direction at point A of the operational amplifier.

[0047] Exemplarily, the chip 100 may further include a reference generation module configured to generate a reference voltage and / or a reference current, which may be provided to the IDAC to ensure the accuracy and stability of the output current of the IDAC.

[0048] In a possible implementation, the current conversion submodule may include a first current-type digital-to-analog converter, a second current-type digital-to-analog converter, a first switch, and a second switch.

[0049] Figure 3 FIG. 1 shows a schematic structural diagram of a calibration module according to an embodiment of the present application. Figure 3 As shown, the operational amplifier to be calibrated (i.e. Figure 3 The positive output terminal and negative output terminal of the AMP in the comparator (i.e. Figure 3 The two input terminals of the CMP in the comparator are connected, the output terminal of the comparator is connected to the input terminal of the SAR Logic circuit, the output terminal of the SAR Logic circuit is connected to the input terminal of the current conversion submodule, and the output terminal of the current conversion submodule is connected to the operational amplifier. The current conversion submodule includes a first current-type digital-to-analog converter IDAC0, a second current-type digital-to-analog converter IDAC1, a first switch S1 and a second switch S2. The first terminal of S1 is connected to the first terminal of S2, forming the input terminal of the current conversion submodule; the output terminal of IDAC0 is connected to the output terminal of IDAC1, forming the output terminal of the current conversion submodule; the second terminal of S1 is connected to the input terminal of IDAC0; and the second terminal of S2 is connected to the input terminal of IDAC1. Among them, the output current of IDAC0 does not change with temperature, and the output current of IDAC1 is proportional to the absolute temperature (i.e., Kelvin temperature). The specific implementation of IDAC0 and IDAC1 can refer to the relevant technology.

[0050] Controlling the connection between the operational amplifier and the calibration module may further include controlling S1 to be closed and S2 to be open. The control module may control the connection between the operational amplifier and the comparator and control S1 to be closed and S2 to be open. In this way, the connection between the operational amplifier and the calibration module is connected, and IDAC0 can output a first calibration current to the operational amplifier to perform a first calibration of the offset voltage of the operational amplifier.

[0051] For example, IDAC0 can be an N-bit IDAC; N≥2; the comparator is configured to respond to the positive output voltage Vo of the operational amplifier received at the first input terminal in response to the connection between the operational amplifier and the calibration module being turned on. +The SAR logic circuit is configured to compare N times the magnitude of the negative output voltage Vo- of the operational amplifier received at the second input terminal, and output a first comparison signal based on the comparison result; the SAR logic circuit is configured to generate a first current control signal based on successive approximation logic according to the first comparison signal; the first current control signal includes an N-bit binary code; and IDAC0 is configured to generate a first calibration current according to the first current control signal, and output the first calibration current to the operational amplifier.

[0052] The N-bit IDAC can be considered as including N branch currents I N-1 , I N-2 ,……,I0, where I N-1 =2 N-1 *I0,I N-2 =2 N-2 *I0, ..., I1 = 2*I0. The N-bit binary code (i.e., the first current control signal) generated by the SAR Logic circuit during the first calibration process can control the output current of IDAC0 (i.e., the first calibration current). Assume that the N-bit binary code is D N-1 、D N-2 , ..., D0, each bit of binary code controls a branch current, namely D N-1 Corresponding control branch current I N-1 , D N-2 Corresponding control branch current I N-2 , ..., D0 corresponds to the control branch current I0. The output current of IDAC0 is obtained by summing the branch currents corresponding to the binary codes with a code value of 1 in the N-bit binary code. The value of N can be determined by those skilled in the art based on actual needs. The larger the value of N, the higher the calibration accuracy. As an example, N can be 8.

[0053] The process of SAR Logic circuit generating N-bit binary code corresponding to the first calibration based on successive approximation logic is as follows: SAR Logic circuit first converts D N-1 Set to 1 and the remaining binary codes to 0. At this time, the output current of IDAC0 is I N-1 , I N-1 After being injected into the operational amplifier, the comparator outputs Vo to the operational amplifier. + The first comparison is performed with Vo-. When the operational amplifier initially has a positive offset voltage, if the first comparison output of the comparator is 1 (i.e. Vo + >Vo-), indicating that the calibration current is not large enough and the positive offset voltage is not fully calibrated. The calibration current needs to be increased. The SAR Logic circuit determines D N-1 =1; if the first comparison output of the comparator is 0 (i.e. Vo +<Vo-) indicates that the calibration current is too large at this time, and the positive offset voltage is calibrated to a negative offset voltage. It is necessary to reduce the calibration current. The SAR Logic circuit determines D N-1 = 0. In the case where the operational amplifier initially has a negative offset voltage, if the output of the first comparison by the comparator is 0 (i.e., Vo + <Vo-), it indicates that the calibration current is not large enough at this time, and the negative offset voltage is not fully calibrated. It is necessary to increase the calibration current. The SAR Logic circuit determines D N-1 = 1; if the output of the first comparison by the comparator is 1 (i.e., Vo + >Vo-), it indicates that the calibration current is too large at this time, and the negative offset voltage is calibrated to a positive offset voltage. It is necessary to reduce the calibration current. The SAR Logic circuit determines D N-1 = 0.

[0054] After determining the code value of D N-1 , the SAR Logic circuit sets D N-2 to 1, and the remaining binary codes are still 0. At this time, the output current of IDAC0 is D N-1 *I N-1 +I N-2 . After this output current is injected into the operational amplifier, the comparator makes a second comparison of Vo + output by the operational amplifier and Vo-, and outputs a comparison signal (0 or 1) according to the comparison result. The SAR Logic circuit determines the code value of D N-2 according to the comparison signal corresponding to the second comparison. Next, the SAR Logic circuit sets D N-3 , ……, D0 to 1 in turn, and repeats the above process. After each comparison by the comparator, the SAR Logic circuit can determine whether the code value of a binary digit is 0 or 1 according to the comparison result. After the comparator makes N comparisons, the SAR Logic circuit can finally determine N-bit binary codes. The finally determined N-bit binary codes can be called the N-bit binary codes corresponding to the first calibration. The SAR Logic circuit includes a first register, and the N-bit binary codes corresponding to the first calibration can be stored in the first register and provided to IDAC0. IDAC0 generates and outputs the final first calibration current according to the N-bit binary codes corresponding to the first calibration, completing the first calibration of the offset voltage of the operational amplifier.

[0055] In this way, by adjusting the code value of the N-bit binary codes bit by bit from the highest bit to the lowest bit by the SAR Logic circuit to adjust the output current of IDAC0, the offset voltage of the operational amplifier can be dichotomously approximated to zero, thereby realizing the first calibration of the offset voltage of the operational amplifier.

[0056] The first calibration current generated by IDAC0 can be recorded as I1. After the first calibration is completed, S1 needs to be kept closed so that IDAC0 can continue to inject I1 into the operational amplifier to maintain the calibration effect of the first calibration.

[0057] For example, the comparator can be controlled to compare Vo+ and Vo- according to the chip clock signal. For example, the comparator can be controlled to compare Vo+ and Vo- when the rising edge or falling edge of the clock signal arrives.

[0058] Exemplarily, the first determination module 105 may include a counter, which may count the number of times the comparator compares Vo+ and Vo-. When the counter counts the number of comparisons to N times, the first determination module 105 may determine that the first calibration of the offset voltage is completed, and send a first determination signal to the control module 104 so that the control module 104 controls the on-chip heater 102 to turn on and heat the chip 100.

[0059] As an example, the second determination module 106 may include a timer that measures the heating time of the chip 100 by the on-chip heater. Those skilled in the art may estimate the time required to heat the chip to a preset temperature as a preset heating time. If the second determination module 106 determines, based on the timer's measurement, that the heating time has reached the preset heating time, it may determine that the chip 100 has been heated to the preset temperature and send a second determination signal to the calibration module 103 and the control module 104.

[0060] As another example, the second determination module 106 may include a temperature sensor, which can detect the temperature of the chip 100 and send the detected chip temperature to the second determination module 106. When the second determination module 106 determines that the chip temperature reaches the preset temperature, it determines that the chip 100 is heated to the preset temperature and sends a second determination signal to the calibration module 103 and the control module 104.

[0061] It should be noted that the present application does not limit the implementation of the second determination module 106 , as long as the second determination module 106 can determine that the chip is heated to the preset temperature.

[0062] Illustratively, control module 104 is further configured to control S2 to close in response to a second confirmation signal. Upon receiving the second confirmation signal, control module 104 controls on-chip heater 102 to turn off and closes S2 to connect IDAC1 to the calibration module. IDAC1 can output a second calibration current to the operational amplifier to perform a second calibration of the operational amplifier's offset voltage.

[0063] Exemplarily, IDAC1 can be an N-bit IDAC; the comparator is further used to compare the sizes of Vo+ and Vo- N times in response to a second determination signal, and output a second comparison signal based on the comparison result; the SAR Logic circuit is further used to generate a second current control signal based on successive approximation logic according to the second comparison signal; the second current control signal includes an N-bit binary code; IDAC1 is used to generate a second calibration current according to the second current control signal, and output the second calibration current to the operational amplifier.

[0064] After receiving the second confirmation signal, the calibration module 103 starts a new round of comparisons of Vo+ and Vo- output by the operational amplifier in the comparator. The SAR Logic circuit adjusts the code value of the N-bit binary code bit by bit based on successive approximation logic to adjust the second calibration current generated by IDAC1. After the comparator performs a new round of N comparisons, the SAR Logic circuit finally determines the N-bit binary code. The finally determined N-bit binary code can be referred to as the N-bit binary code corresponding to the second calibration. The process of the SAR Logic circuit determining the N-bit binary code corresponding to the second calibration can refer to the process of the SAR Logic circuit determining the N-bit binary code corresponding to the first calibration, and will not be repeated here. The SAR Logic circuit includes a second register. The N-bit binary code corresponding to the second calibration can be stored in the second register and provided to IDAC1. IDAC1 generates and outputs the final second calibration current based on the N-bit binary code corresponding to the second calibration, completing the second calibration of the offset voltage of the operational amplifier.

[0065] The second calibration current ultimately generated by IDAC1 can be recorded as I2. After the first calibration is completed, IDAC0 continues to inject I1 into the operational amplifier to calibrate the offset voltage of the operational amplifier at room temperature. After the chip is heated to the preset temperature, the offset voltage of the operational amplifier changes compared to room temperature. On the basis of injecting I1 into the operational amplifier, I2 is injected into the operational amplifier to calibrate the offset voltage of the operational amplifier at the preset temperature. The second calibration is actually calibrating the offset voltage temperature drift of the operational amplifier. After completing the second calibration, it is necessary to keep S1 and S2 closed so that IDAC0 and IDAC1 continue to inject I1 and I2 into the operational amplifier, thereby maintaining the calibration effect of the offset voltage and offset voltage temperature drift of the operational amplifier.

[0066] Illustratively, after the calibration of the offset voltage and the offset voltage temperature drift of the operational amplifier is completed, the connection between the operational amplifier and the comparator may be disconnected.

[0067] The embodiment of the present application uses an operational amplifier, a comparator, a SAR Logic circuit, and an IDAC to form an offset voltage calibration loop. Through the control of this loop, the input offset voltage of the operational amplifier can be divided into two and approached to zero. When the first calibration is performed at room temperature, no offset voltage temperature drift is generated, and the calibration current is generated by IDAC0 whose output current does not change with temperature; when the second calibration is performed at a preset temperature, offset voltage temperature drift is generated. The second calibration is actually calibrating the offset voltage temperature drift. The use of IDAC1 whose output current changes with temperature can generate a temperature-related calibration current. Since the offset voltage temperature drift is related to temperature changes, the temperature-related calibration current can better calibrate the offset voltage temperature drift. Experiments have shown that through Figure 2 The on-chip heater shown controls the chip at different temperatures. Figure 3 The calibration module shown calibrates the offset voltage of the operational amplifier at different temperatures, ultimately achieving excellent calibration effects of significantly reducing the input offset voltage of the operational amplifier by 98.8% and significantly reducing the input offset voltage temperature drift by 89%.

[0068] It should be noted that although the embodiments of the present application are based on Figure 3 The structure shown is used as an example to introduce the calibration module in the chip proposed in this application. Those skilled in the art should understand that this application should not be limited to this. The calibration module in the chip proposed in this application can be designed according to actual needs, as long as the calibration module can calibrate the offset voltage of the operational amplifier.

[0069] The present application also proposes a self-calibration method for the offset voltage and offset voltage temperature drift of an operational amplifier. The method can be applied to the chip for self-calibrating the offset voltage and offset voltage temperature drift of an operational amplifier proposed in the present application.

[0070] Figure 4 A flow chart of a method for self-calibrating offset voltage and offset voltage temperature drift of an operational amplifier according to an embodiment of the present application is shown. Figure 4 As shown, the method may include:

[0071] S401, controlling the connection between the positive input terminal and the negative input terminal of the operational amplifier, or inputting the same voltage to the positive input terminal and the negative input terminal of the operational amplifier; and controlling the connection between the operational amplifier and the calibration module.

[0072] S402 : When it is determined that the operational amplifier and the calibration module are connected, input a first calibration current into the operational amplifier to perform a first calibration of the offset voltage of the operational amplifier.

[0073] S403 : When it is determined that the first calibration is completed, turn on the on-chip heater to heat the chip.

[0074] S404. When it is determined that the chip is heated to a preset temperature, turn off the on-chip heater and input a second calibration current into the operational amplifier to perform a second calibration of the offset voltage of the operational amplifier, thereby achieving calibration of the offset voltage temperature drift of the operational amplifier.

[0075] The implementation process of S401 to S404 can refer to the above description of the chip for self-calibrating the offset voltage and offset voltage temperature drift of the operational amplifier, and this application will not elaborate on this.

[0076] The self-calibration method for the offset voltage and offset voltage temperature drift of the operational amplifier of the embodiment of the present application performs a first calibration on the offset voltage of the operational amplifier at room temperature, then turns on the on-chip heater to heat the chip to a preset temperature, and performs a second calibration on the offset voltage of the operational amplifier at the preset temperature, thereby achieving calibration of the offset voltage temperature drift of the operational amplifier. The method of the embodiment of the present application can conveniently and quickly calibrate the offset voltage and offset voltage temperature drift of the operational amplifier with the help of the on-chip heater, can reduce the offset voltage and offset voltage temperature drift of the operational amplifier within a larger temperature range, and is applicable to various operational amplifier structures. Compared with existing static calibration methods, the method of the embodiment of the present application has better calibration effect and a wider range of applicability.

[0077] While various embodiments of the present application have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A chip for self-calibrating operational amplifier offset voltage and offset voltage temperature drift, characterized in that: The chip includes an operational amplifier, an on-chip heater, a calibration module, a control module, a first determination module and a second determination module; The control module is configured to control the connection between the positive input terminal and the negative input terminal of the operational amplifier, or input the same voltage to the positive input terminal and the negative input terminal of the operational amplifier; and control the connection between the operational amplifier and the calibration module; The calibration module is configured to output a first calibration current to the operational amplifier in response to the connection between the operational amplifier and the calibration module being turned on, so as to perform a first calibration on the offset voltage of the operational amplifier; The first determining module is configured to output a first determination signal to the control module when determining that the first calibration is completed; The control module is further configured to, in response to the first determination signal, turn on the on-chip heater to heat the chip; The second determination module is configured to output a second determination signal to the control module and the calibration module when determining that the chip is heated to a preset temperature; The control module is further configured to turn off the on-chip heater in response to the second determination signal; The calibration module is further configured to output a second calibration current to the operational amplifier in response to the second determination signal, so as to perform a second calibration on the offset voltage of the operational amplifier, thereby calibrating the offset voltage temperature drift of the operational amplifier; The calibration module includes a comparison submodule, a successive approximation logic submodule, and a current conversion submodule. Controlling the connection between the operational amplifier and the calibration module includes: controlling the connection between the positive output terminal of the operational amplifier and the first input terminal of the comparison submodule, and controlling the connection between the negative output terminal of the operational amplifier and the second input terminal of the comparison submodule; The current conversion submodule includes a first current-type digital-to-analog converter, a second current-type digital-to-analog converter, a first switch and a second switch; Controlling the connection between the operational amplifier and the calibration module further includes: controlling the first switch to be closed and the second switch to be open; The control module is further configured to control the second switch to be closed in response to the second determination signal.

2. The chip according to claim 1, characterized in that The on-chip heater includes a serpentine metal on-chip heater fabricated using a top metal layer of the chip.

3. The chip according to claim 1 or 2, characterized in that: The first input terminal of the comparison submodule is connected to the positive output terminal of the operational amplifier; the second input terminal of the comparison submodule is connected to the negative output terminal of the operational amplifier; the output terminal of the comparison submodule is connected to the input terminal of the successive approximation logic submodule; the output terminal of the successive approximation logic submodule is connected to the input terminal of the current conversion submodule; and the output terminal of the current conversion submodule is connected to the operational amplifier.

4. The chip according to claim 3, characterized in that The first end of the first switch is connected to the first end of the second switch, forming the input end of the current conversion submodule; the output end of the first current-type digital-to-analog converter is connected to the output end of the second current-type digital-to-analog converter, forming the output end of the current conversion submodule; the second end of the first switch is connected to the input end of the first current-type digital-to-analog converter; and the second end of the second switch is connected to the input end of the second current-type digital-to-analog converter.

5. The chip according to claim 4, characterized in that The output current of the first current-type digital-to-analog converter does not change with temperature; the output current of the second current-type digital-to-analog converter is proportional to the absolute temperature.

6. The chip according to claim 5, characterized in that The first current-type digital-to-analog converter is an N-bit current-type digital-to-analog converter; N≥2; the comparison submodule is configured to compare N times the positive output voltage output by the positive output terminal of the operational amplifier received by the first input terminal and the negative output voltage output by the negative output terminal of the operational amplifier received by the second input terminal in response to the connection between the operational amplifier and the calibration module, and output a first comparison signal according to the comparison result; The successive approximation logic submodule is configured to generate a first current control signal based on successive approximation logic according to the first comparison signal; the first current control signal includes an N-bit binary code; The first current-type digital-to-analog converter is configured to generate the first calibration current according to the first current control signal, and output the first calibration current to the operational amplifier.

7. The chip according to claim 6, characterized in that The first determining module includes a counter; the counter is used to count the number of comparisons performed by the comparing submodule; The first determining module is further configured to determine that the first calibration is completed when the counter counts the number of comparisons to N times.

8. The chip according to claim 6, characterized in that The second current-mode digital-to-analog converter is an N-bit current-mode digital-to-analog converter; The comparison submodule is further configured to compare the positive output voltage and the negative output voltage N times in response to the second determination signal, and output a second comparison signal according to the comparison result; The successive approximation logic submodule is further configured to generate a second current control signal based on successive approximation logic according to the second comparison signal; the second current control signal includes an N-bit binary code; The second current-type digital-to-analog converter is configured to generate the second calibration current according to the second current control signal, and output the second calibration current to the operational amplifier.

9. The chip according to claim 1, characterized in that The second determining module includes a timer: the timer is used to time the heating time of the chip by the on-chip heater; the second determining module is further used to determine that the chip is heated to the preset temperature when it is determined based on the timer that the heating time reaches the preset heating time; or, The second determination module includes a temperature sensor: the temperature sensor is used to detect the temperature of the chip and send the detected chip temperature to the second determination module; the second determination module is also used to determine that the chip is heated to the preset temperature when it is determined that the chip temperature reaches the preset temperature.

10. A method for self-calibration of offset voltage and offset voltage temperature drift of an operational amplifier, characterized in that: The chip according to any one of claims 1 to 9; the method comprising: Controlling the connection between the positive input terminal and the negative input terminal of the operational amplifier, or inputting the same voltage to the positive input terminal and the negative input terminal of the operational amplifier; and controlling the connection between the operational amplifier and the calibration module; When it is determined that the operational amplifier and the calibration module are connected, inputting a first calibration current into the operational amplifier to perform a first calibration of the offset voltage of the operational amplifier; When it is determined that the first calibration is completed, turning on an on-chip heater to heat the chip; When it is determined that the chip is heated to a preset temperature, the on-chip heater is turned off and a second calibration current is input to the operational amplifier to perform a second calibration of the offset voltage of the operational amplifier, thereby achieving calibration of the offset voltage temperature drift of the operational amplifier.

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