Fully-differential wide common-mode input operational amplifier circuit

Abstract

The invention provides a fully-differential wide common-mode input operational amplifier circuit which comprises a differential common-mode operational amplifier OP, a first link, a second link, a resistor R1 and a resistor R2, one end of the resistor R1 and one end of the resistor R2 are connected with input signals VIN and VIP respectively, the other end of the resistor R1 is connected with the positive-phase input end of the differential common-mode operational amplifier OP and one end of the first link, and the other end of the second link is connected with the negative-phase input end of the differential common-mode operational amplifier OP. The other end of the resistor R2 is connected with the inverting input end of the differential common-mode operational amplifier OP and one end of the second link, the inverting output end of the differential common-mode operational amplifier OP is connected with the other end of the first link, and the non-inverting output end of the differential common-mode operational amplifier OP is connected with the other end of the second link. And the differential common-mode operational amplifier OP adopts low-voltage differential input geminate transistors. The driving capacity is high, the occupied area is small, and the offset of the system can be reduced.

Description

Technical Field

[0001] The invention relates to an operational amplifier circuit, in particular to a fully differential wide common-mode input operational amplifier circuit, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] Fully differential wide common-mode input operational amplifier circuits are widely used in a variety of applications. The wide common-mode input architecture can play an important role in high-precision current sampling applications. For example, in the current sampling circuit of a domain drive motor chip, the input common-mode range is required to meet -5V to 60V.

[0003] like Figure 7 The figure shows a traditional operational amplifier with a differential circuit using a high-voltage MOS tube as the input pair. Although the structure is simple in design, it has many deficiencies and defects: 1. For extremely high-precision current sampling circuits, high-voltage differential input MOS pairs will introduce a relatively large offset; 2. A large number of input pairs are required in the high-precision current sampling circuit to ensure that the system offset can be small. Because the area of ​​a high-voltage tube is much larger than that of a low-voltage tube, if all high-voltage MOS are used as input pairs, it will occupy a large area; 3. The VTH of the high-voltage MOS input pair will be greater than that of the low-voltage MOS. Therefore, in order to achieve the same current driving capability, the number of high-voltage MOS input pairs required will obviously be more. Generally, the total number of input high-voltage MOS pairs needs to be greater than 30, which will further increase the chip area.

[0004] In summary, high-voltage MOS input pairs will introduce a larger offset and increase the circuit area, which will have an adverse impact on the design performance and cost of the entire chip. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a fully differential wide common-mode input operational amplifier circuit, which adopts a low-voltage MOS input pair tube, has strong driving capability and occupies a small area.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A fully differential wide common-mode input operational amplifier circuit comprises a differential common-mode operational amplifier OP, a first link, a second link, a resistor R1 and a resistor R2, wherein one end of the resistor R1 is connected to an input signal VIN, one end of the resistor R2 is connected to an input signal VIP, the other end of the resistor R1 is connected to a positive phase input end of the differential common-mode operational amplifier OP and one end of the first link and generates a signal VIP1, the other end of the resistor R2 is connected to an inverting input end of the differential common-mode operational amplifier OP and one end of the second link and generates a signal VIN1, the inverting output end of the differential common-mode operational amplifier OP is connected to the other end of the first link and generates a signal VOUTN1, the positive phase output end of the differential common-mode operational amplifier OP is connected to the other end of the second link and generates a signal VOUTP1, and the differential common-mode operational amplifier OP adopts a low-voltage differential input pair tube.

[0007] Furthermore, the first link includes a gain modulation module dm_gain_trim1, a high-voltage MOS tube HVMOS1 and a resistor R3, one end of the gain modulation module dm_gain_trim1 is connected to the signal VOUTN1, the other end of the gain modulation module dm_gain_trim1 is connected to the source of the high-voltage MOS tube HVMOS1, the gate of the high-voltage MOS tube HVMOS1 is connected to the control signal EN1, the drain of the high-voltage MOS tube HVMOS1 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the signal VIP1.

[0008] Furthermore, the second link includes a gain modulation module dm_gain_trim2, a high-voltage MOS tube HVMOS2 and a resistor R4, one end of the gain modulation module dm_gain_trim2 is connected to the signal VOUTP1, the other end of the gain modulation module dm_gain_trim2 is connected to the source of the high-voltage MOS tube HVMOS2, the gate of the high-voltage MOS tube HVMOS2 is connected to the control signal EN2, the drain of the high-voltage MOS tube HVMOS2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the signal VIN1.

[0009] Furthermore, the differential common-mode operational amplifier OP includes a main control circuit, a bias circuit, a common-mode feedback circuit and an Offset adjustment circuit. The bias circuit provides bias current and bias voltage for the main control circuit, the common-mode feedback circuit and the Offset adjustment circuit. The main control circuit converts different high-voltage common-mode input signals into low-voltage common-mode output signals and performs differential mode amplification. The common-mode feedback circuit provides a common-mode output low voltage for the main control circuit. The Offset adjustment circuit reduces the input Offset voltage of the main control circuit.

[0010] Furthermore, the main control circuit includes a low-voltage NMOS tube NM1, a low-voltage NMOS tube NM2, a low-voltage NMOS tube NM3, a high-voltage NMOS tube HVNM1, a high-voltage NMOS tube HVNM2, a high-voltage NMOS tube HVNM3, a low-voltage PMOS tube PM1 and a low-voltage PMOS tube PM2, the gate of the low-voltage NMOS tube NM1 is connected to the signal VIP1, the gate of the low-voltage NMOS tube NM2 is connected to the signal VIN1, the gate of the low-voltage NMOS tube NM1 is connected to the gate of the low-voltage NMOS tube NM2 and the drain of the high-voltage NMOS tube HVNM1 and generates a voltage signal V1, the gate of the high-voltage NMOS tube HVNM1 is connected to the voltage signal VBN2, the source of the high-voltage NMOS tube HVNM1 is connected to the drain of the low-voltage NMOS tube NM3, and the gate of the low-voltage NMOS tube NM3 is connected to the voltage signal VBN1 , the source of the low voltage NMOS tube NM3 is connected to the negative voltage power supply LVSS, the drain of the low voltage NMOS tube NM1 is connected to the source of the high voltage NMOS tube HVNM2 and generates a voltage signal V2, the drain of the low voltage NMOS tube NM2 is connected to the source of the high voltage NMOS tube HVNM3 and generates a voltage signal V3, the gate of the high voltage NMOS tube HVNM2 and the gate of the high voltage NMOS tube HVNM3 are connected to the voltage signal VBN3, the drain of the high voltage NMOS tube HVNM2 is connected to the drain of the low voltage PMOS tube PM1, the drain of the high voltage NMOS tube HVNM3 is connected to the drain of the low voltage PMOS tube PM2, the gate of the low voltage PMOS tube PM1 and the gate of the low voltage PMOS tube PM2 are connected to the voltage signal VBP1, and the source of the low voltage PMOS tube PM1 and the source of the low voltage PMOS tube PM2 are connected to the high voltage power supply HVDD.

[0011] Furthermore, the main control circuit also includes a Zener diode D1 and a Zener diode D2, the anode of the Zener diode D1 is connected to the source of the low-voltage NMOS tube NM1, the cathode of the Zener diode D1 is connected to the gate of the low-voltage NMOS tube NM1, the anode of the Zener diode D2 is connected to the source of the low-voltage NMOS tube NM2, and the cathode of the Zener diode D2 is connected to the gate of the low-voltage NMOS tube NM2.

[0012] Furthermore, the main control circuit further includes a low-voltage NMOS tube NM4, a low-voltage NMOS tube NM5, a low-voltage NMOS tube NM6, a high-voltage NMOS tube HVNM4, a low-voltage PMOS tube PM3 and a low-voltage PMOS tube PM4, the source of the low-voltage NMOS tube NM6 is connected to the negative voltage power supply LVSS, the gate of the low-voltage NMOS tube NM6 generates a voltage signal VBN1, the drain of the low-voltage NMOS tube NM6 is connected to the source of the high-voltage NMOS tube HVNM4, the gate of the high-voltage NMOS tube HVNM4 generates a voltage signal VBN2, the drain of the high-voltage NMOS tube HVNM4 is connected to the low-voltage NMOS tube NM The source of the low voltage NMOS tube NM5 is connected to the voltage signal V1, the gate of the low voltage NMOS tube NM5 is connected to the drain of the low voltage NMOS tube NM5 and the source of the low voltage NMOS tube NM4, the gate of the low voltage NMOS tube NM4 is connected to the drain of the low voltage NMOS tube NM4 and the drain of the low voltage PMOS tube PM4 and generate the voltage signal VBN3, the gate of the low voltage PMOS tube PM4 is connected to the voltage signal VBP3, the source of the low voltage PMOS tube PM4 is connected to the drain of the low voltage PMOS tube PM3, the gate of the low voltage PMOS tube PM3 is connected to the voltage signal VBP2, and the source of the low voltage PMOS tube PM3 is connected to the high voltage power supply HVDD.

[0013] Furthermore, the main control circuit further includes a low-voltage NMOS tube NM6, a low-voltage NMOS tube NM7, a high-voltage NMOS tube HVNM5, a high-voltage NMOS tube HVNM6 and a resistor R5, one end of the resistor R5 is connected to the high-voltage power supply HVDD, the other end of the resistor R5 is connected to the drain of the high-voltage NMOS tube HVNM6, the gate of the high-voltage NMOS tube HVNM6 is connected to the voltage signal VBN3, the source of the high-voltage NMOS tube HVNM6 is connected to the high-voltage NMOS tube HVNM5 The drain of the high-voltage NMOS tube HVNM5 is connected to and generates a voltage signal ISO, the gate of the high-voltage NMOS tube HVNM5 is connected to the voltage signal VBN6, the source of the high-voltage NMOS tube HVNM5 is connected to the drain of the low-voltage NMOS tube NM6, the gate of the low-voltage NMOS tube NM6 is connected to the voltage signal VBN5, the source of the low-voltage NMOS tube NM6 is connected to the drain of the low-voltage NMOS tube NM7, the gate of the low-voltage NMOS tube NM7 is connected to the voltage signal VBN4, and the source of the low-voltage NMOS tube NM7 is grounded.

[0014] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a fully differential wide common-mode input operational amplifier circuit, which adopts a low-voltage MOS input pair tube, and can effectively improve the adverse effects brought by the traditional architecture; firstly, the low-voltage MOS input pair tube has good matching performance, and can achieve high-precision matching, thereby reducing the offset of the system; secondly, the low-voltage MOS input pair tube has strong driving capability and occupies a small area, which is of great help to the layout of the chip and the control of cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of a fully differential wide common-mode input operational amplifier circuit of the present invention.

[0016] Figure 2 Schematic diagram of the differential common-mode operational amplifier OP of the present invention.

[0017] Figure 3 Schematic diagram of the main control circuit of the present invention Figure 1 .

[0018] Figure 4 Schematic diagram of the main control circuit of the present invention Figure 2 .

[0019] Figure 5 Schematic diagram of the main control circuit of the present invention Figure 3 .

[0020] Figure 6 It is a process cross-sectional view of an input low-voltage MOS pair tube according to an embodiment of the present invention.

[0021] Figure 7 It is a schematic diagram of a conventional high-voltage MOS input pair tube circuit in the prior art. DETAILED DESCRIPTION

[0022] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0023] like Figure 1 As shown, a fully differential wide common-mode input operational amplifier circuit of the present invention includes a differential common-mode operational amplifier OP, a first link, a second link, a resistor R1 and a resistor R2, one end of the resistor R1 is connected to the input signal VIN, one end of the resistor R2 is connected to the input signal VIP, the other end of the resistor R1 is connected to the positive phase input end of the differential common-mode operational amplifier OP and one end of the first link and generates a signal VIP1, the other end of the resistor R2 is connected to the inverting input end of the differential common-mode operational amplifier OP and one end of the second link and generates a signal VIN1, the inverting output end of the differential common-mode operational amplifier OP is connected to the other end of the first link and generates a signal VOUTN1, the positive phase output end of the differential common-mode operational amplifier OP is connected to the other end of the second link and generates a signal VOUTP1, and the differential common-mode operational amplifier OP adopts a low-voltage differential input pair tube.

[0024] The first link includes a gain modulation module dm_gain_trim1, a high-voltage MOS tube HVMOS1 and a resistor R3, one end of the gain modulation module dm_gain_trim1 is connected to a signal VOUTN1, the other end of the gain modulation module dm_gain_trim1 is connected to a source of the high-voltage MOS tube HVMOS1, a gate of the high-voltage MOS tube HVMOS1 is connected to a control signal EN1, a drain of the high-voltage MOS tube HVMOS1 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to a signal VIP1.

[0025] The second link includes a gain modulation module dm_gain_trim2, a high-voltage MOS tube HVMOS2 and a resistor R4, one end of the gain modulation module dm_gain_trim2 is connected to the signal VOUTP1, the other end of the gain modulation module dm_gain_trim2 is connected to the source of the high-voltage MOS tube HVMOS2, the gate of the high-voltage MOS tube HVMOS2 is connected to the control signal EN2, the drain of the high-voltage MOS tube HVMOS2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the signal VIN1.

[0026] like Figure 2 As shown, the differential common-mode operational amplifier OP includes a main control circuit, a bias circuit, a common-mode feedback circuit and an Offset adjustment circuit. The bias circuit provides bias current and bias voltage for the main control circuit, the common-mode feedback circuit and the Offset adjustment circuit. The main control circuit converts different high-voltage common-mode input signals into low-voltage common-mode output signals and performs differential mode amplification. The common-mode feedback circuit provides the main control circuit with a common-mode output low voltage. The Offset adjustment circuit reduces the input Offset voltage of the main control circuit. The present invention mainly relates to the improvement of the main control circuit part. The bias circuit, the common-mode feedback circuit and the Offset adjustment circuit all adopt the existing technology, so their specific circuit structures are not repeated in this application.

[0027] like Figure 3As shown, the main control circuit includes a low voltage NMOS tube NM1, a low voltage NMOS tube NM2, a low voltage NMOS tube NM3, a high voltage NMOS tube HVNM1, a high voltage NMOS tube HVNM2, a high voltage NMOS tube HVNM3, a low voltage PMOS tube PM1 and a low voltage PMOS tube PM2, a gate of the low voltage NMOS tube NM1 is connected to a signal VIP1, a gate of the low voltage NMOS tube NM2 is connected to a signal VIN1, a gate of the low voltage NMOS tube NM1 is connected to a gate of the low voltage NMOS tube NM2 and a drain of the high voltage NMOS tube HVNM1 and generates a voltage signal V1, a gate of the high voltage NMOS tube HVNM1 is connected to a voltage signal VBN2, a source of the high voltage NMOS tube HVNM1 is connected to a drain of the low voltage NMOS tube NM3, a gate of the low voltage NMOS tube NM3 is connected to a voltage signal VBN1, and a low voltage PMOS tube PM2 is connected to a gate of the low voltage NMOS tube NM1. The source of the low-voltage NMOS tube NM3 is connected to the negative voltage power supply LVSS, the drain of the low-voltage NMOS tube NM1 is connected to the source of the high-voltage NMOS tube HVNM2 and generates a voltage signal V2, the drain of the low-voltage NMOS tube NM2 is connected to the source of the high-voltage NMOS tube HVNM3 and generates a voltage signal V3, the gate of the high-voltage NMOS tube HVNM2 and the gate of the high-voltage NMOS tube HVNM3 are connected to the voltage signal VBN3, the drain of the high-voltage NMOS tube HVNM2 is connected to the drain of the low-voltage PMOS tube PM1, the drain of the high-voltage NMOS tube HVNM3 is connected to the drain of the low-voltage PMOS tube PM2, the gate of the low-voltage PMOS tube PM1 and the gate of the low-voltage PMOS tube PM2 are connected to the voltage signal VBP1, and the source of the low-voltage PMOS tube PM1 and the source of the low-voltage PMOS tube PM2 are connected to the high-voltage power supply HVDD.

[0028] Among them, the low voltage NMOS tube NM1 and the low voltage NMOS tube NM2 are low voltage MOS input pair tubes, and the high voltage NMOS tube HVNM2 and the high voltage NMOS tube HVNM3 are used to isolate the input end high voltage from the low voltage NMOS tube NM1 and the low voltage NMOS tube NM2.

[0029] The main control circuit also includes a Zener diode D1 and a Zener diode D2, the anode of the Zener diode D1 is connected to the source of the low-voltage NMOS tube NM1, the cathode of the Zener diode D1 is connected to the gate of the low-voltage NMOS tube NM1, the anode of the Zener diode D2 is connected to the source of the low-voltage NMOS tube NM2, and the cathode of the Zener diode D2 is connected to the gate of the low-voltage NMOS tube NM2. The Zener diode D1 and the Zener diode D2 are used to prevent overvoltage between different terminals of the input pair of tubes. Especially in some abnormal situations, such as when the input common-mode voltage difference is large or abnormal voltage coupling occurs.

[0030] like Figure 4As shown, the main control circuit also includes a low-voltage NMOS tube NM4, a low-voltage NMOS tube NM5, a low-voltage NMOS tube NM6, a high-voltage NMOS tube HVNM4, a low-voltage PMOS tube PM3 and a low-voltage PMOS tube PM4. The source of the low-voltage NMOS tube NM6 is connected to the negative voltage power supply LVSS, the gate of the low-voltage NMOS tube NM6 generates a voltage signal VBN1, the drain of the low-voltage NMOS tube NM6 is connected to the source of the high-voltage NMOS tube HVNM4, the gate of the high-voltage NMOS tube HVNM4 generates a voltage signal VBN2, the drain of the high-voltage NMOS tube HVNM4 is connected to the source of the low-voltage NMOS tube NM5, the gate of the high-voltage NMOS tube HVNM4 generates a voltage signal VBN2, and the drain of the high-voltage NMOS tube HVNM4 is connected to the gate of the low-voltage NMOS tube NM5. The source is connected to the voltage signal V1, the gate of the low voltage NMOS tube NM5 is connected to the drain of the low voltage NMOS tube NM5 and the source of the low voltage NMOS tube NM4, the gate of the low voltage NMOS tube NM4 is connected to the drain of the low voltage NMOS tube NM4 and the drain of the low voltage PMOS tube PM4 and generates a voltage signal VBN3, the gate of the low voltage PMOS tube PM4 is connected to the voltage signal VBP3, the source of the low voltage PMOS tube PM4 is connected to the drain of the low voltage PMOS tube PM3, the gate of the low voltage PMOS tube PM3 is connected to the voltage signal VBP2, and the source of the low voltage PMOS tube PM3 is connected to the high voltage power supply HVDD.

[0031] like Figure 4 As shown, by selecting a suitable voltage signal VBN3, a good isolation effect can be achieved.

[0032] Through analysis, the voltage signal VBN3 can be expressed as: VBN3=V1+VGS nm5 +VGS nm4 (1) Where V1 is the voltage value of the voltage signal V1, VGS nm5 is the gate-source voltage of the low-voltage NMOS tube NM5, VGS nm4 It is the gate-source voltage of the low voltage NMOS tube NM4.

[0033] From this we can get: V2= V1+VGS nm5 +VGS nm4 -VGS hvnm2 (2) Where V2 is the voltage value of the voltage signal V2, VGS hvnm2 is the gate-source voltage of the high-voltage NMOS tube HVNM2; Similarly, we can get: V3= V1+VGS nm5 +VGS nm4 -VGS hvnm3 (3) Where V3 is the voltage value of the voltage signal V3, VGS hvnm3It is the gate-source voltage of the high-voltage NMOS tube HVNM3.

[0034] From formulas (1), (2) and (3), it can be found that the voltage signal V1 differs from the voltage signal V2 and the voltage signal V3 by only a VGS value. By properly adjusting the VGS values ​​of the low-voltage NMOS tube NM5 and the low-voltage NMOS tube NM4, it can be ensured that the input pair tubes will not operate in the linear region and that there will be no VDS overvoltage risk for the input pair tubes.

[0035] like Figure 5 As shown, the main control circuit further includes a low voltage NMOS tube NM6, a low voltage NMOS tube NM7, a high voltage NMOS tube HVNM5, a high voltage NMOS tube HVNM6 and a resistor R5, one end of the resistor R5 is connected to the high voltage power supply HVDD, the other end of the resistor R5 is connected to the drain of the high voltage NMOS tube HVNM6, the gate of the high voltage NMOS tube HVNM6 is connected to the voltage signal VBN3, the source of the high voltage NMOS tube HVNM6 is connected to the drain of the high voltage NMOS tube HVNM5 The gate of the high-voltage NMOS tube HVNM5 is connected to the voltage signal VBN6, the source of the high-voltage NMOS tube HVNM5 is connected to the drain of the low-voltage NMOS tube NM6, the gate of the low-voltage NMOS tube NM6 is connected to the voltage signal VBN5, the source of the low-voltage NMOS tube NM6 is connected to the drain of the low-voltage NMOS tube NM7, the gate of the low-voltage NMOS tube NM7 is connected to the voltage signal VBN4, and the source of the low-voltage NMOS tube NM7 is grounded.

[0036] It should be noted that the current flowing through the low voltage PMOS tube PM3 needs to be the same as the current flowing through the low voltage NMOS tube NM6, otherwise it will affect the current value flowing through the input pair tube.

[0037] Depend on Figure 6 It can be seen that the low-voltage input pair has NBL in the process profile, and P-EPI is surrounded by NBL. Because P-EPI and the body have the same potential, it is also necessary to pay attention to whether there is an overvoltage risk between NBL and the body. Since the potential of NBL will be connected to ISO, it is necessary to set a suitable ISO voltage. It should be noted that the ISO voltage cannot be negative, otherwise there will be a large leakage between ISO and PSUB, which may also easily cause latch up. If LVSS is not negative, the ISO potential can borrow the potential of V2 or V3, but when LVSS is negative, V2 and V3 may also be negative, so it is inappropriate to borrow the potential of V2 or V3.

[0038] Therefore, this application builds Figure 5 The circuit structure shown is used to generate the voltage signal ISO and ISO= V1+VGS nm5 +VGS nm4 -VGS hvnm6 (4) Among them, VGS hvnm6 It is the gate-source voltage of the high-voltage NMOS tube HVNM3.

[0039] It can be seen that the voltage signal ISO and the voltage signal V1 also differ by 1 VGS, which can ensure that the ISO voltage of the input pair tube is greater than the body voltage, and also ensure that there is no overvoltage risk between ISO and the body. Figure 5 From the circuit architecture, it can be found that even if the voltage signal VBN3 is a negative voltage, the voltage signal ISO will not be a negative voltage, and the minimum voltage value of the voltage signal ISO will be clamped to 0V. The function of the high-voltage NMOS tube HVNM5 is also to isolate the low-voltage device from the high voltage. It can be found that although the input pair of tubes has become a low-voltage tube, the negative impact is the addition of 5 high-voltage tubes. However, since the high-voltage input pair of tubes in the traditional high-voltage input pair of tubes is actually composed of more than 30 high-voltage tubes, and the high-voltage tubes of this application are all single high-voltage MOS tubes, after comprehensive calculation, it is found that the total circuit area is still much smaller than the traditional architecture, because at least 30 input high-voltage mos pairs of tubes will be saved, and the effect is quite considerable.

[0040] The present invention ingeniously realizes the transformation of the input pair tube from a high voltage structure to a low voltage structure by constructing VBN3 and ISO voltage, making an important contribution to improving chip performance, reducing area and saving cost.

[0041] The present invention provides a fully differential wide common-mode input operational amplifier circuit, which adopts a low-voltage MOS input pair tube, and can effectively improve the adverse effects brought by the traditional architecture; firstly, the low-voltage MOS input pair tube has good matching performance, and can achieve high-precision matching, so as to reduce the offset of the system; secondly, the low-voltage MOS input pair tube has strong driving capability and occupies a small area, which is of great help to the layout of the chip and the control of cost.

[0042] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A fully differential wide common-mode input operational amplifier circuit, characterized in that: It includes a differential common-mode operational amplifier OP, a first link, a second link, a resistor R1 and a resistor R2, one end of the resistor R1 is connected to an input signal VIN, one end of the resistor R2 is connected to an input signal VIP, the other end of the resistor R1 is connected to a positive phase input end of the differential common-mode operational amplifier OP and one end of the first link and generates a signal VIP1, the other end of the resistor R2 is connected to an inverting input end of the differential common-mode operational amplifier OP and one end of the second link and generates a signal VIN1, the inverting output end of the differential common-mode operational amplifier OP is connected to the other end of the first link and generates a signal VOUTN1, the positive phase output end of the differential common-mode operational amplifier OP is connected to the other end of the second link and generates a signal VOUTP1, and the differential common-mode operational amplifier OP adopts a low-voltage differential input pair tube.

2. The fully differential wide common-mode input operational amplifier circuit according to claim 1, characterized in that: The first link includes a gain modulation module dm_gain_trim1, a high-voltage MOS tube HVMOS1 and a resistor R3, one end of the gain modulation module dm_gain_trim1 is connected to a signal VOUTN1, the other end of the gain modulation module dm_gain_trim1 is connected to a source of the high-voltage MOS tube HVMOS1, a gate of the high-voltage MOS tube HVMOS1 is connected to a control signal EN1, a drain of the high-voltage MOS tube HVMOS1 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to a signal VIP1.

3. The fully differential wide common-mode input operational amplifier circuit according to claim 1, characterized in that: The second link includes a gain modulation module dm_gain_trim2, a high-voltage MOS tube HVMOS2 and a resistor R4, one end of the gain modulation module dm_gain_trim2 is connected to the signal VOUTP1, the other end of the gain modulation module dm_gain_trim2 is connected to the source of the high-voltage MOS tube HVMOS2, the gate of the high-voltage MOS tube HVMOS2 is connected to the control signal EN2, the drain of the high-voltage MOS tube HVMOS2 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the signal VIN1.

4. The fully differential wide common-mode input operational amplifier circuit according to claim 1, characterized in that: The differential common-mode operational amplifier OP includes a main control circuit, a bias circuit, a common-mode feedback circuit and an Offset adjustment circuit. The bias circuit provides bias current and bias voltage for the main control circuit, the common-mode feedback circuit and the Offset adjustment circuit. The main control circuit converts different high-voltage common-mode input signals into low-voltage common-mode output signals and performs differential-mode amplification. The common-mode feedback circuit provides a common-mode output low voltage for the main control circuit. The Offset adjustment circuit reduces the input Offset voltage of the main control circuit.

5. The fully differential wide common-mode input operational amplifier circuit according to claim 1, characterized in that: The main control circuit comprises a low voltage NMOS tube NM1, a low voltage NMOS tube NM2, a low voltage NMOS tube NM3, a high voltage NMOS tube HVNM1, a high voltage NMOS tube HVNM2, a high voltage NMOS tube HVNM3, a low voltage PMOS tube PM1 and a low voltage PMOS tube PM2, a gate of the low voltage NMOS tube NM1 is connected to a signal VIP1, a gate of the low voltage NMOS tube NM2 is connected to a signal VIN1, a gate of the low voltage NMOS tube NM1 is connected to a gate of the low voltage NMOS tube NM2 and a drain of the high voltage NMOS tube HVNM1 and generates a voltage signal V1, a gate of the high voltage NMOS tube HVNM1 is connected to a voltage signal VBN2, a source of the high voltage NMOS tube HVNM1 is connected to a drain of the low voltage NMOS tube NM3, a gate of the low voltage NMOS tube NM3 is connected to a voltage signal VBN1, and a low voltage The source of the NMOS tube NM3 is connected to the negative voltage power supply LVSS, the drain of the low voltage NMOS tube NM1 is connected to the source of the high voltage NMOS tube HVNM2 and generates a voltage signal V2, the drain of the low voltage NMOS tube NM2 is connected to the source of the high voltage NMOS tube HVNM3 and generates a voltage signal V3, the gate of the high voltage NMOS tube HVNM2 and the gate of the high voltage NMOS tube HVNM3 are connected to the voltage signal VBN3, the drain of the high voltage NMOS tube HVNM2 is connected to the drain of the low voltage PMOS tube PM1, the drain of the high voltage NMOS tube HVNM3 is connected to the drain of the low voltage PMOS tube PM2, the gate of the low voltage PMOS tube PM1 and the gate of the low voltage PMOS tube PM2 are connected to the voltage signal VBP1, and the source of the low voltage PMOS tube PM1 and the source of the low voltage PMOS tube PM2 are connected to the high voltage power supply HVDD.

6. The fully differential wide common-mode input operational amplifier circuit according to claim 5, characterized in that: The main control circuit also includes a Zener diode D1 and a Zener diode D2, wherein the anode of the Zener diode D1 is connected to the source of the low-voltage NMOS tube NM1, the cathode of the Zener diode D1 is connected to the gate of the low-voltage NMOS tube NM1, the anode of the Zener diode D2 is connected to the source of the low-voltage NMOS tube NM2, and the cathode of the Zener diode D2 is connected to the gate of the low-voltage NMOS tube NM2.

7. The fully differential wide common-mode input operational amplifier circuit according to claim 5, characterized in that: The main control circuit further includes a low-voltage NMOS tube NM4, a low-voltage NMOS tube NM5, a low-voltage NMOS tube NM6, a high-voltage NMOS tube HVNM4, a low-voltage PMOS tube PM3 and a low-voltage PMOS tube PM4. The source of the low-voltage NMOS tube NM6 is connected to the negative voltage power supply LVSS, the gate of the low-voltage NMOS tube NM6 generates a voltage signal VBN1, the drain of the low-voltage NMOS tube NM6 is connected to the source of the high-voltage NMOS tube HVNM4, the gate of the high-voltage NMOS tube HVNM4 generates a voltage signal VBN2, the drain of the high-voltage NMOS tube HVNM4 is connected to the source of the low-voltage NMOS tube NM5, and the gate of the high-voltage NMOS tube HVNM4 generates a voltage signal VBN2. The gate of the low voltage NMOS tube NM5 is connected to the drain of the low voltage NMOS tube NM5 and the source of the low voltage NMOS tube NM4, the gate of the low voltage NMOS tube NM4 is connected to the drain of the low voltage NMOS tube NM4 and the drain of the low voltage PMOS tube PM4 and generates a voltage signal VBN3, the gate of the low voltage PMOS tube PM4 is connected to the voltage signal VBP3, the source of the low voltage PMOS tube PM4 is connected to the drain of the low voltage PMOS tube PM3, the gate of the low voltage PMOS tube PM3 is connected to the voltage signal VBP2, and the source of the low voltage PMOS tube PM3 is connected to the high voltage power supply HVDD.

8. The fully differential wide common-mode input operational amplifier circuit according to claim 7, characterized in that: The main control circuit also includes a low-voltage NMOS tube NM6, a low-voltage NMOS tube NM7, a high-voltage NMOS tube HVNM5, a high-voltage NMOS tube HVNM6 and a resistor R5, one end of the resistor R5 is connected to the high-voltage power supply HVDD, the other end of the resistor R5 is connected to the drain of the high-voltage NMOS tube HVNM6, the gate of the high-voltage NMOS tube HVNM6 is connected to the voltage signal VBN3, the source of the high-voltage NMOS tube HVNM6 is connected to the drain of the high-voltage NMOS tube HVNM5 and generates a voltage signal ISO, the gate of the high-voltage NMOS tube HVNM5 is connected to the voltage signal VBN6, the source of the high-voltage NMOS tube HVNM5 is connected to the drain of the low-voltage NMOS tube NM6, the gate of the low-voltage NMOS tube NM6 is connected to the voltage signal VBN5, the source of the low-voltage NMOS tube NM6 is connected to the drain of the low-voltage NMOS tube NM7, the gate of the low-voltage NMOS tube NM7 is connected to the voltage signal VBN4, and the source of the low-voltage NMOS tube NM7 is grounded.

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