Low-power-consumption digital filter circuit and filtering method thereof

Abstract

The invention discloses a low-power-consumption digital filter circuit and a filtering method thereof, the low-power-consumption digital filter circuit comprises a 2-N-power frequency divider and a counter, a first input end of the 2-N-power frequency divider inputs a signal sig, a second input end of the 2-N-power frequency divider inputs a high-speed clock signal clk, a third input end of the 2-N-power frequency divider inputs a preset frequency division value, and a second input end of the 2-N-power frequency divider inputs a high-speed clock signal clk. A total low effective reset signal is input to a fourth input end of the N-th power frequency divider of the 2, a first output end of the N-th power frequency divider of the 2 is connected with a first input end of the counter pair and generates a signal slowclk, a second output end of the N-th power frequency divider of the 2 is connected with a second input end of the counter pair and generates a signal sigsync, the counter inputs a pre-designed numerical value cntexp to a third input end, and a second input end of the counter pair is connected with a fourth input end of the N-th power frequency divider of the 2. And the output end of the timer outputs a signal sigout. According to the invention, signal filtering under the condition of lowest power consumption is realized.

Description

Technical Field

[0001] The present invention relates to a filtering circuit and a filtering method thereof, in particular to a low-power consumption digital filtering circuit and a filtering method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] In the digital-to-analog interface, there is often a need for filtering for signals from analog to digital. High-frequency interference can be filtered out using an analog RC circuit, and low-frequency interference can usually be filtered out using a digital counter. In particular, the analog-to-digital abnormal alarm signal that often appears in the digital-to-analog interface is usually 0. It will only become high when an abnormal error occurs, and once it becomes high, it will be latched. For this type of signal, interference with high levels needs to be filtered out, but interference with low levels can be ignored.

[0003] Nowadays, large-scale VLSI is becoming more and more popular, and full synchronous design is popular because it is friendly to the back-end process of IC design. However, this design method will bring extremely high power consumption, especially when the single input clock frequency is very high and the filtered interference requires a long counting cycle to determine whether it is interference, and multiple counters are required to perform frequent flip counting, which brings great power consumption. Summary of the invention

[0004] The present invention provides a low-power digital filtering circuit and a filtering method thereof, which reduce dynamic power consumption and have a lower counter bit number.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A low-power digital filter circuit comprises a 2-N power frequency divider and a counter, wherein a signal sig is input to the first input terminal of the 2-N power frequency divider, a high-speed clock signal clk is input to the second input terminal of the 2-N power frequency divider, a preset frequency division value is input to the third input terminal of the 2-N power frequency divider, a total low effective reset signal is input to the fourth input terminal of the 2-N power frequency divider, a first output terminal of the 2-N power frequency divider is connected to the first input terminal of the counter pair and generates a signal slow_clk, a second output terminal of the 2-N power frequency divider is connected to the second input terminal of the counter pair and generates a signal sig_sync, a pre-designed value cnt_exp is input to the third input terminal of the counter pair, and an output terminal of the timer outputs a signal sig_out.

[0006] Furthermore, the 2-to-N power frequency divider divides the high-speed clock signal clk according to a preset frequency division value.

[0007] Further, the 2N power frequency divider comprises a D flip-flop D1, a D flip-flop D2, a D flip-flop D3, a D flip-flop D4, an OR gate OR1, an OR gate OR2, an OR gate OR3, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, a multiple-choice selector and a synchronizer, the input end of the synchronizer is connected to the signal sig, the rst end of the synchronizer is connected to the total low effective reset signal, the output end of the synchronizer is connected to the set end of the D flip-flop D1, the set end of the D flip-flop D2, the set end of the D flip-flop D3 and the set end of the D flip-flop D4 and generates a signal The signal sig_sync, the clk terminal of the D flip-flop D1 is connected to the high-speed clock signal clk, the Q terminal of the D flip-flop D1 is connected to the first input terminal of the OR gate OR1, the input terminal of the inverter INV1 and the first input terminal of the multiple-select-one selector, the second input terminal of the OR gate OR1 is connected to the second preset frequency division value EN2 or the third preset frequency division value EN3 or the fourth preset frequency division value EN4, the output terminal of the inverter INV1 is connected to the D terminal of the D flip-flop D1, the output terminal of the OR gate OR1 is connected to the clk terminal of the D flip-flop D2, the Q terminal of the D flip-flop D2 is connected to the first input terminal, the inverter INV1 and the first input terminal of the OR gate OR2. The input end of the phase inverter INV2 is connected to the second input end of the multiple-select-one selector, the second input end of the OR gate OR2 is connected to the third preset frequency division value EN3 or the fourth preset frequency division value EN4, the output end of the inverter INV2 is connected to the D end of the D flip-flop D2, the output end of the OR gate OR2 is connected to the clk end of the D flip-flop D3, the Q end of the D flip-flop D3 is connected to the first input end of the OR gate OR3, the input end of the inverter INV3 and the third input end of the multiple-select-one selector, the second input end of the OR gate OR3 is connected to the fourth preset frequency division value EN4, the output end of the inverter INV3 is connected to the D flip-flop D 3, the output end of the OR gate OR3 is connected to the clk end of the D flip-flop D4, the Q end of the D flip-flop D4 is connected to the input end of the inverter INV4 and the fourth input end of the multiple-selection selector, the output end of the inverter INV4 is connected to the D end of the D flip-flop D4, the fifth input end of the multiple-selection selector is connected to the first preset frequency division value EN1, the second preset frequency division value EN2, the third preset frequency division value EN3 or the fourth preset frequency division value EN4, the output end of the multiple-selection selector is connected to the input end of the inverter INV5, and the output end of the inverter INV5 generates a signal slow_clk.

[0008] Furthermore, the counter adopts a traveling wave frequency division counter.

[0009] A filtering method for a low-power digital filtering circuit comprises the following steps: According to the preset frequency division value set in advance, the multiple-select-one selector selects the required frequency division clock as the signal slow_clk, and at the same time, according to the preset frequency division value set in advance, the clock input signal of the unnecessary output signal DIV is locked to 1 by the OR gate to prevent the inversion of the output signal DIV, thereby reducing the power consumption of the entire circuit; Set the pre-designed value cnt_exp in advance and ensure that the pre-designed value cnt_exp is stable during the entire working period; When the 2N power divider starts working, the signal sig_sync will become high, and the signal slow_clk will send out the divided clock signal; the counter adds 1 at the rising edge of each divided clock signal, and compares the accumulated value of the counter with the pre-designed value cnt_exp. If they are equal, the accumulated value of the counter will no longer increase, and the signal sig_out will become high; If there is an interference signal on the signal sig, the interference signal causes the signal sig to become high for several clock cycles and the time is less than the preset frequency division value and the pre-designed value cnt_exp, that is, the accumulated value of the counter is less than the pre-designed value cnt_exp, and the signal sig_out remains low; If the time when the signal sig is high is greater than or equal to the preset frequency division value and the pre-designed value cnt_exp, the signal sig_out will become high after the filtering time. When the signal sig becomes low again, 2 high-speed clock signal clk cycles later, the signal sig_out also becomes low.

[0010] Furthermore, the preset frequency division value is set and ensured to be stable during the entire working period; When the total low effective reset signal and the signal sig are both high, and after two cycles of the high-speed clock signal clk, the signal sig_sync output by the synchronizer becomes high and the 2-N power divider starts to work; For the D flip-flop D1, when the signal sig_sync is low, the output signal DIV1 of the D flip-flop D1 is high; when the signal sig_sync is high, the output DIV1 of the D flip-flop D1 is inverted at the rising edge of the high-speed clock signal clk, so the output signal DIV1 is a two-frequency clock of the high-speed clock signal clk; For the D flip-flop D2, the output signal DIV1 is used as the input clock signal. When the signal sig_sync is low, the output signal DIV2 of the D flip-flop D2 is high. When the signal sig_sync is high, the output signal DIV2 of the D flip-flop D2 is inverted at the rising edge of the output signal DIV1. Therefore, the output signal DIV2 is a two-frequency clock of the output signal DIV1, and is also a four-frequency clock of the high-speed clock signal clk. For the D flip-flop D3, the output signal DIV2 is used as the input clock signal. When the signal sig_sync is low, the output signal DIV3 of the D flip-flop D3 is high; when the signal sig_sync is high, the output signal DIV3 of the D flip-flop D3 is inverted at the rising edge of the output signal DIV2, so the output signal DIV3 is a two-frequency clock of the output signal DIV2, and is also an eight-frequency clock of the high-speed clock signal clk; For the D flip-flop D4, the output signal DIV3 is used as the input clock signal. When the signal sig_sync is low, the output signal DIV4 of the D flip-flop D4 is high. When the signal sig_sync is high, the output signal DIV4 of the D flip-flop D4 is inverted at the rising edge of the output signal DIV3. Therefore, the output signal DIV4 is a two-divided clock of the output signal DIV3, and is also a 16-divided clock of the high-speed clock signal clk.

[0011] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a low-power digital filtering circuit and a filtering method thereof. First, a high-speed clock is slowed down by a frequency divider because the high-speed clock has high power consumption. On the other hand, a lower-speed counting clock reduces the number of bits of the counter and also reduces power consumption. At the same time, the present invention selects a 2N-power frequency division method and implements the frequency division function with the simplest circuit, which greatly reduces dynamic power consumption. Finally, the chain structure of the frequency division method ensures that when the frequency divider is not working, only the CLK end of the first-stage frequency division register DIV1 has dynamic power consumption, and all other frequency division registers have no dynamic power consumption. At the same time, the counter has no dynamic power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of a low-power digital filter circuit of the present invention.

[0013] Figure 2 Schematic diagram of a 2-to-N power frequency divider of the present invention.

[0014] Figure 3 4 is a working waveform diagram of the frequency divider according to the embodiment of the present invention.

[0015] Figure 4 1 is a working waveform diagram of a counter pair according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0017] like Figure 1 As shown, a low-power digital filter circuit of the present invention comprises a 2-N power frequency divider and a counter, the first input terminal of the 2-N power frequency divider inputs a signal sig, the second input terminal of the 2-N power frequency divider inputs a high-speed clock signal clk, the third input terminal of the 2-N power frequency divider inputs a preset frequency division value, the fourth input terminal of the 2-N power frequency divider inputs a total low-effective reset signal, the first output terminal of the 2-N power frequency divider is connected to the first input terminal of the counter pair and generates a signal slow_clk, the second output terminal of the 2-N power frequency divider is connected to the second input terminal of the counter pair and generates a signal sig_sync, the third input terminal of the counter pair inputs a pre-designed value cnt_exp, and the output terminal of the timer outputs a signal sig_out.

[0018] The 2N power divider divides the high-speed clock signal clk according to the preset division value. 2N power division means that the divider can only divide the input clock according to integer powers of 2 such as 2, 4, 8, 16, etc. There are several advantages to using 2N power division: first, such a divider is the simplest and has the lowest power consumption; second, if a large division coefficient is required, the circuit expansion is also very simple; third, an OR gate is inserted between each level output and the next level input, and when the next few levels of registers do not need to work, the power consumption of the subsequent circuit can be reduced. Fourth, the divider only works when the input signal is high, which can also reduce the power consumption of the circuit.

[0019] like Figure 2As shown, the 2N power frequency divider includes a D flip-flop D1, a D flip-flop D2, a D flip-flop D3, a D flip-flop D4, an OR gate OR1, an OR gate OR2, an OR gate OR3, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, a multiple-choice selector and a synchronizer, wherein the input end of the synchronizer is connected to the signal sig, the rst end of the synchronizer is connected to the total low effective reset signal, and the output end of the synchronizer is connected to the set end of the D flip-flop D1, the set end of the D flip-flop D2, the set end of the D flip-flop D3 and the set end of the D flip-flop D4 and generates a signal si g_sync, the clk terminal of the D flip-flop D1 is connected to the high-speed clock signal clk, the Q terminal of the D flip-flop D1 is connected to the first input terminal of the OR gate OR1, the input terminal of the inverter INV1 and the first input terminal of the multiple-select selector, the second input terminal of the OR gate OR1 is connected to the second preset frequency division value EN2 or the third preset frequency division value EN3 or the fourth preset frequency division value EN4, the output terminal of the inverter INV1 is connected to the D terminal of the D flip-flop D1, the output terminal of the OR gate OR1 is connected to the clk terminal of the D flip-flop D2, the Q terminal of the D flip-flop D2 is connected to the first input terminal of the OR gate OR2, the input terminal of the inverter INV1 and the first input terminal of the multiple-select selector. The input end of INV2 is connected to the second input end of the multiple-select-one selector, the second input end of the OR gate OR2 is connected to the third preset frequency division value EN3 or the fourth preset frequency division value EN4, the output end of the inverter INV2 is connected to the D end of the D flip-flop D2, the output end of the OR gate OR2 is connected to the clk end of the D flip-flop D3, the Q end of the D flip-flop D3 is connected to the first input end of the OR gate OR3, the input end of the inverter INV3 and the third input end of the multiple-select-one selector, the second input end of the OR gate OR3 is connected to the fourth preset frequency division value EN4, the output end of the inverter INV3 is connected to the D flip-flop D3 The D end of the D trigger D4 is connected, the output end of the OR gate OR3 is connected to the clk end of the D trigger D4, the Q end of the D trigger D4 is connected to the input end of the inverter INV4 and the fourth input end of the multiple-select selector, the output end of the inverter INV4 is connected to the D end of the D trigger D4, the fifth input end of the multiple-select selector is connected to the first preset frequency division value EN1, the second preset frequency division value EN2, the third preset frequency division value EN3 or the fourth preset frequency division value EN4, the output end of the multiple-select selector is connected to the input end of the inverter INV5, and the output end of the inverter INV5 generates a signal slow_clk.

[0020] The present invention uses a ripple counter to divide the high-speed clock first, and selects one of the outputs of each frequency division register at the same time, and uses the selected clock as the counting clock of the subsequent counter. While ensuring a certain degree of freedom in frequency division, the frequency division circuit is reduced to the extreme, greatly reducing dynamic power consumption. At the same time, several tricks are cleverly used to reduce the requirements for asynchronous signal delay, and the smallest design area and the lowest dynamic power consumption are achieved while keeping the original back-end process unchanged.

[0021] The counter adopts a ripple frequency division counter. The present invention adopts a ripple counting method to divide the frequency of a single input clock, and uses the divided clock as the counter clock. When the input signal to be filtered is continuously high, the counter counts. As long as the input signal to be filtered is low, the counter is immediately cleared. Only when the input signal to be filtered is continuously high and the count value of the counter reaches a preset value, it is considered that the effective signal becomes high, otherwise the input high is filtered out as interference.

[0022] A filtering method for a low-power digital filtering circuit comprises the following steps: Set the preset frequency division value and ensure that the preset frequency division value is stable during the entire working period. Otherwise, the frequency of the output signal slow_clk will be unstable at the moment of frequency division value switching. Or do not use the output signal slow_clk during the period when the preset frequency division value changes, and use it after the clock frequency of the signal is stable.

[0023] When the total low effective reset signal and the signal sig are both high, and after two cycles of the high-speed clock signal clk, the signal sig_sync output by the synchronizer becomes high and the 2-N power divider starts to work.

[0024] For the D flip-flop D1, when the signal sig_sync is low, the output signal DIV1 of the D flip-flop D1 is high; when the signal sig_sync is high, the output DIV1 of the D flip-flop D1 is inverted at the rising edge of the high-speed clock signal clk, so the output signal DIV1 is a two-divided clock of the high-speed clock signal clk.

[0025] For the D flip-flop D2, the output signal DIV1 is used as the input clock signal. When the signal sig_sync is low, the output signal DIV2 of the D flip-flop D2 is high. When the signal sig_sync is high, the output signal DIV2 of the D flip-flop D2 is inverted at the rising edge of the output signal DIV1. Therefore, the output signal DIV2 is a two-divided clock of the output signal DIV1, and is also a four-divided clock of the high-speed clock signal clk.

[0026] For the D flip-flop D3, the output signal DIV2 is used as the input clock signal. When the signal sig_sync is low, the output signal DIV3 of the D flip-flop D3 is high. When the signal sig_sync is high, the output signal DIV3 of the D flip-flop D3 is inverted at the rising edge of the output signal DIV2. Therefore, the output signal DIV3 is a two-divided clock of the output signal DIV2, and is also an eight-divided clock of the high-speed clock signal clk.

[0027] For the D flip-flop D4, the output signal DIV3 is used as the input clock signal. When the signal sig_sync is low, the output signal DIV4 of the D flip-flop D4 is high. When the signal sig_sync is high, the output signal DIV4 of the D flip-flop D4 is inverted at the rising edge of the output signal DIV3. Therefore, the output signal DIV4 is a two-divided clock of the output signal DIV3, and is also a 16-divided clock of the high-speed clock signal clk.

[0028] According to the preset division value set in advance, the multiple-selector selects the required division clock as the signal slow_clk, and at the same time, according to the preset division value set in advance, the clock input signal of the unnecessary output signal DIV is locked to 1 by the OR gate to prevent the inversion of the output signal DIV, thereby reducing the power consumption of the entire circuit.

[0029] like Figure 3 As shown, when the preset frequency division value {EN1, EN2, EN3, EN4} = 4'b1110, the total low effective reset signal is high, and sig changes high and then changes low.

[0030] Set the pre-designed value cnt_exp in advance and ensure that the pre-designed value cnt_exp is stable during the entire working period. Otherwise, the counter output signal sig_out may be erroneous.

[0031] When the 2N power divider starts working, the signal sig_sync will become high, and the signal slow_clk will send out the divided clock signal; the counter adds 1 at the rising edge of each divided clock signal, and compares the accumulated value of the counter with the pre-designed value cnt_exp. If they are equal, the accumulated value of the counter will no longer increase, and the signal sig_out will become high.

[0032] If there is an interference signal on the signal sig, the interference signal causes the signal sig to become high for several clock cycles and the time is less than the preset frequency division value and the pre-designed value cnt_exp, that is, the accumulated value of the counter is less than the pre-designed value cnt_exp, and the signal sig_out remains low.

[0033] If the time when the signal sig is high is greater than or equal to the preset frequency division value and the pre-designed value cnt_exp, the signal sig_out will become high after the filtering time. When the signal sig becomes low again, 2 high-speed clock signal clk cycles later, the signal sig_out also becomes low.

[0034] like Figure 4 Signal sig is shown going high long enough to cause signal sig_out to go high.

[0035] It can be seen that the 2N power frequency divider eliminates the need for the counter to operate at a high-speed clock frequency, thereby saving power consumption. At the same time, the 2N power frequency divider uses a step-by-step triggering method, which can ensure that clock frequency division is achieved with a minimum number of logic gates and the highest signal inversion efficiency. The present invention achieves signal filtering with the lowest power consumption.

[0036] The present invention provides a low-power digital filtering circuit and a filtering method thereof. Firstly, a high-speed clock is slowed down by a frequency divider because the high-speed clock has high power consumption. On the other hand, a lower-speed counting clock reduces the number of bits of a counter and also reduces power consumption. At the same time, the present invention selects a 2-N power frequency division method and implements the frequency division function with the simplest circuit, which greatly reduces dynamic power consumption. Finally, the chain structure of the frequency division method ensures that when the frequency divider is not working, only the CLK end of the first-stage frequency division register DIV1 has dynamic power consumption, and all other frequency division registers have no dynamic power consumption. At the same time, the counter has no dynamic power consumption.

[0037] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A low power consumption digital filter circuit, characterized in that: It comprises a 2'N power frequency divider and a counter, wherein the first input terminal of the 2'N power frequency divider inputs a signal sig, the second input terminal of the 2'N power frequency divider inputs a high-speed clock signal clk, the third input terminal of the 2'N power frequency divider inputs a preset frequency division value, the fourth input terminal of the 2'N power frequency divider inputs a total low-valid reset signal, the first output terminal of the 2'N power frequency divider is connected to the first input terminal of the counter pair and generates a signal slow_clk, the second output terminal of the 2'N power frequency divider is connected to the second input terminal of the counter pair and generates a signal sig_sync, the third input terminal of the counter pair inputs a pre-designed value cnt_exp, and the output terminal of the timer outputs a signal sig_out.

2. A low power consumption digital filter circuit according to claim 1, characterized in that: The 2-to-N power frequency divider divides the high-speed clock signal clk according to a preset frequency division value.

3. A low power consumption digital filter circuit according to claim 1, characterized in that: The 2N power frequency divider comprises a D flip-flop D1, a D flip-flop D2, a D flip-flop D3, a D flip-flop D4, an OR gate OR1, an OR gate OR2, an OR gate OR3, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, a multiple-choice selector and a synchronizer, wherein the input end of the synchronizer is connected to the signal sig, the rst end of the synchronizer is connected to the total low effective reset signal, and the output end of the synchronizer is connected to the set end of the D flip-flop D1, the set end of the D flip-flop D2, the set end of the D flip-flop D3 and the set end of the D flip-flop D4 and generates a signal si g_sync, the clk terminal of the D flip-flop D1 is connected to the high-speed clock signal clk, the Q terminal of the D flip-flop D1 is connected to the first input terminal of the OR gate OR1, the input terminal of the inverter INV1 and the first input terminal of the multiple-select selector, the second input terminal of the OR gate OR1 is connected to the second preset frequency division value EN2 or the third preset frequency division value EN3 or the fourth preset frequency division value EN4, the output terminal of the inverter INV1 is connected to the D terminal of the D flip-flop D1, the output terminal of the OR gate OR1 is connected to the clk terminal of the D flip-flop D2, the Q terminal of the D flip-flop D2 is connected to the first input terminal of the OR gate OR2, the input terminal of the inverter INV1 and the first input terminal of the multiple-select selector. The input end of INV2 is connected to the second input end of the multiple-select-one selector, the second input end of the OR gate OR2 is connected to the third preset frequency division value EN3 or the fourth preset frequency division value EN4, the output end of the inverter INV2 is connected to the D end of the D flip-flop D2, the output end of the OR gate OR2 is connected to the clk end of the D flip-flop D3, the Q end of the D flip-flop D3 is connected to the first input end of the OR gate OR3, the input end of the inverter INV3 and the third input end of the multiple-select-one selector, the second input end of the OR gate OR3 is connected to the fourth preset frequency division value EN4, the output end of the inverter INV3 is connected to the D flip-flop D3 The D end of the D trigger D4 is connected, the output end of the OR gate OR3 is connected to the clk end of the D trigger D4, the Q end of the D trigger D4 is connected to the input end of the inverter INV4 and the fourth input end of the multiple-select selector, the output end of the inverter INV4 is connected to the D end of the D trigger D4, the fifth input end of the multiple-select selector is connected to the first preset frequency division value EN1, the second preset frequency division value EN2, the third preset frequency division value EN3 or the fourth preset frequency division value EN4, the output end of the multiple-select selector is connected to the input end of the inverter INV5, and the output end of the inverter INV5 generates a signal slow_clk.

4. A low power consumption digital filter circuit according to claim 1, characterized in that: The counter adopts a traveling wave frequency division counter.

5. A filtering method for a low-power digital filtering circuit according to any one of claims 1 to 4, characterized in that The following steps are involved: According to the preset frequency division value set in advance, the multiple-select-one selector selects the required frequency division clock as the signal slow_clk, and at the same time, according to the preset frequency division value set in advance, the clock input signal of the unnecessary output signal DIV is locked to 1 by the OR gate to prevent the inversion of the output signal DIV, thereby reducing the power consumption of the entire circuit; Set the pre-designed value cnt_exp in advance and ensure that the pre-designed value cnt_exp is stable during the entire working period; When the 2N power divider starts working, the signal sig_sync will become high, and the signal slow_clk will send out the divided clock signal; the counter adds 1 at the rising edge of each divided clock signal, and compares the accumulated value of the counter with the pre-designed value cnt_exp. If they are equal, the accumulated value of the counter will no longer increase, and the signal sig_out will become high; If there is an interference signal on the signal sig, the interference signal causes the signal sig to become high for several clock cycles and the time is less than the preset frequency division value and the pre-designed value cnt_exp, that is, the accumulated value of the counter is less than the pre-designed value cnt_exp, and the signal sig_out remains low; If the time when the signal sig is high is greater than or equal to the preset frequency division value and the pre-designed value cnt_exp, the signal sig_out will become high after the filtering time. When the signal sig becomes low again, 2 high-speed clock signal clk cycles later, the signal sig_out also becomes low.

6. The filtering method according to claim 5, characterized in that: Set the preset frequency division value and ensure that the preset frequency division value is stable during the entire working period; When the total low effective reset signal and the signal sig are both high, and after two cycles of the high-speed clock signal clk, the signal sig_sync output by the synchronizer becomes high and the 2-N power divider starts to work; For the D flip-flop D1, when the signal sig_sync is low, the output signal DIV1 of the D flip-flop D1 is high; when the signal sig_sync is high, the output DIV1 of the D flip-flop D1 is inverted at the rising edge of the high-speed clock signal clk, so the output signal DIV1 is a two-frequency clock of the high-speed clock signal clk; For the D flip-flop D2, the output signal DIV1 is used as the input clock signal. When the signal sig_sync is low, the output signal DIV2 of the D flip-flop D2 is high; when the signal sig_sync is high, the output signal DIV2 of the D flip-flop D2 is inverted at the rising edge of the output signal DIV1, so the output signal DIV2 is a two-frequency clock of the output signal DIV1, and is also a four-frequency clock of the high-speed clock signal clk; For the D flip-flop D3, the output signal DIV2 is used as the input clock signal. When the signal sig_sync is low, the output signal DIV3 of the D flip-flop D3 is high; when the signal sig_sync is high, the output signal DIV3 of the D flip-flop D3 is inverted at the rising edge of the output signal DIV2, so the output signal DIV3 is a two-frequency clock of the output signal DIV2, and is also an eight-frequency clock of the high-speed clock signal clk; For the D flip-flop D4, the output signal DIV3 is used as the input clock signal. When the signal sig_sync is low, the output signal DIV4 of the D flip-flop D4 is high. When the signal sig_sync is high, the output signal DIV4 of the D flip-flop D4 is inverted at the rising edge of the output signal DIV3. Therefore, the output signal DIV4 is a two-divided clock of the output signal DIV3, and is also a 16-divided clock of the high-speed clock signal clk.

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