Second-order continuous time sigma-delta modulator circuit

Abstract

The invention discloses a second-order continuous time sigma-delta modulator circuit, which comprises a first-order continuous time modulator circuit and a second-order continuous time modulator circuit, the circuit comprises a first-stage active RC integrator, a second-stage active RC integrator, a divider resistor R31, a divider resistor R32, a comparator CMP, a delay unit DZ1, a delay unit DZ2, a first-stage current type feedback IDAC-F11, a first-stage current type feedback IDAC-F12, a second-stage current type feedback IDAC-F21, a second-stage current type feedback IDAC-F22, a third-stage resistance type feedback RDAC-F1, a third-stage resistance type feedback RDAC-F2, a buffer F1 and a buffer F2. The current type DAC is used for replacing a resistance type DAC, so that the clock noise influence is reduced, and meanwhile, the area of the circuit is reduced.

Description

Technical Field

[0001] The invention relates to a modulator circuit, in particular to a second-order continuous-time sigma-delta modulator circuit, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] An analog-to-digital data converter is a circuit that converts analog signals in the real world into digital signals. In magnetic signal applications, due to the large range of changes in magnetic signals, the analog-to-digital data converter used is required to have a large dynamic range, which also requires that the out-of-band noise be significantly attenuated during signal processing, increasing the difficulty of filter design. If the loop transfer function of the continuous-time sigma-delta analog-to-digital converter is designed to not contain a constant term, its STF (signal transfer function) will have filtering characteristics near the Nyquist frequency, so that the continuous-time sigma-delta analog-to-digital data converter can have a natural anti-aliasing characteristic, which can relax the design requirements for the filter in front of the ADC and save power and area. In addition, the continuous-time sigma-delta analog-to-digital data converter has a resistor input and is easy to drive. For the continuous-time sigma-delta analog-to-digital data converter, its stability is an issue that must be considered for design. For Sigma-delta modulators of different structures, the intuitive basis for determining its stability is related to the out-of-band noise gain of the modulator. For a second-order Sigma-delta modulator, its out-of-band noise gain should be controlled to be less than 2. In order to apply the anti-aliasing characteristics of the continuous-time Sigma-delta modulator, the input signal cannot be introduced at the input node of the comparator. Therefore, it is best to use the CIFB structure to implement it. For the second-order CIFB structure modulator, the roll-off of its signal transfer function at high frequencies is 1 / S 2 , and has a strong ability to suppress out-of-band noise.

[0003] The classic continuous-time sigma-delta analog-to-digital data converter structure is shown in the figure below. Figure 5 : It is mainly composed of integrator, comparator and DAC. One limitation of continuous-time sigma-delta analog-to-digital data converter is that the non-ideal jitter of the clock will affect the feedback characteristics of the DAC. This effect cannot be removed by loop filtering. If it is not processed, it will seriously affect the effective number of bits of the analog-to-digital data converter.

[0004] For a continuous-time sigma-delta modulator, its output accuracy is mainly related to the signal itself, power supply voltage, reference voltage, circuit noise, and clock noise. The noise performance of the signal itself is determined by the signal itself. The noise performance of the power supply voltage and reference voltage can be controlled by modules such as LDO. The noise of the circuit itself can be controlled by increasing the current and circuit area. In chiplet design, the clock is usually generated directly by the OSC circuit. The clock performance generated by the OSC circuit is usually poor and difficult to eliminate in the design, so it has a great impact on the performance of the continuous-time sigma-delta modulator.

[0005] exist Figure 5 The output can be expressed as follows: ; where e q (s) represents the quantization noise of the comparator, which is shaped by the high-pass filter in the loop, e dac (s) represents the clock noise reflected in the DAC, which is not shaped by the loop and directly affects the performance of the modulator.

[0006] The noise introduced by the clock circuit jitter can be estimated by the following formula: ; where σ Δt is the standard deviation of clock jitter, T s is the period of the clock, and OSR is the oversampling rate of the modulator.

[0007] In order to reduce the impact of this part of noise, the industry usually uses multi-bit quantizers or introduces FIR DAC to reduce the amplitude of noise. However, traditional resistive FIR DAC usually requires the use of a large number of resistors, which often occupy a large area and increase the cost of the chip. Summary of the invention

[0008] The technical problem to be solved by the present invention is to provide a second-order continuous-time sigma-delta modulator circuit, which reduces clock noise and circuit area at the same time.

[0009] In order to solve the above technical problems, the technical solution adopted by the present invention is: A second-order continuous-time sigma-delta modulator circuit comprises a first-stage active RC integrator, a second-stage active RC integrator, a voltage-dividing resistor R31, a voltage-dividing resistor R32, a comparator CMP, a delay unit DZ1, a delay unit DZ2, a first-stage current-type feedback IDAC-F11, a first-stage current-type feedback IDAC-F12, a second-stage current-type feedback IDAC-F21, a second-stage current-type feedback IDAC-F22, a third-stage resistor-type feedback RDAC-F1, a third-stage resistor-type feedback RDAC-F2, a buffer F1 and a buffer F2, wherein the negative phase input terminal of the first-stage active RC integrator is connected to an input signal VIP, and the negative phase input terminal of the first-stage active RC integrator is connected to an input signal VIP. The positive phase input terminal is connected to the input signal VIN, the positive phase output terminal of the first-stage active RC integrator is connected to the positive phase input terminal of the second-stage active RC integrator, the negative phase output terminal of the first-stage active RC integrator is connected to the negative phase input terminal of the second-stage active RC integrator, the positive phase output terminal of the second-stage active RC integrator is connected to one end of the voltage dividing resistor R31, the other end of the voltage dividing resistor R31 is connected to the negative phase input terminal of the comparator CMP, the negative phase output terminal of the second-stage active RC integrator is connected to one end of the voltage dividing resistor R32, the other end of the voltage dividing resistor R32 is connected to the positive phase input terminal of the comparator CMP, the positive phase output terminal of the comparator CMP is connected to the input terminal of the buffer F1 and the input terminal of the delay unit DZ1, the buffer F1 The output end of the comparator CMP generates an output signal VOUTP, the negative phase output end of the comparator CMP is connected to the input end of the buffer F2 and the input end of the delay unit DZ2, the output end of the buffer F2 generates an output signal VOUTN, the output end of the delay unit DZ1 is connected to the input end of the first-stage current-type feedback IDAC-F11, the input end of the second-stage current-type feedback IDAC-F21 and the input end of the third-stage resistance-type feedback RDAC-F1, the output end of the first-stage current-type feedback IDAC-F11 is connected to the negative phase input end of the operational amplifier in the first-stage active RC integrator, the output end of the second-stage current-type feedback IDAC-F21 is connected to the negative phase input end of the operational amplifier in the second-stage active RC integrator The output end of the third-stage resistive feedback RDAC-F1 is connected to the negative phase input end of the comparator CMP, the output end of the delay unit DZ2 is connected to the input end of the first-stage current-type feedback IDAC-F12, the input end of the second-stage current-type feedback IDAC-F22 and the input end of the third-stage resistive feedback RDAC-F2, the output end of the first-stage current-type feedback IDAC-F12 is connected to the positive phase input end of the operational amplifier in the first-stage active RC integrator, the output end of the second-stage current-type feedback IDAC-F22 is connected to the positive phase input end of the operational amplifier in the second-stage active RC integrator, and the output end of the third-stage resistive feedback RDAC-F2 is connected to the positive phase input end of the comparator CMP.

[0010] Further, the first-stage active RC integrator includes an integrating resistor R11, an integrating resistor R12, an integrating capacitor C11, an integrating capacitor C12 and an operational amplifier OTA1, one end of the integrating resistor R11 serves as a negative phase input end of the first-stage active RC integrator, the other end of the integrating resistor R11 is connected to one end of the integrating capacitor C11, the negative phase input end of the operational amplifier OTA1 and the output end of the first-stage current-type feedback IDAC-F11, the positive phase output end of the operational amplifier OTA1 is connected to the other end of the integrating capacitor C11 and serves as a positive phase output end of the first-stage active RC integrator, one end of the integrating resistor R12 serves as a positive phase input end of the first-stage active RC integrator, the other end of the integrating resistor R12 is connected to one end of the integrating capacitor C12, the positive phase input end of the operational amplifier OTA1 and the output end of the first-stage current-type feedback IDAC-F12, the negative phase output end of the operational amplifier OTA1 is connected to the other end of the integrating capacitor C12 and serves as a negative phase output end of the first-stage active RC integrator.

[0011] Further, the second-stage active RC integrator includes an integrating resistor R21, an integrating resistor R22, an integrating capacitor C21, an integrating capacitor C22 and an operational amplifier OTA2, one end of the integrating resistor R21 serves as a negative phase input end of the second-stage active RC integrator, the other end of the integrating resistor R21 is connected to one end of the integrating capacitor C21, the negative phase input end of the operational amplifier OTA2 and the output end of the second-stage current-type feedback IDAC-F21, the positive phase output end of the operational amplifier OTA2 is connected to the other end of the integrating capacitor C21 and serves as a positive phase output end of the second-stage active RC integrator, one end of the integrating resistor R22 serves as a positive phase input end of the second-stage active RC integrator, the other end of the integrating resistor R22 is connected to one end of the integrating capacitor C22, the positive phase input end of the operational amplifier OTA2 and the output end of the second-stage current-type feedback IDAC-F22, the negative phase output end of the operational amplifier OTA2 is connected to the other end of the integrating capacitor C22 and serves as a negative phase output end of the second-stage active RC integrator.

[0012] Further, the delay unit DZ1 and the delay unit DZ2 respectively include D flip-flops D0~D7, the Clk terminals of the D flip-flops D0~D7 are connected to the clock signal CLK, the Set terminals of the D flip-flops D0~D7 are connected to the reset signal RESET, the D terminal of the D flip-flop D0 is connected to the input signal IN, the Q terminals of the D flip-flops D0~D7 sequentially generate output signals DOP~D7P, and the Q non-terminals of the D flip-flops D0~D7 sequentially generate output signals DON~D7N, and for two adjacent D flip-flops D(n-1) and Dn, n=1, 2, ..., 7, the Q terminal of the D flip-flop D(n-1) is connected to the D terminal of the D flip-flop Dn.

[0013] Further, the first-stage current-type feedback IDAC-F11, the first-stage current-type feedback IDAC-F12, the second-stage current-type feedback IDAC-F21 and the second-stage current-type feedback IDAC-F22 respectively include eight current-type basic units, each of which includes a PMOS tube MP0, a PMOS tube MP1, a PMOS tube MP2, an NMOS tube MN0, an NMOS tube MN1 and an NMOS tube MN2, the source of the PMOS tube MP0 is connected to the power supply VDD, the gate of the PMOS tube MP0 is connected to the bias voltage Vbiasp, the drain of the PMOS tube MP0 is connected to the source of the PMOS tube MP1 and the gate of the PMOS tube MP2 The source of the PMOS tube MP1 is connected to the gate of the NMOS tube MN1, the gate of the PMOS tube MP1 is connected to the gate of the NMOS tube MN1, the input signal VIPi, i=1, 2, ..., 8, the gate of the PMOS tube MP2 is connected to the gate of the NMOS tube MN2, the input signal VINi, the drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN1 and generates an output signal VON, the drain of the PMOS tube MP2 is connected to the drain of the NMOS tube MN2 and generates an output signal VOP, the source of the NMOS tube MN1 is connected to the source of the NMOS tube MN2 and the drain of the NMOS tube MN0, the gate of the NMOS tube MN0 is connected to the bias voltage Vbiasn, and the source of the NMOS tube MN0 is grounded.

[0014] Furthermore, the third-stage resistive feedback RDAC-F1 and the third-stage resistive feedback RDAC-F2 respectively include eight resistive basic units, each resistive basic unit includes a switching switch SW0 and a resistor R0, a first input end of the switching switch SW0 is connected to an input signal VP, a second input end of the switching switch SW0 is connected to an input signal VN, an output end of the switching switch SW0 is connected to one end of the resistor R0, and the other end of the resistor R0 generates an output signal OUT, and a control end of the switching switch SWO is connected to a control signal Sj, j=0, 1, ..., 7.

[0015] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a second-order continuous-time sigma-delta modulator circuit, which uses a current-type DAC to replace a resistor-type DAC to reduce the influence of clock noise while reducing the area of ​​the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of a second-order continuous-time sigma-delta modulator circuit of the present invention.

[0017] Figure 2 It is a schematic diagram of the delay unit of the present invention.

[0018] Figure 3 Schematic diagram of the current-feedback IDAC-F of the present invention.

[0019] Figure 4 Schematic diagram of the resistive feedback RDAC-F of the present invention.

[0020] Figure 5 is a schematic diagram of a first-order sigma-delta modulator circuit in the prior art. DETAILED DESCRIPTION

[0021] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0022] like Figure 1As shown, a second-order continuous-time sigma-delta modulator circuit of the present invention comprises a first-stage active RC integrator, a second-stage active RC integrator, a voltage-dividing resistor R31, a voltage-dividing resistor R32, a comparator CMP, a delay unit DZ1, a delay unit DZ2, a first-stage current-type feedback IDAC-F11, a first-stage current-type feedback IDAC-F12, a second-stage current-type feedback IDAC-F21, a second-stage current-type feedback IDAC-F22, a third-stage resistor-type feedback RDAC-F1, a third-stage resistor-type feedback RDAC-F2, a buffer F1 and a buffer F2, wherein the negative phase input terminal of the first-stage active RC integrator is connected to the input signal VIP, and the first-stage active The positive phase input terminal of the RC integrator is connected to the input signal VIN, the positive phase output terminal of the first-stage active RC integrator is connected to the positive phase input terminal of the second-stage active RC integrator, the negative phase output terminal of the first-stage active RC integrator is connected to the negative phase input terminal of the second-stage active RC integrator, the positive phase output terminal of the second-stage active RC integrator is connected to one end of the voltage-dividing resistor R31, the other end of the voltage-dividing resistor R31 is connected to the negative phase input terminal of the comparator CMP, the negative phase output terminal of the second-stage active RC integrator is connected to one end of the voltage-dividing resistor R32, the other end of the voltage-dividing resistor R32 is connected to the positive phase input terminal of the comparator CMP, the positive phase output terminal of the comparator CMP is connected to the input terminal of the buffer F1 and the input terminal of the delay unit DZ1, and the buffer is connected to the positive phase input terminal of the comparator CMP. The output end of the buffer F1 generates an output signal VOUTP, the negative phase output end of the comparator CMP is connected to the input end of the buffer F2 and the input end of the delay unit DZ2, the output end of the buffer F2 generates an output signal VOUTN, the output end of the delay unit DZ1 is connected to the input end of the first-stage current-type feedback IDAC-F11, the input end of the second-stage current-type feedback IDAC-F21 and the input end of the third-stage resistance-type feedback RDAC-F1, the output end of the first-stage current-type feedback IDAC-F11 is connected to the negative phase input end of the operational amplifier in the first-stage active RC integrator, the output end of the second-stage current-type feedback IDAC-F21 is connected to the negative phase input end of the operational amplifier in the second-stage active RC integrator The output end of the third-stage resistive feedback RDAC-F1 is connected to the negative phase input end of the comparator CMP, the output end of the delay unit DZ2 is connected to the input end of the first-stage current-type feedback IDAC-F12, the input end of the second-stage current-type feedback IDAC-F22 and the input end of the third-stage resistive feedback RDAC-F2, the output end of the first-stage current-type feedback IDAC-F12 is connected to the positive phase input end of the operational amplifier in the first-stage active RC integrator, the output end of the second-stage current-type feedback IDAC-F22 is connected to the positive phase input end of the operational amplifier in the second-stage active RC integrator, and the output end of the third-stage resistive feedback RDAC-F2 is connected to the positive phase input end of the comparator CMP.

[0023] The first-stage current-type feedback IDAC-F11, IDAC-F12 and the second-stage current-type feedback IDAC-F21, IDAC-F22 and delay units DZ1, DZ2 jointly attenuate the clock jitter noise and reduce the impact of clock jitter. The first-stage feedback DAC and the second-stage feedback DAC both use current-type DACs, which trade part of the power consumption for the DAC layout area. The third-stage resistance-type feedback RDAC-F1, RDAC-F2 and delay units DZ1, DZ2 together form a compensation DAC to compensate for the changes in the loop transfer function caused by the first-stage feedback DAC and the second-stage feedback DAC. The third-stage feedback DAC uses a resistance-type DAC, which together with the voltage-dividing resistors R31, R32 forms a resistance-dividing network in front of the comparator CMP to control the amplitude of the signal at the input end of the comparator CMP.

[0024] The first-stage active RC integrator includes an integrating resistor R11, an integrating resistor R12, an integrating capacitor C11, an integrating capacitor C12 and an operational amplifier OTA1, one end of the integrating resistor R11 serves as a negative phase input end of the first-stage active RC integrator, the other end of the integrating resistor R11 is connected to one end of the integrating capacitor C11, the negative phase input end of the operational amplifier OTA1 and the output end of the first-stage current-type feedback IDAC-F11, the positive phase output end of the operational amplifier OTA1 is connected to the other end of the integrating capacitor C11 and serves as the positive phase output end of the first-stage active RC integrator, one end of the integrating resistor R12 serves as the positive phase input end of the first-stage active RC integrator, the other end of the integrating resistor R12 is connected to one end of the integrating capacitor C12, the positive phase input end of the operational amplifier OTA1 and the output end of the first-stage current-type feedback IDAC-F12, the negative phase output end of the operational amplifier OTA1 is connected to the other end of the integrating capacitor C12 and serves as the negative phase output end of the first-stage active RC integrator.

[0025] The second-stage active RC integrator includes an integrating resistor R21, an integrating resistor R22, an integrating capacitor C21, an integrating capacitor C22 and an operational amplifier OTA2, one end of the integrating resistor R21 serves as a negative phase input end of the second-stage active RC integrator, the other end of the integrating resistor R21 is connected to one end of the integrating capacitor C21, the negative phase input end of the operational amplifier OTA2 and the output end of the second-stage current type feedback IDAC-F21, the positive phase output end of the operational amplifier OTA2 is connected to the other end of the integrating capacitor C21 and serves as the positive phase output end of the second-stage active RC integrator, one end of the integrating resistor R22 serves as the positive phase input end of the second-stage active RC integrator, the other end of the integrating resistor R22 is connected to one end of the integrating capacitor C22, the positive phase input end of the operational amplifier OTA2 and the output end of the second-stage current type feedback IDAC-F22, the negative phase output end of the operational amplifier OTA2 is connected to the other end of the integrating capacitor C22 and serves as the negative phase output end of the second-stage active RC integrator.

[0026] like Figure 2 As shown, the delay unit DZ1 and the delay unit DZ2 respectively include D flip-flops D0 to D7, the Clk terminals of the D flip-flops D0 to D7 are connected to the clock signal CLK, the Set terminals of the D flip-flops D0 to D7 are connected to the reset signal RESET, the D terminal of the D flip-flop D0 is connected to the input signal IN, the Q terminals of the D flip-flops D0 to D7 sequentially generate output signals DOP to D7P, and the Q non-terminals of the D flip-flops D0 to D7 sequentially generate output signals DON to D7N. For two adjacent D flip-flops D(n-1) and Dn, n=1, 2, ..., 7, the Q terminal of the D flip-flop D(n-1) is connected to the D terminal of the D flip-flop Dn. The reset signal RESET is controlled by the system, and the module is reset by RESET when the system is initialized. In normal operation, eight flip-flops form a delay unit, and the D flip-flop input signal is latched in turn at the rising edge of the CLK signal. Finally, the output terminals of the eight flip-flops sequentially transmit the input signal IN at intervals of one clock cycle to achieve filtering.

[0027] like Figure 3As shown, the first-stage current-type feedback IDAC-F11, the first-stage current-type feedback IDAC-F12, the second-stage current-type feedback IDAC-F21 and the second-stage current-type feedback IDAC-F22 respectively include eight current-type basic units, each of which includes a PMOS tube MP0, a PMOS tube MP1, a PMOS tube MP2, an NMOS tube MN0, an NMOS tube MN1 and an NMOS tube MN2, the source of the PMOS tube MP0 is connected to the power supply VDD, the gate of the PMOS tube MP0 is connected to the bias voltage Vbiasp, the drain of the PMOS tube MP0 is connected to the source of the PMOS tube MP1 and the source of the PMOS tube MP2 The gate of the PMOS tube MP1 and the gate of the NMOS tube MN1 are connected to the input signal VIPi, i=1, 2, ..., 8, the gate of the PMOS tube MP2 and the gate of the NMOS tube MN2 are connected to the input signal VINi, the drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN1 and generates an output signal VON, the drain of the PMOS tube MP2 is connected to the drain of the NMOS tube MN2 and generates an output signal VOP, the source of the NMOS tube MN1 is connected to the source of the NMOS tube MN2 and the drain of the NMOS tube MN0, the gate of the NMOS tube MN0 is connected to the bias voltage Vbiasn, and the source of the NMOS tube MN0 is grounded. The DAC selects current through input signals VIPi and VINi. VIPi and VINi are a pair of logically opposite signals. When VIPi is high and VINi is low, the output VON draws current from the external circuit and the output VOP injects current into the external circuit. On the contrary, when VIPi is low and VINi is high, the output VON injects current into the external circuit and the output VOP draws current from the external circuit.

[0028] like Figure 4 As shown, the third-level resistive feedback RDAC-F1 and the third-level resistive feedback RDAC-F2 respectively include eight resistive basic units, each of which includes a switching switch SW0 and a resistor R0, the first input end of the switching switch SW0 is connected to the input signal VP, the second input end of the switching switch SW0 is connected to the input signal VN, the output end of the switching switch SW0 is connected to one end of the resistor R0, the other end of the resistor R0 generates an output signal OUT, and the control end of the switching switch SWO is connected to the control signal Sj, j=0, 1, ..., 7. When the control signal Sj of the switch is high, the switch input end is connected to the input signal VN, and the circuit returns to a low level; when Sj is low, the switch input end is connected to the input signal VP, and the circuit returns to a high level. Finally, the output voltage of the RDAC is obtained by weighted average of the output voltages of the eight small modules.

[0029] The present invention provides a second-order continuous-time sigma-delta modulator circuit, which uses a current-type DAC to replace a resistance-type DAC to reduce the influence of clock noise and reduce the area of ​​the circuit at the same time.

[0030] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A second-order continuous-time sigma-delta modulator circuit, characterized in that: It includes a first-stage active RC integrator, a second-stage active RC integrator, a voltage-dividing resistor R31, a voltage-dividing resistor R32, a comparator CMP, a delay unit DZ1, a delay unit DZ2, a first-stage current-type feedback IDAC-F11, a first-stage current-type feedback IDAC-F12, a second-stage current-type feedback IDAC-F21, a second-stage current-type feedback IDAC-F22, a third-stage resistor-type feedback RDAC-F1, a third-stage resistor-type feedback RDAC-F2, a buffer F1 and a buffer F2. The negative phase input terminal of the first-stage active RC integrator is connected to the input signal VIP, the positive phase input terminal of the first-stage active RC integrator is connected to the input signal VIN, and the first The positive phase output terminal of the active RC integrator is connected to the positive phase input terminal of the second-stage active RC integrator, the negative phase output terminal of the first-stage active RC integrator is connected to the negative phase input terminal of the second-stage active RC integrator, the positive phase output terminal of the second-stage active RC integrator is connected to one end of the voltage-dividing resistor R31, the other end of the voltage-dividing resistor R31 is connected to the negative phase input terminal of the comparator CMP, the negative phase output terminal of the second-stage active RC integrator is connected to one end of the voltage-dividing resistor R32, the other end of the voltage-dividing resistor R32 is connected to the positive phase input terminal of the comparator CMP, the positive phase output terminal of the comparator CMP is connected to the input terminal of the buffer F1 and the input terminal of the delay unit DZ1, and the output terminal of the buffer F1 generates an output signal VO UTP, the negative phase output terminal of the comparator CMP is connected to the input terminal of the buffer F2 and the input terminal of the delay unit DZ2, the output terminal of the buffer F2 generates an output signal VOUTN, the output terminal of the delay unit DZ1 is connected to the input terminal of the first-stage current-type feedback IDAC-F11, the input terminal of the second-stage current-type feedback IDAC-F21 and the input terminal of the third-stage resistance-type feedback RDAC-F1, the output terminal of the first-stage current-type feedback IDAC-F11 is connected to the negative phase input terminal of the operational amplifier in the first-stage active RC integrator, the output terminal of the second-stage current-type feedback IDAC-F21 is connected to the negative phase input terminal of the operational amplifier in the second-stage active RC integrator, and the output terminal of the third-stage resistance-type feedback RDAC-F1 is connected to the negative phase input terminal of the operational amplifier in the second-stage active RC integrator. The output end of the resistive feedback RDAC-F1 is connected to the negative phase input end of the comparator CMP, the output end of the delay unit DZ2 is connected to the input end of the first-stage current-type feedback IDAC-F12, the input end of the second-stage current-type feedback IDAC-F22 and the input end of the third-stage resistive feedback RDAC-F2, the output end of the first-stage current-type feedback IDAC-F12 is connected to the positive phase input end of the operational amplifier in the first-stage active RC integrator, the output end of the second-stage current-type feedback IDAC-F22 is connected to the positive phase input end of the operational amplifier in the second-stage active RC integrator, and the output end of the third-stage resistive feedback RDAC-F2 is connected to the positive phase input end of the comparator CMP.

2. A second-order continuous-time sigma-delta modulator circuit according to claim 1, characterized in that: The first-stage active RC integrator comprises an integrating resistor R11, an integrating resistor R12, an integrating capacitor C11, an integrating capacitor C12 and an operational amplifier OTA1, one end of the integrating resistor R11 serves as a negative phase input end of the first-stage active RC integrator, the other end of the integrating resistor R11 is connected to one end of the integrating capacitor C11, the negative phase input end of the operational amplifier OTA1 and the output end of the first-stage current-type feedback IDAC-F11, the positive phase output end of the operational amplifier OTA1 is connected to the other end of the integrating capacitor C11 and serves as the positive phase output end of the first-stage active RC integrator, one end of the integrating resistor R12 serves as the positive phase input end of the first-stage active RC integrator, the other end of the integrating resistor R12 is connected to one end of the integrating capacitor C12, the positive phase input end of the operational amplifier OTA1 and the output end of the first-stage current-type feedback IDAC-F12, the negative phase output end of the operational amplifier OTA1 is connected to the other end of the integrating capacitor C12 and serves as the negative phase output end of the first-stage active RC integrator.

3. A second-order continuous-time sigma-delta modulator circuit according to claim 1, characterized in that: The second-stage active RC integrator comprises an integrating resistor R21, an integrating resistor R22, an integrating capacitor C21, an integrating capacitor C22 and an operational amplifier OTA2, one end of the integrating resistor R21 serves as a negative phase input end of the second-stage active RC integrator, the other end of the integrating resistor R21 is connected to one end of the integrating capacitor C21, the negative phase input end of the operational amplifier OTA2 and the output end of the second-stage current-type feedback IDAC-F21, the positive phase output end of the operational amplifier OTA2 is connected to the other end of the integrating capacitor C21 and serves as the positive phase output end of the second-stage active RC integrator, one end of the integrating resistor R22 serves as the positive phase input end of the second-stage active RC integrator, the other end of the integrating resistor R22 is connected to one end of the integrating capacitor C22, the positive phase input end of the operational amplifier OTA2 and the output end of the second-stage current-type feedback IDAC-F22, the negative phase output end of the operational amplifier OTA2 is connected to the other end of the integrating capacitor C22 and serves as the negative phase output end of the second-stage active RC integrator.

4. A second-order continuous-time sigma-delta modulator circuit according to claim 1, characterized in that: The delay unit DZ1 and the delay unit DZ2 respectively include D flip-flops D0~D7, the Clk terminals of the D flip-flops D0~D7 are connected to the clock signal CLK, the Set terminals of the D flip-flops D0~D7 are connected to the reset signal RESET, the D terminal of the D flip-flop D0 is connected to the input signal IN, the Q terminals of the D flip-flops D0~D7 generate output signals DOP~D7P in sequence, and the Q non-terminals of the D flip-flops D0~D7 generate output signals DON~D7N in sequence. For two adjacent D flip-flops D(n-1) and Dn, n=1, 2, ..., 7, the Q terminal of the D flip-flop D(n-1) is connected to the D terminal of the D flip-flop Dn.

5. A second-order continuous-time sigma-delta modulator circuit according to claim 1, characterized in that: The first-stage current-type feedback IDAC-F11, the first-stage current-type feedback IDAC-F12, the second-stage current-type feedback IDAC-F21 and the second-stage current-type feedback IDAC-F22 respectively include eight current-type basic units, each of which includes a PMOS tube MP0, a PMOS tube MP1, a PMOS tube MP2, an NMOS tube MN0, an NMOS tube MN1 and an NMOS tube MN2, the source of the PMOS tube MP0 is connected to the power supply VDD, the gate of the PMOS tube MP0 is connected to the bias voltage Vbiasp, the drain of the PMOS tube MP0 is connected to the source of the PMOS tube MP1 and the source of the PMOS tube MP2, and the The gate of the PMOS tube MP1 is connected to the gate of the NMOS tube MN1 and is connected to the input signal VIPi, where i=1, 2, ..., 8. The gate of the PMOS tube MP2 is connected to the gate of the NMOS tube MN2 and is connected to the input signal VINi. The drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN1 and generates an output signal VON. The drain of the PMOS tube MP2 is connected to the drain of the NMOS tube MN2 and generates an output signal VOP. The source of the NMOS tube MN1 is connected to the source of the NMOS tube MN2 and the drain of the NMOS tube MN0. The gate of the NMOS tube MN0 is connected to the bias voltage Vbiasn. The source of the NMOS tube MN0 is grounded.

6. A second-order continuous-time sigma-delta modulator circuit according to claim 1, characterized in that: The third-stage resistive feedback RDAC-F1 and the third-stage resistive feedback RDAC-F2 respectively include eight resistive basic units, each resistive basic unit includes a switching switch SW0 and a resistor R0, a first input end of the switching switch SW0 is connected to an input signal VP, a second input end of the switching switch SW0 is connected to an input signal VN, an output end of the switching switch SW0 is connected to one end of the resistor R0, and the other end of the resistor R0 generates an output signal OUT, and a control end of the switching switch SWO is connected to a control signal Sj, j=0, 1, ..., 7.

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