High-definition image rotating system and method based on FPGA

Abstract

The invention provides a high-definition image rotating system and method based on an FPGA. The high-definition image rotating system comprises a receiving module, a display module and a control module. The receiving module receives and stores the image data in the YUV422 format, and analyzes the image data to obtain a write instruction and image coordinate information; the display module generates a reading instruction according to the display information and the image coordinate information, and outputs rotating image data in a YUV422 format; and the control module reads the image data stored in the receiving module according to the write instruction and stores the image data in the DDR particles according to a preset storage mode, and reads the image data stored in the DDR particles to the display module according to the read instruction and a preset reading mode. According to the method, the image data in the low-speed YUV422 format is used and cached into the DDR, so that the input image data is greatly reduced, the image data can correspond to the bit width of DDR particles, the DDR space is utilized to the maximum extent, the processing efficiency of image rotation is improved, and the image rotation speed is improved. The problem of how to improve the image rotation display efficiency while not occupying excessive resources is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing and data storage, and in particular to a high-definition image rotation system and method based on FPGA. Background Art

[0002] With the continuous development and improvement of information technology, higher requirements are placed on the resolution of image display, such as 1080P, 2160p, 3840p and other high-definition resolutions; at the same time, the display mode is not all conventional horizontal screen display, and many vertical screen displays have been added to meet people's diverse display needs.

[0003] In order to achieve 90-degree rotation of the image, static random access memory (SRAM) is usually used. Although this device has no delay in reading and writing data, it is too expensive and not suitable for large-scale applications. Alternatively, DDR3 is used, using its BURST burst technology, that is, each time an address is read / written, 8 data are output / input, but because various data alignment and clock alignment are required inside the DDR3 particles, each time data is read and written in a DDR bank, a read / write command will be generated, resulting in low efficiency and affecting the resolution of image display.

[0004] In addition, for images of larger size, the existing technology needs to divide the image into regions, rotate the image based on each region separately, write it into DDR, and realize the image rotation by recalculating the image coordinates and then reading them out. This method will undoubtedly use a lot of calculation processes and occupy more hardware resources. Summary of the invention

[0005] The purpose of the present invention is to provide a high-definition image rotation system and method based on FPGA, so as to at least solve the problem of how to improve the image rotation display efficiency without occupying too many resources.

[0006] In order to solve the above technical problems, the present invention provides a high-definition image rotation system based on FPGA, including a receiving module, a display module and a control module; The receiving module is used to receive and store image data in YUV422 format, and parse the image data to obtain write instructions and image coordinate information; the display module is used to generate read instructions according to the display information and image coordinate information, and output rotated image data in YUV422 format; the control module is used to read the image data stored in the receiving module according to the write instructions, and store the image data in the DDR particles according to a preset storage method, and is also used to read the image data stored in the DDR particles to the display module according to a preset reading method according to the read instructions; The DDR particle includes a plurality of storage areas, each of which has a plurality of storage blocks. When image data is stored in the DDR particle, the image data of the same row is sequentially stored in different storage blocks of different storage areas in units of rows, and the storage starting position of the image data of the next row is one storage area later than the storage starting position of the image data of the previous row.

[0007] Optionally, in the FPGA-based high-definition image rotation system, the receiving module includes an image acquisition unit, a write FIFO unit, and an input storage unit; The image acquisition unit is used to receive image data in YUV422 format and parse the image data to obtain write instructions and image coordinate information; the write FIFO unit is used to store write instructions; and the input storage unit is used to store image data in YUV422 format.

[0008] Optionally, in the FPGA-based high-definition image rotation system, the image acquisition unit includes an IDDR subunit, a splicing subunit, a write storage address generation subunit, a coordinate generation subunit and a frame start subunit; The IDDR subunit is used to receive image data in YUV422 format and convert the image data from dual-edge image data into two single-edge sub-image data; the splicing subunit is used to splice the two single-edge sub-image data output by the IDDR subunit to obtain one single-edge image data; the write storage address generation subunit is used to receive a row synchronization signal and generate a write enable signal and a write address signal; the coordinate generation subunit is used to receive a row start signal and generate image coordinate information, and the image coordinate information includes image row coordinate information and image column coordinate information; the frame start subunit is used to receive a frame start signal and generate frame information; the write instruction includes a write enable signal, a write address signal, image row coordinate information and frame information.

[0009] Optionally, in the FPGA-based high-definition image rotation system, the storage space of the input storage unit is twice the width of the maximum input image; the image data is stored in the input storage unit in a ping-pong manner, and is read out from the input storage unit in a ping-pong manner.

[0010] Optionally, in the FPGA-based high-definition image rotation system, the display module includes an output storage unit, a read FIFO unit and an image output unit; The output storage unit is used to store image data read from DDR particles; the image output unit is used to obtain display information and image coordinate information, and generate a read instruction based on the display information and image coordinate information, and is also used to output the image data stored in the output storage unit, and generate a synchronization code to output the rotated image data in YUV422 format; the read FIFO unit is used to store the read instruction.

[0011] Optionally, in the FPGA-based high-definition image rotation system, the image output unit includes a read instruction generation subunit, a synchronization code generation subunit and an ODDR subunit; The read instruction generation subunit is used to generate a read instruction based on display information and image coordinate information; the synchronization code generation subunit is used to generate a synchronization code based on image coordinate information; the ODDR subunit is used to restore the image data stored in the output storage unit from single-edge image data to double-edge image data to output rotated image data in YUV422 format.

[0012] Optionally, in the FPGA-based high-definition image rotation system, the control module includes a read-write arbitration unit, a state controller, a control signal generation unit, a command address generation unit, and a DDR physical layer; The read / write arbitration unit is used to receive write instructions and read instructions, and start the state controller according to the write instruction or the read instruction in a first-in-first-out arbitration mode; the state controller is used to generate an address signal and a read / write command for controlling the DDR physical layer according to the write instruction or the read instruction; the control signal generation unit is used to generate a read address signal according to the write instruction; and is also used to generate a write address signal according to the read instruction; The command address generation unit is used to send the image data stored in the receiving module to the DDR particles through the DDR physical layer using address signals, read and write commands and read address signals; and is also used to read image data from the DDR particles through the DDR physical layer and write them into the display module using address signals, read and write commands and write address signals.

[0013] In order to solve the above technical problems, the present invention further provides a high-definition image rotation method based on FPGA, which is applied to the high-definition image rotation system based on FPGA as described in any one of the above items, and the high-definition image rotation method comprises: Receive and store image data in YUV422 format; Parsing image data to obtain write instructions and image coordinate information; Read the image data stored in the receiving module according to the write instruction, and store the image data in the DDR particles according to the preset storage method; Generate a read instruction according to the display information and the image coordinate information; According to the read instruction, the image data stored in the DDR particles is read out according to the preset reading method to output the rotated image data in the YUV422 format.

[0014] Optionally, in the FPGA-based high-definition image rotation method, the method of parsing image data to obtain write instructions and image coordinate information includes: Convert the received YUV422 format image data from a dual-edge image data format into two channels of single-edge sub-image data; Splicing two channels of single-edge sub-image data to obtain one channel of single-edge image data; Receive a line synchronization signal and generate a write enable signal and a write address signal; receiving a row start signal and generating image coordinate information, wherein the image coordinate information includes image row coordinate information and image column coordinate information; Receive a frame start signal and generate frame information; The write instruction includes a write enable signal, a write address signal, image row coordinate information and frame information.

[0015] Optionally, in the FPGA-based high-definition image rotation method, the method of reading the image data stored in the receiving module according to the write instruction and storing the image data in the DDR particles according to a preset storage method includes: Receive write instruction; According to the first-in-first-out arbitration method, a read address signal, an address signal and a read-write command are generated according to the write instruction; According to the read address signal, the image data is read from the receiving module, and according to the address signal and the read and write commands, the read image data is sent to the DDR particles through the DDR physical layer.

[0016] Optionally, in the FPGA-based high-definition image rotation method, the method of generating a read instruction according to the display information and the image coordinate information includes: Generate a read instruction according to the display information and the image coordinate information; Generate a synchronization code based on the image coordinate information.

[0017] Optionally, in the FPGA-based high-definition image rotation method, the method of reading the image data stored in the DDR particles according to a preset reading method according to the read instruction to output the rotated image data in the YUV422 format includes: Receive read command; Generate write address signal, address signal and read / write command according to read instruction in first-in-first-out arbitration mode; Read image data from DDR particles through the DDR physical layer according to the address signal and the read / write command, and write the read image data into the display module according to the write address signal; The image data is restored from a single-edge image data format to a dual-edge image data format, and the rotated image data in the YUV422 format is output.

[0018] The FPGA-based high-definition image rotation system and method provided by the present invention include a receiving module, a display module and a control module; the receiving module is used to receive and store image data in YUV422 format, and parse the image data to obtain write instructions and image coordinate information; the display module is used to generate read instructions according to the display information and image coordinate information, and output the rotated image data in YUV422 format; the control module is used to read the image data stored in the receiving module according to the write instruction, and store the image data in DDR particles according to a preset storage method, and is also used to read the image data stored in the DDR particles to the display module according to a preset reading method according to the read instruction. By using low-speed YUV422 format image data and caching it in DDR, not only the input image data is greatly reduced, but also the image data can correspond to the bit width of the DDR particles, maximizing the use of DDR space, improving the processing efficiency of image rotation, and solving the problem of how to improve the image rotation display efficiency without occupying too many resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A structural block diagram of the high-definition image rotation system based on FPGA provided in this embodiment; Figure 2 A schematic diagram of the structure of a receiving module provided in this embodiment; Figure 3 A schematic diagram of the structure of the image acquisition unit provided in this embodiment; Figure 4 A schematic diagram of the structure of the display module provided in this embodiment; Figure 5 A schematic diagram of the structure of an image output unit provided in this embodiment; Figure 6 A schematic diagram of the structure of the control module provided in this embodiment; Figure 7 A flowchart of a high-definition image rotation method based on FPGA provided in this embodiment; Figure 8 A schematic diagram of the connection of each module unit in the FPGA-based high-definition image rotation system provided in this embodiment; Fig. 9 A schematic diagram of the writing format of image data in the DDR particles provided in this embodiment; Fig.10 A schematic diagram of the readout format of image data in the DDR particles provided in this embodiment; Fig.11 A schematic diagram of a structure in which 8 columns of data provided in this embodiment are written into a RAM; Fig.12 A schematic diagram of a storage method of image data in an output storage unit provided in this embodiment. DETAILED DESCRIPTION

[0020] The FPGA-based high-definition image rotation system and method proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often a part of the actual structure. In particular, the emphasis that each drawing needs to show is different, and sometimes different proportions are used.

[0021] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0022] In order to clearly illustrate the implementation scheme of the transceiver delay calibration system and method provided in this embodiment, the technical terms involved in this embodiment are explained as follows: ASIC: Application Specific Integrated Circuit, application-specific integrated circuit; FPGA: Field Programmable Gate Array, field programmable gate array; DDR SDRAM: Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory, referred to as DDR; IDDR: input double-data-rate, input double data rate; ORRD: output double-data-rate, output double data rate; MC: Memory Controller, memory controller; PHY: Physical Layer, physical layer; FIFO: First Input First Output, first in first out; RAM: Random Access Memory, random access memory; SRAM: Static Random-Access Memory, static random access memory; RGB: Read Green Blue, red, green and blue primary colors; YUV: YCbCr, a color encoding based on brightness and chrominance; CMD:Command, command; BANK: a block in DDR; TTL: Transistor Transistor Logic, level standard; HDMI: High Definition Multimedia Interface, high-definition multimedia interface; DE: A single-bit synchronization signal used for image display, indicating the effective display portion of the image; HS: A single-bit synchronization signal used for image display, indicating the starting point of each line of the image; VS: A single-bit synchronization signal used for image display, indicating the start mark of each frame of the image.

[0023] This embodiment provides a high-definition image rotation system based on FPGA, such as Figure 1 As shown, it includes a receiving module, a display module and a control module; The receiving module is used to receive and store image data in YUV422 format, and to parse the image data to obtain write instructions and image coordinate information; the display module is used to generate read instructions according to the display information and image coordinate information, and to output rotated image data in YUV422 format; the control module is used to read the image data stored in the receiving module according to the write instructions, and store the image data in the DDR particles according to a preset storage method, and is also used to read the image data stored in the DDR particles to the display module according to a preset reading method according to the read instructions.

[0024] The FPGA-based high-definition image rotation system provided in this embodiment uses low-speed YUV422 format image data and caches it in DDR. Compared with the conventional YUV444 format image data, the input image data is greatly reduced, and the image data can correspond to the bit width of DDR particles, maximizing the use of DDR space and improving the processing efficiency of image rotation. Based on FPGA design, the implementation of each functional unit can be flexibly set to replace the existing SRAM solution, effectively reducing costs and solving the problem of how to improve the image rotation display efficiency without occupying too many resources.

[0025] Furthermore, in this embodiment, if Figure 2 As shown, the receiving module includes an image acquisition unit, a write FIFO unit and an input storage unit. The image acquisition unit is used to receive image data in YUV422 format and parse the image data to obtain write instructions and image coordinate information; the write FIFO unit is used to store write instructions; and the input storage unit is used to store image data in YUV422 format.

[0026] Specifically, in this embodiment, the image acquisition unit includes an IDDR subunit, a splicing subunit, a write storage address generation subunit, a coordinate generation subunit and a frame start subunit.

[0027] Among them, Figure 3 As shown, the IDDR subunit is used to receive the image data rx_ttl[31:0] in YUV422 format, which is dual-edge image data. The IDDR subunit converts the dual-edge image data rx_ttl[31:0] into two single-edge image data p[31:0] and n[31:0]; the splicing subunit is used to splice the two single-edge sub-image data output by the IDDR subunit to obtain the single-edge image data rx_data[63:0]; the write storage address generation subunit is used to receive the row The synchronization signal rx_rtl_de is used to generate a write enable signal rx_en and a write address signal rx_waddr; the coordinate generation subunit is used to receive a row start signal rx_rtl_hs and generate image coordinate information, wherein the image coordinate information includes image row coordinate information cnt_x and image column coordinate information cnt_y; the frame start subunit is used to receive a frame start signal rx_rtl_vs and generate frame information frame; the write instruction includes a write enable signal, a write address signal, image row coordinate information and frame information.

[0028] In practical applications, considering that the external input image data is usually dual-edge image data, the IDDR hard core can be used to convert the dual-edge image data into two single-edge image data, and then splice them, thereby realizing the conversion of the input dual-edge clock 32-bit data into single-edge clock 64-bit data.

[0029] The write storage address generation subunit uses the line synchronization signal rx_rtl_de to generate a write enable signal rx_en and a write address signal rx_waddr, and accumulates the write address signal rx_waddr according to the rising edge of the input clock, thereby realizing sequential storage of image data in the input storage unit; at the same time, the write storage address generation subunit also generates a line synchronization flag signal de_flag, and provides the line synchronization flag signal de_flag to the coordinate generation subunit.

[0030] The frame start subunit obtains the frame start flag signal vs_flag by clock sampling the input frame start signal rx_rtl_vs, and controls the frame signal frame to increase by 1 after each frame start flag signal vs_flag; at the same time, the frame start flag signal vs_flag is also provided to the coordinate generation subunit.

[0031] The coordinate generation subunit receives the line start signal rx_rtl_hs, and relocates the coordinate starting point using the frame start flag signal vs_flag and the line synchronization flag signal de_flag, and generates image coordinate information cnt_x and cnt_y.

[0032] Furthermore, in order to ensure that the image data can be effectively stored and can be read out by subsequent control modules in a certain order, in this embodiment, the storage space of the input storage unit is twice the width of the maximum input image.

[0033] In a specific embodiment, the input storage unit may be a RAM, and its storage length is 8192, so that it can be compatible with the cache of image data of 4K@60Hz and below, meeting existing image display requirements.

[0034] Furthermore, the image data is stored in the input storage unit in a ping-pong manner, and is read out from the input storage unit in a ping-pong manner, thereby maximizing the data reading and writing efficiency.

[0035] Furthermore, in this embodiment, the write FIFO unit stores the write instruction and image coordinate information output by the image acquisition unit, including frame information, row coordinate information, etc. The write FIFO unit can also output a write empty signal rx_empty to inform the control module that new image data has been acquired to be read.

[0036] Furthermore, in this embodiment, if Figure 4As shown, the display module includes an output storage unit, a read FIFO unit and an image output unit. The output storage unit is used to store image data read from DDR particles; the image output unit is used to obtain display information and image coordinate information, and generate a read instruction according to the display information and image coordinate information, and is also used to output the image data stored in the output storage unit, and generate a synchronization code to output the rotated image data in the YUV422 format; the read FIFO unit is used to store the read instruction.

[0037] Specifically, in this embodiment, the image output unit includes a read instruction generation subunit, a synchronization code generation subunit and an ODDR subunit.

[0038] Among them, Figure 5 As shown, the read instruction generation subunit is used to generate a read instruction according to display information and image coordinate information, wherein the read instruction includes a FIFO enable signal fifo_en and a FIFO data signal fifo_data; the synchronization code generation subunit is used to generate a synchronization code according to the image coordinate information, wherein the synchronization code includes a line synchronization signal de, a line start signal hs and a frame start signal vs; the ODDR subunit is used to restore the image data (including p[31:0] and n[31:0]) stored in the output storage unit from single-edge image data to double-edge image data, so as to output high-definition YUV422 format rotated image data HDMI.

[0039] In practical applications, considering that during the image rotation process, the reading and writing of image data are all performed as single-edge image data, therefore, in order to output dual-edge image data, the single-edge image data can be restored to dual-edge image data with the help of the ODDR hard core.

[0040] Furthermore, in order to rotate the output image compared to the original input image and to efficiently read out the image data for display, in this embodiment, the image data read out from the DDR particles are stored in the output storage unit in sequence.

[0041] In a specific embodiment, the output storage unit may be a RAM, and the RAM may be divided into a plurality of storage spaces for correspondingly storing corresponding image data, thereby improving image display efficiency.

[0042] Furthermore, in this embodiment, the read FIFO unit stores the read instruction output by the image output unit. The read FIFO unit can also output a read empty signal tx_empty to inform the control module that the display module is idle and can read new image data.

[0043] Furthermore, in this embodiment, if Figure 6As shown, the control module includes a read-write arbitration unit, a state controller, a control signal generation unit, a command address generation unit and a DDR physical layer.

[0044] The read / write arbitration unit is used to receive write instructions and read instructions, and start the state controller according to the write instruction or the read instruction in a first-in-first-out arbitration manner. Specifically, the write instruction is obtained through the write FIFO unit of the receiving module, and the read instruction is obtained through the read FIFO unit of the display module.

[0045] Furthermore, the state controller is used to generate an address signal and a read / write command for controlling the DDR physical layer according to a write instruction or a read instruction.

[0046] And, the control signal generating unit is used to generate a read address signal according to a write instruction, and to generate a write address signal according to a read instruction. Specifically, the control signal generating unit includes a read signal generating unit and a write signal generating unit, the read signal generating unit is used to generate a read address signal, and the write signal generating unit is used to generate a write address signal.

[0047] Furthermore, the command address generation unit is used to send the image data stored in the receiving module to the DDR particles through the DDR physical layer using address signals, read / write commands and read address signals; and is also used to read image data from the DDR particles through the DDR physical layer and write them into the display module using address signals, read / write commands and write address signals.

[0048] The entire writing process of the control module is roughly as follows: the read-write arbitration unit controls the start-up of the state controller according to the write instruction; the state controller generates the necessary address signals and write commands to control the DDR physical layer, and the read signal generation unit generates a read address signal and sends it to the input storage unit in the receiving module, thereby reading the image data in the input storage unit and passing it to the command address generation unit; the command address generation unit writes the acquired image data into the DDR particles through the DDR physical layer according to the address signal and write command.

[0049] The entire reading process of the storage control unit is roughly as follows: the read-write arbitration unit controls the state controller to start according to the read instruction; the state controller generates the necessary address signal and read command to control the DDR physical layer, and the command address generation unit reads the image data in the DDR particles through the DDR physical layer according to the address signal and the read command, and provides it to the write signal generation unit; the write signal generation unit generates a write address signal, and the command address generation unit writes the read data into the output storage unit in the display module according to the write address signal.

[0050] The FPGA-based high-definition image rotation system provided in this embodiment uses an external dedicated chip to convert the HDMI input signal into a low-speed TTL signal in the YUV422 format, and then caches it in the DDR, so that the image data input to the FPGA is reduced by 1 / 3 compared with the original YUV444 format; moreover, the DDR particles usually use a 16-bit bit width, which just corresponds to the 16-bit data in the YUV422 format, and maximizes the use of the DDR space itself; in addition, by writing the input image data into the DDR in sequence each time, and then storing the read image data to be rotated in sequence in the output storage unit, not only the read and write operations of the DDR are achieved to achieve the highest efficiency, but also the efficient display of the rotated image is achieved, thereby replacing the original high-cost SRAM solution and solving the high-efficiency read and write problem required for image rotation.

[0051] This embodiment also provides a high-definition image rotation method based on FPGA, which is applied to the high-definition image rotation system based on FPGA as described above. Figure 7 As shown, the high-definition image rotation method includes: S1, receives and stores image data in YUV422 format; S2, parsing the image data to obtain writing instructions and image coordinate information; S3, reading the image data stored in the receiving module according to the write instruction, and storing the image data in the DDR particles according to a preset storage method; S4, generating a read instruction according to the display information and the image coordinate information; S5, according to the read instruction, the image data stored in the DDR particles are read out in a preset reading mode to output the rotated image data in the YUV422 format.

[0052] The FPGA-based high-definition image rotation method provided in this embodiment uses low-speed YUV422 format image data and caches it in DDR, which not only greatly reduces the input image data, but also enables the image data to correspond to the bit width of DDR particles, maximizes the use of DDR space, and improves the processing efficiency of image rotation; by reading and writing image data in sequence, efficient rotation display of image data is achieved, solving the problem of how to improve the efficiency of image rotation display without occupying too many resources.

[0053] See below Figure 8 , the implementation process of the high-definition image rotation method based on FPGA provided in this embodiment is described in detail.

[0054] Specifically, in this embodiment, step S1 is to receive and store image data in YUV422 format.

[0055] In practical applications, the input image data may be an image video stream of specifications such as 1k@60Hz, 2k@60Hz, and 4K@60Hz. In addition, an external dedicated chip may be used to convert the original image video data signal in other formats into a TTL signal in the YUV422 format, and the converted TTL signal is input as image data into the receiving module of the FPGA-based high-definition image rotation system provided in this embodiment. Specifically, the image acquisition unit of the receiving module receives the image data in the YUV422 format, and the input storage unit stores the image data in the YUV422 format.

[0056] Furthermore, in this embodiment, in step S2, the method of parsing the image data to obtain the write instruction and the image coordinate information includes: S21, converting the received YUV422 format image data from a dual-edge image data format into two-channel single-edge sub-image data. Specifically, in this embodiment, the IDDR sub-unit in the image acquisition unit converts the image data from a dual-edge image data format into two-channel single-edge sub-image data.

[0057] S22, splicing two paths of single-edge sub-image data to obtain one path of single-edge image data. Specifically, in this embodiment, the splicing sub-unit in the image acquisition unit splices the image data and outputs the single-edge image data rx_data.

[0058] At this time, the single edge image data rx_data is stored in the input storage unit together with its input storage address information rx_waddr.

[0059] S23, receiving a line synchronization signal and generating a write address signal. Specifically, in this embodiment, the write storage address generation subunit in the image acquisition unit receives the line synchronization signal rx_rtl_de and generates a write enable signal rx_en and a write address signal rx_waddr.

[0060] S24, receiving a row start signal and generating image coordinate information, wherein the image coordinate information includes image row coordinate information and image column coordinate information. Specifically, in this embodiment, the coordinate generation subunit in the image acquisition unit receives the row start signal rx_rtl_hs and generates image coordinate information, wherein the image coordinate information includes image row coordinate information cnt_x and image column coordinate information cnt_y.

[0061] S25, receiving a frame start signal and generating frame information. Specifically, in this embodiment, the frame start subunit in the image acquisition unit receives the frame start signal rx_rtl_vs and generates frame information frame.

[0062] At this time, the write enable signal rx_en, the write address signal rx_waddr, the image row coordinate information cnt_x, the image column coordinate information cnt_y, the frame information frame, etc. are stored in the write FIFO unit.

[0063] Further, in this embodiment, step S3, the method of reading the image data stored in the receiving module according to the write instruction and storing the image data in the DDR particles according to the preset storage method includes: S31, receiving a write instruction. Specifically, the write FIFO unit first generates a write empty signal rx_empty and inputs it to the read-write arbitration unit of the control module, so that the read-write arbitration unit is informed that there is new image data to be read; at the same time, the write FIFO unit also inputs the first-in-first-out write data signal fifo_wdata to the read-write arbitration unit, so that the read-write arbitration unit controls the state controller to start.

[0064] S32, according to the first-in-first-out arbitration method, generate a read address signal, an address signal and a read / write command according to the write instruction. Specifically, after the state controller is started, it generates the necessary address signal and read / write command for controlling the DDR physical layer according to the write instruction, and the read / write command is specifically a write command; and the read signal generation unit generates a read address signal raddr according to the write instruction.

[0065] S33, according to the read address signal, read the image data from the receiving module, and according to the address signal and the read and write command, send the read image data to the DDR particle through the DDR physical layer. Specifically, according to the read address signal raddr, read the corresponding image data wdata[127:0] from the input storage unit, and send it to the command address generation unit, and then the command address generation unit writes the acquired image data into the DDR particle through the DDR physical layer according to the address signal and the write command.

[0066] The DDR particle includes a plurality of storage areas, each of which has a plurality of storage blocks. In the process of writing image data into the DDR particle, the command address generation unit controls the image data to store the image data of the same row in different storage blocks of different storage areas in units of rows, and the storage start position of the image data of the next row is one storage area later than the storage start position of the image data of the previous row, that is, Fig. 9 Specifically, to meet the display format of 4K images, in this embodiment, the DDR particles include 8 storage areas (banks), each of which has 4096 storage blocks (blocks). Data is stored in each storage block in units of rows.

[0067] In practical applications, since DDR3 usually uses 8 pixels of data per command burst, that is, 128 bits of width for storage, the first row of data of the horizontal screen image is stored as follows: Fig. 9 The flow direction of the left arrow in the figure, where block1-1 means storing the first 8 data of the first line of the input image as the first group, and the address stores 8 pixel values ​​in a continuous burst; similarly, block1-2 means storing the second group of 8 data of the first line, that is, data of 9 to 16 pixel values; after storing block1-8, the data storage returns to the space of block1-1 and is connected to the address of the first storage to store the image data of the next line. In this way, each time a group of data is sent, it is stored between different storage areas (banks), achieving the highest efficiency in the write DDR direction.

[0068] After writing one row of image data, write the second row of image data. The storage method is different from the previous row, and the starting point needs to be delayed by one storage area (bank) than the previous row. As shown in the data storage flow direction of the right arrow of 9 in the figure, the starting point is block2-1 in bank2, indicating that the first set of data of the second row of image is stored, followed by block2-2 in bank3 to store the second set of data of the second row of image, and so on, storing a maximum of 4K, or 4096 rows of data.

[0069] Furthermore, in this embodiment, step S4, the method of generating a read instruction according to the display information and the image coordinate information includes: S41, generating a read instruction according to the display information and the image coordinate information. Specifically, in this embodiment, the read instruction is generated by a read instruction generating subunit in the image output unit in the display module, wherein the read instruction includes a FIFO enable signal fifo_en and a FIFO data signal fifo_data.

[0070] S42, generating a synchronization code according to the image coordinate information. Specifically, in this embodiment, the synchronization code generating subunit in the image output unit in the display module generates the synchronization code according to the image coordinate information, wherein the synchronization code includes a line synchronization signal de, a line start signal hs and a frame start signal vs.

[0071] Further, in this embodiment, in step S5, the method of reading the image data stored in the DDR particles according to the read instruction in a preset reading mode to output the rotated image data in the YUV422 format includes: S51, receiving a read instruction. Specifically, the read FIFO unit first generates a read empty signal tx_empty and inputs it to the read-write arbitration unit of the control module, so that the read-write arbitration unit knows that new image data can be read; at the same time, the read FIFO unit also inputs a first-in-first-out read data signal fifo_rdata to the read-write arbitration unit, so that the read-write arbitration unit controls the state controller to start.

[0072] S52, in accordance with the first-in-first-out arbitration method, generate a write address signal, an address signal and a read / write command according to the read instruction. Specifically, after the state controller is started, it generates the necessary address signal and read / write command for controlling the DDR physical layer according to the read instruction. At this time, the read / write command is specifically a read command; and the write signal generation unit generates a write address signal waddr according to the read instruction.

[0073] S53, according to the address signal and the read / write command, the image data is read from the DDR particle through the DDR physical layer, and the read image data is written into the display module according to the write address signal. Specifically, according to the address signal and the read command, the corresponding image data rdata[127:0] is read from the DDR particle through the DDR physical layer, and then the command address generation unit writes the acquired image data into the output storage unit of the display module according to the write address signal waddr.

[0074] In the process of reading the image data from the DDR particles, in order to realize the display of the input image rotated 90 degrees, the data stored horizontally needs to be read vertically, that is, the first row of data read is the first column of data written. In this embodiment, the problem of low reading efficiency of DDR in the same bank is taken into consideration during the writing process, so the image data is written into different banks each time. Therefore, when reading the image data, it is also necessary to adopt a corresponding reading of different banks each time to improve the reading efficiency; at the same time, since the frame jump signal is used to store the image data, a maximum of 2 frames of image data can be stored. When reading, a frame of image data needs to be cached in DDR3 before the read operation can be performed.

[0075] In practical applications, such as Fig.10As shown in the figure, the first 9 rows of data (block9) in a frame of image stored in the horizontal screen in the DDR particle are displayed. In order to maximize the efficiency of DDR read and write operations, the first row of data displayed in the vertical screen is the first block of bank1, namely block1-1, followed by the second block of bank2, namely block2-1. The first 8 columns of data in the horizontal screen are read in sequence to obtain the first 8 rows of data after rotation. The bank reading order is as shown in the arrow direction in the figure, block1-1, block2-1, block3-1, block4-1, block5-1, block6-1, block7-1, block8-1, block9-1... After reading 8 banks, it returns to bank1 and continues to read the address data of the next row. The read data is written into the RAM group in the output storage unit according to the instruction signal of the write signal generation unit.

[0076] Corresponding to the read-out method, considering that the read-out rotated longitudinal data requires at least reading the 8 columns of data before the horizontally stored data, if 8 columns and a maximum of 4k row data are read at one time, and all the data are written into a group of RAM, the difficulty of timing convergence will increase. Therefore, in this embodiment, the output storage unit has 8 groups of RAM to store 8 columns of data respectively, thereby effectively avoiding the timing problem caused by too large RAM.

[0077] like Fig.11 As shown in the figure, it is a schematic diagram of the structure of writing 8 columns of data into a RAM. The RAM is divided into high and low address bits, each occupying half of the entire RAM. This method can easily implement ping-pong operation. For the 8 columns of data read before rotation, they are stored in RAM in columns through the write signal generation unit. Fig.12 As shown, the data stored in the first RAM1 is the first column of the horizontal screen image, and the data stored in the second RAM2 is the second column of the horizontal screen image. Ping-pong storage is used to achieve data alternating storage. After the low bits of the 8 groups of RAM are stored, the high address of the first group of RAM1 is looped to continue caching until the last row of data displayed vertically is cached.

[0078] S54, restore the image data from the single-edge image data format to the dual-edge image data format, and output the rotated image data in the YUV422 format. Specifically, in this embodiment, the ODDR subunit in the image output unit restores the image data (including p[31:0] and n[31:0]) from the single-edge image data to the dual-edge image data, so as to output the high-definition YUV422 format rotated image data HDMI.

[0079] The FPGA-based high-definition image rotation method provided in this embodiment improves the writing and reading methods of image data in DDR particles, writes image data into different banks, and reads them out from different banks accordingly, thereby effectively improving the reading and writing efficiency of DDR particles and meeting the high frame rate requirements of image rotation display.

[0080] The FPGA-based high-definition image rotation method provided in this embodiment makes full use of the burst characteristics of DDR and uses 8 data to transmit together, thereby improving data transmission efficiency. At the same time, 8 groups of output RAMs are used to store the 8 columns of output data before rotation, which not only reduces the cache pressure but also makes the timing of the entire system easier to converge.

[0081] In practical applications, if the FPGA system only realizes the rotation of image data, the DDR particle refresh function in the microcontroller MC can be omitted, and only the DFI interface of the DDR physical layer can be used to realize the reading and writing of image data, thereby saving the response time of the entire system and speeding up the reading and writing efficiency.

[0082] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0083] The FPGA-based high-definition image rotation system and method provided in this embodiment include a receiving module, a display module and a control module; the receiving module is used to receive and store image data in YUV422 format, and parse the image data to obtain write instructions and image coordinate information; the display module is used to generate read instructions according to the display information and image coordinate information, and output the rotated image data in YUV422 format; the control module is used to read the image data stored in the receiving module according to the write instruction, and store the image data in the DDR particles according to the preset storage method, and also to read the image data stored in the DDR particles to the display module according to the read instruction according to the preset reading method. By using low-speed YUV422 format image data and caching it in DDR, not only the input image data is greatly reduced, but also the image data can correspond to the bit width of the DDR particles, maximizing the use of DDR space, improving the processing efficiency of image rotation, and solving the problem of how to improve the image rotation display efficiency without occupying too many resources.

[0084] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high-definition image rotation system based on FPGA, characterized in that: It includes a receiving module, a display module and a control module; The receiving module is used to receive and store image data in YUV422 format, and parse the image data to obtain write instructions and image coordinate information; the display module is used to generate read instructions according to the display information and image coordinate information, and output rotated image data in YUV422 format; the control module is used to read the image data stored in the receiving module according to the write instructions, and store the image data in the DDR particles according to a preset storage method, and is also used to read the image data stored in the DDR particles to the display module according to a preset reading method according to the read instructions; The DDR particle includes a plurality of storage areas, each of which has a plurality of storage blocks. When image data is stored in the DDR particle, the image data of the same row is sequentially stored in different storage blocks of different storage areas in units of rows, and the storage starting position of the image data of the next row is one storage area later than the storage starting position of the image data of the previous row.

2. The FPGA-based high-definition image rotation system according to claim 1, characterized in that: The receiving module includes an image acquisition unit, a write FIFO unit and an input storage unit; The image acquisition unit is used to receive image data in YUV422 format and parse the image data to obtain write instructions and image coordinate information; the write FIFO unit is used to store write instructions; and the input storage unit is used to store image data in YUV422 format.

3. The FPGA-based high-definition image rotation system according to claim 2, characterized in that: The image acquisition unit includes an IDDR subunit, a splicing subunit, a write storage address generation subunit, a coordinate generation subunit and a frame start subunit; The IDDR subunit is used to receive image data in YUV422 format and convert the image data from dual-edge image data into two single-edge sub-image data; the splicing subunit is used to splice the two single-edge sub-image data output by the IDDR subunit to obtain one single-edge image data; the write storage address generation subunit is used to receive a row synchronization signal and generate a write enable signal and a write address signal; the coordinate generation subunit is used to receive a row start signal and generate image coordinate information, and the image coordinate information includes image row coordinate information and image column coordinate information; the frame start subunit is used to receive a frame start signal and generate frame information; the write instruction includes a write enable signal, a write address signal, image row coordinate information and frame information.

4. The FPGA-based high-definition image rotation system according to claim 2, characterized in that: The storage space of the input storage unit is twice the width of the maximum input image; the image data is stored in the input storage unit in a ping-pong manner, and is read out from the input storage unit in a ping-pong manner.

5. The FPGA-based high-definition image rotation system according to claim 1, characterized in that: The display module includes an output storage unit, a read FIFO unit and an image output unit; The output storage unit is used to store image data read from DDR particles; the image output unit is used to obtain display information and image coordinate information, and generate a read instruction based on the display information and image coordinate information, and is also used to output the image data stored in the output storage unit, and generate a synchronization code to output the rotated image data in YUV422 format; the read FIFO unit is used to store the read instruction.

6. The FPGA-based high-definition image rotation system according to claim 5, characterized in that: The image output unit includes a read instruction generation subunit, a synchronization code generation subunit and an ODDR subunit; The read instruction generation subunit is used to generate a read instruction based on display information and image coordinate information; the synchronization code generation subunit is used to generate a synchronization code based on image coordinate information; the ODDR subunit is used to restore the image data stored in the output storage unit from single-edge image data to double-edge image data to output rotated image data in YUV422 format.

7. The FPGA-based high-definition image rotation system according to claim 1, characterized in that: The control module includes a read-write arbitration unit, a state controller, a control signal generation unit, a command address generation unit and a DDR physical layer; The read / write arbitration unit is used to receive write instructions and read instructions, and start the state controller according to the write instruction or the read instruction in a first-in-first-out arbitration mode; the state controller is used to generate an address signal and a read / write command for controlling the DDR physical layer according to the write instruction or the read instruction; the control signal generation unit is used to generate a read address signal according to the write instruction; and is also used to generate a write address signal according to the read instruction; The command address generation unit is used to send the image data stored in the receiving module to the DDR particles through the DDR physical layer using address signals, read and write commands and read address signals; and is also used to read image data from the DDR particles through the DDR physical layer and write them into the display module using address signals, read and write commands and write address signals.

8. A high-definition image rotation method based on FPGA, applied to the high-definition image rotation system based on FPGA as claimed in any one of claims 1 to 7, characterized in that: The high-definition image rotation method comprises: Receive and store image data in YUV422 format; Parsing image data to obtain write instructions and image coordinate information; Read the image data stored in the receiving module according to the write instruction, and store the image data in the DDR particles according to the preset storage method; Generate a read instruction according to the display information and the image coordinate information; According to the read instruction, the image data stored in the DDR particles is read out according to the preset reading method to output the rotated image data in the YUV422 format.

9. The FPGA-based high-definition image rotation method according to claim 8, characterized in that: The method for parsing image data to obtain write instructions and image coordinate information includes: Convert the received YUV422 format image data from a dual-edge image data format into two channels of single-edge sub-image data; Splicing two channels of single-edge sub-image data to obtain one channel of single-edge image data; Receive a line synchronization signal and generate a write enable signal and a write address signal; receiving a row start signal and generating image coordinate information, wherein the image coordinate information includes image row coordinate information and image column coordinate information; Receive a frame start signal and generate frame information; The write instruction includes a write enable signal, a write address signal, image row coordinate information and frame information.

10. The FPGA-based high-definition image rotation method according to claim 8, characterized in that: The method of reading the image data stored in the receiving module according to the write instruction and storing the image data in the DDR particles according to the preset storage method includes: Receive write instruction; According to the first-in-first-out arbitration method, a read address signal, an address signal and a read-write command are generated according to the write instruction; According to the read address signal, the image data is read from the receiving module, and according to the address signal and the read and write commands, the read image data is sent to the DDR particles through the DDR physical layer.

11. The FPGA-based high-definition image rotation method according to claim 8, characterized in that: The method for generating a read instruction according to display information and image coordinate information comprises: Generate a read instruction according to the display information and the image coordinate information; Generate a synchronization code based on the image coordinate information.

12. The FPGA-based high-definition image rotation method according to claim 8, characterized in that: The method of reading the image data stored in the DDR particles according to the read instruction in a preset reading mode to output the rotated image data in the YUV422 format includes: Receive read command; Generate write address signal, address signal and read / write command according to read instruction in first-in-first-out arbitration mode; Read image data from DDR particles through the DDR physical layer according to the address signal and the read / write command, and write the read image data into the display module according to the write address signal; The image data is restored from a single-edge image data format to a dual-edge image data format, and the rotated image data in the YUV422 format is output.

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