Vertical gallium nitride tunneling power diode and method of making same

Abstract

The application discloses a vertical gallium nitride tunneling power diode, and mainly solves the problem that a traditional vertical gallium nitride junction barrier power diode cannot simultaneously realize low opening voltage, large conduction current and high breakdown voltage, and comprises a substrate (1), a drift layer (2), an anode (8) and a cathode (9), recesses (3) are arranged on the left and right sides of the drift layer, a gradually changing tunneling layer (4) and a modulation layer (7) are sequentially arranged above the recesses; the gradually changing tunneling layer is provided with 2n-1 rectangular array holes (5) which are equidistant and have the same size; a tunneling enhancement layer (6) is arranged in the array holes and is used for improving the forward conduction current; the anode is located on the upper surface of the modulation layer and the upper surface of the tunneling enhancement layer, forms a Schottky contact with the gradually changing tunneling layer, forms an ohmic contact with the modulation layer, and realizes electrical connection. The application reduces the opening voltage and the reverse leakage current, improves the conduction current and the breakdown voltage, and can be used as a power switching device of a power electronic system.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronics, and particularly relates to a Schottky diode device, which can be used in power electronic systems. BACKGROUND

[0002] With the increasing demand for renewable energy systems, electric vehicles, aerospace systems and consumer electronics will require more efficient and fast power electronic devices, and power switching devices as important components of power electronic systems are important components for energy conversion and control. In order to break the limitations of silicon-based materials on device performance, the third generation semiconductor gallium nitride material has been widely used in the preparation of power devices. Due to the advantages of large band gap, high saturated electron drift velocity and large critical electric field strength, gallium nitride material can realize higher current density and higher voltage range.

[0003] In recent years, a large number of research works have been carried out on high-performance vertical gallium nitride diodes at home and abroad. Generally, vertical gallium nitride PN junction diodes have higher voltage resistance and lower leakage current than vertical gallium nitride Schottky diodes, but the turn-on voltage of vertical gallium nitride PN junction diodes is greater than 3V, resulting in large conduction loss of power switching circuit.

[0004] In order to reduce the switching loss of the device while maintaining the voltage resistance, reference Mg-implanted vertical GaN junction barrier Schottky rectifiers with low on resistance, low turn-on voltage, and nearly ideal nondestructive breakdown voltage, Applied Physics Letters, Vol. 121, No. 20, 2022 discloses a vertical gallium nitride junction barrier power diode, as shown in Figure 1As shown. It includes: substrate 1, drift layer 2, P-type block 3, anode 4, cathode 5;The structure of anode 4 and drift layer 2 forms Schottky contact, and forms ohmic contact with P-type block 3, and the Schottky junction of the device is opened when the forward operation is conducted, and the depletion region of P-type block 3 is expanded to transfer the electric field peak to the inside of the drift layer 2 when the reverse operation is conducted, and the Schottky junction interface is protected. Although the structure can improve the reverse withstand voltage to some extent, the high breakdown voltage requires a small P-type block spacing, otherwise, the low on-resistance and high on-current require a large P-type block spacing, and the large P-type block spacing will result in large reverse leakage current and small breakdown voltage of the device. Therefore, the contradiction makes the device unable to realize low on-resistance and high breakdown voltage simultaneously. In addition, the preparation conditions of local P-type gallium nitride material are relatively complex, the equipment requirements are relatively high, and the impurity activation rate is not high, resulting in that the reverse leakage of the junction barrier Schottky diode is still relatively large, and the withstand voltage is relatively low. Therefore, it is necessary to reduce the forward conduction loss and the reverse leakage current, and realize the power diode with high breakdown voltage and low on-resistance. SUMMARY

[0005] The purpose of the present application is to solve the technical problems of the prior art, and to provide a vertical gallium nitride tunneling power diode, which can realize low opening voltage and reduce the reverse leakage of the device, so as to improve the reverse breakdown voltage and reduce the on-resistance.

[0006] In order to achieve the above purpose, the technical scheme of the present application is as follows:

[0007] 1. A vertical gallium nitride tunneling power diode, comprising: a substrate 1, a drift layer 2, an anode 8, a cathode 9, and a recess 3 provided on the left and right sides of the drift layer 2, characterized in that:

[0008] The recess 3 is sequentially provided with a gradual change tunneling layer 4 and a modulation layer 7, the gradual change tunneling layer 4 is provided with 2n-1 rectangular array holes 5 which are equally spaced and have the same size, and a tunneling enhancement layer (6) is arranged in the array hole 5 for improving the forward conduction current.

[0009] The anode 8 is located on the upper surface of the modulation layer 7 and the upper surface of the tunneling enhancement layer 6, and is used for realizing electrical connection.

[0010] Further, the substrate 1 is made of gallium nitride material; the graded tunneling layer 4 is made of AlGaN material with an increasing Al component from bottom to top, and the Al component ranges from 0 to 35%. When the device conducts forward, it forms an AlGaN / GaN heterojunction structure with the drift layer 2, polarizes out two-dimensional electron gas, increases the forward conduction current, and can increase the current during the turn-on process by increasing the tunneling probability of carriers, reduce the forward turn-on voltage of the device. When the device blocks reverse, it is beneficial to increase the barrier layer height of the Schottky junction and reduce the reverse leakage current.

[0011] Further, the tunneling enhancement layer 6 is made of any one of Ta2O5, ZrO2, HfO2, and TiO2 with a high-K dielectric material having a dielectric constant greater than that of the AlGaN material, which is used to increase the tunneling probability of carriers, increase the forward conduction current, and reduce the turn-on voltage.

[0012] The modulation layer 7 is made of P-type NiO material with a hole concentration of 1×10 18 ~8×10 20 cm -3 , which is used to inject holes into the drift layer 2 to attract more electrons to participate in conduction and increase the forward conduction current. When the device blocks reverse, it shields the Schottky surface electric field, transfers the electric field peak to the inside of the drift layer 2, avoids premature breakdown of the device at the Schottky junction, and improves the voltage withstand capacity of the device.

[0013] Further, for the groove 3, its depth is a, its width is b, and the distance between adjacent two grooves is c, and b < c is satisfied; for the graded tunneling layer 4, its thickness k1 is 5~10 nm, and the length k2 of its left and right ends extending horizontally outside the groove 3 is 20~100 nm; for the modulation layer 7, its thickness k3 is 80~300 nm, and the horizontal overlapping length k4 of its left and right ends with the graded tunneling layer 4 outside the groove 3 is 10~50 nm.

[0014] Further, the tunneling enhancement layer 6 is composed of 2n - 1 equally spaced and same-sized rectangular high-K dielectric blocks. The horizontal width of each high-K dielectric block is t, the interval between adjacent two high-K dielectric blocks is c2, the horizontal distance between the first high-K dielectric block on the left and the modulation layer 7 on the left is c1, the horizontal distance between the first high-K dielectric block on the right and the modulation layer 7 on the right is c1, and c1 > 0, c2 > t > 0, c1 = c2.

[0015] Further, a Schottky contact is formed between the anode 8 and the graded tunneling layer 4; an ohmic contact is formed between the anode 8 and the modulation layer 7.

[0016] 2. A method for fabricating a vertical gallium nitride tunneling power diode, which is characterized by comprising the following steps:

[0017] A) Epitaxially grow n on the substrate 1- GaN semiconductor material is formed on the drift layer 2;

[0018] B) A first mask is made on the drift layer 2, and a groove 3 is etched on the drift layer 2 by using the mask;

[0019] C) A second mask is made on the drift layer 2, and AlGaN semiconductor material is epitaxially grown on the surface of the drift layer 2 and the bottom and sidewall of the groove 3 by using the mask, so that a graded tunnel layer 4 with a thickness of 5-10 nm is formed;

[0020] D) A third mask is made on the drift layer 2 and the graded tunnel layer 4, and an array hole 5 is etched on the graded tunnel layer 4 by using the mask;

[0021] E) A fourth mask is made on the drift layer 2 and the graded tunnel layer 4, and a high-K dielectric is filled in the array hole 5 by using the mask to form a tunnel enhancement layer 6;

[0022] F) A fifth mask is made on the back of the substrate 1, and a metal is deposited on the back of the substrate 1 by using the mask, and rapid thermal annealing is performed to form a cathode 9;

[0023] G) A sixth mask is made on the drift layer 2, the graded tunnel layer 4 and the tunnel enhancement layer 6, and a P-type NiO material is sputtered on the graded tunnel layer 4 by using the mask, and a modulation layer (7) with a thickness of 80-300 nm is formed through a stripping process;

[0024] H) A seventh mask is made on the drift layer 2, the graded tunnel layer 4 and the modulation layer 7, and a metal is deposited to form an anode 8 by using the mask, and the preparation of the whole device is completed.

[0025] Compared with the conventional vertical GaN junction type barrier power diode, the device has the following advantages:

[0026] Firstly, the device adds a graded tunnel layer formed of AlGaN material, which can generate electron tunneling current at a smaller forward voltage, quickly reach the current required when the device is turned on, and thus reduce the opening voltage of the device

[0027] When reverse blocking, since the band gap of AlGaN is larger than that of GaN, the barrier height of the Schottky junction can be increased, the probability of electrons in the metal flowing into the semiconductor can be reduced, and the reverse leakage current under the same voltage can be inhibited; and since the graded tunnel layer is inserted between the modulation layer and the drift layer, the reverse leakage current of the heterojunction formed by the P-type NiO and the N-type gallium nitride can be inhibited

[0028] Secondly, the device of the application is provided with 2n-1 rectangular array holes with equal intervals and same size in the middle of the gradual change tunneling layer, and is provided with a tunneling enhancement layer in the array holes, and the different dielectric constant properties of the gradual change tunneling layer and the tunneling enhancement layer are used to make the peak value of the transverse electric field change suddenly at the interface of the two materials, induce the barrier width at the interface to be narrowed, and further greatly improve the tunneling probability of the carriers, increase the forward conduction current, and reduce the opening voltage.

[0029] Thirdly, the device of the application uses P-type NiO material to form the modulation layer, compared with the P-type gallium nitride material with low impurity activation rate and difficult to improve hole concentration, the P-type NiO material has simple preparation process and high hole concentration, thereby increasing the number of carriers injected into the drift layer when the device is in forward conduction, and improving the conduction current and reducing the conduction resistance.

[0030] Fourthly, the device of the application uses the groove structure, so that the P-type NiO material penetrates into the drift layer, and the depletion region of the hetero-PN junction formed by the modulation layer and the drift layer can be expanded when the device is in reverse blocking, so that the peak value of the electric field on the Schottky junction surface can be greatly reduced, and the voltage resistance of the device can be improved.

[0031] Fifthly, the gradual change tunneling layer of the device of the application is inserted between the modulation layer and the drift layer, so that the reverse leakage current of the heterojunction formed by the P-type NiO and the N-type gallium nitride can be inhibited. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a structure diagram of a traditional vertical gallium nitride junction type barrier power diode;

[0033] Figure 2 is a structure diagram of a vertical gallium nitride tunneling power diode of the application;

[0034] Figure 3 is a flowchart for realizing the vertical gallium nitride tunneling power diode of the application;

[0035] Figure 4 is a forward conduction curve diagram of simulating the device of the application and the traditional vertical gallium nitride junction type barrier power diode;

[0036] Figure 5 is a reverse breakdown curve diagram of simulating the device of the application and the traditional vertical gallium nitride junction type barrier power diode. DETAILED DESCRIPTION

[0037] The embodiments and effects of the application are described in further detail below with reference to the accompanying drawings.

[0038] REFERENCE Figure 2The vertical gallium nitride tunneling power diode of the present example comprises: a substrate 1, a drift layer 2, a groove 3, a gradual tunneling layer 4, an array hole 5, a tunneling enhancement layer 6, a modulation layer 7, an anode 8, and a cathode 9.

[0039] The substrate 1 is made of gallium nitride homogenous substrate.

[0040] The drift layer 2 is located on the upper part of the substrate 1 and is made of gallium nitride.

[0041] The groove 3 is located on the left and right sides of the drift layer 2, has a depth a of 10-200 nm, a width b of 10-500 nm, a spacing c of 5-450 nm between adjacent two grooves, and satisfies b<c.

[0042] The gradual tunneling layer 4 is located on the upper surface of the drift layer 2 and the bottom and sidewall of the groove 3, is made of AlGaN material with gradually increasing Al component from bottom to top, has an Al component range of 0-20%, a thickness k1 of 5-10 nm, and a length k2 of 20-100 nm of the left and right ends extending laterally outside the groove 3.

[0043] The array hole 5 is located between the two grooves on the upper surface of the drift layer 2.

[0044] The tunneling enhancement layer 6 is located inside the array hole 5 and is made of any one of Ta2O5, ZrO2, HfO2, and TiO2 high-K dielectric material with a dielectric constant greater than that of AlGaN material.

[0045] The modulation layer 7 is located on the upper surface of the gradual tunneling layer 4 and is made of P-type NiO material, has a thickness k3 of 80-300 nm, a hole concentration of 1×10 19 ~8×10 20 cm -3 , and a lateral overlapping length k4 of 10-50 nm of the left and right ends with the gradual tunneling layer 4 outside the groove 3.

[0046] The anode 8 is located on the upper surface of the gradual tunneling layer 4, the tunneling enhancement layer 6, and the modulation layer 7, and forms a Schottky contact with the gradual tunneling layer 4 and an Ohmic contact with the modulation layer 7.

[0047] The cathode 9 is located on the lower surface of the substrate 1 and forms an Ohmic contact therebetween.

[0048] Reference Figure 3 The method for manufacturing the vertical gallium nitride tunneling power diode of the present example is given as follows.

[0049] Example 1: The thickness k1 of the graded tunneling layer 4 is 5 nm, the Al composition range is 0-20%, the length k2 of the lateral extension of the left and right ends of the graded tunneling layer 4 outside the groove 3 is 20 nm, the array hole is 5 large, the width t of each array hole is 1 μm, the spacing c2 between the adjacent two holes is 1.5 μm, the spacing cl of the outermost hole and the side modulation layer 7 is 7 μm, and the vertical gallium nitride tunneling power diode is used for the tunneling enhancement layer 6.

[0050] Step 1. Make the drift layer 2, as Figure 3 a.

[0051] The n-type GaN with a thickness of 5 μm and a doping concentration of 1 x 10 14 cm -3 - is epitaxially grown on the gallium nitride substrate 1 using the metal organic chemical vapor deposition technology to form the drift layer 2. The process conditions are: the temperature is 800°C, the pressure is 30 Torr, SiH4 is used as the doping source, the hydrogen flow is 4000 sccm, the ammonia flow is 4000 sccm, and the gallium source flow is 100 μmol / min.

[0052] Step 2. Make the groove 3, as Figure 3 b.

[0053] The first mask is made on the drift layer 2, and the groove is etched on the drift layer 2 using the reactive ion etching technology using the mask, the etching depth is 2 μm, the width is 10 μm, the spacing between adjacent grooves is 30 μm, and the groove 3 is formed. The etching process conditions are: the Cl2 flow is 15 sccm, the pressure is 10 mTorr, and the power is 100 W.

[0054] Step 3. Make the graded tunneling layer 4, as Figure 3 c.

[0055] The second mask is made on the drift layer 2, and the AlGaN material with a thickness of 5 nm is epitaxially grown on the drift layer 2 and the bottom and sidewall of the groove 3 using the metal organic chemical vapor deposition technology using the mask, and the graded tunneling layer 4 is formed. The process conditions are: the temperature is 800°C, the pressure is 30 Torr, the hydrogen flow is 4000 sccm, the ammonia flow is 3500 sccm, the gallium source flow is 30 μmol / min, and the aluminum source flow is 5 μmol / min.

[0056] Step 4. Make the array hole 5, as Figure 3 d.

[0057] ​The third mask is made on the drift layer 2 and the gradual tunneling layer 4, and the gradual tunneling layer 4 is etched by using the mask and the reactive ion etching technology, with an etching depth of 5 nm, to form the array hole 5. The process conditions are as follows: the Cl2 flow rate is 10 sccm, the pressure is 5 mTorr, and the power is 50 W.

[0058] Step 5. The tunneling enhancement layer 6 is made, as shown in FIG. 6, by Figure 3 e.

[0059] The fourth mask is made on the drift layer 2 and the gradual tunneling layer 4, and the HfO2 is deposited in the array hole 5 by using the mask and the radio frequency magnetron reactive sputtering technology to form the tunneling enhancement layer 6. The process conditions are as follows: the sputtering pressure in the reaction chamber is 0.1 Pa, the O2 and Ar flow rates are 1 sccm and 8 sccm respectively, and the temperature is 200°C.

[0060] Step 6. The cathode 9 is made, as shown in FIG. 7, by Figure 3 f.

[0061] The fifth mask is made on the back of the substrate 1, and the metal is deposited on the back of the substrate 1 by using the mask and the electron beam evaporation technology, wherein the deposited metal is a Ti / Au / Ni metal combination, i.e., Ti, Au and Ni from bottom to top, with thicknesses of 0.02 μm, 0.3 μm and 0.05 μm respectively, and the electron beam evaporation process conditions are as follows: the vacuum degree is 1.8 x 10 -3 Pa, the power is 350 W, and the evaporation rate is

[0062] The deposited metal is then subjected to rapid thermal annealing to form the cathode 9, and the thermal annealing process conditions are as follows: the temperature is 850°C, and the time is 35 s.

[0063] Step 7. The modulation layer 7 is made, as shown in FIG. 8, by Figure 3 g.

[0064] The sixth mask is made on the drift layer 2, the gradual tunneling layer 4 and the tunneling enhancement layer 6, and the P-type NiO material is sputtered on the gradual tunneling layer 4 by using the mask and the low-temperature sputtering technology, to form the modulation layer 7 with a thickness of 80 nm by a stripping process. The process conditions are as follows: the vacuum degree is 4.0 x 10 -4 Pa, the radio frequency power is 100 W, the O2 flow rate is 1 sccm, and the Ar flow rate is 1 sccm.

[0065] Step 8. The anode 8 is made, as shown in FIG. 9, by Figure 3 h.

[0066] A seventh mask is made on the drift layer 2, the graded tunneling layer 4 and the modulation layer 7, and a metal is deposited on the graded tunneling layer 4 and the modulation layer 7 by using the electron beam evaporation technique, wherein the deposited metal is Ni, and the process conditions are: vacuum degree is 5x10 -4 Pa, power is 200W, and evaporation rate is The anode 8 is formed, and the whole device is completed.

[0067] In the second embodiment, the thickness k1 of the graded tunneling layer 4 is 8nm, the Al component ranges from 0 to 20%, the length k2 of the lateral extension of the left and right ends of the graded tunneling layer 4 out of the groove 3 is 50nm, the array hole 5 is 11, the width t of each hole is 1.5μm, the distance c2 between the adjacent two holes is 2μm, the distance c1 between the outermost hole and the left modulation layer 7 or the right modulation layer 7 is 5μm, and the tunneling enhancement layer 6 is a vertical gallium nitride tunneling power diode using TiO2 material.

[0068] Step one. The drift layer 2 is made, for example, Figure 3 a.

[0069] The n-type GaN with the thickness of 10μm and the doping concentration of 5x10 15 cm -3 - is epitaxially grown on the gallium nitride substrate 1 by using the metal organic chemical vapor deposition technique under the process conditions of the temperature of 900℃, the pressure of 45Torr, the hydrogen flow of 5000sccm, the ammonia flow of 4600sccm, and the gallium source flow of 160μmol / min, and the drift layer 2 is formed.

[0070] Step two. The groove 3 is made, for example, Figure 3 b.

[0071] The first mask is made on the drift layer 2, and the drift layer 2 is etched on both sides by using the reactive ion etching technique under the process conditions of the Cl2 flow of 15sccm, the pressure of 10mTorr, and the power of 110W, the etching depth is 4μm, the width is 15μm, and the distance between the adjacent grooves is 50μm, and the groove 3 is formed.

[0072] Step three. The graded tunneling layer 4 is made, for example, Figure 3 c.

[0073] The second mask is made on the drift layer 2, and the AlGaN material with the thickness k1 of 8nm is epitaxially grown on the drift layer 2 and the two grooves 3 by using the metal organic chemical vapor deposition technique under the process conditions of the temperature of 950℃, the pressure of 45Torr, the hydrogen flow of 5000sccm, the ammonia flow of 3800sccm, the gallium source flow of 40μmol / min, and the aluminum source flow of 5μmol / min, and the graded tunneling layer 4 is formed.​

[0074] Step 4. Fabricate array holes 5, as shown. Figure 3 d.

[0075] A third mask was fabricated on the drift layer 2 and the gradient tunneling layer 4. Under the process conditions of Cl2 flow rate of 10 sccm, pressure of 5 mTorr, and power of 50 W, reactive ion etching was used to etch the gradient tunneling layer 4 to a depth of 8 nm, forming array holes 5.

[0076] Step 5. Fabricate tunneling reinforcement layer 6, as follows Figure 3 e.

[0077] A fourth mask was fabricated on the drift layer 2 and the gradient tunneling layer 4. Under the process conditions of a sputtering pressure of about 50 Pa in the reaction chamber, flow rates of O2 and Ar of 10 sccm and 50 sccm respectively, and a temperature of 200 °C, TiO2 was deposited in the array hole 5 using radio frequency magnetron reactive sputtering technology to form the tunneling enhancement layer 6.

[0078] Step 6. Fabricate cathode 9, as follows Figure 3 f.

[0079] 6.1) A mask is fabricated for the fifth time on the back side of substrate 1, under a vacuum of 8 × 10⁻⁶. -4 Pa, power is 400W, evaporation rate is Under the specified process conditions, metal was deposited on the back side of substrate 1 using electron beam evaporation technology. The deposited metal was a Ti / Al / Au / Ni metal combination, namely Ti, Al, Ni, and Au from bottom to top, with thicknesses of 0.02 μm, 0.14 μm, 0.055 μm, and 0.045 μm, respectively.

[0080] 6.2) The deposited metal is rapidly annealed under process conditions of 860℃ and 30s to form cathode 9.

[0081] Step 7. Create modulation layer 7, as shown. Figure 3 g.

[0082] A sixth mask was fabricated on drift layer 2, gradient tunneling layer 4, and tunneling reinforcement layer 6, under a vacuum of 3.0 × 10⁻⁶. - 4 Under the process conditions of Pa, RF power of 100W, O2 flow rate of 1sccm and Ar flow rate of 1sccm, P-type NiO material with a thickness k3 of 150nm is sputtered on the graded tunneling layer 4 using RF magnetron reactive sputtering technology to form modulation layer 7.

[0083] Step 8. Fabricate anode 8, as follows Figure 3 h.

[0084] A seventh mask was fabricated on drift layer 2, gradient tunneling layer 4, and modulation layer 7, under a vacuum of 1.6 × 10⁻⁶. -3 Pa, power is 350W, evaporation rate is Under the specified process conditions, metal Wu was deposited on the tunneling layer 4 and modulation layer 5 using electron beam evaporation technology to form the anode 8, thus completing the fabrication of the entire device.

[0085] Example 3: The gradient tunneling layer 4 is fabricated with a thickness k1 of 10 nm and an Al composition ranging from 0% to 20%; there are 13 array holes, each with a width t of 3 μm, a spacing c2 of 5 μm between two adjacent holes, and a spacing c1 of 10 μm between the outermost hole and the modulation layer 7; the tunneling enhancement layer 6 is a vertical gallium nitride tunneling power diode made of Ta2O5 material.

[0086] Step A. Create drift layer 2, as follows Figure 3 a.

[0087] Set the vacuum level to 1.0 × 10⁻⁶. -10 The process conditions included mbar, RF power of 400W, N2 as the reactant, and a high-purity Ga source. Molecular beam epitaxy was used to epitaxially grow a 12μm thick substrate with a doping concentration of 1×10⁻⁶ on substrate 1. 16 cm -3 n - Type GaN, forming drift layer 2.

[0088] Step B. Create groove 3, as shown Figure 3 b.

[0089] With process conditions set at a Cl2 flow rate of 15 sccm, a pressure of 10 mTorr, and a power of 100 W, a mask was fabricated for the first time on the drift layer 2. Reactive ion etching was then used to etch two grooves 3 with a depth of 5 μm and a width of 20 μm on both sides of the drift layer 2, forming two grooves 3 with a spacing of 80 μm.

[0090] Step C. Fabricate the gradient tunneling layer 4, as follows Figure 3 c.

[0091] The process conditions were set as follows: temperature 900℃, pressure 80 Torr, hydrogen flow rate 4800 sccm, ammonia flow rate 4900 sccm, gallium source flow rate 150 μmol / min, and aluminum source flow rate 50 μmol / min. A mask was fabricated a second time on the drift layer 2. Using metal-organic chemical vapor deposition, AlGaN material with a thickness k1 of 10 nm was epitaxially grown on the upper surface of the drift layer 2 and on the bottom and sidewalls of the groove 3 to form a gradient tunneling layer 4.

[0092] Step D. Fabricate array holes 5, as shown Figure 3 d.

[0093] The process conditions are set as follows: Cl2flow rate is 10 sccm, pressure is 5 mTorr, and power is 50 W. The third mask is made on the drift layer 2 and the gradual tunneling layer 4. The gradual tunneling layer 4 is etched to a depth of 10 nm by using the reactive ion etching technology to form the array hole 5.

[0094] Step E. The tunneling enhancement layer 6 is made as follows: Figure 3 e.

[0095] The process conditions are set as follows: sputtering gas pressure in the reaction chamber is 300 Pa, O2and Ar flow rates are 50 sccm and 100 sccm respectively, and temperature is 900 °C. The fourth mask is made on the drift layer 2 and the gradual tunneling layer 4. The Ta2O5is deposited in the array hole 5 by using the radio frequency magnetron reactive sputtering technology to form the tunneling enhancement layer 6.

[0096] Step F. The cathode 9 is made as follows: Figure 3 f.

[0097] The fifth mask is made on the back of the substrate 1. The metal is deposited on the back of the substrate 1 by using the electron beam evaporation technology under the process conditions of a vacuum degree less than 1.8 x 10 -3 Pa, power is 500 W, and evaporation rate is The deposited metal is a Ti / Al / Mo / Au metal combination, i.e. Ti, Al, Mo and Au from bottom to top, and the thicknesses are 0.02 μm, 0.1 μm, 0.03 μm and 0.03 μm respectively. Then, the rapid thermal annealing is performed under the process conditions of a temperature of 860 °C and a time of 30 s to form the cathode 9.

[0098] Step G. The modulation layer 7 is made as follows: Figure 4 g.

[0099] The sixth mask is made on the drift layer 2, the gradual tunneling layer 4 and the tunneling enhancement layer 6. The P-type NiO material with a thickness k3 of 300 nm is sputtered on the gradual tunneling layer 4 by using the radio frequency magnetron reactive sputtering technology under the process conditions of a vacuum degree of 300 Pa, O2flow rate of 50 sccm and Ar flow rate of 100 sccm by using the sixth mask to form the modulation layer 7.

[0100] Step H. The anode 8 is made as follows: Figure 4 h.

[0101] The seventh mask is made on the drift layer 2, the gradual tunneling layer 4 and the modulation layer 7. The metal is deposited on the drift layer 2 by using the electron beam evaporation technology under the process conditions of a vacuum degree of 1.8 x 10 - 3 Pa, power is 1000 W, and evaporation rate is The seventh mask is used to form the anode 8 by electron beam evaporation technology under the gradual change tunneling layer 4 and the modulation layer 7, and the whole device is completed.

[0102] The effect of the present application can be further illustrated by the following simulation results.

[0103] Simulation 1: The forward conduction characteristics of the traditional vertical gallium nitride junction type barrier power diode and the device of the third embodiment of the present application are simulated by using the simulation software Silvaco, and the results are shown in Figure 5 From Figure 5 It can be seen that the turn-on voltage of the device of the present application is 0.4V, and the turn-on voltage of the traditional junction barrier Schottky diode is 0.7V. It shows that the device of the present application has the advantages of large conduction current and small conduction resistance.

[0104] Simulation 2: The breakdown characteristics of the traditional vertical gallium nitride junction type barrier power diode and the device of the third embodiment of the present application are simulated by using the simulation software Silvaco, and the results are shown in ​ From ​ It can be seen that the breakdown voltage of the device of the present application is about 1560V, and the breakdown voltage of the traditional vertical gallium nitride junction type barrier power diode is only about 660V, which shows that the device of the present application has better voltage resistance than the traditional device.

[0105] The above description is only three specific embodiments of the present application, and does not constitute a limitation on the present application. Obviously, for those skilled in the art, after understanding the content and principles of the present application, various modifications and changes in form and details can be made according to the method of the present application without departing from the principles and scope of the present application, for example, in addition to using metal organic chemical vapor deposition technology and molecular beam epitaxy technology, hydride vapor phase epitaxy technology and atomic layer deposition technology can also be used to prepare AlGaN and GaN materials; in addition to using radio frequency magnetron reactive sputtering technology, atomic layer deposition technology and plasma enhanced chemical vapor deposition technology can also be used to prepare the tunneling enhancement layer; in addition to using Ta2O5, ZrO2, HfO2 dielectric, TiO2 dielectric can also be used for the tunneling enhancement layer; in addition to using the process conditions of pressure 1.0×10 - 10 mbar and radio frequency power 400W, other process parameters in the range of pressure 1.0×10 -10 ~7.0×10 -10 mbar and radio frequency power 100~800W can also be used, but these modifications and changes based on the present application are still within the protection scope of the claims of the present application.

Claims

1. A vertical gallium nitride tunneling power diode, comprising: The substrate (1), drift layer (2), anode (8), and cathode (9) are characterized by having grooves (3) on both sides of the drift layer (2). A gradient tunneling layer (4) and a modulation layer (7) are sequentially arranged above the groove (3). The gradient tunneling layer (4) has 2n-1 equally spaced rectangular array holes (5) of the same size in the middle. A tunneling enhancement layer (6) is arranged inside the array holes (5) to improve the forward conduction current. Where n is the number of array holes (5) from the edge to the center. The anode (8) is located on the upper surface of the modulation layer (7) and the upper surface of the tunneling reinforcement layer (6) for achieving electrical connection; The gradient tunneling layer (4) is made of AlGaN material with the Al composition gradually increasing from bottom to top; The tunneling reinforcement layer (6) is made of any one of the high-k dielectric materials with a dielectric constant greater than that of AlGaN material, such as Ta2O5, ZrO2, HfO2, and TiO2. The modulation layer (7) is made of P-type NiO material.

2. The vertical gallium nitride tunneling power diode according to claim 1, characterized in that: The substrate (1) is made of gallium nitride material; The Al composition in the gradient tunneling layer (4) ranges from 0 to 35%. When the device is forward-biased, it forms an AlGaN / GaN heterojunction structure with the drift layer (2), polarizes a two-dimensional electron gas, increases the forward conduction current, and can increase the current during the turn-on process by increasing the tunneling probability of charge carriers, thereby reducing the forward turn-on voltage of the device. When the device is reverse-biased, it is beneficial to increase the barrier layer height of the Schottky junction and reduce the reverse leakage current.

3. The vertical gallium nitride tunneling power diode according to claim 1, characterized in that: The tunneling enhancement layer (6) is used to increase the tunneling probability of charge carriers, increase the forward conduction current, and reduce the turn-on voltage. The hole concentration in the modulation layer (7) is 1×10 18 ~8×10 20 cm -3 It is used to attract more electrons to participate in conduction by injecting holes into the drift layer (2), thereby increasing the forward conduction current; when the device is reverse blocked, it shields the electric field on the Schottky surface, transfers the electric field peak to the interior of the drift layer (2), avoids the device from breaking down prematurely at the Schottky junction, and improves the device's withstand voltage capability.

4. The vertical gallium nitride tunneling power diode according to claim 1, characterized in that: The groove (3) has a depth of a, a width of b, and a spacing of c between two adjacent grooves, and satisfies b. <c; The gradient tunneling layer (4) has a thickness k1 of 5~10nm and a length k2 of 20~100nm extending laterally outside the groove (3) at its left and right ends. The modulation layer (7) has a thickness k3 of 80~300nm, and its left and right ends are connected to the gradient tunneling layer (4) outside the groove (3). The lateral overlap length k4 is 10~50nm.

5. The vertical gallium nitride tunneling power diode according to claim 1, characterized in that: The tunneling enhancement layer (6) is composed of 2n-1 equally spaced and identical rectangular high-K dielectric blocks. The lateral width of each high-K dielectric block is t, the interval between two adjacent high-K dielectric blocks is c2, the lateral distance between the first high-K dielectric block on the left and the left modulation layer (7) is c1, the lateral distance between the first high-K dielectric block on the right and the right modulation layer (7) is c1, and c1>0, c2>t>0, c1=c2.

6. The vertical gallium nitride tunneling power diode according to claim 1, characterized in that: A Schottky contact is formed between the anode (8) and the gradient tunneling layer (4); An ohmic contact is formed between the anode (8) and the modulation layer (7).

7. A method for fabricating a vertical gallium nitride tunneling power diode, characterized in that: Includes the following steps: A) Epitaxial growth of n on substrate (1) - GaN semiconductor material, forming a drift layer (2); B) A mask is first made on the drift layer (2), and the mask is used to etch grooves (3) on the drift layer (2). C) A mask is fabricated a second time on the drift layer (2). Using the mask, AlGaN semiconductor material is epitaxially grown on the upper surface of the drift layer (2) and the bottom and sidewalls of the groove (3) to form a gradient tunneling layer (4) with a thickness of 5~10nm. D) A mask is fabricated for the third time on the drift layer (2) and the gradient tunneling layer (4), and the mask is used to etch an array of holes (5) on the gradient tunneling layer (4). E) A mask is fabricated for the fourth time on the drift layer (2) and the gradient tunneling layer (4), and the high-K medium is filled in the array hole (5) to form a tunneling enhancement layer (6). F) A mask is fabricated for the fifth time on the back of the substrate (1). Metal is deposited on the back of the substrate (1) using the mask and then rapidly annealed to form a cathode (9). G) A mask is fabricated for the sixth time on the drift layer (2), the gradient tunneling layer (4) and the tunneling enhancement layer (6). P-type NiO material is sputtered on the gradient tunneling layer (4) using the mask, and a modulation layer (7) with a thickness of 80~300nm is formed by peeling process. H) A mask is fabricated for the seventh time on the drift layer (2), the gradient tunneling layer (4) and the modulation layer (7), and metal is deposited using the mask to form the anode (8), thus completing the fabrication of the entire device.

8. The method according to claim 7, characterized in that: Step A) Epitaxial growth n - Both AlGaN semiconductor material and step C) epitaxial growth of AlGaN semiconductor material are performed using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), wherein: The process conditions for the aforementioned organometallic chemical vapor deposition technique are as follows: Temperature: 800~1000℃, Pressure: 30~100 Torr, Hydrogen flow rate: 4000~6000 sccm Ammonia flow rate is 3500~5500 sccm, gallium source flow rate is 100~300 μmol / min. The aluminum source flow rate is 5~50 μmol / min; The molecular beam epitaxy technique has the following process conditions: The pressure is 1.0 × 10⁻⁶. -10 ~7.0×10 -10 mbar, RF power is 100~800W, The reactants are N2 and a high-purity Ga source.

9. The method according to claim 7, characterized in that: The fabrication of the tunneling enhancement layer in step E) and the fabrication of the modulation layer in step G) both employ radio frequency magnetron reactive sputtering technology, with the following process conditions: The sputtering pressure in the reaction chamber is 0.1~300 Pa. O2 flow rate is 1~50 sccm Ar flow rate is 1~100 sccm Temperature range: 100~600 ℃; In step F), the cathode is fabricated, and in step H), the anode is fabricated. Both processes employ electron beam evaporation to deposit metal, and the process conditions are as follows: Vacuum degree: 5×10 -4 ~1.8×10 -3 Pa, Power: 200~1000W, evaporation rate less than 3Å / s; The rapid hot annealing process conditions are: temperature 800~900℃, time 30~75s.

10. The method according to claim 7, characterized in that: The fabrication of the grooves in step B) and the fabrication of the array holes in step D) both employ reactive ion etching technology, with the following process conditions: Cl2 flow rate: 15~60 sccm Pressure: 10~100 mTorr Power range: 100~500W.

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