Power semiconductor device and manufacturing method thereof
By improving the process of power semiconductor devices, using doping type and mask technology to reduce the cell size of the device, the problem of on-resistance cannot be reduced and better on-response performance is achieved.
Patent Information
- Application Number
- CN202510152334.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-11
- Publication Date
- 2025-06-06
AI Technical Summary
Due to device performance and process limitations, existing power semiconductor devices cannot further reduce the cell size, so the on-resistance cannot be further reduced.
By improving the device process, a second doped type bulk region is formed using a semiconductor layer of the first doped type, and an input region and a gate structure are formed through mask technology to ensure that there is no lateral overlap region between the gate structure and the input region, thereby reducing the cell size.
The cell size of power semiconductor devices is reduced, the on-resistance is reduced, and the device on-conductivity is improved.
Smart Images
Figure CN120111918A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a power semiconductor device and a method for manufacturing the same. Background Art
[0002] On-resistance is the resistance of a power semiconductor device in the on state. This parameter is crucial for evaluating the performance of power semiconductor devices because it directly affects the power consumption, efficiency and thermal management of power semiconductor devices. Reducing on-resistance is one of the important directions for improving power semiconductor devices. The on-resistance of a power semiconductor device is closely related to the cell size. A smaller cell size corresponds to a smaller on-resistance. However, the existing power semiconductor devices cannot further reduce the cell size due to the limitations of device performance and device process, so the on-resistance of power semiconductor devices cannot be further reduced. Summary of the invention
[0003] In view of the above problems, the purpose of the present application is to provide a power semiconductor device and a method for manufacturing the same, so as to reduce the cell size of the power semiconductor device by improving the device process, thereby reducing the on-resistance of the power semiconductor device.
[0004] According to a first aspect of the present application, a method for manufacturing a power semiconductor device is provided, comprising: providing a semiconductor layer of a first doping type; forming a body region of a second doping type in the semiconductor layer, the second doping type being different from the first doping type; forming a first mask layer on a first surface of the semiconductor layer, the opening position of the first mask layer corresponding to the position of an input region in the body region; forming the input region of the first doping type using the first mask layer; removing a portion of the first mask layer outside a region where a gate structure is to be formed, aligning a side wall of the region where a gate structure is to be formed with a target side wall of the input region; forming a second mask layer, the second mask layer covering other regions except the region of the first surface of the semiconductor layer covered by the first mask layer; removing the first mask layer to form an opening position of the second mask layer; and forming the gate structure at the opening position of the second mask layer.
[0005] According to a second aspect of the present application, a power semiconductor device is provided. The power semiconductor device is manufactured by any one of the manufacturing methods described in the first aspect.
[0006] The manufacturing method of the power semiconductor device provided by the present application includes: forming a body region of a second doping type in a semiconductor layer of a first doping type, forming an input region of the first doping type in the body region by using a first mask layer formed on the first surface of the semiconductor layer, and forming a gate structure at the opening position of the second mask layer after forming the opening position of the second mask layer, wherein after the input region is formed, the first mask layer is removed outside the region where the gate structure is to be formed, and then a second mask layer is formed and the second mask layer covers other regions except the region of the first surface of the semiconductor layer covered by the first mask layer, and then the first mask layer is removed to form the opening position of the second mask layer. A side wall of the region where the gate structure is to be formed is aligned with the target side wall of the input region, so that one side of the opening position of the second mask layer formed by removing the first mask layer is aligned with the target side wall of the input region, so that the gate structure formed at the opening position of the second mask layer no longer has a lateral overlap region with the input region, so that the cell size of the power semiconductor device is reduced, and the on-resistance of the power semiconductor device is reduced accordingly. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings:
[0008] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a cell of a conventional metal oxide semiconductor field effect transistor;
[0009] Figure 2 Shown is a flow chart of a method for manufacturing a power semiconductor device provided by an embodiment of the present application;
[0010] Figure 3a to Figure 3u Shown is a schematic diagram of the execution results of each step in a method for manufacturing a power semiconductor device provided in an embodiment of the present application.
[0011] Description of reference numerals: 100-cell; 101-semiconductor layer; 101a-substrate; 101b-epitaxial layer; 101c-current spreading layer; 102-body region; 103-source region; 104-body contact region; 105-gate structure; 105a-gate oxide layer; 105b-gate conductor; 106-interlayer dielectric layer; 107-source electrode layer; 108-drain electrode layer; 200-cell; 201-semiconductor layer; 201a-substrate; 201b-epitaxial layer; 201c-current spreading layer; 202-body region; 2 03-input region; 204-body contact region; 205-gate structure; 205a-gate oxide layer; 205b-gate conductor; 205b'-conductive layer; 206-interlayer dielectric layer; 206'-insulating dielectric layer; 207-input region electrode layer; 208-output region electrode layer; 209-sacrificial structure; 209'-photoresist layer; m0-middle mask layer; m1-first mask layer; m2-second mask layer; m3-third mask layer; m4-fourth mask layer; m5-fifth mask layer; p1-patterned photoresist. DETAILED DESCRIPTION
[0012] In the following drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.
[0013] The on-resistance of a power semiconductor device is closely related to the cell size. A smaller cell size corresponds to a smaller on-resistance. Common power semiconductor devices include metal-oxide-semiconductor field-effect transistors (MOSFET) and insulated-gate bipolar transistors (IGBT). Figure 1 A cell of a metal oxide semiconductor field effect transistor is shown as an example to illustrate that multiple parameters that indirectly affect the on-resistance are affected by affecting the cell size.
[0014] Reference Figure 1 The cell 100 of the metal oxide semiconductor field effect transistor includes: a semiconductor layer 101, a body region 102 located in the semiconductor layer 101, a source region 103 located in the body region 102, a body contact region 104 located in the semiconductor layer 101 and adjacent to the body region 102 and the source region 103 in the body region 102, and a gate structure 105 located on the first surface of the semiconductor layer 101, the gate structure 105 including a gate oxide layer 105a and a gate conductor 105b. The cell 100 may also include the following: Figure 1As shown, an interlayer dielectric layer 106 is arranged around the gate structure 105, and a source electrode layer 107 is located on the first surface of the semiconductor layer 101 and a drain electrode layer 108 is located on the second surface of the semiconductor layer 101, so that the source electrode layer 107 can be separated from the gate structure 105 by the interlayer dielectric layer 106 when in contact with the surface of the source region 103.
[0015] The semiconductor layer 101 may include a substrate 101a, an epitaxial layer 101b and a current spreading layer (CSL) 101c stacked from bottom to top. The semiconductor layer 101 and the source region 103 have a first doping type, and the body region 102 and the body contact region 104 have a second doping type. The first doping type is one of N-type doping and P-type doping, and the second doping type is the other of N-type doping and P-type doping, wherein N-type doping refers to the addition of impurity elements that can provide additional free electrons into the semiconductor material, usually pentavalent elements such as phosphorus, arsenic, antimony, etc.; P-type doping refers to the addition of impurity elements that can generate holes into the semiconductor material, usually trivalent elements such as boron, gallium, indium, etc. Figure 1 In the example shown, the first doping type is N-type doping, the second doping type is P-type doping, and the source region 103 is heavily N-type doped compared to the semiconductor layer 101 , and the body contact region 104 is heavily P-type doped compared to the body region 102 .
[0016] Figure 1 In the semiconductor layer 101 shown, on the first side of the gate structure 105, a body contact region 104 and a body region 102 are sequentially arranged from far to near the gate structure 105; on the second side of the gate structure 105, a body contact region 104 and a body region 102 are sequentially arranged from far to near the gate structure 105. The first side and the second side of the gate structure 105 are opposite, and the structure on the first side of the gate structure 105 and the structure on the second side of the gate structure 105 are symmetrically arranged. The first side of the gate structure 105 is taken as an example for description. On the first side of the gate structure 105, the body region 102 has a set of opposite first sidewalls B 1 B 2 and the second side wall C 1 C 2 The side wall of the body region 102 adjacent to the body contact region 104 is the first side wall B 1 B 2 , a side wall of the source region 103 and a first side wall B of the body region 102 1 B 2 The sidewall of the source region 103 opposite to the body contact region 104 is the target sidewall A. 1 A 2 .
[0017] like Figure 1 As shown: (1) On the first side of the gate structure 105, the sidewall E of the interlayer dielectric layer 106 1 E 2 to the side wall F of the source electrode layer 107 1 F 2 The distance is half of the source ohmic contact width, and the source ohmic contact width is expressed as Lohmic; (2) The interlayer dielectric layer 106 is located at the first side of the gate structure 105 and the sidewall E of the interlayer dielectric layer 106 1 E 2 The width of the region between is the lateral distance between the gate conductor 105b and the source electrode layer 107, which is represented by Lgs; (3) There is a lateral overlap region between the gate structure 105 and any source region 103 . The width of the lateral overlap region is also referred to as the gate-source lateral overlap width, which is expressed as Loverrlap. (4) The target sidewall A of the source region 103 in any body region 102 1 A 2 The second side wall C of the body region 102 1 C 2 The area between is the channel region, and the width of the channel region is represented by Lch; (5) The second sidewall C of the body region 102 on the first side of the gate structure 105 1 C 2 The second sidewall C of the body region 102 on the second side of the gate structure 105 1 C 2 The area between them is the JFET (Junction Field Effect Transistor) region, and the width of the JFET region is represented by Ljfet.
[0018] The size L1 of the cell 100 is expressed by the following formula (1) based on the above parameters. The parameters in formula (1) have reached the current process capability limit, so it is difficult to further reduce the size of the cell 100, resulting in the device on-resistance cannot be further reduced.
[0019] L1=Lohmic+Lgs×2+Loverlap×2+Lch×2+Ljfet (1) In view of this, an embodiment of the present application provides a method for manufacturing a power semiconductor device. Figure 2 FIG. 1 is a flow chart of a method for manufacturing a power semiconductor device according to an embodiment of the present application. Figure 2 As shown, the manufacturing method includes: Step S110, providing a semiconductor layer of a first doping type; Step S120, forming a body region of a second doping type in the semiconductor layer, where the second doping type is different from the first doping type; Step S130, forming a first mask layer on the first surface of the semiconductor layer, wherein the opening position of the first mask layer corresponds to the position of the input region in the body region; Step S140, forming an input region of a first doping type using a first mask layer; Step S150, removing the portion of the first mask layer outside the region where the gate structure is to be formed, and aligning a side wall of the region where the gate structure is to be formed with a target side wall of the input region; Step S160, forming a second mask layer, wherein the second mask layer covers other regions except the first surface region of the semiconductor layer covered by the first mask layer; Step S170, removing the first mask layer to form an opening position of the second mask layer; and Step S180 , forming a gate structure at the opening position of the second mask layer.
[0020] Specifically, the first mask layer is used to form an input region of the first doping type, that is, the first mask layer is used to perform ion implantation so that ions of the first doping type are implanted at positions in the body region corresponding to the opening positions of the first mask layer to form the input region of the first doping type; the second mask layer also has an opening position, so that the second mask layer is used to form a gate structure only on the portion of the first surface of the semiconductor located at the opening position of the second mask layer.
[0021] It should be noted that the manufacturing method provided in the embodiment of the present application is applicable to manufacturing a variety of power semiconductor devices having the structures involved in the above steps, including metal oxide semiconductor field effect transistors and insulated gate bipolar transistors. It should be understood that when the power semiconductor device manufactured is a metal oxide semiconductor field effect transistor, the input region in the above steps is a source region; when the power semiconductor device manufactured is an insulated gate bipolar transistor, the input region in the above steps is an emitter region.
[0022] In the embodiment of the present application, after forming the input region by using the first mask layer, the portion of the first mask layer outside the region where the gate structure is to be formed is removed, and then a second mask layer is formed and the second mask layer covers other regions except the first surface region of the semiconductor layer covered by the first mask layer, and then the first mask layer is removed to form an opening position of the second mask layer, so that the opening position of the second mask layer is ensured to coincide with the region where the gate structure is to be formed by a self-alignment process, wherein a side wall of the region where the gate structure is to be formed is aligned with a target side wall of the input region, and thus a side wall of the gate structure formed at the opening position of the second mask layer is also aligned with a target side wall of the input region, that is, the gate structure no longer has a lateral overlap region with the input region, and the gate-source lateral overlap width Loverlap in formula (1) can be controlled to be substantially equal to 0 due to process improvement, so that the cell size of the power semiconductor device is allowed to be further reduced, the on-resistance of the power semiconductor device can be correspondingly reduced, and the on-performance of the device can be correspondingly improved.
[0023] Figure 3a to Figure 3u FIG. 1 is a schematic diagram showing the execution results of each step in a method for manufacturing a power semiconductor device provided in an embodiment of the present application. Figures 3a to 3u The manufacturing method of power semiconductor devices is introduced in detail.
[0024] Step S110, providing a semiconductor layer of a first doping type, in the case where the power semiconductor device is a metal oxide semiconductor field effect transistor, can be as follows: Figure 3a The method includes: forming an epitaxial layer 201b on a substrate 201a and forming a current spreading layer 201c on the epitaxial layer 201b, so as to obtain a semiconductor layer 201 including the substrate 201a, the epitaxial layer 201b and the current spreading layer 201c. Specifically, the substrate 201a, the epitaxial layer 201b and the current spreading layer 201c have the same doping type, and all have the first doping type. The substrate 201a can be a silicon substrate, a strained silicon substrate, a germanium substrate, a germanium silicon substrate, a silicon carbide substrate, a III-V compound substrate, etc., and is not limited to the examples listed above. The epitaxial layer 201b can be formed by epitaxial growth on the surface of the substrate 201a.
[0025] In the case where the power semiconductor device is an insulated gate bipolar transistor, step S110 provides a semiconductor layer of the first doping type, which may include: forming a base region on the buffer region to obtain a semiconductor layer including the buffer region and the base region. The buffer region and the base region also have the same doping type, and both have the first doping type.
[0026] Furthermore, the manufacturing method provided by the embodiment of the present disclosure may further include: forming a body contact region of the second doping type in the semiconductor layer before step S120.
[0027] Figure 3bFIG. 2 shows a body contact region 204 formed in the semiconductor layer 201 using a fourth mask layer m4 located on the first surface of the semiconductor layer 201. For an embodiment in which the semiconductor layer 201 includes a substrate 201a, an epitaxial layer 201b, and a current spreading layer 201c, the body contact region 204 is formed as shown in FIG. Figure 3b As shown, the body region is located in the current spreading layer 201 c included in the semiconductor layer 201 , and the body region formed in step S120 is also located in the current spreading layer 201 c included in the semiconductor layer 201 . Figure 3b In the embodiment, the fourth mask layer m4 has openings at the edges of the first and second sides opposite to the first surface of the semiconductor layer 201, so that the body contact region 204 formed by ion implantation using the fourth mask layer m4 is located at the first side edge and the second side edge of the first surface of the semiconductor layer 201.
[0028] Step S120, forming a body region of the second doping type in the semiconductor layer, may include: forming the body region in the semiconductor layer using a third mask layer located on the first surface of the semiconductor layer.
[0029] Figure 3c The third mask layer m3 located on the first surface of the semiconductor layer 201 is used to form a body region 202 in the semiconductor layer 201. The body region 202 includes opposite first sidewalls B 1 B 2 and the second side wall C 1 C 2 , first side wall B 1 B 2 It is adjacent to the body contact region 204 located on the same side in the semiconductor layer 201 . Figure 3c In the process, the third mask layer m3 is opened above the area with a width d1 where the body region 202 is to be formed in the semiconductor layer 201, and is opened above the area with a target width d2 of the body contact region 204 adjacent to the body region 202, so that ion implantation is performed using the third mask layer m3 to form the body region 202 adjacent to the body contact region 204 on the same side and to ensure that the body contact region 204 with a doping concentration greater than that of the body region 202 is formed.
[0030] Step S130, forming a first mask layer on the first surface of the semiconductor layer, may include: forming an intermediate mask layer covering the first surface of the semiconductor layer and the third mask layer, and etching back the intermediate mask layer to remove the portion of the intermediate mask layer on the first surface of the semiconductor layer and the top of the third mask layer to obtain the first mask layer.
[0031] Figure 3dFIG. 2 shows that an intermediate mask layer m0 is formed to cover the first surface of the semiconductor layer 201 and the third mask layer m3. The intermediate mask layer m0 can be formed by a deposition process, which can ensure that the thickness of the intermediate mask layer m0 is relatively uniform. It should be understood that since the third mask layer m3 has a groove, the intermediate mask layer m0 is Figure 3d The top of the third mask layer m3 and the groove wall of the groove in the third mask layer m3 and the portion of the first surface of the semiconductor layer 201 located in the groove in the third mask layer m3 are covered. Figure 3d In the embodiment, the thickness of the intermediate mask layer m0 is the channel width Lch, so the portion of the intermediate mask layer m0 on the groove wall in the third mask layer m3 has the channel width Lch. It should be noted that as long as the target width d2 is not greater than the channel width Lch, it can ensure that the input region 203 formed later will not overlap with the body contact region 204 on the same side, wherein the target width d2 being equal to the channel width Lch can make the input region 203 formed later adjacent to the body contact region 204 on the same side.
[0032] Figure 3e The middle mask layer m0 is etched back to remove the middle mask layer m0 on the first surface of the semiconductor layer 201 and the top of the third mask layer m3, thereby obtaining a first mask layer m1 consisting of the third mask layer m3 and the middle mask layer m0 at the grooved wall in the third mask layer m3.
[0033] Step S140, using the first mask layer to form an input region of the first doping type, which may be formed as follows: Figure 3f The input area 203 is shown.
[0034] like Figure 3f As shown, the input area 203 has a target side wall A 1 A 2 When the target width d2 is equal to the channel width Lch, the portion of the intermediate mask layer m0 on the groove wall in the third mask layer m3 has the target width d2, so the first mask layer m1 can accurately form an input region 203 with a width of (d1-d2), and the input region 203 is aligned with the target sidewall A. 1 A 2 The opposite wall is the first side wall B of the body region 202. 1 B 2 Adjacent, target side wall A of input area 203 1 A 2 The second sidewall C of the body region 202 1 C 2 There is a preset spacing between them with a width Lch of the channel region.
[0035] The first mask layer m1 is formed by growing an intermediate mask layer m0 on the third mask layer m3 and etching the intermediate mask layer m0 back without a mask. The slot width of the first mask layer m1 is controlled by controlling the thickness of the intermediate mask layer m0. The position and width of the input region 203 are controlled in combination with the control of the formation region of the first mask layer m1. Since the first mask layer m1 is formed without using a mask plate and a photolithography process after the third mask layer m3 is formed, the first mask layer m1 is formed by a sidewall self-alignment process. The first mask layer m1 will not be affected by the photolithography accuracy, so the first mask layer m1 has a high accuracy, so that the input region 203 formed based on the first mask layer m1 can have a high accuracy in both position and size.
[0036] Step S150, removing the first mask layer outside the region where the gate structure is to be formed, may include: forming a covering Figure 3f The photoresist on the first surface of the semiconductor layer 201 and the first mask layer m1 is shown; the part covering the target part of the first mask layer m1 is removed by a photolithography process, and the Figure 3g The patterned photoresist p1 is shown, wherein the target portion is the portion of the first mask layer m1 outside the region where the gate structure is to be formed; the first mask layer m1 is subjected to a second selective etching process using the patterned photoresist p1 as a mask.
[0037] It should be noted that Figure 3g The semiconductor layer 201 is divided into a first region and a second region by the symmetry axis indicated by the dotted line. A body contact region 204 and a body region 202 are sequentially provided in the first region from far to near the symmetry axis, and a body contact region 204 and a body region 202 are also sequentially provided in the second region from far to near the symmetry axis. Therefore, a side wall of the gate structure region to be formed and a target side wall A of the input region 203 are 1 A 2 In the case of alignment, the target part should be Figure 3g The part encircled by a dotted circle.
[0038] In some examples, the material used for the first mask layer m1 is silicon oxide, that is, the third mask layer m3 and the intermediate mask layer m0 are made of the same material and both are made of silicon oxide, and the second selective etching process is wet etching and the etchant used is hydrofluoric acid or buffered oxide etchant (BOE), so that the target portion of the first mask layer m1 can be removed well. Figure 3h shown.
[0039] The second mask layer formed in step S160 and the first mask layer are made of different materials. The step S170 performed thereafter to remove the first mask layer may include: etching the first mask layer by a first selective etching process.
[0040] In some examples, during the execution of step S160, the following may be formed: Figure 3i The second mask layer m2 shown in FIG. 1 is formed by etching back the second mask layer m2 to form a Figure 3j The second mask layer m2 shown is flush with the surface of the first mask layer m1, that is, the second mask layer m2 covers other regions except the first surface region of the semiconductor layer 201 covered by the first mask layer m1.
[0041] In some examples, the material used for the first mask layer m1 is silicon oxide, the material used for the second mask layer m2 is silicon nitride, the first selective etching process is wet etching and the etchant used is hydrofluoric acid or buffered oxide etching solution, so that the first mask layer m1 can be removed well, and the second mask layer m2 will not be damaged. It should be understood that the removal of the first mask layer in step S170 is to remove the remaining part of the first mask layer after the execution of step S150, that is, Figure 3j As shown, the portion of the first mask layer m1 in the region where the gate structure is to be formed is removed. Figure 3j After the first mask layer m1 is partially removed in the region where the gate structure is to be formed, Figure 3k As shown, after the first mask layer m1 is partially removed from the region where the gate structure is to be formed, an opening position of the second mask layer m2 is formed.
[0042] Step S180, forming a gate structure at the opening position of the second mask layer, may include: Figure 3l As shown in FIG. 1 , a gate oxide layer 205a is formed at the opening position of the second mask layer m2; Figure 3m As shown, a conductive layer 205b' is formed covering the sidewalls of the opening of the gate oxide layer 205a and the second mask layer m2; Figure 3o As shown in FIG. 1 , the opening of the second mask layer m2 is filled with the conductive layer 205b′ to form a sacrificial structure 209; based on the sacrificial structure 209, the top of the conductive layer 205b′ is removed to form a Figure 3p The gate conductor 205b is shown. Figure 3p The gate conductor 205b shown is recessed in the middle region to increase the surface area, so that a metal silicide connection layer with a larger area can be formed on the gate conductor 205b, thereby effectively reducing the gate resistance and improving the device speed.
[0043] In the case where the power semiconductor device is a silicon carbide device, the above-mentioned process of forming the gate oxide layer 205a may include: growing a gate oxide in an area located within the opening of the second mask layer m2 on the first surface of the semiconductor layer 201, and then performing a high-temperature annealing treatment on the grown gate oxide in a nitrogen-containing gas environment to form the gate oxide layer 205a. The gate oxide layer 205a formed in this way has reduced interface defect density due to the high-temperature treatment, thereby improving the channel mobility.
[0044] The conductive layer 205b' can be formed by deposition, for example, by depositing polysilicon material to form the conductive layer 205b'. The conductive layer 205b' formed by deposition can ensure that the thickness of the conductive layer 205b' is relatively uniform. Figure 3m As shown, the top of the second mask layer m2 is also covered, that is, the surface of the second mask layer m2 outside the opening is also covered. Figure 3n As shown in FIG. 1 , a photoresist layer 209' is formed on the conductive layer 205b' and the photoresist layer 209' is etched back to form a Figure 3o The sacrificial structure 209 shown in FIG. 2 is a schematic diagram of a sacrificial structure 209. In the case where the conductive layer 205b' also covers the top of the second mask layer m2, the portion of the conductive layer 205b' covering the top of the second mask layer m2 is also removed. It should be understood that after the gate conductor 205b is formed, the sacrificial structure 209 and the second mask layer m2 are both removed as shown in FIG. Figure 3q Shown is removed.
[0045] Since the opening position of the second mask layer m2 is located at the target side wall A of the input region 203 in the first region 1 A 2 The target side wall A of the input area 203 in the second region 1 A 2 Therefore, the gate oxide layer 205a and the gate conductor 205b formed at the opening of the second mask layer m2 do not have a lateral overlap region with the input region 203. Since the first mask layer m1 is used to form the input region 203, and the second mask layer m2 is formed based on the first mask layer m1 and then used to form the gate structure 205, the gate structure 205 is a structure formed by a self-alignment process and does not have a lateral overlap region with the input region 203 due to the self-alignment process.
[0046] Furthermore, the manufacturing method provided in the embodiment of the present disclosure may also include: Figure 3uAs shown, an interlayer dielectric layer 206 and an input region electrode layer 207 are formed on the first surface of the semiconductor layer 201, the interlayer dielectric layer 206 covers the top and sidewalls of the gate structure 205, and the input region electrode layer 207 covers the surface of the input region 203. It should be understood that, since the interlayer dielectric layer 206 covers the sidewalls of the gate structure 205, in the embodiment of the present disclosure, when there is no lateral overlap between the gate structure 205 and the input region 203, the input region electrode layer 207 covers a portion of the surface of the input region 203, and the input region electrode layer 207 does not contact the gate conductor 205b due to the presence of the interlayer dielectric layer 206.
[0047] In some examples, you can first Figure 3r As shown in FIG. 1 , an insulating dielectric layer 206′ is formed covering the first surface of the semiconductor layer 201 and the gate structure 205, and then as shown in FIG. Figure 3s As shown in FIG. 1 , a fifth mask layer m5 is formed on the surface of the insulating dielectric layer 206′. The projection of the fifth mask layer m5 on the first surface of the semiconductor layer 201 overlaps with the gate structure 205 and also overlaps with a portion of the input region 203 close to the gate structure 205. The insulating dielectric layer 206′ is etched using the fifth mask layer m5 to expose a portion of the surface of the input region 203, thereby obtaining the following: Figure 3t The interlayer dielectric layer 206 shown covers the top and sidewalls of the gate structure 205. The interlayer dielectric layer 206 can be made of the same insulating material as the gate oxide layer 205a, for example, both are made of silicon oxide. The material used for the fifth mask layer m5 can be photoresist.
[0048] Afterwards, Figure 3t The fifth mask layer m5 shown in FIG. is removed, and as shown in FIG. Figure 3u As shown in FIG. 2 , an input region electrode layer 207 covering the interlayer dielectric layer 206 and the first surface of the semiconductor layer 201 is formed. Figure 3u As shown, an output region electrode layer 208 is formed to cover the second surface of the semiconductor layer 201. Specifically, the input region electrode layer 207 and the output region electrode layer 208 can be formed by depositing metal on the first surface and the second surface of the semiconductor layer 201 and performing metal annealing.
[0049] When the power semiconductor device is a metal oxide semiconductor field effect transistor, the output region electrode layer 208 is used as a drain, and the input region electrode layer 207 is used as a source. When the power semiconductor device is an insulated gate bipolar transistor, the output region electrode layer 208 is used as a collector, and the input region electrode layer 207 is used as an emitter.
[0050] Corresponding to the manufacturing method of the power semiconductor device provided in the above embodiments, another embodiment of the present application also provides a power semiconductor device, which is manufactured by any one of the manufacturing methods provided in the above embodiments, so that there is no lateral overlapping area between its inner gate structure and the input area, so that the cell size can be reduced and the device conduction performance can be improved.
[0051] Figure 3u The figure shows a cell of a power semiconductor device provided in an embodiment of the present application. Figure 3u , the size L2 of the cell 200 is expressed based on the formula (2) shown below. Comparing formula (1) and formula (2), when the four parameters Lohmic, Lgs, Lch and Ljfet have the same values, Figure 3u The size L2 of the cell 200 shown is smaller than Figure 1 The size of the cell 100 shown is L1, so the power semiconductor device constructed by the cell 200 has better conduction performance.
[0052] L2=Lohmic+Lgs×2+Lch×2+Ljfet(2)
[0053] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.
Claims
1. A method for manufacturing a power semiconductor device, comprising: providing a semiconductor layer of a first doping type; forming a body region of a second doping type in the semiconductor layer, the second doping type being different from the first doping type; forming a first mask layer on the first surface of the semiconductor layer, wherein the opening position of the first mask layer corresponds to the position of the input region in the body region; forming the input region of the first doping type using the first mask layer; removing a portion of the first mask layer outside a region where a gate structure is to be formed, wherein a side wall of the region where a gate structure is to be formed is aligned with a target side wall of the input region; forming a second mask layer, wherein the second mask layer covers other regions except the first surface region of the semiconductor layer covered by the first mask layer; removing the first mask layer to form an opening position of the second mask layer; as well as The gate structure is formed at the opening position of the second mask layer.
2. The manufacturing method according to claim 1, wherein: The first mask layer and the second mask layer are made of different materials, and removing the first mask layer includes: etching the first mask layer through a first selective etching process.
3. The manufacturing method according to claim 1, wherein: The material used for the first mask layer is silicon oxide, the material used for the second mask layer is silicon nitride, the first selective etching process is wet etching and the etchant used is hydrofluoric acid or buffered oxide etching solution.
4. The manufacturing method according to claim 1, wherein: Forming a body region of a second doping type in the semiconductor layer, comprising: forming the body region in the semiconductor layer using a third mask layer located on a first surface of the semiconductor layer; A first mask layer is formed on the first surface of the semiconductor layer, including: forming an intermediate mask layer covering the first surface of the semiconductor layer and the third mask layer, and etching back the intermediate mask layer to remove portions of the intermediate mask layer on the first surface of the semiconductor layer and on top of the third mask layer to obtain the first mask layer.
5. The manufacturing method according to claim 4, further comprising: Before forming a body region of the second doping type in the semiconductor layer, forming a body contact region of the second doping type in the semiconductor layer, the body contact region being adjacent to a first side wall of the body region to be formed later; wherein a wall of the input region formed later that is opposite to the target sidewall is adjacent to the first sidewall of the body region, a preset spacing between the target sidewall and the second sidewall of the body region is a target width, and the first sidewall and the second sidewall are a set of opposite sidewalls of the body region; The third mask layer opens over a region of the semiconductor layer where the body region is to be formed and over a region of the body contact region adjacent to the target width of the body region.
6. The manufacturing method according to claim 1, wherein: Removing a portion of the first mask layer outside a region where a gate structure is to be formed, comprising: forming a photoresist covering the first surface of the semiconductor layer and the first mask layer; Removing the portion of the photoresist covering the target portion of the first mask layer by a photolithography process to obtain a patterned photoresist, wherein the target portion is the portion of the first mask layer outside the region where the gate structure is to be formed; The patterned photoresist is used as a mask to perform a second selective etching process on the first mask layer.
7. The manufacturing method according to claim 6, wherein: The material used for the first mask layer is silicon oxide, the second selective etching process is wet etching and the etchant used is hydrofluoric acid or buffered oxide etching solution.
8. The manufacturing method according to claim 1, wherein: The gate structure is formed at the opening position of the second mask layer, comprising: forming a gate oxide layer at the opening position of the second mask layer; forming a conductive layer covering the gate oxide layer and the sidewalls of the opening of the second mask layer; filling the opening of the second mask layer where the conductive layer is formed to form a sacrificial structure; A top portion of the conductive layer is removed based on the sacrificial structure to form a gate conductor.
9. The manufacturing method according to claim 1, further comprising: An interlayer dielectric layer and an input region electrode layer are formed on the first surface of the semiconductor layer, wherein the interlayer dielectric layer covers the top and sidewalls of the gate structure, and the input region electrode layer covers the surface of the input region. 10 . A power semiconductor device, wherein the power semiconductor device is manufactured by the manufacturing method according to claim 1 .