Preparation method of semiconductor device and CMOS (Complementary Metal Oxide Semiconductor) device

Abstract

The invention provides a preparation method of a semiconductor device, and the method comprises the steps: carrying out a second ion implantation process, so as to compensate ions which penetrate through a first graphical photoresist layer and are implanted in an ion implantation damage region of a well pre-forming region covered by the first graphical photoresist layer in the first ion implantation process; in other words, the second ion implantation process can compensate the ion implantation damage area caused by the fact that the thickness of the first patterned photoresist layer is reduced and the first patterned photoresist layer is penetrated in the first ion implantation process, so that the ion implantation concentration of each well region is not affected, and the performance of the device is ensured. By adopting the preparation method disclosed by the invention, the requirement on the thickness of the photoresist layer in the deep trap ion implantation process can be effectively reduced on the premise of ensuring that the ion implantation concentration of each trap region is not influenced, and the relatively thin photoresist layer is adopted, so that the relatively poor overall appearance of the relatively thick photoresist layer after exposure can be effectively avoided; therefore, the technological process space of the photoresist layer is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a method for preparing a semiconductor device and a CMOS device. Background Art

[0002] In the semiconductor manufacturing process, multiple processes require ion implantation of semiconductor devices. The energy of ion implantation in each process is different, and ion implantation only needs to be performed at predetermined locations. Other locations need to be covered and blocked with photoresist to prevent ion implantation from affecting device performance. The thickness of photoresist is different, and the blocking ability to ion implantation is different. If the photoresist is too thin, ions can easily break through and the purpose of protection cannot be achieved; if the photoresist is too thick, it is difficult to control the overall morphology of the photoresist after exposure, resulting in undesirable phenomena such as ion implantation dose loss, which affects device performance. Therefore, it is particularly important to increase the process space of photoresist and reduce the impact on device performance.

[0003] As the device feature size decreases, the device complexity increases, and more and more ion implantations are required to complete a device doping area. Especially when performing well ion implantation, the ion implantation depth is deeper and the injection energy is also required to be higher. In order to prevent ions from being implanted into non-predetermined positions, the thickness of the photoresist is required to be higher, such as a thickness of 1.2μm to 1.6μm. However, as mentioned above, when the photoresist is thicker, due to the smaller feature size (CD, Critical Dimension) of the device, the morphology of the photoresist after exposure is poor. After ion implantation, it is easy to cause adverse phenomena such as device threshold voltage drift or isolation structure failure, resulting in reduced device performance. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for preparing a semiconductor device and a CMOS device, which is used to solve the problem that when a thicker photoresist is used for covering and blocking to achieve deeper ion implantation in the prior art, the overall morphology of the thicker photoresist is poor after exposure, and after ion implantation, it is easy to cause undesirable phenomena such as ion implantation dose loss (doselose), causing the device threshold voltage to drift or the isolation structure to fail, resulting in reduced device performance.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor device, the method comprising:

[0006] A semiconductor substrate is provided, wherein the semiconductor substrate includes two types of well pre-formation regions, and the two types of well pre-formation regions need to be subsequently subjected to different ion implantation processes to form corresponding well regions;

[0007] A first patterned photoresist layer is formed on the semiconductor substrate, wherein the first patterned photoresist layer exposes one type of the well pre-formation area and covers another type of the well pre-formation area or the well area; when the other type of the well pre-formation area has not been subjected to an ion implantation process to form a well area, the area covered by the first patterned photoresist layer is the well pre-formation area; when the other type of the well pre-formation area has been subjected to an ion implantation process to form a well area, the area covered by the first patterned photoresist layer is the well area;

[0008] Performing a first ion implantation process on the semiconductor substrate to form a well region in the exposed well pre-formation region, and the first ion implantation process simultaneously penetrates the first patterned photoresist layer to form an ion implantation damaged region in the well pre-formation region or the well region covered by the first patterned photoresist layer;

[0009] Before or after the above-mentioned first ion implantation process, a second ion implantation process is performed on the well pre-formation area or the well area covered by the first patterned photoresist layer to compensate for the ions implanted into the ion implantation damaged area of ​​the well pre-formation area or the well area covered by the first patterned photoresist layer during the first ion implantation process.

[0010] Optionally, the ion implantation type of the second ion implantation process is opposite to the ion implantation type of the corresponding compensated ion implantation damaged area.

[0011] Furthermore, the ion implantation type of the second ion implantation process is N-type ions or P-type ions, and the ions implanted into the ion implantation damaged area are N-type ions or P-type ions.

[0012] Furthermore, the N-type ions include phosphorus ions, and the P-type ions include boron ions.

[0013] Optionally, the thinner the thickness of the first patterned photoresist layer is, the greater the ion implantation dose of the second ion implantation process is.

[0014] Furthermore, the thinner the thickness of the first patterned photoresist layer is, the greater the ion implantation energy of the second ion implantation process is.

[0015] Optionally, the semiconductor device is a CMOS device, and the two types of well pre-formation regions are respectively a P-well pre-formation region of an NMOS device and an N-well pre-formation region of a PMOS device; or the semiconductor device is a semiconductor device including a deep well isolation structure, the deep well isolation structure includes two first well regions and one second well region, and the two first well regions are formed in one type of the well pre-formation regions, and the one second well region is formed in another type of the well pre-formation regions.

[0016] Furthermore, when the semiconductor device is a CMOS device, the ion implantation energy of the second ion implantation process is 1 KeV to 150 KeV, including end points.

[0017] Furthermore, the ion implantation dose of the second ion implantation process is 1E11 atom / cm 2 ~1E14atom / cm 2 , including the endpoint values.

[0018] Optionally, performing the second ion implantation process includes: removing the first patterned photoresist layer; forming a second patterned photoresist layer on the semiconductor substrate, the second patterned photoresist layer exposing the well pre-formation area where the ion implantation damage area is located and covering the well area; performing the second ion implantation process on the semiconductor substrate, and the second ion implantation process does not penetrate the second patterned photoresist layer.

[0019] The present invention also provides a method for preparing a CMOS device, the method comprising:

[0020] A semiconductor substrate is provided, wherein the semiconductor substrate includes two types of well pre-formation regions, and the two types of well pre-formation regions need to be subsequently subjected to different ion implantation processes to form corresponding well regions;

[0021] Forming a first patterned photoresist layer on the semiconductor, wherein the first patterned photoresist layer exposes one type of the well pre-formation region and covers another type of the well pre-formation region;

[0022] Performing a first ion implantation process on the semiconductor substrate to form a second well region in the well pre-formation region exposed by the first patterned photoresist layer, and at the same time, the first ion implantation process penetrates the first patterned photoresist layer to form a first ion implantation damaged region in the well pre-formation region covered by the first patterned photoresist layer;

[0023] Performing a second ion implantation process on the semiconductor substrate based on the first patterned photoresist layer, and the second ion implantation process does not penetrate the first patterned photoresist layer, thereby forming a second compensation at a preset depth of the second well region;

[0024] removing the first patterned photoresist layer;

[0025] forming a second patterned photoresist layer on the semiconductor, wherein the second patterned photoresist layer exposes another type of the well pre-formation region and covers the second well region;

[0026] Performing a third ion implantation process on the semiconductor substrate to form a first well region in the well pre-formation region exposed by the second patterned photoresist layer, and at the same time, the third ion implantation process penetrates the second patterned photoresist layer to form a second ion implantation damaged region in the second well region covered by the second patterned photoresist layer, wherein the ions implanted in the second ion implantation damaged region generate a neutralization compensation with the second compensation;

[0027] A fourth ion implantation process is performed on the semiconductor substrate based on the second patterned photoresist layer, and the fourth ion implantation process does not penetrate the second patterned photoresist layer, thereby forming a first compensation at a preset depth of the first well region, and the first compensation is neutralized with the ions injected into the first ion implantation damage area.

[0028] As described above, the method for preparing a semiconductor device of the present invention performs a second ion implantation process to compensate for the ions implanted in the ion implantation damage area of ​​the well pre-formation area covered by the first patterned photoresist layer during the first ion implantation process, that is, the second ion implantation process can compensate and neutralize the ion implantation damage area caused by the first ion implantation process penetrating the first patterned photoresist layer due to the thinning of the first patterned photoresist layer, so that the net doping concentration of the ions implanted in each well area is not affected, and the device performance is guaranteed. Therefore, the preparation method of the present invention can effectively reduce the requirements for the thickness of the photoresist layer in the deep well ion implantation process while ensuring that the net doping ion implantation concentration of each well area is not affected. The use of a relatively thin photoresist layer can effectively avoid the poor overall morphology of the thicker photoresist layer after exposure, resulting in the loss of ion implantation dose and other undesirable phenomena, so that the process space of the photoresist layer can be improved, the process difficulty can be reduced, and the device performance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 8 It is a schematic cross-sectional structure diagram of each step in the preparation process of a semiconductor device including a deep well isolation structure according to the first embodiment of the present invention.

[0030] Fig. 9 Shown is a voltage / current relationship curve diagram of a deep well isolation structure in a semiconductor device including a deep well isolation structure according to the first embodiment of the present invention; wherein curve 1 represents a voltage / current relationship curve of the deep well isolation structure obtained when the phosphorus ions in the N-type well region do not penetrate the photoresist layer and do not enter the P-type well region, and curve 2 represents a voltage / current relationship curve of the deep well isolation structure obtained when the phosphorus ions in the N-type well region penetrate the photoresist layer and enter the P-type well region.

[0031] Fig.10 The voltage / current relationship curve of the deep well isolation structure in the semiconductor device including the deep well isolation structure according to the first embodiment of the present invention is shown. Fig. 9Curve 3 is added to the curve graph, and Curve 3 represents the voltage / current relationship curve of the deep well isolation structure obtained when phosphorus ions in the N-type well region penetrate the photoresist layer into the P-type well region and boron ions are added to compensate in the P-type well region.

[0032] Figures 11 to 17 It is a schematic diagram of the cross-sectional structure of each step in the preparation process of the CMOS device according to the second embodiment of the present invention.

[0033] Fig.18 Shown is a graph of the relationship between the depth of ion implantation and doping concentration in the P-type well region before annealing in the CMOS device of the second embodiment of the present invention; wherein, curve 1 represents the relationship between the depth of boron ion implantation and doping concentration in the P-well obtained when the boron ions in the N-type well region do not penetrate the photoresist layer and do not enter the P-type well region during injection, and curve 2 represents the relationship between the depth of boron ion implantation and doping concentration in the P-well obtained when the boron ions in the N-type well region penetrate the photoresist layer and enter the P-type well region during injection.

[0034] Fig.19 Display as Fig.18 A depth / doping concentration relationship curve of boron ion implantation in a P-type well region of a CMOS device after annealing.

[0035] Fig. 20 The graph shows the relationship between the depth of ion implantation and the doping concentration in the P-type well region before annealing in the CMOS device of the second embodiment of the present invention. Fig.18 Curve 3 is added on the basis of the curve graph, and Curve 3 represents the relationship curve of the implantation depth / doping concentration of the compensated phosphorus ions when phosphorus ion compensation is added in the P-type well region.

[0036] Fig.21 Display as Fig. 20 A depth / net doping concentration relationship curve of net ion implantation after annealing in a P-type well region in a CMOS device; wherein, curve 1 represents the depth / net doping concentration relationship curve obtained when the boron ions in the N-type well region do not penetrate the photoresist layer and do not enter the P-type well region during implantation, curve 2 represents the depth / net doping concentration relationship curve obtained when the boron ions in the N-type well region penetrate the photoresist layer and enter the P-type well region during implantation, and curve 3 represents the depth / net doping concentration relationship curve obtained when the boron ions in the N-type well region penetrate the photoresist layer and enter the P-type well region during implantation and phosphorus ions are added in the P-type well region for compensation.

[0037] Component number description

[0038] 10 Semiconductor substrate

[0039] 100 Well pre-formation area

[0040] 11 Deep well isolation structure

[0041] 12 Shallow Trench Isolation

[0042] 13 First patterned photoresist layer

[0043] 130 Window

[0044] 14 Second patterned photoresist layer

[0045] 140 Window

[0046] 15 Ion implantation damage area

[0047] 150 Compensation

[0048] 151 First ion implantation damage area

[0049] 152 Second ion implantation damage area

[0050] 153 First Compensation

[0051] 154 Second Compensation

[0052] 160 N-type heavily doped region

[0053] 161 P-type heavily doped region

[0054] 17 Well region

[0055] 170 N-type well region

[0056] 171 P-type well region

[0057] 18 CMOS devices

[0058] 19 Source / Drain Region

[0059] 20 Gate

[0060] 21 Gate sidewall DETAILED DESCRIPTION

[0061] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0062] See also Figures 1 to 21It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0063] This embodiment provides a method for preparing a semiconductor device, the method comprising:

[0064] A semiconductor substrate is provided, wherein the semiconductor substrate includes two types of well pre-formation regions, and the two types of well pre-formation regions need to be subsequently subjected to different ion implantation processes to form corresponding well regions;

[0065] A first patterned photoresist layer is formed on the semiconductor substrate, wherein the first patterned photoresist layer exposes one type of the well pre-formation area and covers another type of the well pre-formation area or the well area; when the other type of the well pre-formation area has not undergone an ion implantation process to form a well area, the area covered by the first patterned photoresist layer is the well pre-formation area; when the other type of the well pre-formation area has undergone an ion implantation process to form a well area, the area covered by the first patterned photoresist layer is the well area; that is, when the first ion implantation process is subsequently performed, the area covered by the first patterned photoresist layer may have been formed into a well area through the ion implantation process, so when the first ion implantation process is subsequently performed, the ion implantation damage area is formed in the well area; it is also possible that when the first ion implantation process is subsequently performed, the area covered by the first patterned photoresist layer has not yet undergone an ion implantation process to form a well area, so when the first ion implantation process is subsequently performed, the ion implantation damage area is formed in the well pre-formation area;

[0066] Performing a first ion implantation process on the semiconductor substrate to form a well region in the exposed well pre-formation region, and the first ion implantation process simultaneously penetrates the first patterned photoresist layer to form an ion implantation damaged region in the well pre-formation region or the well region covered by the first patterned photoresist layer;

[0067] Before or after the above-mentioned first ion implantation process, a second ion implantation process is performed on the well pre-formation area or the well area covered by the first patterned photoresist layer to compensate for the ions implanted into the ion implantation damaged area of ​​the well pre-formation area or the well area covered by the first patterned photoresist layer during the first ion implantation process.

[0068] The method for preparing the semiconductor device of the present embodiment performs a second ion implantation process to compensate for the ions injected into the ion implantation damaged area of ​​the well pre-formed area covered by the first patterned photoresist layer during the first ion implantation process. That is, the second ion implantation process can compensate and neutralize the ion implantation damaged area caused by the first ion implantation process penetrating the first patterned photoresist layer due to the thinning of the first patterned photoresist layer, so that the net doping concentration of the ions implanted in each well area is not affected, thereby ensuring the performance of the device. Therefore, the preparation method of the present embodiment can effectively reduce the requirements for the thickness of the photoresist layer during the deep well ion implantation process while ensuring that the net doping ion implantation concentration of each well area is not affected. The use of a relatively thin photoresist layer can effectively avoid the poor overall morphology of a thicker photoresist layer after exposure, resulting in the loss of ion implantation dose and other undesirable phenomena, thereby increasing the process space of the photoresist layer, reducing the process difficulty, and improving the device performance. For example, for the same deep well ion implantation, the preparation method of the present embodiment can reduce the thickness of the photoresist. about.

[0069] Generally speaking, the type of ions injected in the second ion implantation process is opposite to the type of ions injected into the corresponding compensated ion implantation damaged area. For example, when the type of ions injected in the second ion implantation process is N-type ions, the type of ions injected into the corresponding compensated ion implantation damaged area is P-type ions; when the type of ions injected in the second ion implantation process is P-type ions, the type of ions injected into the corresponding compensated ion implantation damaged area is N-type ions. Commonly used N-type ions are P (phosphorus) or As (arsenic), and commonly used P-type ions are B (boron) or BF 2 (boron fluoride).

[0070] As a preferred example, the thinner the thickness of the first patterned photoresist layer, the greater the ion implantation dose in the second ion implantation process. This is mainly because the thinner the thickness of the photoresist layer, the worse the blocking ability to ion implantation, so that the ion concentration of the formed ion implantation damaged area is greater, and correspondingly, a larger implantation dose is required in the second ion implantation process to achieve better compensation effect.

[0071] As another preferred example, the thinner the thickness of the first patterned photoresist layer, the greater the ion implantation energy of the second ion implantation process. This is mainly because the thinner the thickness of the photoresist layer, the worse the blocking ability to ion implantation, so that the depth of the formed ion implantation damage area is deeper. Correspondingly, in the second ion implantation process, a larger ion implantation energy is used to effectively reach the depth of the ion implantation damage area, thereby achieving an effective compensation effect.

[0072] As another preferred example, performing a second ion implantation process includes: first removing the first patterned photoresist layer; then forming a second patterned photoresist layer on the semiconductor substrate, and the second patterned photoresist layer exposes the well pre-formation area where the ion implantation damage area is located and covers the formed well area; then performing a second ion implantation process on the semiconductor substrate, and the second ion implantation process does not penetrate the second patterned photoresist layer. This is because the purpose of the second ion implantation process is to compensate for the ions injected into the ion implantation damage area caused when the well area was formed. Since they have passed through most of the blocking effect of the first patterned photoresist layer, the ion depth of the ion implantation damage area is very shallow relative to the depth of the well area. Therefore, when performing the second ion implantation process, the second patterned photoresist layer can play a good blocking role and is not penetrated.

[0073] The preparation method of this embodiment and the beneficial effects that can be achieved are described in detail below with reference to a specific semiconductor device example.

[0074] Embodiment 1

[0075] The semiconductor device in this embodiment is a semiconductor device including a deep well isolation structure. In existing semiconductor devices, different device regions are usually arranged and isolated from each other by including a deep well isolation structure, and the isolation region is formed by ion implantation. Figure 7 As shown, a deep well isolation structure 11 is formed by performing deep well ion implantation in the substrate 10 to form a deep well structure with different doping types, such as Figure 7 The two well regions 17 on the left are P-type well regions, and the well region 17 on the right is an N-type well region. Well regions of different conductivity types need to be formed by ion implantation respectively, and because the implantation depth of the well region is deep, a very thick photoresist layer is required as a mask barrier layer in the prior art. However, when the photoresist layer is thick, the morphology will become very poor after exposure and patterning (generally, the pattern window will be a trapezoidal shape with a large top and a small bottom), and the area to be ion implanted cannot be completely exposed, thereby causing adverse phenomena such as doselose after ion implantation. In this embodiment, especially when the N-type well region is formed by ion implantation, the injected ions easily penetrate the photoresist layer and enter the P-type well region, forming an ion implantation damage region in the P-type well region.

[0076] like Fig. 9As shown, a voltage / current relationship curve diagram of an example deep well isolation structure is shown, wherein curve 1 represents the voltage / current relationship curve of the deep well isolation structure obtained when the phosphorus ions do not penetrate the photoresist layer and enter the P-type well region when the N-type well region is formed by ion implantation, and this curve can be used as a comparison benchmark; curve 2 represents the voltage / current relationship curve of the deep well isolation structure obtained when the phosphorus ions penetrate the photoresist layer and enter the P-type well region when the N-type well region is formed by ion implantation, that is, an ion implantation damage region is generated in the P-type well region. By comparing curves 1 and 2, it can be seen that after the ion implantation damage region is generated, the breakdown voltage BV of the deep well isolation structure is reduced from 8.8V to 8.4V (the breakdown voltage is generally defined as the voltage value when the current reaches 1e-07A), that is, the withstand voltage value of the deep well isolation structure is reduced by 0.4V.

[0077] Based on this, the preparation method of this embodiment includes the following steps:

[0078] like Figure 1 As shown, step S1 is first performed to provide a semiconductor substrate 10, wherein the semiconductor substrate 10 includes two types of well pre-formation regions 100. The two types of well pre-formation regions 100 are subsequently subjected to different ion implantation processes to form corresponding well regions. For example, the two well pre-formation regions 100 on the left are subsequently formed into P-type well regions by ion implantation, and the well pre-formation region 100 on the right is subsequently formed into an N-type well region by ion implantation.

[0079] As an example, a shallow trench isolation 12 may be formed between two adjacent well pre-forming regions 100 , and the specific preparation process may adopt existing conventional processes, and no excessive limitation is made here.

[0080] like Figure 2 As shown, step S2 is then performed to form a first patterned photoresist layer 13 having a window 130 on the semiconductor substrate 10 , wherein the first patterned photoresist layer 13 exposes the well pre-forming region 100 on the right and covers the well pre-forming region 100 on the left.

[0081] In this step, the thickness of the first patterned photoresist layer 13 can be coated relatively thinly compared to the prior art to ensure that a first patterned photoresist layer 13 with better morphology can be obtained when the photoresist layer is exposed and patterned after coating. Therefore, in this step, the thickness selection window of the photoresist layer is larger.

[0082] like Figure 3As shown, step S3 is then performed to perform a first ion implantation process on the semiconductor substrate 10 to form a well region 17 in the exposed right side well pre-formation region 100. Here, the well region 17 is selected as an N-type well region. At the same time, the first ion implantation process penetrates the first patterned photoresist layer 13 to form an ion implantation damage region 15 in the well pre-formation region 100 covered by the first patterned photoresist layer 13 on the left side.

[0083] It should be noted that the depth distribution and concentration distribution of the ion implantation damaged area 15 are related to the parameters such as the type of ions implanted in the first ion implantation process, the implantation energy, the material of the semiconductor substrate 10, and the thickness of the first patterned photoresist layer 13, and no excessive restrictions are made here. However, it can be understood that since most of the energy of the ions implanted in the ion implantation damaged area 15 has been blocked by the first patterned photoresist layer 13, the implantation concentration and depth of the ion implantation damaged area 15 are definitely smaller than the implantation concentration and depth of the right well area 17; in addition, it can be understood that generally, when the ions are implanted at a deeper position to form the right well area 17, the blocking performance of the first patterned photoresist layer 13 is lower and the risk of being broken down is greater. When the depth of the ion implantation in the right well area 17 becomes shallower and shallower, the blocking performance of the first patterned photoresist layer 13 gradually improves and the risk of being broken down gradually decreases. Therefore, generally, when the ions are implanted at a deeper position to form the well area, the ion implantation damaged area 15 is formed.

[0084] As an example, after this step is completed, the first patterned photoresist layer 13 needs to be removed.

[0085] like Figure 6 As shown, step S4 is finally performed. After the above-mentioned first ion implantation process, a second ion implantation process is performed on the well pre-formation area 100 covered by the first patterned photoresist layer 13, that is, the second ion implantation process is performed on the well pre-formation area 100 on the left to form a compensation 150. The compensation 150 is used to compensate for the ions implanted during the first ion implantation process that penetrate the first patterned photoresist layer 13 in the ion implantation damage area 15 of the well pre-formation area 100 covered by it, as shown in FIG. Figure 6 In the ion implantation damaged area 15, a compensation 150 is formed by the second ion implantation process, and the two offset each other, so that the net ion doping concentration here is basically not affected, thereby achieving the purpose of not affecting the breakdown voltage of the isolation structure.

[0086] As an example, performing the second ion implantation process includes: Figure 4 As shown, a second photoresist layer is first formed on the semiconductor substrate 10 and patterned to obtain a second patterned photoresist layer 14, wherein the second patterned photoresist layer 14 exposes the two well pre-formed regions 100 on the left and covers the well region 17 on the right; Figure 6 As shown, the second ion implantation process is then performed. As described above, since the depth of the ion implantation damaged area 15 is generally shallow, the second patterned photoresist layer 14 can generally play a good blocking role and prevent it from being penetrated.

[0087] As an example, Figure 5 As shown, after forming the second patterned photoresist layer 14, ion implantation can be performed on the two well pre-formation regions 100 on the left to form two well regions 17. In this embodiment, the two well regions 17 are selected to be P-type well regions. The ion implantation process of this step has a much greater implantation depth and concentration than the second ion implantation process. Figure 7 As shown, after removing the second patterned photoresist layer 14, a deep well isolation structure 11 is obtained, in which the ion implantation damaged area 15 in the two well regions 17 on the left is compensated by the compensation 150, so the ion implantation parameters in the two well regions 17 on the left will not be affected.

[0088] As an example, Figure 8 As shown, after forming the deep well isolation structure 11, the step of forming heavily doped regions on the three well regions 17 is also included. Figure 8 In the figure, from left to right, the two well regions on the left are P-type well regions 171, and the well region on the right is N-type well region 170; a P-type heavily doped region 161 is formed on the first P-type well region 171 on the left, an N-type heavily doped region 160 is formed on the second P-type well region 171 in the middle, and an N-type heavily doped region 160 is formed on the N-type well region 170 on the right.

[0089] like Fig.10 FIG. 1 shows a voltage / current relationship curve of a deep well isolation structure obtained by the preparation method of this embodiment, and FIG. Fig. 9 The two curves are compared, wherein Curve 3 represents the voltage / current relationship curve of the deep well isolation structure obtained when the phosphorus ions injected in the N-type well region penetrate the photoresist layer and enter the P-type well region and the boron ions are added to the P-type well region for compensation. By comparing Curve 1, Curve 2 and Curve 3, it can be seen that Curve 3 is basically coincident with Curve 1, that is, the preparation method of this embodiment effectively improves the breakdown voltage BV of the deep well isolation structure, and at the same time, it can also increase the process space of the thickness of the photoresist layer during ion implantation.

[0090] Of course, the deep well isolation structure in the semiconductor device including the deep well isolation structure shown in this embodiment is as follows: Figure 7 From left to right in the figure are the arrangement of P-type well region, P-type well region and N-type well region, that is, the arrangement of PPN. Figure 7The directional sequence can also be an arrangement of N-type well region, N-type well region and P-type well region, that is, an arrangement of NNP, or an arrangement of NPN, PNP, etc., as long as well regions of the same doping type are formed in one type of well pre-formation region, and well regions of another doping type are formed in another type of well pre-formation region.

[0091] Embodiment 2

[0092] The semiconductor device in this embodiment is a CMOS device. The CMOS device generally includes an NMOS device and a PMOS device. The NMOS device is formed in a P-type well region, and the PMOS device is formed in an N-type well region. The P-type well region and the N-type well region are deep well regions. Therefore, at the beginning of device preparation, it is necessary to prepare the P-type well region and the N-type well region based on the photoresist layer as a mask for ion implantation.

[0093] This embodiment focuses on the preparation process of the P-type well region and the N-type well region in the CMOS device, including the following steps:

[0094] like Fig.11 As shown, step S1 is first performed to provide a semiconductor substrate 10, wherein the semiconductor substrate 10 includes two types of well pre-formation regions 100, one of which is subsequently formed into a P-type well region after ion implantation, and the other is subsequently formed into an N-type well region after ion implantation.

[0095] As an example, a shallow trench isolation 12 may be formed between two adjacent well pre-forming regions 100 , and the specific preparation process may adopt existing conventional processes, and no excessive limitation is made here.

[0096] like Fig.12 As shown, step S2 is then performed to form a first patterned photoresist layer 13 having a window 130 on the semiconductor substrate 10, wherein the first patterned photoresist layer 13 exposes (through the window 130) the well pre-formation region 100 on the left and covers the well pre-formation region 100 on the right.

[0097] In this step, the thickness of the first patterned photoresist layer 13 can be coated relatively thinly compared to the prior art to ensure that a first patterned photoresist layer 13 with better morphology can be obtained when the photoresist layer is exposed and patterned after coating. Therefore, in this step, the thickness selection window of the photoresist layer is larger.

[0098] like Fig.12As shown, step S3 is then performed to perform a first ion implantation process on the semiconductor substrate 10 to form a well region 17 in the exposed left well pre-formation region 100. Here, the well region 17 is selected as a P-type well region, and an NMOS device is subsequently formed in the P-type well region. At the same time, the first ion implantation process penetrates the first patterned photoresist layer 13 to form a first ion implantation damage area 151 in the well pre-formation region 100 on the right covered by it.

[0099] It should be noted that the depth distribution and concentration distribution of the first ion implantation damaged area 151 are related to the type of ions implanted in the first ion implantation process, the implantation energy, the material of the semiconductor substrate 10, and the thickness of the first patterned photoresist layer 13, and are not overly limited here. However, it can be understood that since most of the energy of the ions implanted in the first ion implantation damaged area 151 has been blocked by the first patterned photoresist layer 13, the implantation concentration and depth of the first ion implantation damaged area 151 are definitely smaller than the implantation concentration and depth of the left well area 17.

[0100] like Fig.13 As shown, step S4 is then performed to perform a second ion implantation process on the semiconductor substrate based on the first patterned photoresist layer 13, and the second ion implantation process does not penetrate the first patterned photoresist layer 13, thereby forming a second compensation 154 at a preset depth of the well region 17 on the left.

[0101] The depth and concentration distribution of the second compensation 154 are set according to the depth and concentration of the second ion implantation damage area formed subsequently. As a specific example, the ion implantation energy of the second ion implantation process can be 1Kev to 150Kev, including end values, such as 1Kev, 10Kev, 30Kev, 50Kev, 70Kev, 90Kev, 110Kev, 120Kev, 150Kev, etc. On this basis, the ion implantation dose of the second ion implantation process can be 1E11atom / cm 2 ~1E14atom / cm 2 , including the endpoint value, for example, 1E11 atoms / cm 2 、5E11 atom / cm 2 、7E11 atom / cm 2 、2E12atom / cm 2 、3E12 atom / cm 2 、5E12 atom / cm 2 、7E12 atom / cm 2 、9E12 atom / cm 2 、1E13 atom / cm2 、2E13 atom / cm 2 、3E13 atom / cm 2 、7E13 atom / cm 2 、9E13 atom / cm 2 , 1E14 atom / cm 2 etc.

[0102] As an example, after this step is completed, the first patterned photoresist layer 13 needs to be removed.

[0103] like Fig.14 As shown, step S5 is then performed to form a second patterned photoresist layer 14 having a window 140 on the semiconductor substrate 10. The second patterned photoresist layer 14 exposes (through the window 140) the well pre-formation region 100 on the right and covers the well region 17 on the left.

[0104] In this step, the thickness of the second patterned photoresist layer 14 can be coated relatively thinly compared to the prior art to ensure that a second patterned photoresist layer 14 with better morphology can be obtained when the photoresist layer is exposed and patterned after coating. Therefore, in this step, the thickness selection window of the photoresist layer is larger.

[0105] like Fig.14 As shown, step S6 is then performed to perform a third ion implantation process on the semiconductor substrate 10 to form a well region 17 in the exposed right well pre-formation region 100. Here, the well region 17 is selected as an N-type well region, and a PMOS device is subsequently formed in the N-type well region. At the same time, the third ion implantation process penetrates the second patterned photoresist layer 14 to form a second ion implantation damage area 152 in the well region 17 on the left side covered by it. The second ion implantation damage area 152 is just neutralized and compensated by the second compensation 154 preset in the previous step S4.

[0106] like Fig.15 As shown, step S7 is then performed to perform a fourth ion implantation process on the semiconductor substrate based on the second patterned photoresist layer 14, and the fourth ion implantation process does not penetrate the second patterned photoresist layer 14, thereby forming a first compensation 153 at a preset depth of the well region 17 on the right, and the first compensation 153 can just compensate for the first ion implantation damage area 151 formed in the previous step S3. Thus, as Fig.16 As shown, after removing the second patterned photoresist layer 14, the formed P-type well region 171 and the N-type well region 170 will not produce a change in the net doping ion implantation concentration.

[0107] As a specific example, the ion implantation energy of the fourth ion implantation process can be 1Kev to 150Kev, including endpoint values, such as 1Kev, 10Kev, 30Kev, 50Kev, 70Kev, 90Kev, 110Kev, 120Kev, 150Kev, etc. On this basis, the ion implantation dose of the fourth ion implantation process can be 1E11atom / cm 2 ~1E14atom / cm 2 , including the endpoint value, for example, 1E11 atoms / cm 2 、5E11 atom / cm 2 、7E11 atom / cm 2 , 2E12 atom / cm 2 、3E12 atom / cm 2 、5E12 atom / cm 2 、7E12 atom / cm 2 、9E12 atom / cm 2 , 1E13 atom / cm 2 、2E13atom / cm 2 、3E13 atom / cm 2 、7E13 atom / cm 2 、9E13 atom / cm 2 , 1E14 atom / cm 2 etc.

[0108] like Fig.17 As shown, after forming the P-type well region 171 and the N-type well region 170 , other conventional processes for forming a MOS tube structure are also included, such as the process of forming source / drain regions 19 , gate sidewalls 21 and gate 20 .

[0109] like Figures 18 to 21 , which is a curve diagram of the simulation effect of the MOS device obtained by using the compensation preparation method of this embodiment and the MOS device obtained by not using the compensation preparation method of this embodiment using TCAD simulation software, wherein the main simulation is the relationship curve diagram of the depth / doping concentration of the ion implantation in the P-type well region finally obtained when the boron ions injected during the formation of the N-type well region penetrate the photoresist layer and enter the P-type well region and do not penetrate the photoresist layer and enter the P-type well region. Fig.18 and Fig.19The graphs are respectively the relationship curves of the depth / doping concentration of the boron ion implantation in the P-type well region before annealing and after annealing, wherein Curve 1 represents the relationship curve of the boron ion implantation depth / doping concentration in the P-type well region obtained when the boron ions in the N-type well region do not penetrate the photoresist layer and do not enter the P-type well region during the implantation, and this curve can be used as a comparison benchmark; Curve 2 represents the relationship curve of the boron ion implantation depth / doping concentration in the P-type well region obtained when the boron ions in the N-type well region penetrate the photoresist layer and enter the P-type well region during the implantation, that is, an ion implantation damage zone is generated in the P-type well region. By comparing Curve 1 and Curve 2, it can be seen that, whether before or after annealing, the boron ion concentration in the P-type well region in Curve 2 has obvious fluctuations within the depth range of about 0.05μm to 0.17μm, and the boron ion concentration is relatively higher than that in Curve 1, which is mainly because an obvious ion implantation damage zone is generated in this area. Fig. 20 In the figure, curve 3 is added, that is, the compensation method of this embodiment is adopted, and curve 3 represents the depth / doping concentration relationship curve of phosphorus ion compensation when an ion implantation damage area is generated in curve 2 and phosphorus ion compensation is added to the ion implantation damage area. Fig. 20 After the middle curve 3 compensates for the ion implantation damage area of ​​the P-type well region, we get Fig.21 Curve 3 in the figure shows Fig.21 Curve 3 represents the depth / net doping concentration relationship curve obtained when the boron ions in the N-type well region penetrate the photoresist layer and enter the P-type well region during injection and phosphorus ions are added to compensate in the P-type well region. Curve 1 represents the depth / net doping concentration relationship curve obtained when the boron ions in the N-type well region do not penetrate the photoresist layer and do not enter the P-type well region during injection. Curve 2 represents the depth / net doping concentration relationship curve obtained when the boron ions in the N-type well region penetrate the photoresist layer and enter the P-type well region during injection. By comparing curves 1, 2 and 3, it can be seen that curve 3 is basically coincident with curve 1, that is, the preparation method of this embodiment does not affect the net doping concentration of the P-type well region, and at the same time, the process space of the thickness of the photoresist layer during ion injection can be increased.

[0110] Of course, the CMOS device shown in this embodiment has the situation that the photoresist is punched through to form the ion implantation damaged area when preparing the ion implantation process of the N-type well region and the P-type well region, and the corresponding ion implantation damaged area is compensated twice. However, in practice, according to the different requirements of the preparation process of the N-type well region and the P-type well region, the thickness of the photoresist layer as the ion implantation barrier layer will be different, and the situation that the photoresist is punched through to form the ion implantation damaged area may only occur when forming one of the well regions. At this time, it is only necessary to compensate for the ion implantation damaged area, and there is no need to use the two compensations of this embodiment.

[0111] In summary, the present invention provides a method for preparing a semiconductor device, which performs a second ion implantation process to compensate for the ions implanted in the ion implantation damage area of ​​the well pre-formation area covered by the first patterned photoresist layer during the first ion implantation process, that is, the second ion implantation process can compensate and neutralize the ion implantation damage area caused by the first ion implantation process penetrating the first patterned photoresist layer due to the thinning of the first patterned photoresist layer, so that the net doping concentration of the ions implanted in each well area is not affected, and the device performance is guaranteed. Therefore, the preparation method of the present invention can effectively reduce the requirements for the thickness of the photoresist layer in the deep well ion implantation process while ensuring that the net doping ion implantation concentration of each well area is not affected. The use of a relatively thin photoresist layer can effectively avoid the poor overall morphology of the thicker photoresist layer after exposure, resulting in the loss of ion implantation dose and other undesirable phenomena, so that the process space of the photoresist layer can be improved, the process difficulty can be reduced, and the device performance can be improved. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0112] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor device, It is characterized in that The preparation method comprises: A semiconductor substrate is provided, wherein the semiconductor substrate includes two types of well pre-formation regions, and the two types of well pre-formation regions need to be subsequently subjected to different ion implantation processes to form corresponding well regions; A first patterned photoresist layer is formed on the semiconductor substrate, wherein the first patterned photoresist layer exposes one type of the well pre-formation area and covers another type of the well pre-formation area or the well area; when the other type of the well pre-formation area has not been subjected to an ion implantation process to form a well area, the area covered by the first patterned photoresist layer is the well pre-formation area; when the other type of the well pre-formation area has been subjected to an ion implantation process to form a well area, the area covered by the first patterned photoresist layer is the well area; Performing a first ion implantation process on the semiconductor substrate to form a well region in the exposed well pre-formation region, and the first ion implantation process simultaneously penetrates the first patterned photoresist layer to form an ion implantation damaged region in the well pre-formation region or the well region covered by the first patterned photoresist layer; Before or after the above-mentioned first ion implantation process, a second ion implantation process is performed on the well pre-formation area or the well area covered by the first patterned photoresist layer to compensate for the ions implanted into the ion implantation damaged area of ​​the well pre-formation area or the well area covered by the first patterned photoresist layer during the first ion implantation process.

2. The method for preparing a semiconductor device according to claim 1, Features: The ion implantation type of the second ion implantation process is opposite to the ion implantation type of the corresponding ion implantation damaged area to be compensated.

3. The method for preparing a semiconductor device according to claim 2, Features: The ion implantation type of the second ion implantation process is N-type ions or P-type ions, and the ions implanted into the ion implantation damaged area are N-type ions or P-type ions.

4. The method for preparing a semiconductor device according to claim 3, Features: The N-type ions include phosphorus ions, and the P-type ions include boron ions.

5. The method for preparing a semiconductor device according to claim 1, Features: The thinner the thickness of the first patterned photoresist layer is, the greater the ion implantation dose of the second ion implantation process is.

6. The method for preparing a semiconductor device according to claim 1 or 5, Features: The thinner the thickness of the first patterned photoresist layer is, the greater the ion implantation energy of the second ion implantation process is.

7. The method for preparing a semiconductor device according to claim 1, Features: The semiconductor device is a CMOS device, and the two types of well pre-formation regions are respectively a P-well pre-formation region of an NMOS device and an N-well pre-formation region of a PMOS device; or the semiconductor device is a semiconductor device including a deep well isolation structure, the deep well isolation structure includes two first well regions and one second well region, and the two first well regions are formed in one type of the well pre-formation regions, and the one second well region is formed in another type of the well pre-formation regions.

8. The method for preparing a semiconductor device according to claim 7, Features: When the semiconductor device is a CMOS device, the ion implantation energy of the second ion implantation process is 1 KeV to 150 KeV, including end values.

9. The method for preparing a semiconductor device according to claim 8, Features: The ion implantation dose of the second ion implantation process is 1E11 atom / cm 2 ~1E14 atoms / cm 2 Endpoint values ​​are included.

10. The method for preparing a semiconductor device according to claim 1, It is characterized in that Executing the second ion implantation process includes: removing the first patterned photoresist layer; forming a second patterned photoresist layer on the semiconductor substrate, wherein the second patterned photoresist layer exposes the well pre-formation area where the ion implantation damage area is located and covers the well area; executing the second ion implantation process on the semiconductor substrate, and the second ion implantation process does not penetrate the second patterned photoresist layer.

11. A method for preparing a CMOS device, It is characterized in that The preparation method comprises: A semiconductor substrate is provided, wherein the semiconductor substrate includes two types of well pre-formation regions, and the two types of well pre-formation regions need to be subsequently subjected to different ion implantation processes to form corresponding well regions; Forming a first patterned photoresist layer on the semiconductor, wherein the first patterned photoresist layer exposes one type of the well pre-formation region and covers another type of the well pre-formation region; Performing a first ion implantation process on the semiconductor substrate to form a second well region in the well pre-formation region exposed by the first patterned photoresist layer, and at the same time, the first ion implantation process penetrates the first patterned photoresist layer to form a first ion implantation damaged region in the well pre-formation region covered by the first patterned photoresist layer; Performing a second ion implantation process on the semiconductor substrate based on the first patterned photoresist layer, and the second ion implantation process does not penetrate the first patterned photoresist layer, thereby forming a second compensation at a preset depth of the second well region; removing the first patterned photoresist layer; forming a second patterned photoresist layer on the semiconductor, wherein the second patterned photoresist layer exposes another type of the well pre-formation region and covers the second well region; Performing a third ion implantation process on the semiconductor substrate to form a first well region in the well pre-formation region exposed by the second patterned photoresist layer, and at the same time, the third ion implantation process penetrates the second patterned photoresist layer to form a second ion implantation damaged region in the second well region covered by the second patterned photoresist layer, wherein the ions implanted in the second ion implantation damaged region generate a neutralization compensation with the second compensation; A fourth ion implantation process is performed on the semiconductor substrate based on the second patterned photoresist layer, and the fourth ion implantation process does not penetrate the second patterned photoresist layer, thereby forming a first compensation at a preset depth of the first well region, and the first compensation is neutralized with the ions injected into the first ion implantation damage area.

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