Inter-integrated circuit (I2C) device with internal bus stuck recovery

Abstract

Systems and methods related to a serial communication device are provided. An example integrated circuit (IC) device includes an interface circuit coupled to a two-wire serial communication bus having a serial clock (SI) line and a serial data (SDA) bus line. The IC device further includes a bus stuck recovery circuit to monitor a local SDA fault condition at the IC device based on a plurality of clock cycles during driving the SDA bus line to a first signal state by an internal SDA signal (e.g., generated by the IC device), the clock cycles based on a clock signal received from the SCI line; and releasing the SDA bus line independent of the internal SDA signal in response to the local SDA fault condition, where the SDA bus line is in a second signal state different from the first signal state based on the releasing.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional patent application No. 17 / 957,182, filed on September 30, 2022, entitled “Inter-Integrated Circuit (I2C) Device with Internal Bus Stuck Recovery,” which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to electronic devices, and more particularly to serial communication devices (eg, inter-integrated circuit (I2C) devices). Background Art

[0004] Electronic circuits and systems can communicate with each other via a communication link called a "bus". Various bus architectures are known. In some examples, a bus can have as few as two active conductors, although it can include additional conductors for other functions. For example, an I2C bus can include two communication lines, a serial data (SDA) line and a serial clock (SCL) line.

[0005] The I2C bus can be used to provide communication between two integrated circuits (ICs), for example, two or more ICs on a printed circuit board (PCB) or ICs on different PCBs. The I2C bus can also be used as a network link between electronic systems, such as in automation or control system applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] To provide a more complete understanding of the present disclosure and its features and advantages, reference is made to the following description, taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts and wherein:

[0007] Figure 1 is a schematic diagram illustrating an exemplary serial communication system including a master device and a slave device according to some embodiments of the present disclosure, wherein the slave device includes circuitry for recovering from an internal serial data (SDA) bus stuck condition;

[0008] Figure 2 An exemplary state machine for recovering from an external bus stuck condition is shown;

[0009] Figure 3 is a schematic diagram illustrating an exemplary implementation of an internal SDA stuck recovery circuit according to some embodiments of the present disclosure;

[0010] Figure 4 is a timing diagram illustrating exemplary data communications over an Inter-Integrated Circuit (I2C) bus for a data byte write operation;

[0011] Figure 5is a timing diagram showing exemplary data communication on an I2C bus for burst writes;

[0012] Figure 6 is a timing diagram illustrating exemplary data communication on an I2C bus for a data byte read operation;

[0013] Figure 7 is a timing diagram illustrating exemplary data communication over an I2C bus for a burst read;

[0014] Figure 8 is a timing diagram illustrating an exemplary I2C bus stuck recovery scheme according to some embodiments of the present disclosure;

[0015] Fig. 9 is a flow chart illustrating an exemplary method for communicating over an I2C bus with internal SDA bus jam recovery according to some embodiments of the present disclosure; and

[0016] Fig.10 is a block diagram of an exemplary electrical device that may implement at least some of the internal SDA bus stuck recovery mechanisms discussed herein according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] Overview

[0018] The systems, methods, and devices of the present disclosure each have several innovative embodiments, no single embodiment of which is solely responsible for all of the desirable attributes disclosed herein.The details of one or more implementations of the subject matter described in this specification are set forth in the description below and the drawings.

[0019] The Inter-Integrated Circuit (I2C) bus is a high integrity, robust serial bus used for control purposes in many systems. The main components that make up the system are at least one master device and one sub-device. The master device may also be referred to as a master device, and the sub-device may also be referred to as a slave device. The master device and the sub-device may communicate with each other through a two-wire communication bus, which may be referred to as an I2C bus. The I2C bus may include a serial clock (SCL) line and a serial data (SDA) line. In order to distinguish the external SDA line between the master device and the sub-device from the internal SDA line at the sub-device (as will be discussed more fully below), the present disclosure may refer to the external SDA line as an SDA bus line. According to the I2C communication protocol (a standardized protocol used in industry), the SDA bus line is bidirectional half-duplex. That is, at a given time, the master device may send and the sub-device may receive data on the SDA bus line; or the sub-device sends and the master device receives data on the SDA bus line.

[0020] The master device can be responsible for generating a clock signal and providing the clock signal to the sub-device via the SCL line. The master device can initiate a message and define the transmission direction on the SDA bus line. That is, the sub-device may not send data unless it has been requested by the master device. For this reason, each sub-device on the I2C bus can be assigned a specific (unique) device address, and the master device can select a specific sub-device for communication by specifying the address of a specific sub-device. The communication cycle between the master device and the sub-device can start with the master device sending a start command (start condition) and end with the master device sending a stop command (stop condition). When the SCL line is high, the start condition can be defined by a high-to-low transition on the SDA bus line. The stop condition can be defined by a low-to-high transition on the SDA bus line while the SCL line is high. The communication between the start and end of the communication cycle can include the address of the sub-device communicating on the SDA bus, the register address for reading or writing, the data read, or the data to be written. In addition, for the address, register address, and data of each sub-device being communicated, there is a confirmation (ACK) sent by the corresponding receiver on the SDA bus line. The communication between the master device and the sub-device can be in bytes, where eight clock cycles are used to communicate the address, register address, or 8 bits of data of the corresponding sub-device, and one clock cycle is used for the device to respond with an ACK (e.g., from a receiver device). In the case of the last data byte of the communication, the master device can send a negative ACK (NACK) to signal that there is no additional data to be sent. In some examples, the master device uses the I2C communication protocol to read (one or more) register values ​​from the sub-device or write values ​​to (one or more) registers at the sub-device.

[0021] In order to facilitate bidirectional communication through the SDA bus line, the SDA bus line can be connected to the power rail via a pull-up resistor. That is, the pull-up resistor can be connected to the SDA bus line on one end and to the power rail on the other end. In the case where the SDA bus line is released by the master device or the sub-device, the pull-up resistor can pull up the SDA bus line voltage to the power rail. In other words, when the SDA bus line is released, the SDA bus line can be at a logic high voltage level. In this way, if any of the master device or the sub-device wants to drive the SDA bus line to a high level, the device can simply release (or "let go") the SDA bus line. Since no device can force a high level on the SDA bus, this means that the I2C bus will not encounter communication problems, where one device may attempt to transmit a logic high level while another device is transmitting a logic low level, resulting in a short circuit (e.g., connecting the power rail to ground potential).

[0022] Under normal circumstances, the master device can read data from the sub-device or write data to the sub-device through the I2C bus. However, in some cases, the I2C bus can enter a stuck (or deadlock) state (e.g., an indefinite stuck condition), wherein further communication between the master device and the sub-device is impossible. A bus stuck event can be generally referred to as an unknown state or a fault condition. A bus stuck event can be caused by a variety of reasons. As an example, a bus stuck event can be caused by the interruption of communication between the master device and the sub-device, such as in the middle of a byte transmission. As another example, a bus stuck event can be caused by a soft error, which can be caused by a series of phenomena associated with the interaction of high-energy particles (A particles, cosmic ray neutrons and muons, high-energy ions, and X-rays and y-rays), also causing the IC to enter an unknown state. In general, a sub-device can enter an unknown state for various reasons. Various techniques can be used to recover from this bus fault (or stuck condition) at the I2C bus. For example, if a sub-device has a dedicated reset pin, a hardware reset signal can be sent to the sub-device via the reset pin to reset the sub-device. If the sub-device does not have a dedicated reset pin (e.g., due to reduced pin count to reduce footprint and / or cost), the master device can send a hardware reset command (e.g., a start command and / or a stop command) to the sub-device to reset the communication port of the sub-device, followed by a soft reset to reinitialize the sub-device (i.e., a reset of the entire sub-device) so that the master device can once again communicate with the sub-device. In some instances, the sub-device can be power cycled to recover from an unknown state.

[0023] Generally, there are various techniques for I2C master devices to solve global I2C bus faults or recover from global I2C bus faults, but not for bus faults inside I2C sub-devices. However, in some cases, sub-devices may be stuck in transmit mode (or non-receiving state), wherein the internal SDA signal line at the sub-device may be stuck in (e.g., indefinitely) logic low level when such as unknown state or fault event. The internal SDA signal line may carry a signal that drives the SDA bus line to logic low or releases the SDA bus line (to logic high). When the internal SDA signal is maintained at a logic low level, the SDA bus line may be maintained at a logic low level accordingly. In this way, the sub-device may not receive any command from the master device, and a power cycle may be required to recover from the internal SDA bus stuck state.

[0024] Therefore, the present disclosure provides a technology for detecting an internal SDA bus fault for an I2C sub-device, and when detected, automatically recovers from an internal SDA bus fault without having to power cycle the I2C sub-device. According to one aspect of the present disclosure, an integrated circuit (IC) device may include an interface circuit coupled to a two-wire serial communication bus having an SCL line and an SDA bus line. In a certain aspect, the two-wire serial communication bus is an I2C bus, and the IC device is an I2C sub-device, and can be coupled to an I2C master device via an I2C bus (e.g., an external bus). In order to solve the internal SDA bus fault problem discussed above, the IC device may additionally include an internal bus stuck recovery circuit. The internal bus stuck recovery circuit can monitor the internal SDA signal on the internal SDA signal line at the IC device. The internal SDA signal can be generated by the IC device (locally or internally), and can carry data to be transmitted on the SDA bus line. The IC device may include a circuit to drive the SDA bus line to a low level or release the SDA bus line according to the internal SDA signal. For example, the SDA bus line may be driven low when the bit value to be transmitted is 0, and the SDA bus line may be released when the bit value to be transmitted is 1. The internal bus stuck recovery circuit may determine whether an internal SDA bus fault condition has occurred based on the monitoring.

[0025] As used herein, an internal SDA bus fault condition may refer to a stuck or deadlocked condition at the internal SDA signal line of a sub-device, causing the sub-device to be unable to further communicate with the corresponding master device. By observing the I2C communication protocol, there is a maximum number of continuous clock cycles (e.g., 9 clock cycles) during which the SDA bus line (and correspondingly the internal SDA signal) can be maintained at a logic low under normal operation. In this way, the internal SDA signal stays (or is stuck) at a logic low duration longer than the maximum number of continuous clock cycles, which can be used as an indication of an internal SDA bus fault. The present disclosure may interchangeably use the terms "internal SDA bus fault", "internal SDA bus fault condition", "internal SDA bus stuck condition", and "local SDA bus fault condition" to refer to a condition in which the internal SDA signal at a sub-device illegally occupies the SDA bus line (maintained at a logic low for a duration longer than a threshold number of clock cycles).

[0026] Therefore, the internal bus stuck recovery circuit can determine whether an internal SDA bus fault condition has occurred based on the number of consecutive clock cycles that the internal SDA signal remains at a logic low. In this regard, when the number of consecutive clock cycles that the internal SDA signal stays at a logic low is greater than a threshold number of cycle counts (e.g., set according to an I2C communication protocol), the internal bus stuck recovery circuit can determine that an internal SDA bus fault condition has occurred. Conversely, when the number of consecutive clock cycles that the SDA signal remains at a logic low does not exceed the threshold number of cycle counts, the internal bus stuck recovery circuit can determine that an internal SDA bus fault condition has not occurred.

[0027] If the internal bus stuck recovery circuit determines that the internal SDA bus fault condition has not occurred, the internal bus stuck recovery circuit can control the SDA bus line based on the internal SDA signal. However, if the internal bus stuck recovery circuit determines that the internal SDA bus fault condition has occurred, the internal bus stuck recovery circuit can release control of the SDA bus line. In other words, upon detecting the occurrence of the internal SDA bus fault condition, the internal bus stuck recovery circuit can release control of the SDA bus line independently of the internal SDA signal.

[0028] The systems, schemes, and mechanisms described herein advantageously enable an I2C sub-device to automatically recover from an internal SDA bus stuck condition without power cycling the sub-device. Although the present disclosure is described in the context of detection and recovery of internal SDA bus failures at a sub-device implementing the I2C communication protocol, the disclosed techniques are applicable for use with other serial communication protocols.

[0029] Figure 1 1 is a schematic diagram illustrating an exemplary serial communication system 100 including a master device 104 and a slave device 102, wherein the slave device 102 includes circuitry for recovering from an internal SDA bus stuck condition, according to some embodiments of the present disclosure. At a high level, the slave device 102 may include an internal bus stuck recovery circuit 120 to monitor an internal SDA bus fault or stuck condition at the slave device 102 and recover from the internal SDA bus fault or stuck condition when detected.

[0030] like Figure 1As shown, the sub-device 102 can be coupled to the master device 104 via a bus 108. The bus 108 can include an SCL line 107 and a bidirectional SDA bus line 109. In some aspects, the sub-device 102 can be an I2C sub-device, the master device 104 can be an I2C master device, the bus 108 can be an I2C bus, and the sub-device 102 and the master device 104 can communicate with each other through the bus 108 according to the I2C communication protocol. In some examples, each of the sub-device 102 or the master device 104 can be part of an IC device. In some examples, the master device 104 can be a microcontroller (MCU), and the sub-device 102 can be a peripheral device (e.g., a sensor, an LED driver, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a memory, an optical device, etc.). For simplicity, Figure 1 The master device 104 is shown communicating with one sub-device. However, the master device 104 can communicate with any suitable number of sub-devices 102 (e.g., 2, 3, 4, or more). In addition, each of the master device 104 and the sub-devices 102 may include other components not shown. For example, the sub-device 102 may include a register block that includes registers that can be read or written by the master device 104. In some examples, the sub-device 102 may be similar to Fig.10 Device 2400 or may be a part of device 2400.

[0031] like Figure 1 As further shown, the SCL line 107 can be connected to a power rail (e.g., Vdd) via a resistor 130, wherein the resistor 130 can be connected to the SCL line 107 at one end and to Vdd at the other end. Similarly, the SDA bus line 109 can be connected to a power rail (e.g., Vdd) via a resistor 132, wherein the resistor 132 can be connected to the SDA bus line 109 at one end and to Vdd at the other end. Resistors 130 and 132 can be referred to as pull-up resistors. In this regard, the master device 104 can trigger the clock signal 134 between logic high and logic low by releasing the SCL line 107 (so that the pull-up resistor 130 can pull the SCL line 107 to Vdd) and driving the SCL line 107 to low, respectively. In a similar manner, the master device 104 or the sub-device 102 can release the SDA bus line 109 (so that the pull-up resistor 132 can pull the SDA bus line 109 to Vdd) or drive the SCL line 107 to logic low. Generally speaking, a transmitter device may release the SDA bus line 109 to transmit a bit value of “1” or drive the SDA bus line 109 to a logic low voltage level (eg, ground) to transmit a bit value of “0.” A receiver device may release the SDA bus line 109 and let the transmitter device control the SDA bus line 109 .

[0032] like Figure 1 As further shown, the master device 104 may include a master controller 140 and a state machine circuit 150. The master controller 140 may be coupled to the bus 108. More specifically, the master controller 140 may include a driver device 142 coupled to the SCL line 107, a driver device 148 coupled to the SDA bus line 109, and a buffer 146. The driver device 142 may drive the SCL line 107 to a logic low or release the SCL line 107 (so that the pull-up resistor 130 may pull the SCL line 107 to Vdd). The master controller 140 may transmit the clock signal on the SCL line 107 to the daughter device 102 via the driver device 142. Similarly, the driver device 148 may drive the SDA bus line 109 to a logic low or release the SDA bus line 109 (so that the pull-up resistor 132 may pull the SDA bus line 109 to Vdd). The master controller 140 may transmit the data signal 137 on the SDA bus line 109 to the sub-device 102 via the driver device 148. The buffer 146 may receive the data signal 136 from the SDA bus line 109 and buffer the received data signal 136. The transmission of the signal 137 and the reception of the signal 136 may occur at different times (e.g., because the SDA bus line 109 is a bidirectional half-duplex transmission line). For simplicity, Figure 1 The circuits for clock generation, data generation, and data reception are not shown. The state machine circuit 150 may include a state machine (e.g., Figure 2 The state machine 200 of the embodiment of the present invention may be configured to detect a bus fault at the SDA bus line 109 and to resolve or recover from the bus fault, as will be discussed more fully below. A bus fault on the SDA bus line 109 may be referred to as an external bus fault.

[0033] like Figure 1As further shown, the sub-device 102 may include a sub-controller 110 (e.g., an interface circuit) and an internal bus stuck recovery circuit 120. The sub-controller 110 may be coupled to the bus 108. More specifically, the sub-controller 110 may include a buffer 112 coupled to the SCL line 107 and a buffer 114 coupled to the SDA bus line 109. The buffer 112 may receive a clock signal 134 from the SCL line 107, buffer the received clock signal 134, and provide the buffered clock signal (shown by 125) to the internal bus stuck recovery circuit 120 via a signal line 118 (shown as scl_to_chip). The buffer 114 may receive a data signal 137 from the SDA bus line 109, buffer the received data signal 137, and provide the buffered data signal to a data receiving circuit (not shown) at the sub-device 102 via a signal line 119 (shown as sda_to_chip). Although not shown, in some examples, the received clock signal 134 may also be provided to the data receiving circuit for data reception.

[0034] The sub-controller 110 may further include a transistor 116. Figure 1 Transistor 116 is illustrated as an N-type metal oxide semiconductor (NMOS) transistor, but transistor 116 can be a field effect transistor (FET), a P-type metal oxide semiconductor (PMOS) transistor, or any suitable type of device. As shown, transistor 116 is coupled between the internal bus stuck recovery circuit 120 and the SDA bus line 109. That is, the gate terminal (G) of transistor 116 is connected to the output of the internal bus stuck recovery circuit 120 via the pull-down signal line 126, the drain terminal (D) of transistor 116 is connected to the SDA bus line 109, and the source terminal (S) of transistor 116 is connected to the voltage Vss (e.g., ground potential). Transistor 116 can be turned on or off based on the gate voltage (shown by signal 128) provided on the pull-down signal line 126. Signal 128 can be output by the internal bus stuck recovery circuit 120, as will be referred to below Figure 3More fully discussed. When transistor 116 is turned on, SDA bus line 109 is pulled down (or driven) to Vss (e.g., corresponding to a logic low state). Conversely, when transistor 116 is turned off, SDA bus line 109 is released, wherein resistor 132 can pull SDA bus line 109 to Vdd (e.g., corresponding to a logic high state). In some aspects, each of driver devices 142 and 148 at master controller 140 can operate substantially the same as transistor 116. In an example, driver device 142 can include a transistor similar to transistor 116, wherein the drain of the transistor can be connected to SCL line 107, the gate of the transistor can be connected to state machine circuit 150, and the source of the transistor can be connected to Vss. Similarly, driver device 148 can include a transistor similar to transistor 116, wherein the drain of the transistor can be connected to SDA bus line 107, the gate of the transistor can be connected to state machine circuit 150, and the source of the transistor can be connected to Vss.

[0035] The internal bus stuck recovery circuit 120 can receive an internal SDA signal 124 via an internal SDA bus or signal line 122 (shown as sda_data). The internal SDA signal 124 can be generated by a data generation circuit (not shown) at the daughter device 102. In some instances, the internal SDA signal 124 may have a default state that is at a logic high (e.g., after a reset or when not transmitting). For transmission, the internal SDA signal 124 can carry data to be sent to the master device 104. In some examples, the data in the SDA signal 124 can be a value retrieved from a register of the daughter device, where the register can have an address corresponding to a register address specified by the master device 104 for the data to be read. As will be described below with reference to Figure 3 As discussed more fully, the internal bus stuck recovery circuit 120 may include logic to monitor the internal SDA signal line 122 for an internal SDA bus fault or stuck condition and to recover from the internal SDA bus fault or stuck condition when the internal SDA bus fault or stuck condition is detected.

[0036] As will be referenced below Figure 4-7More fully discussed, there is a maximum number of clock cycles (e.g., 9 clock cycles) during which the SDA bus line 109 can remain at a logic low under normal operation according to the I2C communication protocol. Therefore, the duration of the internal SDA signal (which drives the SDA bus line 109) remaining at a logic low is longer than the maximum number of consecutive clock cycles, which is an indication that an internal SDA bus fault has occurred. Therefore, the internal bus stuck recovery circuit 120 can monitor the internal SDA bus fault condition at the sub-device 102 based on the number of clock cycles during which the internal SDA signal 124 drives the internal SDA signal line 122 to a logic low (e.g., a first signal state), wherein the clock cycle can be provided by the clock signal 134. More specifically, if the number of clock cycles during which the internal SDA signal 124 drives the internal SDA signal line 122 to a logic low is less than the threshold number of clock cycle counts, the internal bus stuck recovery circuit 120 can determine that no internal SDA bus fault condition has occurred. In an example, the threshold number of clock cycle counts can be set to at least 9 based on the I2C communication protocol. In general, the threshold number of clock cycle counts may be set to any suitable value (e.g., 9, 10, 11, 12) that is greater than 8. Conversely, if the number of clock cycle counts during which the internal SDA signal 124 drives the internal SDA signal line 122 to a logic low satisfies (is greater than or equal to) the threshold number of clock cycle counts, the internal bus stuck recovery circuit 120 may determine that an internal SDA bus fault condition has occurred.

[0037] If no internal SDA bus fault is detected, the internal bus stuck recovery circuit 120 can control the SDA bus line 109 based on the internal SDA signal 124. To this end, when the internal SDA signal 124 is at a logic high, the internal bus stuck recovery circuit 120 can turn off the transistor 116, thereby allowing the resistor 132 to pull the SDA bus line 109 to Vdd (corresponding to a logic high). On the other hand, when the internal SDA signal 124 is at a logic low, the internal bus stuck recovery circuit 120 can turn on the transistor 116, thereby driving the SDA bus line 109 to Vss (corresponding to a logic low).

[0038] However, if an internal SDA bus fault is detected, the internal bus stuck recovery circuit 120 may ignore the internal SDA signal 124 and release control of the SDA bus line 109. In other words, upon detecting an internal SDA bus fault, the internal bus stuck recovery circuit 120 may release control of the SDA bus line 109 independently of the internal SDA signal 124. Releasing control of the SDA bus line 109 may refer to not pulling the SDA bus line 109 to a logic low (e.g., turning off transistor 116) and allowing the pull-up resistor 132 to pull the SDA bus line 109 to Vdd (e.g., a second signal state).

[0039] Although Figure 1 The internal bus stuck recovery circuit 120 is shown as a separate component from the sub-controller 110 , but in some examples, the internal bus stuck recovery circuit 120 may be implemented as part of the sub-controller 110 .

[0040] Figure 2 An exemplary state machine 200 for recovering from an external bus stuck condition is shown. The state machine 200 may be implemented by the master device 104. More specifically, the state machine 200 may be implemented by the state machine circuit 150 at the master device 104 after a bus stuck condition. As described above, the bus stuck condition may be caused by the master device 104 being interrupted in the middle of its communication with the slave device 102, and an external bus failure may occur at the SDA bus line 109, where the SDA bus line 109 is stuck at a logic low. Figure 2 As shown, state machine 200 may include states 202 , 204 , and 206 .

[0041] At state 202 , master device 104 may determine whether SDA bus line 109 is stuck at a logic low (eg, 0). If SDA bus line 109 is stuck at a logic low, state machine 200 may transition to state 204 .

[0042] At state 204, the master device 104 may transmit 9 clock pulses on the SCL line 107. Figure 4-7 As discussed more fully, the I2C communication protocol uses 8 clock cycles for data (e.g., 1 byte) and 1 clock cycle for ACK for each data byte communication. The transmission of 9 clock pulses by the master device 104 can be based on a worst-case scenario, where the master device 104 is interrupted after transmitting an ACK (for the previous data byte communication) to the slave device 102, and the slave device 102 is waiting to transmit 8 bits of data to the master device 104 and receive an ACK or NACK from the master device 104. After transmitting 9 clock pulses, the state machine 200 can repeat state 202.

[0043] At state 202, if the master device 104 determines that the SDA bus line 109 is not stuck at a logic low (i.e., the SDA bus line 109 is at a logic high), the state machine 200 may transition to state 206. At state 206, the master device 104 may perform a normal I2C write to issue a soft reset command to the slave device 102 so that the slave device 102 may be reinitialized. Figure 4-5 An example of an I2C write operation under normal operation is discussed.

[0044] Figure 3is a schematic diagram illustrating an exemplary implementation of an internal SDA data stuck recovery circuit 120 according to some embodiments of the present disclosure. Figure 3 The illustrated implementation is an example. In general, the internal bus stuck recovery circuit 120 may be implemented using any suitable gate and logic circuits to provide similar functionality.

[0045] like Figure 3 As shown, the internal bus stuck recovery circuit 120 may include two input ports 301 and 302 and one output port 303. The input port 302 (e.g., the first port) may be coupled to the internal SDA signal line 122 to receive the internal SDA signal 124 generated locally in the IC device 102. The input port 301 (e.g., the second port) may be coupled to the scl_to_chip signal line 118 to receive the clock signal 125 corresponding to the clock signal 134 received from the SCL line 107. The output port 303 (e.g., the third port) may be coupled to the pull-down signal line 126 to output the signal 128 (e.g., the driver control signal). As described above with reference to Figure 1 As discussed, signal 128 can drive the gate of transistor 116 to turn transistor 116 (at sub-controller 110) on or off, which in turn releases SDA bus line 109 (such that pull-up resistor 132 can pull SDA bus line 109 to Vdd corresponding to a logic high) or pulls SDA bus line 109 to a logic low, respectively.

[0046] like Figure 2 See further. Figure 3 , the internal bus stuck recovery circuit 120 may include NOT gates 310 and 312, a counter circuit 320, and a driver circuit 330. NOT gate 310 may be coupled to input port 301 to receive clock signal 125. NOT gate 312 may be coupled to input port 302 to receive internal SDA signal 124. At a high level, counter circuit 320 may count the number of consecutive clock cycles (clock cycles of clock signal 125) that the internal SDA signal 124 stays at a logic low, and may inhibit driver circuit 330 from driving SDA bus line 109 to a logic low when it is detected that the internal SDA signal 124 stays at a logic low for a duration longer than a threshold number of clock cycles (e.g., set based on an I2C communication protocol).

[0047] The counter circuit 320 may include a plurality of flip-flops 322. The flip-flops 322 are arranged in a cascade configuration, wherein the start flip-flop 322 in the cascade configuration is labeled 322a, and the last flip-flop 322 in the cascade configuration is labeled 322e). In some aspects, the number of flip-flops 322 in the counter circuit 320 may be related to a threshold number of cycle counts used to determine whether the internal SDA signal is stuck at a logic low. For example, under normal operation according to the I2C communication protocol, the SDA bus 109 cannot stay at a logic low for more than 9 clock cycles, so the number of flip-flops 322 in the illustrated example is 9.

[0048] Because the clock cycle is provided by the master device 104, Figure 3 The operation of the internal SDA data stuck recovery circuit 120 shown in FIG. 1 may assume that the master device 104 can detect a stuck state at the SDA bus 109 (global bus stuck state, as described above with reference to FIG. 1 ). Figure 2 ) In general, counter circuit 320 may include any suitable number of flip-flops 322 that is greater than the maximum number of clock cycles that the SDA bus line 109 can be held at a logic low under normal operation. However, if the number of flip-flops 322 is greater than 9, the number of SCL clocks sent by master device 104 may also be greater than 9. That is, an agreement or coordination is required between master device 104 and slave device 102 regarding how master device 104 may handle detection of a global bus stuck at SDA bus 109. In some examples, where master device 104 does not implement state machine 200 (to provide 9 additional clock cycles when the global bus is stuck), a dummy I2C write by master device 104 is performed before sending a hardware reset command to slave device 102.

[0049] As further shown, each flip-flop 322 may include a data port (denoted as D), a clock port (denoted as C), a reset port (denoted as R), and an output port (denoted as Q). For a cascade configuration, the data port of each flip-flop 322 is connected to the output port of the previous flip-flop 322, except for the start flip-flop 322a whose data port is connected to a logic high. In addition, each of the flip-flops 322 is triggered or clocked by a negative edge (e.g., a high to low transition) of the clock signal 125 (shown by scl_b_buf). As will be described below with reference to Figure 6-7 As discussed more fully, clocking the flip-flops 322 based on the negative edge of the clock is important for detecting proper operation. In addition, each flip-flop is reset when the internal SDA signal 124 is at a logic high voltage level.

[0050] The driver circuit 330 may include a NAND gate 332 and a NOT gate 334. The NAND gate 332 may include one input coupled to the internal SDA signal line 122 to receive an inverted version of the internal SDA signal 124 (shown by a bubble at the corresponding input). The NAND gate 332 may include another input coupled to the inverting output port (shown by QN) of the last flip-flop 322e. The output of the counter circuit 320 corresponding to the output from the inverting output port of the flip-flop 322e is shown by 324. The output of the NAND gate 332 may be provided to the NOT gate 334, and the output of the NOT gate 334 may be provided as the driver control signal 128 on the pull-down signal line 126.

[0051] In operation, if the internal SDA signal 124 is at a logic high, the flip-flop 322 may be reset, and the output 324 of the counter circuit 320 (or the inverted output of the last flip-flop 322e) may be at a logic high. When the internal SDA signal 124 is high and the output 324 is high, the output of the NAND gate 332 may be at a logic high. Therefore, the output of the NOT gate 334 may be at a logic low. In other words, the driver control signal 128 may be at a low level, which may turn off the transistor 116, thereby releasing the SDA bus line 109. In this way, the SDA bus line 109 may be at a logic high voltage level.

[0052] However, if the internal SDA signal 124 is at a logic low, the reset of the flip-flop 322 can be released. The logic high level at the data port of the start flip-flop 322a can be propagated to the next flip-flop 322. If the internal SDA signal 124 remains at a low level for more than 9 consecutive clock cycles, the logic high level at the data port of the start flip-flop 322a can be propagated to the data port of the last flip-flop 322e. Therefore, the output 324 (provided by the counter circuit 320) can be a logic low. In this way, the output of the NOT gate 332 can always be at a logic high independent of the internal SDA signal 124, and therefore the output of the NOT gate 334 can always be at a logic low. In other words, the driver control signal 128 can be at a logic low, which can turn off the transistor 116, thereby releasing the SDA bus line 109.

[0053] Before the logic high from the data port of the start flip-flop 322a propagates to the last flip-flop 322e, the output 324 (provided by the counter circuit 320) can remain at a logic high. In this way, the output of the NAND gate 332 can follow the internal SDA signal 124. That is, the output of the NOT gate 332 can be at a logic low, and the output of the NOT gate 334 can be at a logic high, thereby turning on the transistor 116 and causing the SDA bus line 109 to be pulled to a logic low voltage level (e.g., Vss). In this way, the output 324 can operate as a pull-down enable signal. At this point, if the internal SDA signal 124 has not been at a logic low for more than 9 consecutive cycles, the output 324 (of the counter circuit 320) can be at a logic high to enable (or allow) the SDA bus line 109 to be pulled to a logic low voltage level based on the internal SDA signal 124 being at a logic low. However, if the internal SDA signal 124 remains at logic low for more than 9 consecutive clock cycles, the output 324 (of the counter circuit 320 ) may be at logic low to inhibit (or not allow) the SDA bus line 109 to be pulled to a logic low voltage level.

[0054] In some aspects, the IC device may include an interface circuit and an I2C bus stuck recovery circuit. The IC device may correspond to the sub-device 102, the interface circuit may correspond to the sub-controller 110, and the I2C bus stuck recovery circuit may correspond to the internal bus stuck recovery circuit 120. The interface circuit may be used to connect to an I2C bus including an SCL line and an SDA bus line. The I2C bus, the SCL line, and the SDA bus line may correspond to the bus 108, the SCL line 107, and the SDA bus line 109, respectively. The I2C bus stuck recovery circuit may include: a first port (e.g., input port 302) for receiving an SDA signal (internal SDA signal) generated locally at the IC device; a second port (e.g., input port 301) coupled to the interface circuit for receiving a clock signal from the SCL line; and a third port (e.g., output port 303) for outputting a driver control signal (e.g., driver control signal 128) to the interface circuit for driving the SDA bus line. The I2C bus stuck recovery circuit may also include a first logic circuit (e.g., Figure 3 The I2C bus stuck recovery circuit may further include a second logic circuit (e.g., a driver circuit 330) to generate a pull-down enable signal (e.g., output signal 324) to selectively enable or disable the SDA bus line from being pulled to a logic low voltage level. The generation of the pull-down enable signal may be based on the number of consecutive clock cycles of the clock signal during which the internal SDA signal has a logic low. The I2C bus stuck recovery circuit may also include a second logic circuit (e.g., a driver circuit 330) to generate a driver control signal based at least in part on the pull-down enable signal.

[0055] In some aspects of the IC device, the first logic circuit can generate a pull-down-enable signal to disable pulling the SDA bus line to a logic low voltage level based on a number of consecutive clock cycles during which the internal SDA signal has a logic low that meets (is equal to or greater than) a threshold clock cycle count (e.g., set to at least 9 according to an I2C communication protocol). Conversely, the first logic circuit can generate a pull-down-enable signal to enable pulling the SDA bus line to a logic low voltage level based on a number of consecutive clock cycles during which the internal SDA signal has a logic low that is less than the threshold clock cycle count.

[0056] In some aspects, the first circuit may include a plurality of cascaded flip-flops (e.g., flip-flop 322) clocked by the negative edge of the clock signal. In addition, the cascaded flip-flops may be reset based on an internal SDA signal having a logic high at the IC device. In some aspects, the interface circuit may include a transistor (e.g., transistor 116) having a drain terminal coupled to the SDA bus line, a gate terminal coupled to the third port of the I2C bus card recovery circuit, and a source terminal coupled to a voltage rail having a voltage corresponding to a logic low voltage level.

[0057] Figures 4 to 7 Various example read / write operations between the master device 104 and the slave device 102 under normal operation are shown. Figure 4-7 In FIG. 4 , the x-axis may represent time in some arbitrary units. Additionally, SCL 402 may correspond to the clock signal 134 on the SCL line 107 , and sda_data 404 may correspond to the internal SDA signal 124 on the internal SDA signal line 122 .

[0058] Figure 4 4 is a timing diagram illustrating an exemplary data communication 400 over an I2C bus for a data byte write operation. For example, the master device 104 may write a single byte of data to a slave device over the bus 108 as shown in the data communication 400 .

[0059] like Figure 4 As shown, at time T0, master device 104 may also send a start instruction (indicated by start). As described above, a start command or start condition may be defined by a high to low transition on SDA bus line 109 while SCL line 107 is high. At time T1, the master device may send an address of sub-device 102 (indicated by sub-address) requesting communication with sub-device 102. At time T2, upon detecting the sub-address corresponding to sub-device 102, sub-device 102 may respond with an ACK by driving sda_data 404 to a logic low.

[0060] Next at time T3, master device 104 may send a register address indicating which of the registers at slave device 102 is for writing. At time T4, slave device 102 may transmit an ACK to confirm receipt of the register address by driving sda_data 404 to a logic low. Next at time T5, master device 104 may also send data for writing to the register specified by the register address. At time T6, slave device 102 may transmit an ACK to confirm receipt of the data by driving sda_data 404 to a logic low.

[0061] At time T7, the master device 104 may also end the communication 400 by sending a stop command (denoted by STOP). As described above, a stop command or stop condition may be defined by a low to high transition on the SDA bus line 109 while the SCL line 107 is high.

[0062] Figure 5 is a timing diagram showing an exemplary data communication 500 on an I2C bus for burst writes. For example, the master device 104 may write multiple bytes to the slave device via the bus 108, as shown in the data communication 500. Figure 5 As shown, data communication 500 may be similar in many respects to data communication 400, but master device 104 may send two data bytes to slave device instead of a single byte, and slave device 102 may respond to each data byte with an ACK.

[0063] Figure 6 6 is a timing diagram illustrating an exemplary data communication 600 over an I2C bus for a data byte read operation. For example, the master device 104 may read a single byte of data from a slave device over the bus 108 , as shown in the data communication 600 .

[0064] like Figure 6 As shown, at time T0, the master device 104 may send a start command (shown by start), followed by the address of the sub-device 102 at time T1 (shown by subaddress). At time T2, upon detecting the sub-address corresponding to the sub-device 102, the sub-device 102 may respond with an ACK by driving sda_data 404 to a logic low. Next, at time T3, the master device 104 may send a register address indicating which of the registers at the sub-device is used for reading. At time T4, the sub-device 102 may transmit an ACK to confirm receipt of the register address by driving sda_data 404 to a logic low.

[0065] Next, at time T5, the master device 104 may again send a start command, followed by sending the address of the slave device 102 and an indication of the read operation at time T6. At time T7, the slave device 102 may respond with an ACK by driving sda_data 404 to a logic low. Next, at time T8, the slave device 102 may send data read from the register specified by the register address. At time T9, the master device 104 may transmit a NACK to indicate that no additional data is to be transmitted. At time T10, the master device 104 may also send a stop command to end the data communication 600.

[0066] Figure 7 is a timing diagram illustrating an exemplary data communication 700 over an I2C bus for burst reads. For example, the master device 104 may read multiple bytes from the slave device over the bus 108, as shown in the data communication 700. Figure 7 As shown, data communication 700 can be similar in many respects to data communication 600, but the master device 104 can read two data bytes of data from the slave device 102 instead of a single byte, and the master device 104 can respond to each data byte with an ACK if there is more data to send, or respond to each data byte with a NACK if there is no additional data to send.

[0067] from Figure 4-7 It can be seen that the daughter device 102 can release sda_data 404 at the end of each transmitted ACK. Figure 4-5 It can be further seen that when the ACK is sent by the daughter device 102, sda_data 404 can be at logic low for at most one clock cycle. Figure 6-7 It can be further seen that the sub-device 102 can send up to 9 consecutive zero bits, where the first bit can correspond to the ACK of the previous byte (e.g., the address of the sub-device 102 and the read operation indication), and the remaining 8 bits can correspond to the data byte with all 0 bits (represented by Figure 6 602 and Figure 7 702 in FIG. 1 ). Thus, an internal SDA bus fault condition at a daughter device may be detected based on the duration or number of consecutive clock cycles that the internal SDA signal remains at a logic low.

[0068] Figure 8 800 is a timing diagram illustrating an exemplary I2C bus stuck recovery scheme 800 according to some embodiments of the present disclosure. The scheme 800 may be implemented by the master device 104 and the slave device 102. The scheme 800 may be implemented using the same scheme as described above with reference to FIG. Figure 1-7 The same mechanism discussed above applies. Figure 8 In , the x-axis can represent time in some arbitrary units.

[0069] Prior to time T0, sub-device 102 may be in the middle of a communication (eg, communication 600 or 700) with master device 104 over bus 108. At time T0, an unknown status event 802 (a fault condition) exists at sub-device 102.

[0070] At time T1, after the unknown state event 802, the internal SDA signal line 124 is triggered at a logic low, which also drives the SDA bus line 109 to a logic low. The pull-down enable signal 324 can be at a logic high, thereby allowing the internal SDA signal 124 to pull down the SDA bus line 109 (e.g., when the internal SDA signal 124 is at a logic low). At time T2, when the internal SDA signal 124 remains at a logic low for 9 consecutive clock cycles based on the clock signal on the SCL line 107, the pull-down enable signal 324 can be de-asserted (to a logic low) to prohibit the internal SDA signal 124 from pulling or driving the SDA bus line 109 to a logic low. That is, the internal SDA signal 124 can return to a logic high, ready to listen on the SDA bus line 109 (e.g., return to a receive mode). The count of 9 clock cycles is based on the negative edge of the clock signal (the high-to-low transition indicated by the downward arrow). In an example, 9 clock cycles can be counted by the master device 104 at the reference above Figure 2 The status of the discussion is provided during 204.

[0071] At time T3, the master device 104 may send a stop command (shown by 804). The stop command may end the communication interrupted by the unknown state 802. At time T4, after the stop command, the master device 104 and the slave device 102 may return to normal operation 806, where the master device 104 may again communicate with the slave device 102 (e.g., as shown in FIG. 1 ). Figures 4 to 7 shown).

[0072] from Figure 4-7 It can be seen that the internal I2C bus stuck recovery mechanism for the sub-device 102 discussed herein may not affect the normal I2C communication between the master device 104 and the sub-device 102 .

[0073] Fig. 9 1 is a flow chart illustrating an exemplary method 900 for communicating via an I2C bus with a bus jam recovery mechanism according to some embodiments of the present disclosure. The method 900 may be implemented by a sub-device in an I2C communication system, where the sub-device may be coupled to a serial communication bus including an SCL line. In one aspect, the method 900 may be implemented by Figure 1 The method 900 may be implemented by the sub-device 102, the serial communication bus may correspond to the bus 108, the SCL line may correspond to the SCL line 107, and the SDA bus line may correspond to the SDA bus line 109. In one aspect, the method 900 may be implemented by Fig.10 The method 900 can be implemented by using the device 2400 described above. Figure 1-8 Although the operation of method 900 may be described with reference to the specific embodiment of sub-device 102 disclosed herein, method 900 may be performed using any suitable hardware components and / or software components. Fig. 9 In the drawings, each operation is shown once and in a particular order, but the operations may be performed in parallel, reordered, and / or repeated as desired.

[0074] At 902 , an internal SDA signal (eg, internal SDA signal 124 ) generated at an I2C daughter device can be monitored, for example, using an internal bus jam recovery circuit.

[0075] At 904 , a determination may be made to determine whether an internal SDA fault condition has occurred at the I2C daughter device, for example, using the internal bus stuck recovery circuit 120 .

[0076] In some aspects, as part of determining whether an internal SDA fault condition has occurred, the I2C sub-device can use a counter (e.g., Figure 3 The counter circuit 320 of the internal SDA signal drives the SDA bus line to a voltage level (e.g., a logic low voltage level) indicating that the device is operating in a non-receiving state (e.g., a transmit mode) and compares the number of clock cycles to a threshold clock cycle count. The clock cycle can be based on a clock signal received on an SCL line (e.g., SCL line 107). In some aspects, counting the number of clock cycles during which the SDA signal drives the SDA bus line to a non-receiving state can be based on a negative edge (high to low transition) of the clock signal. In some aspects, the threshold clock cycle count (used to determine whether an internal SDA fault condition has occurred) can be based on the number of clock cycles used to transmit a single data byte and a corresponding acknowledgement on the SDA bus line. In some aspects, the threshold clock cycle count is at least 9.

[0077] In a further aspect, as part of determining whether the internal SDA fault condition has occurred, the I2C sub-device may determine that the internal SDA fault condition has occurred based on a number of clock cycles during which the internal SDA signal drives the SDA bus line to a voltage level (e.g., logic low) indicating that the sub-device is operating in a non-receiving state that satisfies a threshold clock cycle count. Conversely, the I2C sub-device may determine that the internal SDA fault condition has not ...

[0078] At 906, in response to determining that the internal SDA fault condition has not occurred, the SDA bus line can be controlled based on the internal SDA signal. In other words, when the internal SDA signal is at a logic high level, the SDA bus line can be released (e.g., so that the pull-up resistor can pull the SDA bus line to a power rail representing a logic high level). Conversely, when the internal SDA is at a logic low, the internal SDA can be pulled to a logic low voltage level.

[0079] In response to determining that an internal SDA fault condition has occurred, control of the SDA bus line may be released at 908. In other words, the internal SDA signal may be ignored or neglected, and the SDA bus line may be released independent of the state of the internal SDA signal (e.g., logic high or logic low).

[0080] In some aspects, the voltage level of the SDA bus line indicating the I2C sub-device operating in a non-receiving state can correspond to a logic low voltage level, and releasing control of the SDA bus line at 908 can include turning off a driver (e.g., transistor 116) that pulls the SDA bus line to the logic low voltage level.

[0081] In some aspects, after releasing control of the SDA bus line at 908, the I2C sub-device can further receive a start command from the SDA bus line and reset a counter (e.g., counter circuit 320) in response to the start command. In an example, after detecting that an internal SDA fault condition has occurred at 904, the I2C sub-device can receive 9 clock pulses (e.g., provided by a corresponding master device in communication with the sub-device) and can release the SDA bus line, as shown in FIG. Figure 8 As shown. The I2C slave device may receive (eg, from the master device) a start command for the next (normal) communication cycle. The start command may operate as a release of the port reset.

[0082] In some aspects, the I2C sub-device may receive a stop command from the SDA bus line after releasing control of the SDA bus line at 908. In some aspects, the sub-device may receive a soft reset command from the SDA bus line after releasing control of the SDA bus line at 908.

[0083] Fig.10 2400, which may include any of the sub-devices 102 having the internal bus stuck recovery circuit 120 disclosed herein, or may include one or more components that perform any of the schemes 800 and / or methods 900 disclosed herein. For example, at least some of the (multiple) devices or components of the device 2400 may include the above referenced Figure 1-9The internal bus stuck recovery circuit 120 discussed. Fig.10 2400, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the electrical device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components may be manufactured onto a single system-on-chip (SoC) die.

[0084] Furthermore, in various embodiments, the device 2400 may not include Fig.10 2400, but the device 2400 may include interface circuitry for coupling to one or more of the components illustrated in the figure. For example, the device 2400 may not include the display device 2406, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 2406 may be coupled. In another set of examples, the device 2400 may not include the audio input device 2418 or the audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which the audio input device 2418 or the audio output device 2408 may be coupled.

[0085] Device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. Processing device 2402 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices.

[0086] In some embodiments, the electrical device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. The memory 2404 may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin transfer torque magnetic random access memory (STT-MRAM).

[0087] In some embodiments, the electrical device 2400 may include a communication device 2412 (e.g., one or more communication devices). For example, the communication device 2412 may be configured to manage wireless communications for transmitting data to and from the electrical device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may transmit data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0088] The communication device 2412 can implement any of a plurality of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), Long Term Evolution (LTE) project together with any modifications, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. One or more communication chips 2412 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The one or more communication chips 2412 may operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The one or more communication chips 2412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G and beyond. In other embodiments, the communication device 2412 may operate according to other wireless protocols. The device 2400 may include an antenna 2422 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0089] In some embodiments, the communication device 2412 may use a protocol to manage wired communications. Wired communications may include electrical, optical, or any other suitable communication protocol. Examples of wired communication protocols that may be enabled by the communication device 2412 include Ethernet, controller area network (CAN), I2C, media oriented systems transport (MOST), or any other suitable wired communication protocol.

[0090] As described above, the communication device 2412 may include multiple communication devices. For example, the first communication device 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and the second communication device 2412 may be dedicated to longer-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others. In some embodiments, the first communication device 2412 may be dedicated to wireless communications, and the second communication device 2412 may be dedicated to wired communications.

[0091] Device 2400 may include battery / power circuit 2414. Battery / power circuit 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of device 2400 to an energy source separate from device 2400 (e.g., AC line power, voltage provided by a car battery, etc.).

[0092] Device 2400 may include a display device 2406 (or a corresponding interface circuit, for example, including the above-mentioned sub-controller 110 and internal bus jam recovery circuit 120). Display device 2406 may include any visual indicator, for example, a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0093] Device 2400 may include an audio output device 2408. Audio output device 2408 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0094] The device 2400 may include an audio input device 2418 (or a corresponding interface circuit, for example, including the above-mentioned sub-controller 110 and the internal bus jam recovery circuit 120). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (for example, a musical instrument with a musical instrument digital interface MIDI output).

[0095] Device 2400 may include a GPS device 2416 (or corresponding interface circuitry, e.g., including the above-described subcontroller 110 and internal bus jam recovery circuit 120). GPS device 2416 may communicate with a satellite-based system and may receive the location of device 2400, as is known in the art.

[0096] The device 2400 may include other output devices 2410 (or corresponding interface circuits, for example, including the above-mentioned sub-controller 110 and the internal bus stuck recovery circuit 120). Examples of other output devices 2410 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices. In addition, the IC device 100 discussed herein may be included in the other output devices 2410.

[0097] The device 2400 may include other input devices 2420 (or corresponding interface circuits, for example, including the above-mentioned sub-controller 110 and the internal bus jam recovery circuit 120). Examples of other input devices 2420 may include an accelerometer, a gyroscope, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, or a radio frequency identification (RFID) reader. Any suitable device among the display, input, output, communication, or memory devices described above with reference to the device 2400 may be used as Figure 1 IC device 100. Alternatively or additionally, any suitable device among the display, input, output, communication or memory devices described above with reference to device 2400 may be included in a controller or node (eg, master device 104 or sub-device 102).

[0098] Device 2400 can have any desired form factor, such as a handheld or mobile electronic device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, electrical device 2400 can be any other electronic device that processes data. Although device 2400 shows that the communication interface can utilize various components of sub-device 102 as discussed herein, IC sub-device 100 can be implemented by any suitable device for serial communication.

[0099] The following paragraphs provide various examples of the embodiments disclosed herein.

[0100] Example 1 includes a method performed by an inter-integrated circuit (I2C) sub-device coupled to a serial communication bus, the serial communication bus including a serial clock (SCL) line and a serial data (SDA) bus line, the method comprising: monitoring an internal SDA signal generated at the I2C sub-device; determining whether an internal SDA fault condition has occurred based at least in part on the monitoring; in response to determining that an internal SDA fault condition has not occurred, controlling the SDA bus line based on the internal SDA signal; and in response to determining that the internal SDA fault condition has occurred, releasing control of the SDA bus line.

[0101] Example 2 includes the method of Example 1, wherein determining whether the internal SDA fault condition has occurred includes: counting a plurality of clock cycles using a counter, during which the internal SDA signal drives the SDA bus line to a voltage level indicating that the I2C sub-device is operating in a non-receiving state, the clock cycles being based on a clock signal on the SCL line; and comparing the number of clock cycles to a threshold clock cycle count.

[0102] Example 3 includes the method of any one of Examples 1-2, wherein determining whether an internal SDA fault condition has occurred includes: determining that the internal SDA fault condition has occurred based on a number of clock cycles during which the internal SDA signal drives the SDA bus line to a voltage level indicating that the I2C sub-device operating in the non-receiving state satisfies the threshold clock cycle count.

[0103] Example 4 includes the method of any of Examples 1-3, wherein counting the number of clock cycles of the internal SDA signal to drive the SDA bus line to the non-receiving state is based on a negative edge of the clock signal.

[0104] Example 5 includes the method of any of Examples 1-4, wherein the threshold clock cycle count for determining whether an internal SDA fault condition has occurred is based on a number of clock cycles used to communicate a single data byte and corresponding acknowledgement on the SDA bus line.

[0105] Example 6 includes the method of any of Examples 1-5, wherein the threshold clock cycle count for determining whether the internal SDA fault condition has occurred is at least 9.

[0106] Example 7 includes the method of any one of Examples 1-5, wherein the voltage level of the SDA bus line indicating that the I2C sub-device is operating in the non-receiving state corresponds to a logic low voltage level; and releasing control of the SDA bus line includes: turning off a driver that pulls the SDA bus line to the logic low voltage level.

[0107] Example 8 includes the method of any of Examples 1-7, further comprising: receiving a start command from the SDA bus line after releasing control of the SDA bus line; and resetting the counter in response to the start command.

[0108] Example 9 includes the method of Example 1, further comprising receiving a stop command from the SDA bus line after releasing control of the SDA bus line.

[0109] Example 10 includes the method of Example 1, further comprising receiving a soft reset command from the SDA bus line after releasing control of the SDA bus line.

[0110] Example 11 includes an integrated circuit (IC) device, comprising: an interface circuit coupled to a two-wire serial communication bus having a serial clock (SCL) line and a serial data (SDA) bus line; and a bus jam recovery circuit, for: monitoring a local SDA fault condition at the IC device based on multiple clock cycles, during which an internal SDA signal drives the SDA bus line to a first signal state, the clock cycle being based on a clock signal received from the SCL line; and in response to the local SDA fault condition, releasing the SDA bus line independently of the internal SDA signal, wherein the SDA bus line is in a second signal state different from the first signal state based on the release.

[0111] Example 12 includes the IC device of Example 11, wherein the local SDA fault condition is triggered based on a number of clock cycles during which the internal SDA signal drives the SDA bus line to a first signal state that satisfies a threshold clock cycle count.

[0112] Example 13 includes the IC device of any of Examples 11-12, wherein a threshold clock cycle count that triggers the local SDA fault condition is at least 9.

[0113] Example 14 includes the IC device of any of Examples 11-13, wherein the bus stuck recovery circuit includes a counter circuit for counting a number of clock cycles during which the internal SDA signal drives the SDA bus line to the first signal state.

[0114] Example 15 includes the IC device of any of Examples 11-14, wherein the counter circuit is triggered by a negative edge of the clock signal.

[0115] Example 16 includes the IC device of any of Examples 11-15, wherein the counter circuit is activated when the internal SDA signal is in a first signal state and is deactivated when the internal SDA signal is in a second signal state.

[0116] Example 17 includes the IC device of any of Examples 11-16, wherein the counter circuit includes a plurality of cascaded flip-flops.

[0117] Example 18 includes the IC device of any of Examples 11-17, wherein the first signal state corresponds to a logic low voltage level and the second signal state corresponds to a logic high voltage level.

[0118] Example 19 includes the IC device of any of Examples 11-18, wherein the IC device is an I2C sub-device.

[0119] Example 20 includes an integrated circuit (IC) device, including: an interface circuit for connecting to an inter-integrated circuit (I2C) bus having a serial clock (SCL) line and a serial data (SDA) bus line; and an I2C bus stuck recovery circuit, including: a first port for receiving an internal SDA signal generated at the IC device; a second port coupled to the interface circuit to receive a clock signal from the SCL line; a third port for outputting a driver control signal to the interface circuit for driving the SDA bus line; a first logic circuit for generating a pull-down enable signal to selectively enable or disable pulling the SDA bus line to a logic low voltage level, the generating being based on a number of consecutive clock cycles of the clock signal during which the internal SDA signal has a logic low; and a second logic circuit for generating the driver control signal based at least in part on the pull-down enable signal. .

[0120] Example 21 includes the IC device of Example 20, wherein the first logic circuit generates a pull-down enable signal to disable pulling the SDA bus line to a logic low voltage level based on the number of consecutive clock cycles in which the internal SDA signal has a logic low satisfying (e.g., equal to or greater than) a threshold clock cycle count.

[0121] Example 22 includes the IC device of any of Examples 20-21, wherein the first logic circuit generates a pull-down-enable signal to enable pulling the SDA bus line to a logic low voltage level based on a number of consecutive clock cycles in which the internal SDA signal has a logic low being less than a threshold clock cycle count.

[0122] Example 23 includes the IC device of any of Examples 20-22, wherein the threshold clock cycle count is at least 9.

[0123] Example 24 includes the IC device of any of Examples 20-23, wherein the first logic circuit includes a plurality of cascaded flip-flops clocked by a negative edge of the clock signal.

[0124] Example 25 includes the IC device of any of Examples 20-24, wherein the cascade flip-flop is reset based on an internal SDA signal at the IC device having a logic high level.

[0125] Example 26 includes an IC device of any of Examples 20-25, wherein the interface circuit includes a transistor having a drain terminal coupled to the SDA bus line, a gate terminal coupled to a third port of the I2C bus stuck recovery circuit, and a source terminal coupled to a voltage rail having a voltage corresponding to a logic low voltage level.

[0126] Example 27 includes an apparatus comprising means for performing the method of any of Examples 1-10.

[0127] Variations and embodiments

[0128] Although the above reference Figure 1-9 The illustrated exemplary implementations describe embodiments of the present disclosure, but those skilled in the art will recognize that the various teachings described above are applicable to a variety of other implementations.

[0129] In certain contexts, the features discussed herein may be applicable to automotive systems, safety-critical industrial applications, medical systems, scientific instrumentation, wireless and wired communications, radio, radar, industrial process control, audio and video equipment, current sensing, instrumentation (which may be highly precise), and other digital processing-based systems.

[0130] In the discussion of the above embodiments, components of the system, such as flip-flops, NAND gates, NOT gates, buffers, transistors and / or other components can be easily replaced, substituted or otherwise modified to suit the needs of a particular circuit. In addition, it should be noted that the use of complementary electronic devices, hardware, software, etc. provides equally viable options for implementing the teachings of the present disclosure related to internal SDA bus failure recovery at a sub-device in a variety of communication systems.

[0131] Portions of various systems for internal SDA bus fault recovery at a sub-device as proposed herein can include electronic circuits to perform the functions described herein. In some cases, one or more portions of the system may be provided by a processor configured to perform the functions described herein. For example, the processor may include one or more dedicated components, or may include a programmable logic gate configured to perform the functions described herein. The circuit may operate in an analog domain, a digital domain, or a mixed signal domain. In some cases, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-temporary computer-readable storage medium.

[0132] In an example embodiment, any number of circuits of this figure can be implemented on the board of the associated electronic device. The board can be a general circuit board, which can hold various components of the internal electronic system of the electronic device, and further, connectors for other peripheral devices are provided. More specifically, the board can provide an electrical connection through which other components of the system can communicate electrically. Any suitable processor (including DSP, microprocessor, support chipset, etc.), computer-readable non-transient memory element, etc. can be appropriately coupled to the board based on specific configuration needs, processing requirements, computer design, etc. Other components such as external memory, additional sensors, controllers for audio / video display, and peripherals can be attached to the board as plug-in cards, via cables or integrated into the board itself. In various embodiments, the functions described herein can be implemented in simulated form as software or firmware running in one or more configurable (e.g., programmable) elements, which are arranged in a structure to support these functions. The software or firmware providing the simulation can be provided on a non-transient computer-readable storage medium, which includes instructions that allow the processor to perform those functions.

[0133] In another example embodiment, the circuits of the present figures may be implemented as stand-alone modules (e.g., devices having associated components and circuits configured to perform a specific application or function) or as modules inserted into dedicated hardware of an electronic device. Note that specific embodiments of the present disclosure may be readily included in part or in whole in a system-on-chip (SOC) package. A SOC represents an IC that integrates the components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed signal, and typically RF functions: all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), in which multiple separate ICs are located within a single electronic package and are configured to interact closely with each other through the electronic package.

[0134] It is also important to note that all specifications, dimensions, and relationships outlined herein (e.g. Figure 1The number of components of the device and / or sub-device 102, Figure 3 The internal bus stuck recovery circuit 120 of the present invention is provided only for the purpose of example and teaching. Without departing from the spirit of the present disclosure or the scope of the appended claims, such information can be changed considerably. It should be understood that the system can be combined in any suitable manner. Along similar design alternatives, any of the circuits, components, modules and elements shown in the accompanying drawings can be combined in various possible configurations, all of which are obviously within the broad scope of this specification. In the foregoing description, example embodiments have been described with reference to specific processors and / or component arrangements. Without departing from the scope of the appended claims, various modifications and changes can be made to such embodiments. Therefore, the description and the accompanying drawings are considered to be illustrative rather than restrictive.

[0135] Note that, using the numerous examples provided herein, interactions can be described based on two, three, four or more electrical components. However, this is only for the purpose of clarity and example. It should be understood that the system can be combined in any suitable manner. Along similar design alternatives, any of the components, modules and elements shown in the accompanying drawings can be combined in various possible configurations, all of which are clearly within the broad scope of this specification. In some cases, it may be easier to describe one or more functions of a given flow set by referring only to a limited number of electrical components. It should be understood that the circuits taught by the accompanying drawings and the circuits taught therein are easily scalable and can accommodate a large number of components, as well as more complex / complex arrangements and configurations. Therefore, the examples provided should not limit the scope of the circuit or inhibit the broad teachings that may be applied to countless other architectures.

[0136] Note that in this specification, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in "one embodiment," "example embodiment," "embodiment," "another embodiment," "some embodiments," "various embodiments," "other embodiments," "alternative embodiments," etc. are intended to indicate that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiment. Moreover, as used herein, including in the claims, "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of [at least one of A, B, or C] means A or B or C or AB or AC or BC or ABC (i.e., A and B and C).

[0137] Various aspects of the illustrative embodiments are described using terms commonly employed by those skilled in the art to convey the essence of their work to other technicians in the field. For example, the term "connection" means a direct electrical connection between connected objects without any intermediate devices / components, while the term "coupling" means a direct electrical connection between connected objects, or an indirect connection through one or more passive or active intermediate devices / components. In another example, the term "circuitry" means one or more passive and / or active components that are arranged to cooperate with each other to provide the desired functionality. In addition, as used herein, the terms "substantially", "approximately", "about", etc. can be used to generally refer to within + / -20% of a target value based on the context of a specific value as described herein or as known in the art, such as within + / -10% of a target value.

[0138] Numerous other changes, substitutions, variations, alterations, and modifications may be determined by those skilled in the art, and the present disclosure is intended to cover all such changes, substitutions, variations, alterations, and modifications that fall within the scope of the embodiments and the appended claims. Note that all optional features of the above-described apparatus may also be implemented with respect to the methods or processes described herein, and that the details in the examples may be used anywhere in one or more embodiments.

Claims

1. A method performed by an inter-integrated circuit (I2C) sub-device coupled to a serial communication bus, the serial communication bus comprising a serial clock (SCL) line and a serial data (SDA) bus line, the method include: monitoring an internal SDA signal generated at the I2C daughter device; determining, based at least in part on the monitoring, whether an internal SDA fault condition has occurred; in response to determining that an internal SDA fault condition has not occurred, controlling the SDA bus line based on the internal SDA signal; as well as In response to determining that the internal SDA fault condition has occurred, control of the SDA bus line is released.

2. The method of claim 1 , wherein the determining whether the internal SDA fault condition has occurred include: counting, using a counter, a number of clock cycles during which the internal SDA signal drives the SDA bus line to a voltage level indicating that the I2C daughter device is operating in a non-receiving state, the clock cycles being based on a clock signal on the SCL line; as well as The number of clock cycles is compared to a threshold clock cycle count.

3. The method of claim 2, wherein the determining whether an internal SDA fault condition has occurred include: The internal SDA fault condition is determined to have occurred based on a number of clock cycles during which the internal SDA signal drives the SDA bus line to a voltage level indicative of the I2C sub-device operating in the non-receiving state to satisfy the threshold clock cycle count.

4. The method of claim 2, wherein the counting of the number of clock cycles of the internal SDA signal that drives the SDA bus line to the non-receiving state is based on a negative edge of the clock signal.

5. The method of claim 2, wherein the threshold clock cycle count used to determine whether an internal SDA fault condition has occurred is based on a number of clock cycles used to communicate a single data byte and corresponding acknowledgement on the SDA bus line. 6 . The method of claim 2 , wherein the threshold clock cycle count used to determine whether the internal SDA fault condition has occurred is at least 9.

7. The method according to claim 2, in: the voltage level of the SDA bus line indicating that the I2C sub-device is operating in the non-receiving state corresponds to a logic low voltage level; and Releasing control of the SDA bus line includes: The driver that pulls the SDA bus line to the logic low voltage level is turned off.

8. The method according to claim 2, wherein include: receiving a start command from the SDA bus line after releasing control of the SDA bus line; as well as The counter is reset in response to the start command.

9. An integrated circuit (IC) device, include: an interface circuit coupled to a two-wire serial communication bus having a serial clock (SCL) line and a serial data (SDA) bus line; as well as Bus stuck recovery circuit, used for: monitoring a local SDA fault condition at the IC device based on a plurality of clock cycles during which an internal SDA signal drives the SDA bus line to a first signal state, the clock cycles being based on a clock signal received from the SCL line; as well as In response to the local SDA fault condition, the SDA bus line is released independent of the internal SDA signal, wherein the SDA bus line is in a second signal state different from the first signal state based on the releasing.

10. The IC device of claim 9, wherein the local SDA fault condition is triggered based on a number of clock cycles during which the internal SDA signal drives the SDA bus line to a first signal state that satisfies a threshold clock cycle count. 11 . The IC device of claim 10 , wherein a threshold clock cycle count that triggers the local SDA fault condition is at least 9.

12. The IC device of claim 9, wherein the bus stuck recovery circuit comprises a counter circuit for counting a number of clock cycles during which the internal SDA signal drives the SDA bus line to the first signal state.

13. The integrated circuit device of claim 12, wherein the counter circuit is triggered by a negative edge of the clock signal.

14. The IC device of claim 12, wherein the counter circuit is activated when the internal SDA signal is in the first signal state, and the counter circuit is deactivated when the internal SDA signal is in the second signal state.

15. The IC device of claim 9, wherein the first signal state corresponds to a logic low voltage level and the second signal state corresponds to a logic high voltage level.

16. An integrated circuit (IC) device, include: an interface circuit for connecting to an inter-integrated circuit (I2C) bus having a serial clock (SCL) line and a serial data (SDA) bus line; as well as I2C bus stuck recovery circuit, including: a first port for receiving an internal SDA signal generated at the IC device; a second port coupled to the interface circuit to receive a clock signal from the SCL line; A third port outputs a driver control signal to the interface circuit for driving the SDA bus line; a first logic circuit for generating a pull-down enable signal to selectively enable or disable pulling the SDA bus line to a logic low voltage level, the generating being based on a number of consecutive clock cycles of the clock signal during which the internal SDA signal has a logic low; and A second logic circuit is configured to generate the driver control signal based at least in part on the pull-down enable signal.

17. The IC device of claim 16, wherein the first logic circuit generates the pull-down enable signal to disable pulling the SDA bus line to the logic low voltage level based on the number of consecutive clock cycles in which the internal SDA signal has the logic low satisfying a threshold clock cycle count.

18. The IC device of claim 17, wherein the threshold clock cycle count is at least 9.

19. The integrated circuit device according to claim 16, in: The first logic circuit includes a plurality of cascaded flip-flops clocked by the negative edge of the clock signal; and The cascade flip-flop is reset based on an internal SDA signal at the IC device having a logic high.

20. The IC device of claim 16, wherein the interface circuit comprises a transistor having a drain terminal coupled to the SDA bus line, a gate terminal coupled to a third port of the I2C bus stuck recovery circuit, and a source terminal coupled to a voltage rail having a voltage corresponding to the logic low voltage level.

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