A power semiconductor under test gate adjustable resistance circuit

Abstract

The application provides a measured power semiconductor gate adjustable resistance circuit, which comprises two unidirectional conduction adjustable resistance modules, is arranged in parallel between the gate of a measured power semiconductor and a gate driver thereof, and the conduction directions of the two unidirectional conduction adjustable resistance modules are opposite; each adjustable resistance module generates an adjustable resistance between the gate of the measured power semiconductor and the gate driver thereof when conducting, the resistance value of the adjustable resistance is any one in a sequence [1xR base , 2xR base ,..., NxR base ], wherein R base is a basic resistance value; and the parasitic inductance value of the adjustable resistance is less than or equal to an upper limit of parasitic inductance, and NxR base is greater than or equal to a lower limit of a maximum resistance value. Using the circuit provided by the application, the influence of parasitic inductance can be effectively controlled while the turn-on loop resistance and the turn-off loop resistance of the measured power semiconductor are respectively and accurately adjusted during the performance test of the gate of the measured power semiconductor.

Description

Technical Field

[0001] The present application belongs to the field of power semiconductor testing and relates to a gate resistance adjustment technology for power semiconductors. Specifically, an adjustable gate resistance circuit for a power semiconductor to be tested is provided. Background Art

[0002] With the development of new energy and power electronics technology, power semiconductors are increasingly used in electric vehicles, wind power and other fields. The gate switching characteristics of power semiconductors, as an important design parameter, are closely related to the loss and noise of power semiconductors. Therefore, accurately testing the gate switching characteristics of power semiconductors is of great significance to the design and optimization of power semiconductors.

[0003] Currently, double-pulse testing is commonly used to test the gate switching characteristics of power semiconductors. The gate resistor is connected between the gate driver and the power semiconductor gate to adjust the gate switching speed and suppress gate voltage overshoot. Therefore, to match different power semiconductors and their different turn-on / off characteristics, the gate resistor's resistance value needs to be set independently during the turn-on and turn-off processes of the power semiconductor under test. In addition, during the gate switching test, parasitic inductance in the gate loop can cause the switching waveform to oscillate, interfering with the measurement results. Therefore, the parasitic inductance in the gate loop needs to be minimized.

[0004] However, existing double-pulse tests either use a method of directly replacing resistor devices, which is complicated to operate; or use multi-stage resistors in series as gate resistors. However, this structure will cause the superposition of multiple levels of parasitic inductance, affecting the test results; there is also a method of using multi-stage resistors in parallel as gate resistors. Although this structure can reduce parasitic inductance to a certain extent, its resistance adjustment action is complicated, and the gear with a specific resistance value is difficult to obtain. Summary of the Invention

[0005] The present application provides, through an embodiment, a gate adjustable resistance circuit for a power semiconductor under test, comprising two unidirectionally conductive adjustable resistance modules, which are arranged in parallel between the gate of the power semiconductor under test and its gate driver, and the two unidirectionally conductive adjustable resistance modules have opposite conduction directions;

[0006] Each adjustable resistor module is configured to generate an adjustable resistor between the gate of the power semiconductor under test and its gate driver when it is turned on, and the resistance of the adjustable resistor is a sequence of [1×R base ,2×R base ,...,N×R base ], where R base is the basic resistance value;

[0007] Furthermore, the parasitic inductance value of the adjustable resistor is less than or equal to the preset parasitic inductance upper limit, and N×R base Greater than or equal to the preset maximum resistance lower limit.

[0008] Furthermore, each unidirectionally conductive adjustable resistance module includes:

[0009] A multi-stage resistor circuit is composed of at least two cascaded stages of resistor sub-modules, wherein at least one stage of the resistor sub-module is used to provide a basic resistance value, and the resistance values ​​of the resistor sub-modules at each stage can be switched between different integer multiples of the basic resistance value; a Schottky diode is connected in series with the resistor sub-modules at each stage, and switches the on / off state of the unidirectional conductive adjustable resistor module in which it is located based on the potential conditions of its anode and cathode; and a control module is used to enable the resistance values ​​of the resistor sub-modules at each stage to be switched between different integer multiples of the basic resistance value.

[0010] Preferably, each level of resistance submodule includes a main circuit, and at least one level of resistance submodule further includes at least one branch circuit, the main circuits are connected in series with each other, and the branch circuits are only connected in parallel with the main circuit of the same level.

[0011] Furthermore, each main circuit includes a main circuit switching device, a main circuit resistor and a main circuit switch driver, wherein the main circuit resistor is connected in parallel between the drain and source of the main circuit switching device, and the main circuit switch driver is connected between the control module and the gate of the main circuit switching device, and switches the on-off state of the main circuit switching device based on the on-off control signal sent by the control module; each branch circuit includes a branch circuit switching device, a branch resistor and a branch circuit switch driver, wherein the branch resistor is connected in series between the branch circuit switching device and the main circuit of the same level, and the branch circuit switch driver is connected between the control module and the gate of the branch circuit switching device, and switches the on-off state of the branch circuit switching device based on the on-off control signal sent by the control module.

[0012] Preferably, the resistance values ​​of the main resistors and branch resistors included in each stage of the resistance submodule are the same.

[0013] Preferably, the preset upper limit of the parasitic inductance is 30 nH, and the preset lower limit of the maximum resistance is 20Ω.

[0014] Specifically, each unidirectionally conductive adjustable resistance module includes four cascaded resistance submodules, wherein: the first-stage resistance submodule includes a main circuit and a branch circuit, and the resistance values ​​of the main circuit resistor and the branch circuit resistor included in this stage of resistance submodule are both 20Ω; the second-stage resistance submodule includes a main circuit and two branches, and the resistance values ​​of the main circuit resistor and the branch circuit resistor included in this stage of resistance submodule are both 12Ω; the third-stage resistance submodule includes a main circuit and a branch circuit, and the resistance values ​​of the main circuit resistor and the branch circuit resistor included in this stage of resistance submodule are both 2Ω; the fourth-stage resistance submodule includes only one main circuit, and the resistance value of the main circuit resistor included in this stage of resistance submodule is the basic resistance value R base , and R base =1Ω.

[0015] Preferably, the main switch device and the branch switch device are both N-channel enhancement mode MOSFETs; and the control module sends the on-off control signal through an IO expansion chip.

[0016] Preferably, the main circuit resistor and the branch circuit resistor are both thick film resistors.

[0017] The power semiconductor gate adjustable resistance circuit under test provided in the present application has two independently unidirectional conductive adjustable resistance modules. Each resistance module constructs a multi-level main circuit and branch circuit structure through different series and parallel connection methods of multiple switching devices and resistance devices. The main circuit structures of each level are connected in series with each other, and each branch structure is only connected in parallel with the main circuit of the same level. The switching of the resistance value of each level is achieved by controlling the on-off state of the switching device. Then, through the multi-level adjustable resistance sub-module, on the basis of effectively controlling the parasitic inductance, the gate resistance is independently and accurately adjusted in steps of the basic resistance value within the range that meets the maximum resistance requirement, which can fully meet the needs of power semiconductor performance testing with different specifications and parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the use principle of the power semiconductor gate adjustable resistance circuit under test provided in accordance with an embodiment of the present application;

[0019] Figure 2 Schematic diagram of the circuit principle of a unidirectionally conductive adjustable resistor module provided according to an embodiment of the present application;

[0020] Figure 3 Schematic diagram of the circuit principle of a unidirectionally conductive adjustable resistor module provided according to an embodiment of the present application;

[0021] Figure 4 The present invention is a schematic diagram showing the principle of adjusting the gate resistance of a power semiconductor under test using the adjustable gate resistance circuit of the power semiconductor under test provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] Hereinafter, the present application will be further described based on preferred embodiments with reference to the accompanying drawings.

[0023] In the description of the embodiments of the present application, it should be noted that if the terms "upper", "lower", "inner", "outer" and the like indicate an orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or are the orientation or positional relationship in which the products of the embodiments of the present application are usually placed when in use, they are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, in the description of the present application, in order to distinguish different units, words such as first and second are used in this specification, but these are not limited by the order of manufacture, nor can they be understood as indicating or implying relative importance. Their names may be different in the detailed description and claims of the present application.

[0024] The vocabulary in this specification is used to illustrate the embodiments of the present application, but is not intended to limit the present application. It should also be noted that, unless otherwise clearly specified and limited, the terms "disposed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, an indirect connection through an intermediate medium, or a communication between the two components. For those skilled in the art, the specific meanings of the above terms in this application can be specifically understood.

[0025] Some embodiments of the present application provide a power semiconductor gate adjustable resistance circuit to be tested, Figure 1 The schematic diagram of the circuit used in the power semiconductor gate switching characteristics test device is shown in FIG. Figure 1 As shown, the core components of the power semiconductor gate switching characteristic test device include the power semiconductor DUT1 under test connected in series between the positive and negative poles of the DC power supply Udc, the auxiliary power semiconductor DUT2, a gate driver for controlling the on and off states of the power semiconductor DUT1 under test, and an inductor L connected in parallel with the auxiliary power semiconductor DUT2.

[0026] Among them, the gate driver can use various types of signal generators known to technical personnel in this field, and its signal output end is connected to the gate of the power semiconductor DUT1 under test. During the double pulse experiment, the gate driver sends a double pulse signal to its gate according to the specification parameters of the power semiconductor under test, and uses the high and low potentials of the pulse signal to control the opening and closing of the power semiconductor DUT1 under test, so as to measure the gate opening / closing characteristics of the power semiconductor DUT1 under test.

[0027] Furthermore, the gate adjustable resistance circuit of the power semiconductor under test provided in the present application includes two unidirectionally conductive adjustable resistance modules, which are arranged in parallel between the gate and the gate driver of the power semiconductor DUT1 under test, and the conduction directions of the two unidirectionally conductive adjustable resistance modules are opposite.

[0028] Specifically, the multi-stage resistor circuit 1 and the first Schottky diode D1 and Figure 1 The control module not shown in the figure constitutes a unidirectional conductive adjustable resistance module, wherein the multi-stage resistance circuit 1 and the first Schottky diode D1 are connected in series, and the anode and cathode of the first Schottky diode D1 are respectively directed toward the gate driver and the gate of the DUT1. By utilizing its unidirectional conductive characteristic, when the gate driver sends a pulse signal, an open loop of the gate of the power semiconductor DUT1 under test is formed through the adjustable resistance module, and an adjustable resistance is generated between the gate of the DUT1 in the open loop and the gate driver.

[0029] Similarly, the multi-stage resistor circuit 2 and the second Schottky diode D2 and Figure 1 The control module not shown in the figure constitutes another unidirectional conductive adjustable resistance module, wherein the multi-stage resistance circuit 2 is connected in series with the second Schottky diode D2, and the direction of the second Schottky diode D2 is opposite to that of the first Schottky diode D1, that is, its anode and cathode are respectively facing the gate of DUT1 and the gate driver. By utilizing its unidirectional conductive characteristic, after the pulse signal sent by the gate driver ends, a shut-off loop of the gate of the power semiconductor DUT1 under test is formed through the adjustable resistance module, and an adjustable resistance is generated between the gate of DUT1 in the shut-off loop and the gate driver.

[0030] As analyzed in the background technology, different power semiconductors have different turn-on / off characteristics. When testing their gate characteristics, it is necessary to ensure that the gate resistance values ​​of their turn-on circuit and turn-off circuit can be adjusted independently and accurately. At the same time, the parasitic inductance should be reduced as much as possible during the adjustment process to avoid the switching waveform oscillation caused by the parasitic inductance introduced by the gate resistance during the gate switching test. Interference with the measurement results.

[0031] To this end, in the power semiconductor gate adjustable resistance circuit provided by the present application, when any one of the two unidirectionally conductive adjustable resistance modules is turned on to form a gate-on loop or a gate-off loop, the resistance value of the adjustable resistance generated between the gate driver and the DUT1 gate can be set to the sequence [1×R base ,2×R base ,...,N×R base ] (where R baseThe minimum resistance value of the adjustable resistor is the basic resistance value R base , the maximum resistance is the basic resistance value R base N times, and between its minimum and maximum values ​​can be R base The step size is adjusted one by one to achieve precise setting of the gate resistance.

[0032] At the same time, in the embodiment of the present application, when the above-mentioned adjustable resistor module is turned on, the adjustable resistor generated between the gate driver and the gate of DUT1 also meets the following conditions: the parasitic inductance value of the adjustable resistor is less than or equal to the preset parasitic inductance upper limit, and the maximum resistance value of the adjustable resistor (i.e. N×R base ) is greater than or equal to the preset maximum resistance lower limit.

[0033] Basic resistance value R base The size of the adjustable resistor determines the adjustment step size. Obviously, R base The smaller the value, the finer the control of the resistance between the gate driver and the gate of DUT1 can be. However, this will also significantly increase the complexity of the circuit and the parasitic inductance. Therefore, it is necessary to comprehensively consider the turn-on and turn-off characteristics of the power semiconductor under test and the matching resistance range to reasonably set the adjustment accuracy and circuit complexity of the adjustable resistor module.

[0034] For example, in some preferred embodiments, the base resistance value R base It can be set to 1Ω, that is, the resistance of the adjustable resistor can be accurately adjusted between 1Ω, 2Ω, ... to NΩ in steps of 1Ω.

[0035] The lower limit of the maximum resistance value can be determined based on the resistance range that needs to be matched during the turn-on and turn-off processes of the gate of the common power semiconductor device being tested. For example, in some preferred embodiments, the maximum resistance value that the adjustable resistor can reach is not less than 20Ω to ensure that it can test power semiconductor devices that need to match the gate resistance of 20Ω.

[0036] The following combination Figure 2 The embodiment shown in the figure describes in detail the circuit structure of the unidirectionally conducting adjustable resistance module. Figure 2 The nodes GATE+ and GATE- in the circuit are connected to the signal output terminal of the gate driver and the gate of the power semiconductor DUT1 under test, respectively. The anode and cathode of the first Schottky diode D1 are respectively directed toward the nodes GATE+ and GATE-. Therefore, Figure 2 The adjustable resistor module shown is obviously unidirectionally conducted from the gate driver to the gate of the DUT1, which constitutes a gate turn-on loop of the power semiconductor DUT1 under test.

[0037] Furthermore, if Figure 2As shown, in the unidirectionally conductive adjustable resistance module, the multi-stage resistance circuit is composed of four cascaded resistance sub-modules, from the node GATE+ to the first Schottky diode D1 are the first-stage resistance sub-module, the second-stage resistance sub-module, the third-stage resistance sub-module and the fourth-stage resistance sub-module, wherein the fourth-stage resistance sub-module is used to provide the basic resistance value R base , and the resistance values ​​of the first to fourth level resistor submodules can be within the basic resistance value R base Switch between different integer multiples of .

[0038] Specifically, see Figure 2 The first-stage resistance submodule is composed of two switching devices (a first switching device Q1 and a second switching device Q2), two resistors (a first resistor R1 and a second resistor R2) and two switch drivers (a first switch driver O1 and a second switch driver O2). The two ends of the first resistor R1 are respectively connected in parallel with the drain and source of the first switching device Q1. The first switch driver O1 is connected between the control module (not shown in the figure) and the gate of the first switching device Q1, and controls the on and off of the first switching device Q1 by receiving the on-off control signal sent by the control module; the two ends of the second resistor R2 are connected in series between the source of the second switching device Q2 and the source of the first switching device Q1. The second switch driver O2 is connected between the control module and the gate of the second switching device Q2, and controls the on and off of the second switching device Q2 by receiving the on-off control signal sent by the control module.

[0039] By observing the connection mode between the two switching devices and the two resistors, it can be seen that when the control module controls the first switching device Q1 to be turned on through the first switch driver O1, the first resistor R1 and the second resistor R2 are both short-circuited. At this time, the first-stage resistance submodule is equivalent to a wire through which current flows directly (and at this time, the wire has an inductance value, that is, the parasitic inductance L flowing through Q1). m ), when the first switch device Q1 is turned off, the first resistor R1 is connected to the circuit. At the same time, it further switches the resistance and parasitic inductance of the first-stage resistor submodule as a whole according to the on-off state of the second switch device Q2: when the second switch device Q2 is turned off, the current only flows through the first resistor R1. At this time, the resistance of the first-stage resistor submodule is R1, and the parasitic inductance is the parasitic inductance L of the first resistor R1. r When the second switch device Q2 is turned on, the second switch device Q2 is connected in series with the second resistor R2, and then connected in parallel with the first resistor R1 to the circuit. At this time, the resistance of the first-stage resistor submodule is R1R2 / (R1+R2). The parasitic inductance value is determined by the parasitic inductance of the first resistor R1, the second resistor R2 and the second switch device Q2. Assume that the parasitic inductance of each resistor is L r , the parasitic inductance of each switching device is L m, then the parasitic inductance value at this time is L r (L r +L m ) / (2L r +L m Preferably, the resistance values ​​R1 and R2 of the first resistor R1 and the second resistor R2 are the same, that is, the first-stage resistance submodule has three switchable resistance values ​​of 0, R1 / 2 and R1.

[0040] The switching state of the first switching device Q1 determines whether the first-stage resistance submodule generates a resistance connected to the circuit. When it is in the off state, the switching state of the second switching device Q2 is further used to switch the resistance of the resistance connected to the circuit. Therefore, in this application, the structure in which the switching device and the resistor are connected in parallel in each level of the resistance submodule is called the main path, and the corresponding switching device, resistor and main path switch driver are called the main path switching device, main path resistor and main path switch driver (for example Figure 2 The first switch device Q1, the first resistor R1 and the first switch driver Q1 in the circuit are connected in series. The structure of the switch device and the resistor is called a branch, and the corresponding switch device, resistor and switch driver are called branch switch device, branch resistor and branch switch driver (for example, Figure 2 The second switch device Q2, the second resistor R2 and the second switch driver O2 in the circuit). Obviously, each level of the resistance submodule includes a main circuit, and at least one level of the resistance submodule also includes at least one branch circuit (such as Figure 2 The first to third level resistor submodules in the embodiment are connected in series, and the main circuits of the resistor submodules at each level are connected in series, and the branch circuits are only connected in parallel with the main circuits of the same level.

[0041] Similar to the first-stage resistance submodule, the second-stage resistance submodule is composed of three switching devices (third switching device Q3, fourth switching device Q4, fifth switching device Q5), three resistors (third resistor R3, fourth resistor R4, fifth resistor R5) and three switch drivers (third switch driver O3, fourth switch driver O4, fifth switch driver O5), wherein the two ends of the third resistor R3 are respectively connected in parallel with the drain and source of the third switching device Q3, and the third switch driver O3 is connected between the control module and the gate of the third switching device Q3, and controls the third switching device Q3 by receiving the on-off control signal sent by the control module. The switching device Q3 is turned on and off; the two ends of the fourth resistor R4 are connected in series between the source of the fourth switching device Q4 and the source of the third switching device Q3; the fourth switch driver O4 is connected between the control module and the gate of the fourth switching device Q4, and controls the on and off of the fourth switching device Q4 by receiving the on-off control signal sent by the control module; the two ends of the fifth resistor R5 are connected in series between the source of the fifth switching device Q5 and the source of the third switching device Q3; the fifth switch driver O5 is connected between the control module and the gate of the fifth switching device Q5, and controls the on and off of the fifth switching device Q5 by receiving the on-off control signal sent by the control module. Among them, the third switching device Q3 and the third resistor R3 constitute the main circuit of the second-stage resistance submodule, the fourth switching device Q4 and the fourth resistor R4, and the fifth switching device Q5 and the fifth resistor R5 constitute two branches incorporated into the second-stage resistance submodule.

[0042] Using the same analysis method as the first-stage resistor submodule, it can be seen that when the third switch device Q3 is turned on, the second-stage resistor submodule is short-circuited; when all three switch devices are turned off, the resistance of the second-stage resistor submodule is R3 and the parasitic inductance is L r When the third switch device Q3 and the fifth switch device Q5 are turned off and the fourth switch device Q4 is turned on, the resistance of the second-stage resistor submodule is R3R4 / (R3+R4), and the parasitic inductance is L r (L r +L m ) / (2L r +L m ); When the third switch device Q3 is turned off and the fourth switch device Q4 and the fifth switch device Q5 are turned on, the resistance of the second-stage resistance submodule is R3R4R5 / (R3R4+R4R5+R3R5), and the parasitic inductance is L r (L r +L m ) / (3L r +L m ). Preferably, the resistance values ​​of the three resistors R3, R4, and R5 are the same, that is, the second-stage resistance submodule has four switchable resistance values ​​of 0, R3 / 3, R3 / 2, and R3.

[0043] Similar to the first-stage resistor submodule, the third-stage resistor submodule consists of two switching devices (a sixth switching device Q6 and a seventh switching device Q7), two resistors (a sixth resistor R6 and a seventh resistor R7), and two switch drivers (a sixth switch driver O6 and a seventh switch driver O7). The sixth resistor R6 has its two terminals connected in parallel with the drain and source of the sixth switching device Q6, respectively. The sixth switch driver O6 is connected between the control module and the gate of the sixth switching device Q6, and controls the on / off state of the sixth switching device Q6 by receiving an on / off control signal from the control module. The seventh resistor R7 has its two terminals connected in series between the source of the seventh switching device Q7 and the source of the sixth switching device Q6. The seventh switch driver O7 is connected between the control module and the gate of the seventh switching device Q7, and controls the on / off state of the seventh switching device Q7 by receiving an on / off control signal from the control module. The sixth switching device Q6 and the sixth resistor R6 constitute the main circuit of the third-stage resistor submodule, while the seventh switching device Q7 and the seventh resistor R7 constitute a branch circuit incorporated into the third-stage resistor submodule.

[0044] Using the same analysis method as the first-stage resistor submodule, it can be seen that when the sixth switch device Q6 is turned on, the third-stage resistor submodule is short-circuited; when both switches are turned off, the resistance of the third-stage resistor submodule is R6 and the parasitic inductance is L r When the sixth switch device Q6 is turned off and the seventh switch device Q7 is turned on, the resistance of the third-stage resistor submodule is R6R7 / (R6+R7), and the parasitic inductance is L r (L r +L m ) / (2L r +L m ). Preferably, the resistance values ​​of the two resistors R6 and R7 are the same, that is, the third-level resistance submodule has three switchable resistance values ​​of 0, R6 / 2 and R6.

[0045] The fourth level resistance submodule is used to generate basic resistance values, such as Figure 2 As shown, it only includes one main circuit, which is composed of an eighth switch device Q8, an eighth resistor R8 and an eighth switch driver O8, wherein the resistance value of the eighth resistor R8 is the basic resistance value R base , its two ends are respectively connected in parallel with the drain and source of the eighth switch device Q8. The eighth switch driver O8 is connected between the control module and the gate of the eighth switch device Q8. The on-off control signal sent by the control module is received to control the on-off of the eighth switch device Q8. Obviously, the fourth-stage resistance submodule is short-circuited when the eighth switch device Q8 is turned on. When the eighth switch device Q8 is turned off, its resistance value is R8, that is, the basic resistance value R base , the parasitic inductance is L r .

[0046] In some preferred embodiments, each main resistor and branch resistor is a thick film resistor.

[0047] In some preferred embodiments, each main switch device and branch switch device is an N-channel enhancement MOSFET, and preferably, its on-state resistance is less than 50mΩ, so as to reduce the impact of the MOSFET series connection on the loop resistance; since the existing power semiconductor gate voltage is generally -10V to +20V, therefore, considering the gate voltage fluctuation range, the voltage resistance range of each switch device is greater than 25V.

[0048] In some preferred embodiments, Figure 2 As shown, the control module can send on / off control signals to each switch driver via an IO expansion chip using a communication method such as SPI. The above-mentioned methods of expanding IO signals using the IO expansion chip and controlling the on / off state of the switch devices via the switch drivers are well known to those skilled in the art and will not be described in detail here.

[0049] Table 1 below lists in a preferred embodiment, Figure 2 The resistance values ​​of each resistor in the unidirectionally conductive adjustable resistor module are shown.

[0050] Table 1 Resistance values ​​of each resistor in the unidirectional adjustable resistor module

[0051]

[0052]

[0053] Through the circuit analysis of each main circuit and branch circuit of the four-level resistor sub-module, it can be seen that when different resistance values ​​are output, the overall inductance values ​​are different due to the different series and parallel connection modes of the circuit. For this reason, in the embodiment of the present application, by setting the upper limit of parasitic inductance, the inductance values ​​corresponding to each obtainable gate resistance are all smaller than the upper limit of parasitic inductance, thereby minimizing the switching waveform oscillation caused by the parasitic inductance introduced by the gate resistance and the interference to the measurement results during the gate switch test.

[0054] In some preferred embodiments, the upper limit of the parasitic inductance can be determined by the following steps:

[0055] The first step is to simplify the gate drive loop into a second-order system and obtain its damping ratio and natural frequency (the damping ratio and natural frequency are functions of the gate resistance, inductance and input capacitance of the power semiconductor device);

[0056] The second step is to set the upper limit of the gate parasitic inductance L to R g C iss / 4 to avoid the system being in an underdamped (0<ξ<1) oscillation state, where ξ is the damping ratio and R g 、C iss are the gate resistance and input capacitance of the power semiconductor device respectively;

[0057] In the third step, the parasitic inductance upper limit margin obtained in the second step increases with the resistance of the adjustable resistor. Therefore, the influence of the parasitic inductance on the gate voltage change rate, switching loss and crosstalk is further considered to finally determine the parasitic inductance upper limit.

[0058] In some preferred embodiments, through the above steps, the upper limit of the parasitic inductance can be preset to 30nH, and appropriate switching devices Q1 to Q8 are selected based on this upper limit. Through the above settings, it is ensured that the maximum resistance value that the adjustable resistor can reach is not less than 20Ω, and its parasitic inductance does not exceed 30nH at each resistance value that can be reached.

[0059] Taking the example of setting the entire adjustable resistance module to generate a 29Ω gate resistance, by controlling the switch drivers of the resistance submodules at each level, the first switch device Q1 and the second switch device Q2 of the first-level resistance submodule are turned off, thereby generating a 20Ω resistance, whose parasitic inductance is L r The third switch device Q3 of the second-stage resistor submodule is turned off, the fourth switch device Q4 is turned on, and the fifth switch device Q5 is turned off, thereby generating a resistance of 12 / 2Ω, that is, 6Ω, whose parasitic inductance is L r (L r +L m ) / (2L r +L m The sixth switching device Q6 and the seventh switching device Q7 of the third-stage resistor submodule are both turned off, thereby generating a resistance of 2Ω, whose parasitic inductance is L r The eighth switch device Q8 of the fourth-stage resistance submodule is turned off, thereby generating a basic resistance of 1Ω, whose parasitic inductance is L r After the resistor submodules at each level are connected in series, a gate resistance of 29Ω is generated between the gate driver and the gate of DUI1, and the total parasitic inductance of the four-level resistor submodule is (7L 2 r +4L r L m ) / (2L r +L m ).

[0060] Table 2 below lists Figure 2The adjustable resistor module shown here adjusts the gate resistance between 1Ω and 29Ω in 1Ω increments. Table 2 also lists the measured parasitic inductance values ​​for each gate resistor value. It should be understood that the measured parasitic inductance values ​​are determined by the theoretical parasitic inductance values ​​for each combination described above, as well as the parasitic inductance values ​​generated by traces of varying lengths on the actual PCB.

[0061] Table 2 Combination of gate resistance adjustment

[0062]

[0063]

[0064] As can be seen from Table 2, this application adopts Figure 2 The adjustable resistor module shown can achieve continuous adjustment of the gate resistance within the range of 1 to 29 Ω in 1 Ω steps, and its maximum parasitic inductance value is 28.4600 nH.

[0065] It can be seen that this four-stage adjustable resistor structure can achieve as many adjustable resistance levels as possible with as few stages as possible, thereby controlling the influence of parasitic inductance at a low level while meeting the gate resistance adjustment range and adjustment accuracy.

[0066] In contrast, if a cascade method is used with a base resistance value of 1Ω and individual resistors of 2Ω, 4Ω, 8Ω, and 16Ω at each level, to produce a gate resistance of more than 20Ω, it is necessary to connect five resistance sub-circuits in series, which undoubtedly increases the circuit complexity and wire length, and causes the parasitic inductance value to increase accordingly.

[0067] Figure 3 The circuit schematic diagram of the unidirectionally conductive adjustable resistance module provided on the shutdown loop in some embodiments is shown. In the figure, the ninth switch device Q9 to the sixteenth switch device Q16, the ninth resistor R9 to the sixteenth resistor R16, and the ninth switch driver O9 to the sixteenth switch driver 16 constitute the Figure 2 The same circuit structure is used in the CMOS process, and the on / off control signal from the control module is sent to the corresponding switch driver through the IO expansion chip to adjust the resistance. The anode and cathode of the second Schottky diode D2 are respectively oriented toward the GATE- and GATE+ nodes, i.e., the gate of the power semiconductor under test and its gate driver. By setting the second Schottky diode D2 opposite to the first Schottky diode D1, they form a shutdown circuit for the power semiconductor under test, which provides an adjustable resistance during the gate shutdown process of the power semiconductor under test.

[0068] Obviously, the specifications of the ninth switch device Q9 to the sixteenth switch device Q16, the ninth resistor R9 to the sixteenth resistor R16, and the ninth switch driver O9 to the sixteenth switch driver 16 can be set to the same as Figure 2 The corresponding devices in the test may be the same, or may be set to be different according to the turn-off characteristics of the power semiconductor being tested.

[0069] Figure 4 A schematic diagram of the use of the adjustable resistance circuit of the power semiconductor gate under test in some embodiments is shown. The working principle of the circuit has been described in detail above and will not be repeated here.

[0070] The above is a detailed introduction to the specific implementation methods of the present application. For those skilled in the art, several improvements and modifications can be made to the present application without departing from the principles of the present application. These improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A power semiconductor gate adjustable resistance circuit under test, characterized in that: include: Two unidirectionally conductive adjustable resistance modules are arranged in parallel between the gate of the power semiconductor under test and its gate driver, and the conduction directions of the two unidirectionally conductive adjustable resistance modules are opposite; Each adjustable resistor module is configured to generate an adjustable resistor between the gate of the power semiconductor under test and its gate driver when it is turned on. The resistance of the adjustable resistor is a sequence of Any one of is the basic resistance value; And, the parasitic inductance value of the adjustable resistor is less than or equal to a preset parasitic inductance upper limit, and Greater than or equal to the preset maximum resistance lower limit; Each unidirectional adjustable resistor module includes: A multi-stage resistor circuit is composed of at least two cascaded stages of resistor submodules, wherein at least one stage of the resistor submodule is used to provide a basic resistance value, and the resistance values ​​of the resistor submodules at each stage can be switched between different integer multiples of the basic resistance value; The Schottky diode is connected in series with each level of the resistor sub-module, and switches the on / off state of the unidirectional conductive adjustable resistor module based on the potential of its anode and cathode; A control module, used to switch the resistance values ​​of the resistance sub-modules at each level between different integer multiples of the basic resistance value; Each level of the resistance submodule includes a main circuit, and at least one level of the resistance submodule also includes at least one branch circuit, the main circuits are connected in series with each other, and the branches are only connected in parallel with the main circuit of the same level; Each main path includes a main switch device, a main resistor, and a main switch driver. The main resistor is connected in parallel between the drain and source of the main switch device. The main switch driver is connected between the control module and the gate of the main switch device and switches the on / off state of the main switch device based on the on / off control signal sent by the control module. Each branch includes a branch switch device, a branch resistor and a branch switch driver. The branch resistor is connected in series between the branch switch device and the main circuit of the same level. The branch switch driver is connected between the control module and the gate of the branch switch device, and switches the on-off state of the branch switch device based on the on-off control signal sent by the control module.

2. The power semiconductor gate adjustable resistance circuit under test according to claim 1, characterized in that: The resistance values ​​of the main resistors and branch resistors included in each level of the resistance sub-module are the same.

3. The power semiconductor gate adjustable resistance circuit under test according to claim 2, characterized in that: The upper limit of the preset parasitic inductance is 30nH, and the lower limit of the preset maximum resistance is 20 .

4. The power semiconductor gate adjustable resistance circuit under test according to claim 3, characterized in that: Each unidirectionally conductive adjustable resistor module includes four cascaded resistor submodules, wherein: The first level resistor submodule includes a main circuit and a branch circuit, and the resistance values ​​of the main circuit resistor and the branch circuit resistor included in the first level resistor submodule are both 20 ; The second level resistor module includes a main circuit and two branches, and the resistance values ​​of the main circuit resistor and the branch resistor included in this level resistor module are both 12 ; The third level resistor submodule includes a main circuit and a branch circuit, and the resistance values ​​of the main circuit resistor and the branch circuit resistor included in the resistor submodule are both 2 ; The fourth level resistance submodule includes only one main circuit. The resistance value of the main circuit resistor included in this level resistance submodule is the basic resistance value. ,and =1 .

5. The power semiconductor gate adjustable resistance circuit under test according to claim 1, characterized in that: The main switch device and the branch switch device are both N-channel enhancement mode MOSFETs; The control module sends the on-off control signal through the IO expansion chip.

6. The power semiconductor gate adjustable resistance circuit under test according to claim 1, characterized in that: The main circuit resistor and the branch circuit resistor are both thick film resistors.

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