Silicon optical device structure and manufacturing method thereof

Abstract

The invention discloses a silicon optical device structure and a manufacturing method thereof. The silicon optical device structure comprises a first semiconductor structure arranged on a substrate; the first dielectric layer is arranged on the substrate, and the first semiconductor structure is covered with the first dielectric layer; the waveguide structure is arranged on the first dielectric layer and is isolated from the first semiconductor structure; the window is arranged on the surface of the waveguide structure, and the bottom surface of the window penetrates through the surface of the first dielectric layer and is positioned on the first semiconductor structure; the second semiconductor structure is arranged in the window; and the second semiconductor structure is in contact with the first semiconductor structure on the bottom surface of the window. The invention also provides an integration scheme of a high-quality silicon nitride waveguide manufactured by adopting a high-temperature furnace tube process and a germanium-based optical detector with high responsivity, and is compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process, so that the process difficulty is effectively reduced, the process risk is reduced, and the overall performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit process technology, and in particular to a silicon photonic device structure compatible with a CMOS process and a silicon photonic high-temperature furnace tube process and a manufacturing method thereof. Background Art

[0002] Silicon-based optoelectronic technology focuses on nanoscale optoelectronic devices. With the help of the CMOS process platform and the use of SOI substrate, it realizes the conversion and processing of photoelectric signals in the same chip, and has excellent performance such as high bandwidth, low power consumption, anti-interference and high reliability. It has been applied to data centers, quantum computing, laser radar and biosensors and has broad development prospects. Silicon optical devices usually include passive devices and active devices. Passive devices are used to process optical signals, and active devices are used to convert photoelectric signals.

[0003] Due to the particularity of optical signals, although the silicon photonics process can use the CMOS platform to reduce costs, it still needs to add many special processes that are different from conventional CMOS. These special processes usually become difficulties in the development of silicon photonics processes. For example, photodetectors used in optical communication bands (such as O / C / L bands, etc.) are one of the difficulties of silicon photonics platform technology. Due to the limitations of silicon materials themselves, they cannot absorb light in the optical communication band, so it is impossible to directly use silicon materials to make some silicon photonic devices (such as optical receivers). It is usually necessary to switch to III-V materials or germanium materials. Among them, the lattice coefficients between III-V materials and silicon materials do not match, so it is difficult to use epitaxial processes to grow high-quality on silicon materials. Generally, only bonding processes can be used to bond III-V material devices to silicon substrates, which is difficult and costly. In comparison, germanium materials have a good absorption coefficient in the communication band, and the lattice coefficient is slightly different from that of silicon materials. The industry already has a relatively mature germanium epitaxial process on silicon, which can meet the needs of manufacturing germanium-based photodetectors.

[0004] However, in the current germanium-based photodetector structures and process integrations, there are still some process difficulties. For example, when an optical signal reaches the germanium-based photodetector through a silicon waveguide, an additional structure needs to be configured for optical mode matching to improve the responsivity of the germanium-based photodetector. The current technical means usually add a polysilicon optical mode matching structure in the area where the silicon waveguide and the germanium-based photodetector are joined. The specific process scheme includes forming structures such as silicon waveguides and silicon active devices on the top silicon layer of the SOI substrate, then performing polysilicon and dielectric layer deposition and patterning processes to form a polysilicon optical mode matching structure, forming a germanium epitaxial window on the silicon active device, removing the dielectric layer and polysilicon layer in the epitaxial window area, and stopping on the silicon active device structure; then performing a germanium epitaxial process in the epitaxial window to form a germanium-based photodetector structure. However, the above process scheme has the following problems: (1) When etching to form the epitaxial window, it is necessary to take into account the treatment of the polysilicon sidewalls and the surface of the silicon active device structure at the same time, otherwise it will affect the quality of subsequent germanium epitaxy, making it difficult to achieve different treatment requirements through adjustment; (2) When performing the germanium epitaxial process, germanium will grow synchronously on the polysilicon sidewalls in the epitaxial window, thus affecting the epitaxial quality of germanium.

[0005] Furthermore, in silicon photonics technology, although the silicon nitride waveguide formed by the high-temperature furnace tube process can have excellent properties such as low loss, low temperature coefficient, and high uniformity, due to the high process temperature (generally higher than 1000 °C) and the relatively thick film thickness required (generally greater than ), it is difficult to integrate with the polysilicon process in the conventional CMOS process. As a result, the current silicon photonics platforms with germanium-based photodetector devices usually cannot provide this high-temperature furnace tube silicon nitride waveguide process option and can only use the relatively poor-performance CVD silicon nitride waveguide. Summary of the Invention

[0006] The object of the present invention is to overcome the above-mentioned defects existing in the prior art and provide a silicon photonics device structure and a manufacturing method thereof.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] The present invention provides a silicon photonics device structure, including:

[0009] A substrate;

[0010] A first semiconductor structure disposed on the substrate;

[0011] A first dielectric layer disposed on the substrate, the first dielectric layer covering the first semiconductor structure;

[0012] A waveguide structure disposed on the first dielectric layer and isolated from the first semiconductor structure;

[0013] A window provided on the surface of the waveguide structure, the bottom surface of the window passing through the surface of the first dielectric layer and being located on the first semiconductor structure;

[0014] A second semiconductor structure provided in the window, the second semiconductor structure being in contact with the first semiconductor structure located on the bottom surface of the window.

[0015] Furthermore, the first semiconductor structure includes an active device, the second semiconductor structure includes a light receiving portion, and the waveguide structure includes a light mode matching structure.

[0016] Furthermore, a second dielectric layer is provided on the surface of the first dielectric layer, the second dielectric layer covering the waveguide structure and the second semiconductor structure, and a plurality of conductive contact holes are provided in the second dielectric layer. On both sides of the first semiconductor structure, there are a doped first contact region of a first conductivity type and a doped second contact region of a second conductivity type, and each of the conductive contact holes is located on both sides of the waveguide structure and is respectively connected to the first contact region and the second contact region.

[0017] Furthermore, the materials of the first semiconductor structure, the second semiconductor structure, and the waveguide structure are different from each other, and / or the material of the first semiconductor structure includes doped single crystal silicon, the material of the second semiconductor structure includes intrinsic germanium, and the material of the waveguide structure includes silicon nitride formed by a high-temperature furnace tube process.

[0018] Furthermore, the substrate includes an SOI substrate, the SOI substrate includes a substrate silicon layer, a buried oxide layer, and a top silicon layer, the first semiconductor structure is formed on the top silicon layer, and the first dielectric layer covers the buried oxide layer and the first semiconductor structure.

[0019] The present invention also provides a method for manufacturing a silicon optical device structure, including:

[0020] Providing a substrate;

[0021] Forming a first semiconductor structure on the substrate;

[0022] Forming a first dielectric layer on the surface of the substrate to cover the first semiconductor structure;

[0023] Forming a waveguide structure on the first dielectric layer and isolating it from the first semiconductor structure;

[0024] Forming a window on the surface of the waveguide structure such that the bottom surface of the window passes through the surface of the first dielectric layer and is located on the first semiconductor structure;

[0025] A second semiconductor structure is formed in the window, and the second semiconductor structure is brought into contact with the first semiconductor structure located on the bottom surface of the window.

[0026] Further, the providing the substrate and forming the first semiconductor structure on the substrate specifically includes:

[0027] Providing an SOI substrate, the SOI substrate including a substrate silicon layer, a buried oxide layer, and a top silicon layer;

[0028] Using a photolithography and etching process to pattern the top silicon layer to form a top silicon layer pattern, exposing the surface of the buried oxide layer;

[0029] Forming a doped first contact region of a first conductivity type and a doped second contact region of a second conductivity type on both sides of the top silicon layer pattern, thereby forming a doped single-crystalline silicon first semiconductor structure as an active device on the surface of the buried oxide layer of the SOI substrate;

[0030] The forming the first dielectric layer on the surface of the substrate to cover the first semiconductor structure specifically includes:

[0031] Forming a first dielectric layer on the surface of the buried oxide layer to cover the first semiconductor structure.

[0032] Further, the forming the waveguide structure and the window specifically includes:

[0033] Using a high-temperature furnace tube deposition process to form a silicon nitride waveguide layer on the first dielectric layer;

[0034] Performing a partial etching patterning and a partial etching process on the waveguide layer to form a waveguide intermediate structure, and forming a first window on the surface of the waveguide intermediate structure with the bottom surface located in the waveguide layer and making the first window located above the first semiconductor structure between the first contact region and the second contact region;

[0035] Performing a full etching patterning and a full etching process on the waveguide layer to further form a waveguide structure located on the surface of the first dielectric layer and serving as an optical mode matching structure on the basis of the waveguide intermediate structure, and further synchronously forming a second window downward on the basis of the first window with the bottom surface passing through the bottom surface of the waveguide layer and the surface of the first dielectric layer and located on the first semiconductor structure between the first contact region and the second contact region, thereby forming a window formed by the first window and the second window.

[0036] Further, the forming the second semiconductor structure in the window and bringing the second semiconductor structure into contact with the first semiconductor structure located on the bottom surface of the window specifically includes:

[0037] Using an epitaxial process, an intrinsic germanium second semiconductor layer is grown on the top surface of the first semiconductor structure in the window, such that the second semiconductor layer contacts the first contact region and the second contact region on the first semiconductor structure, and fills the window;

[0038] The excess second semiconductor layer outside the window is removed to form a second semiconductor structure as a light receiving portion in the window; and, further comprising:

[0039] A second dielectric layer is formed on the surface of the first dielectric layer, such that the second dielectric layer covers the waveguide structure and the second semiconductor structure as a protective layer;

[0040] Conductive contact holes are formed on the surface of the second dielectric layer, with bottoms respectively connected to the first contact region and the second contact region on both sides of the top surface of the first semiconductor structure.

[0041] Further, when forming the first dielectric layer, a corresponding ratio relationship based on the etching rate ratio between the material of the first dielectric layer and the material of the waveguide layer is formed between a first distance between the surface of the first dielectric layer and the top surface of the first semiconductor structure, and a second distance between the surface of the waveguide layer and the bottom surface of the first window when forming the second window.

[0042] As can be seen from the above technical solutions, in the present invention, by directly providing a window for forming a second semiconductor structure (germanium optical receiving part) on the waveguide structure, an optical mode matching structure located on the waveguide structure can be formed while forming the waveguide. Therefore, the polysilicon material commonly used in manufacturing the optical mode matching structure can be replaced with, for example, silicon nitride material for manufacturing the waveguide. When forming the window, since the window is formed in the waveguide material and the first dielectric layer, only the treatment of the surface of the first semiconductor structure for the bottom surface of the window needs to be considered, thus eliminating the problem of having to simultaneously consider the treatment of the polysilicon sidewalls in the epitaxial window in the past. At the same time, problems such as defects during germanium epitaxy caused by polysilicon in the past are also avoided, thereby reducing the process difficulty, reducing the process risk, and improving the device performance. Moreover, since the use of polysilicon is avoided, a high-quality silicon nitride waveguide layer can be formed by using a high-temperature furnace tube process, and an optical mode matching structure of the same material can be formed. While improving the device responsivity, high-quality waveguides can be provided, thereby improving the device performance, increasing the selection options for device design, and reducing costs. Furthermore, partial etching and full etching steps already existing in the process of manufacturing the waveguide (waveguide structure) can be utilized, and the window (superimposed and repeated etching of the first window and the second window) can be formed by repeating etching in the defined area. Therefore, without using an additional epitaxial window patterning process, the window can be formed while manufacturing the waveguide, thereby further reducing the process cost. Thus, the integration of a high-quality silicon photonics device structure (such as a germanium-based photodetector) compatible with the CMOS process and the silicon photonics high-temperature furnace tube process is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 FIG. is a schematic diagram of a silicon photonics device structure according to a preferred embodiment of the present invention.

[0044] Figures 2 - 10 FIG. is a process flow chart of a method for manufacturing a silicon photonics device structure according to a preferred embodiment of the present invention; wherein, Figure 8 FIG. is a top view showing the relative positions among the silicon nitride waveguide structure (optical mode matching structure), the germanium optical receiving part, and the conductive contact holes, Figure 9 FIG. is Figure 8 a cross-sectional structure schematic diagram taken along the line A-A in FIG., Figure 10 FIG. is Figure 8 a cross-sectional structure schematic diagram taken along the line B-B in FIG. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely below. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art belonging to the field of the present invention. The words such as "including" used herein mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects.

[0046] The following further elaborates on the specific implementation manners of the present invention with reference to the accompanying drawings.

[0047] Reference Figure 1 A silicon photonics device structure of the present invention includes: a substrate 100, a first semiconductor structure 1031 disposed on the substrate 100, a second semiconductor structure 109 disposed on the first semiconductor structure 1031, a waveguide structure 104 disposed above the first semiconductor structure 1031 and on the side of the second semiconductor structure 109, and a first dielectric layer 108 disposed on the substrate 100.

[0048] Among them, the first dielectric layer 108 covers the upper surface of the substrate 100 and encloses the first semiconductor structure 1031 therein. The waveguide structure 104 is disposed on the upper surface of the first dielectric layer 108 and is isolated from the top surface of the first semiconductor structure 1031 by the material of the first dielectric layer 108. A window 105 is disposed on the upper surface of the waveguide structure 104. The bottom surface of the window 105 passes through the upper surface of the first dielectric layer 108 and is located on the top surface of the first semiconductor structure 1031. The second semiconductor structure 109 is filled in the window 105, and the bottom surface of the second semiconductor structure 109 is in contact with the top surface of the first semiconductor structure 1031 located on the bottom surface of the window 105.

[0049] Reference Figure 1 In some embodiments, the first semiconductor structure 1031 includes active devices.

[0050] The second semiconductor structure 109 includes a light receiving portion.

[0051] The waveguide structure 104 includes a light mode matching structure. That is, the light mode matching structure is integrated on the waveguide.

[0052] In some embodiments, the materials of the first semiconductor structure 1031, the second semiconductor structure 109, and the waveguide structure 104 are different from each other. For example, the material of the first semiconductor structure 1031 includes doped single-crystalline silicon; the material of the second semiconductor structure 109 includes intrinsic germanium; the material of the waveguide structure 104 includes silicon nitride formed by a high-temperature furnace tube process. However, it is not limited thereto.

[0053] In some embodiments, the first semiconductor structure 1031 may be a silicon active device. The second semiconductor structure 109 may be a germanium optical receiving part. The waveguide structure 104 may be a silicon nitride waveguide structure 104 integrated with a silicon nitride optical mode matching structure.

[0054] In some embodiments, the substrate 100 includes a SOI substrate 100; the SOI substrate 100 includes a substrate silicon layer 101, a buried oxide layer 102, and a top silicon layer 103. Among them, the first semiconductor structure 1031 is formed on the top silicon layer 103, that is, the first semiconductor structure 1031 is formed by patterning the top silicon layer 103. Therefore, the first dielectric layer 108 can cover both the buried oxide layer 102 and the first semiconductor structure 1031 at the same time.

[0055] Reference Figure 1 In some embodiments, a second dielectric layer 107 is further provided on the surface of the first dielectric layer 108; the second dielectric layer 107 covers the waveguide structure 104 and the second semiconductor structure 109. A plurality of conductive contact holes 106 are provided in the second dielectric layer 107. At the same time, on both sides of the first semiconductor structure 1031, there are a doped first contact region 1032 of the first conductivity type and a doped second contact region 1033 of the second conductivity type. Each conductive contact hole 106 is arranged on both sides of the waveguide structure 104 and is respectively connected to the first contact region 1032 and the second contact region 1033 at the lower end (reference Figure 8 ). The upper end of the conductive contact hole 106 extends out from the upper surface of the second dielectric layer 107. The conductive contact hole 106 may be a tungsten conductive contact hole 106. The first conductivity type may be one of N-type doping and P-type doping, and the second conductivity type may be the other of N-type doping and P-type doping.

[0056] In some embodiments, the material of the first dielectric layer 108 and / or the material of the second dielectric layer 107 includes silicon dioxide or silicon oxynitride, etc., or includes other low dielectric constant materials.

[0057] A metal interconnection layer and other structures may be further provided on the second dielectric layer 107.

[0058] The above silicon optical device structure can be used to form a photodetector, such as a germanium-based photodetector, and can further form a silicon optical optical receiving device.

[0059] The following further elaborates on a method for manufacturing a silicon photonics device structure of the present invention through specific embodiments in combination with the accompanying drawings.

[0060] Reference Figures 2 - 10 . A method for manufacturing a silicon photonics device structure of the present invention can be used to manufacture a silicon photonics device structure of the present invention as described above, for example Figure 1 , and may include the following steps:

[0061] Step S1: Provide a substrate 100.

[0062] As Figure 2 shown, a silicon-on-insulator (SOI) substrate 100 is used to manufacture a silicon photonics device structure of the present invention. The SOI substrate 100 sequentially includes a substrate silicon layer 101, a buried oxide layer 102, and a top silicon layer 103 from bottom to top.

[0063] Step S2: Form a first semiconductor structure 1031 on the substrate 100.

[0064] As Figure 3 shown, first, CMOS-related processes for silicon-based active devices are performed on the SOI substrate 100. Specifically, it includes: using photolithography and etching processes to pattern the top silicon layer 103 of the SOI substrate 100 to form a pattern of the top silicon layer 103 (the pattern of the first semiconductor structure 1031), exposing the upper surface of the buried oxide layer 102. And after cleaning, using ion implantation processes to form a first contact region 1032 doped with the first conductivity type of N-type and a second contact region 1033 doped with the second conductivity type of P-type on both sides of the pattern of the top silicon layer 103 (not shown, please refer to Figure 1 ). Thus, a doped single-crystalline silicon first semiconductor structure 1031 serving as a silicon photonics active device is formed on the surface of the buried oxide layer 102 of the SOI substrate 100.

[0065] Step S3: Form a first dielectric layer 108 on the surface of the substrate 100 to cover the first semiconductor structure 1031.

[0066] As Figure 3 shown, then, using a dielectric deposition process, a first dielectric layer 108 such as silicon dioxide is formed on the upper surface of the SOI substrate 100, that is, a first dielectric layer 108 is formed on the upper surface of the buried oxide layer 102, so that the first dielectric layer 108 covers the buried oxide layer 102 and the first semiconductor structure 1031.

[0067] Among them, the thickness of the first dielectric layer 108 is correlated with the thickness of the waveguide layer formed subsequently, as detailed in the description of the following step S4.

[0068] Step S4: A waveguide structure 104 is formed on the first dielectric layer 108, and a window 105 is formed on the surface of the waveguide structure 104 to isolate the waveguide structure 104 from the first semiconductor structure 1031, and the bottom surface of the window 105 passes through the surface of the first dielectric layer 108 and is located on the first semiconductor structure 1031.

[0069] As Figure 4 shown, then, using a high-temperature furnace tube deposition process, a silicon nitride waveguide layer 1041 is formed on the upper surface of the first dielectric layer 108. The thickness of the silicon nitride waveguide layer 1041 is usually such that the thickness uniformity and the optical refractive index n / optical absorption coefficient k uniformity requirements are less than 0.5% (substrate full-surface uniformity under 1σ condition) to meet the requirements of high-quality silicon nitride waveguides.

[0070] As Figure 5 shown, then, a partial etching patterning and partial etching process are performed on the waveguide layer 1041. This includes: performing a photolithography process on the silicon nitride waveguide layer 1041 to define a partial etching region. This partial etching region needs to include, in addition to the region required for manufacturing the silicon nitride waveguide itself (including the optical mode matching structure), the region required for forming the optical receiving portion, i.e., the epitaxial window 105. Then, using an etching process, part of the silicon nitride material on the waveguide layer 1041 is removed to form the morphology of the waveguide intermediate structure 1042 after partial etching, and a first window 1051 with its bottom surface located in the waveguide layer 1041 is formed on the upper surface of the waveguide intermediate structure 1042. Through photolithography definition, the first window 1051 is located above the first semiconductor structure 1031 between the first contact region 1032 and the second contact region 1033. In this step, the amount of silicon nitride material removed is determined by the design and is usually 30% - 70% of the total thickness of the waveguide layer 1041.

[0071] As Figure 6As shown in the figure, next, the waveguide layer 1041 continues to be fully etched and patterned and the full etching process is carried out. This includes: performing a photolithography process on the silicon nitride waveguide layer 1041 to define the full etching area. The full etching area needs to include, in addition to the area required for manufacturing the silicon nitride waveguide itself (including the optical mode matching structure), the area required for forming the optical receiving part, that is, the epitaxial window 105. Then, using an etching process, all the silicon nitride materials on the defined full etching area are removed to form the required full etching morphology in the silicon nitride waveguide area, that is, on the basis of the waveguide intermediate structure 1042, a waveguide structure 104 located on the surface of the first dielectric layer 108 and serving as an optical mode matching structure is further formed. At the same time, in the defined optical receiving part area (that is, the first window 1051 area), in this step, the material of the first dielectric layer 108 between the bottom surface of the silicon nitride waveguide layer 1041 and the first semiconductor structure 1031 is also removed, and on the basis of the first window 1051, a second window 1052 is further formed downward synchronously through the bottom surface of the waveguide layer 1041 and the surface of the first dielectric layer 108 and located on the first semiconductor structure 1031 between the first contact area 1032 and the second contact area 1033, so as to form a germanium epitaxial window 105 formed by superimposing the first window 1051 and the second window 1052.

[0072] Among them, when forming the first dielectric layer 108, it is necessary to make the thickness of the silicon dioxide first dielectric layer 108 formed in step S3 have a correlation with the thickness of the silicon nitride waveguide layer 1041 formed in this step. That is, it is necessary to make the first distance h between the surface of the first dielectric layer 108 and the top surface of the first semiconductor structure 1031, and the second distance H (that is, the corresponding etching depth when etching the first window 1051) between the surface of the waveguide layer 1041 and the bottom surface of the first window 1051 when forming the second window 1052, form a corresponding ratio relationship based on the etching rate ratio between the silicon dioxide first dielectric layer 108 material and the silicon nitride waveguide layer 1041 material. The purpose is to make a germanium epitaxial window 105 formed after the full etching of silicon nitride, and the over-etching amount caused to the underlying silicon first semiconductor structure 1031 is less, effectively reducing the impact on the first semiconductor structure 1031 as an active device.

[0073] The thickness of the silicon dioxide first dielectric layer 108 can be calculated in the following way:

[0074] For example, for the set thickness of the silicon nitride waveguide layer 1041, assume that of the silicon nitride material is removed during partial etching; during full etching, according to the case where the etching rate ratio of silicon nitride / silicon dioxide is 5:1, the first distance h (thickness) from the surface of the first dielectric layer 108 required to be etched away for window opening to the top surface of the first semiconductor structure 1031 is or so (the second distance H corresponds to ) In this way, it can be ensured that the silicon dioxide material of the first dielectric layer 108 between the bottom surface of the silicon nitride waveguide layer 1041 and the top surface of the first semiconductor structure 1031 is completely etched (etched away) at the defined window 105, and the etching amount of the silicon material of the first semiconductor structure 1031 is small. On this basis, by adding the thickness of the first semiconductor structure 1031 (the top silicon layer 103), the thickness setting value of the first silicon dioxide dielectric layer 108 can be obtained.

[0075] Step S5: Form a second semiconductor structure 109 in the window 105 so that the second semiconductor structure 109 contacts the first semiconductor structure 1031 located on the bottom surface of the window 105.

[0076] As Figure 7 shown, then, using an epitaxial process, an intrinsic germanium second semiconductor layer is grown on the top surface of the first semiconductor structure 1031 in the window 105, so that the intrinsic germanium contacts the first contact region 1032 and the second contact region 1033 on the silicon active device (the first semiconductor structure 1031), and the epitaxial intrinsic germanium second semiconductor layer fills the window 105.

[0077] Among them, the germanium epitaxial process includes steps such as surface pretreatment, low-temperature germanium epitaxy, and high-temperature germanium epitaxy, and annealing is required after epitaxy.

[0078] Then, using a planarization process, the surface of the formed germanium epitaxial second semiconductor layer is planarized. For example, a chemical mechanical polishing method can be used to remove the excess germanium second semiconductor layer material outside the window 105, so that the surface of the germanium second semiconductor layer is flat, thereby forming a germanium second semiconductor structure 109 as the light receiving part in the window 105.

[0079] Furthermore, it also includes:

[0080] Step S6: Form a conductive contact hole 106 on the first semiconductor structure 1031.

[0081] As Figure 9 shown, using a dielectric deposition process, a second dielectric layer 107 is formed on the upper surface of the first dielectric layer 108, so that the second dielectric layer 107 covers the waveguide structure 104 and the second semiconductor structure 109 and can serve as a protective layer.

[0082] After planarizing the surface of the second dielectric layer 107, using a photolithography and etching process, contact hole trenches are formed on the upper surface of the second dielectric layer 107, with the bottoms stopping at the first contact region 1032 and the second contact region 1033 on both sides of the top surface of the first semiconductor structure 1031 respectively.

[0083] Next, a process such as filling the contact hole trench with tungsten contact hole metal is performed to form a conductive contact hole 106 whose bottom is respectively connected to the first contact area 1032 and the second contact area 1033. The top view structure of the completed silicon photonic device is as shown in Figure 8 , which shows the relative positions among the silicon nitride waveguide structure 104 (optical mode matching structure), the germanium optical receiving part (second semiconductor structure 109), and the conductive contact hole 106. Figure 9 shows Figure 8 the cross-sectional structure of the silicon photonic device in the A-A direction in Figure 10 shows Figure 8 the cross-sectional structure of the silicon photonic device in the B-B direction in

[0084] Subsequently, conventional CMOS back-end processes can also be used to further form a metal interconnection layer, etc. on the second dielectric layer 107, which will not be elaborated here.

[0085] The above method of the present invention can fabricate and form a germanium-based photodetector structure as a silicon photonic device, and can further form a silicon photonic optical receiving device.

[0086] In summary, in the present invention, by directly providing a window 105 for forming a second semiconductor structure 109 (germanium optical receiving portion) on the silicon nitride waveguide structure 104, an optical mode matching structure located on the waveguide structure 104 can be formed while forming the waveguide. Therefore, the polysilicon material conventionally used for manufacturing the optical mode matching structure can be replaced with the silicon nitride material for manufacturing the waveguide. When forming the window 105, since the window 105 is formed in the waveguide material and the first dielectric layer 108, only the treatment of the surface of the silicon first semiconductor structure 1031 at the bottom surface of the window 105 needs to be considered, thereby eliminating the problem of having to simultaneously consider the treatment of the polysilicon sidewalls in the epitaxial window 105 in the past. At the same time, problems such as defects during germanium epitaxy caused by polysilicon in the past are also avoided, thereby reducing the process difficulty, reducing the process risk, and improving the device performance. Moreover, since the use of polysilicon is avoided, a high-quality silicon nitride waveguide layer 1041 can be formed by using a high-temperature furnace tube process, and an optical mode matching structure of the same material can be formed. While improving the device responsivity, a high-quality waveguide can be provided, thereby improving the device performance, increasing the selection options for device design, and reducing the cost. Furthermore, partial etching and full etching steps that are already present in the process of manufacturing the waveguide (waveguide structure 104) can be utilized, and the window 105 (superimposed and repeated etching of the first window 1051 and the second window 1052) can be formed by repeating etching in a defined area. Therefore, without using an additional epitaxial window 105 patterning process, the window 105 can be formed while manufacturing the waveguide, thereby further reducing the process cost. The present invention realizes an integrated solution that can simultaneously provide a high-quality silicon nitride waveguide manufactured by a high-temperature furnace tube process and a high-responsivity germanium-based optical detection device, and is compatible with the CMOS process, effectively reducing the process difficulty, reducing the process risk, and improving the overall performance of the device.

[0087] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes fall within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A silicon photonics device structure, characterized in that, it includes: a substrate; a first semiconductor structure disposed on the substrate; a first dielectric layer disposed on the substrate, the first dielectric layer covering the first semiconductor structure; a waveguide structure disposed on the first dielectric layer and isolated from the first semiconductor structure; a window disposed on the surface of the waveguide structure, the bottom surface of the window passing through the surface of the first dielectric layer and located on the first semiconductor structure; a second semiconductor structure disposed in the window, the second semiconductor structure contacting the first semiconductor structure located on the bottom surface of the window.

2. The silicon photonics device structure according to claim 1, characterized in that, the first semiconductor structure includes an active device, the second semiconductor structure includes a light receiving portion, and the waveguide structure includes a light mode matching structure.

3. The silicon photonics device structure according to claim 1, characterized in that, a second dielectric layer is disposed on the surface of the first dielectric layer, the second dielectric layer covering the waveguide structure and the second semiconductor structure, a plurality of conductive contact holes are provided in the second dielectric layer, and a doped first contact region of a first conductivity type and a doped second contact region of a second conductivity type are provided on both sides of the first semiconductor structure, and each of the conductive contact holes is located on both sides of the waveguide structure and is respectively connected to the first contact region and the second contact region.

4. The silicon photonics device structure according to claim 1, characterized in that, the materials of the first semiconductor structure, the second semiconductor structure and the waveguide structure are different from each other, and / or, the material of the first semiconductor structure includes doped single crystal silicon, the material of the second semiconductor structure includes intrinsic germanium, and the material of the waveguide structure includes silicon nitride formed by a high temperature furnace tube process.

5. The silicon photonics device structure according to claim 1, characterized in that, the substrate includes a SOI substrate, the SOI substrate includes a substrate silicon layer, a buried oxide layer and a top silicon layer, the first semiconductor structure is formed on the top silicon layer, and the first dielectric layer covers the buried oxide layer and the first semiconductor structure.

6. A method for manufacturing a silicon photonics device structure, characterized in that, it includes: providing a substrate; forming a first semiconductor structure on the substrate; forming a first dielectric layer on the surface of the substrate to cover the first semiconductor structure; forming a waveguide structure on the first dielectric layer and isolating it from the first semiconductor structure; forming a window on the surface of the waveguide structure so that the bottom surface of the window passes through the surface of the first dielectric layer and is located on the first semiconductor structure; forming a second semiconductor structure in the window so that the second semiconductor structure contacts the first semiconductor structure located on the bottom surface of the window.

7. The method for manufacturing a silicon photonics device structure according to claim 6, characterized in that, the providing the substrate and forming the first semiconductor structure on the substrate specifically includes: providing a SOI substrate, the SOI substrate including a substrate silicon layer, a buried oxide layer and a top silicon layer; Using a photolithography and etching process, pattern the top silicon layer to form a top silicon layer pattern, exposing the surface of the buried oxide layer; Form a doped first contact region of a first conductivity type and a doped second contact region of a second conductivity type on both sides of the top silicon layer pattern, thereby forming a doped single-crystalline silicon first semiconductor structure serving as an active device on the surface of the buried oxide layer of the SOI substrate; Forming a first dielectric layer on the surface of the substrate to cover the first semiconductor structure specifically includes: Form a first dielectric layer on the surface of the buried oxide layer to cover the first semiconductor structure.

8. The method for manufacturing a silicon optical device structure according to claim 7, characterized in that, Forming the waveguide structure and the window specifically includes: Using a high-temperature furnace tube deposition process, form a silicon nitride waveguide layer on the first dielectric layer; Perform partial etching patterning and partial etching process on the waveguide layer to form a waveguide intermediate structure, and form a first window with a bottom surface located in the waveguide layer on the surface of the waveguide intermediate structure, and make the first window located above the first semiconductor structure between the first contact region and the second contact region; Perform full etching patterning and full etching process on the waveguide layer to further form a waveguide structure located on the surface of the first dielectric layer and serving as an optical mode matching structure on the basis of the waveguide intermediate structure, and further synchronously form a second window with a bottom surface passing through the bottom surface of the waveguide layer and the surface of the first dielectric layer on the first semiconductor structure between the first contact region and the second contact region on the basis of the first window, thereby forming a window formed by the first window and the second window.

9. The method for manufacturing a silicon optical device structure according to claim 8, characterized in that, Forming a second semiconductor structure in the window so that the second semiconductor structure contacts the first semiconductor structure located on the bottom surface of the window specifically includes: Using an epitaxial process, grow an intrinsic germanium second semiconductor layer on the top surface of the first semiconductor structure in the window, make the second semiconductor layer contact the first contact region and the second contact region on the first semiconductor structure, and fill the window; Remove the excess second semiconductor layer outside the window to form a second semiconductor structure serving as a light receiving part in the window; and further includes: Form a second dielectric layer on the surface of the first dielectric layer to cover the waveguide structure and the second semiconductor structure as a protective layer; Form conductive contact holes on the surface of the second dielectric layer with bottoms respectively connected to the first contact region and the second contact region on both sides of the top surface of the first semiconductor structure.

10. The method for manufacturing a silicon optical device structure according to claim 8, characterized in that, When forming the first dielectric layer, a corresponding ratio relationship based on the etching rate ratio between the material of the first dielectric layer and the material of the waveguide layer is formed between the first distance between the surface of the first dielectric layer and the top surface of the first semiconductor structure and the second distance between the surface of the waveguide layer and the bottom surface of the first window when forming the second window.

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