An optical chip and a manufacturing method thereof

Abstract

The present invention relates to the technical field of optical chips, and specifically discloses an optical chip and a manufacturing method thereof, which include a multi-layer photonic integrated circuit and an electronic integrated circuit. The multi-layer photonic integrated circuit includes a plurality of sequentially stacked and bonded photonic integrated circuit layers. An optical path for vertical interconnection of optical signals is formed between adjacent photonic integrated circuit layers. The topmost photonic integrated circuit layer is interconnected with the electronic integrated circuit. Free transmission and interconnection of optical signals are realized through multi-layer dielectric waveguides, vertical optical interconnection and optical vias are realized through multi-layer dielectric optical waveguides and structures, and through a multi-layer stacking design, it is convenient to externally connect expansion units, with high design freedom, solving the problem that traditional optical chips with multi-layer structures need to be separately designed for modules for interconnection and have weak adaptability to the current chip architecture.

Description

Technical Field

[0001] This application relates to the technical field of optical chips, and specifically discloses an optical chip and a manufacturing method thereof. Background Art

[0002] With the rapid development of Artificial Intelligence (AI), it is necessary to train and calculate a large amount of data to improve the efficiency of model training and the accuracy of output. However, the processing process requires a large number of linear algebra operations such as matrix multiplication, convolution calculation, and multiply-accumulate operations. These operations require a computing module with high-performance computing power as support.

[0003] In the prior art, parallel optical computing is used as a computing module. With the unique physical properties of photons, compared with analog optical computing and digital optical computing, it is more suitable for the fields of artificial intelligence, big data processing, and high-performance computing. In terms of the speed of matrix multiplication, the single-step operation time of parallel optical computing can reach nanoseconds or even picoseconds, and the bandwidth breaks through 100T bps / mm 2 , and the energy consumption is 1 / 10 of that of an electronic chip. At the same time, the bandwidth of optical interconnection can reach more than 8 Tbps, which is 10 times that of electrical interconnection. And compared with the propagation of an electronic wire of the same length, the propagation delay of an optical fiber is only one-tenth of that of an electronic wire. The signal attenuation of optical interconnection is extremely small at long distances (>1 m), and the energy efficiency is stable at 0.1-1 pJ / bit. In particular, the optical interconnection platform can be compatible with the current electrical interconnection.

[0004] However, the current optical chip architecture increases data movement and memory hierarchy. Due to coherence problems, device losses, and the design of digital-to-analog and analog-to-digital conversion, it is only suitable for low-precision applications and small-scale applications.

[0005] In the prior art, such as Chinese Invention Patent 201911022795.5, a parallel optical computing system for efficiently implementing large-scale matrix operations is disclosed. It is a parallel optical computing system that structures the optical input unit, optical computing unit, and optical output unit through the mode of spatial optics. During the operation process, the data signal does not need to be accessed, and the operation speed is the same as the speed of the optical signal passing through this structure, significantly improving the speed of matrix operations. Through multi-layer design, the input unit and the modulation unit are directly coupled spatially, thereby realizing the integration of storage and computing without an additional storage unit.

[0006] However, during its preparation process, due to signal coupling problems, the precision requirements are relatively high during the interlayer design, and the overall optical chip needs to be designed with a separate module for interconnection, which has weak adaptability to the current chip architecture.

[0007] The present invention provides an optical chip and a manufacturing method thereof to solve the above problems. Summary of the Invention

[0008] The object of the present invention is to solve the problem that a traditional optical chip with a multi-layer structure requires a separate module design for interconnection and has weak adaptability to the current chip architecture.

[0009] To achieve the above object, the basic solution of the present invention provides an optical chip and a manufacturing method thereof, including a multi-layer photonic integrated circuit and an electronic integrated circuit. The multi-layer photonic integrated circuit includes, from top to bottom in sequence:

[0010] A connection layer for transmitting optical signals;

[0011] An intermediate layer for amplifying optical signals;

[0012] A bottom layer for parallel transmission and calculation of optical signals;

[0013] The connection layer, the intermediate layer and the bottom layer are all photonic integrated circuit layers. Optical paths for vertical interconnection of optical signals are formed between the connection layer and the intermediate layer, and between the intermediate layer and the bottom layer. The connection layer is interconnected with the electronic integrated circuit.

[0014] Further, the connection layer is provided with a modulator coupler, a compact splitter, a coupled waveguide and an optoelectronic interconnection electrode for optical signal input / output and optoelectronic conversion;

[0015] The intermediate layer is provided with an input end face coupled amplification waveguide and an output end face coupled amplification waveguide for optical signal amplification and transmission;

[0016] The bottom layer is provided with a cross waveguide matrix and a straight waveguide for parallel transmission and calculation of optical signals;

[0017] There are vertical interconnection incoming light paths between the compact splitter, the input end face coupled amplification waveguide and the cross waveguide matrix, and vertical interconnection outgoing light paths between the cross waveguide matrix, the output end face coupled amplification waveguide and the coupled waveguide.

[0018] Further, the compact splitter includes two groups of splitters respectively arranged on both sides of the connection layer and arranged in horizontal and vertical directions respectively. The coupled waveguide includes a horizontal coupled waveguide and a vertical coupled waveguide connected to one end of the horizontal coupled waveguide. The optoelectronic interconnection electrodes are respectively connected to the non-coupled ends of the horizontal coupled waveguide and the vertical coupled waveguide.

[0019] Further, the input end face coupled amplification waveguide includes a horizontal signal coupling section one and vertical signal coupling sections one connected to both ends;

[0020] The output end-face coupled amplified waveguide includes a second horizontal signal coupling section and second vertical signal coupling sections connected at both ends;

[0021] The first vertical signal coupling section at one end is vertically interconnected with the output optical fiber respectively, and the second vertical signal coupling section at one end is vertically interconnected with the vertical coupling waveguide respectively.

[0022] Furthermore, the cross waveguide matrix includes a number of cross waveguides arranged in a matrix and having adjacent ends interconnected, and the straight waveguide is provided at the connection of the cross waveguides;

[0023] The input ends of the cross waveguide matrix are vertically interconnected with the remaining first vertical signal coupling sections respectively, and the output ends of the cross waveguide matrix are vertically interconnected with the remaining second vertical signal coupling sections respectively.

[0024] Furthermore, a number of extended waveguide layers, all of which are photon integrated circuit layers, are connected between the connection layer and the intermediate layer. Optical coupling is performed between adjacent extended waveguide layers using trapezoidal optical vias and they are arranged in a staggered manner. The area of the coupling surface in the input direction of the trapezoidal optical via is larger than the area of the coupling surface in the output direction.

[0025] Furthermore, a parallel optical computing unit is further provided on the bottom layer. The parallel optical computing unit is a number of micro-ring computing units arranged in an array. The micro-ring computing unit includes a micro-ring coupling waveguide and a phase change material region provided therein for performing phase modulation on an optical signal.

[0026] Furthermore, a parallel optical computing unit is further provided on the bottom layer. The parallel optical computing unit is a number of Mach-Zehnder units arranged in a cascaded structure. The Mach-Zehnder unit includes a Mach-Zehnder coupling element and a thermal phase modulation unit for performing phase shift calculation on an optical signal.

[0027] The basic solution of the present invention further provides a manufacturing method of an optical chip for manufacturing an optical chip as described above, including the following steps:

[0028] Step S01: Deposit a BOX layer, a first waveguide layer, and a first cladding layer on a silicon wafer base layer in sequence. Integrate a pre-designed coupling waveguide, a modulator coupling, and an optoelectronic interconnection electrode in the waveguide layer, and then remove the base layer by polishing to obtain a connection layer;

[0029] Step S02: Deposit a BOX layer, a third waveguide layer, a third cladding layer, a second waveguide layer, and a second cladding layer on a silicon-based wafer base layer in sequence;

[0030] Step S03: Bond the connection layer and the intermediate layer by an end-face bonding technique to obtain a multi-layer photon integrated circuit;

[0031] Step S04: Connect the connection points of the electronic integrated circuit and the optoelectronic interconnection electrodes on the connection layer of the multi-layer photonic integrated circuit to achieve the interconnection between the electronic integrated circuit and the multi-layer photonic integrated circuit, and obtain an optical chip.

[0032] The principle and effect of this solution are as follows:

[0033] Compared with the prior art, the optical chip of the present invention is a high-density and low-loss 3D photon transmission chip. It realizes the free transmission and interconnection of optical signals through multi-layer dielectric waveguides, realizes optical vertical interconnection through multi-layer dielectric optical waveguides and structures, and through multi-layer stacking design, not only reduces data movement and memory hierarchy, improves critical path delay and system energy efficiency, but also facilitates external expansion units, has high design freedom, and solves the problem that the traditional optical chip with a multi-layer structure needs to be separately designed for interconnection and has weak adaptability to the current chip architecture. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0035] Figure 1 Shows a horizontal cross-sectional view of the optical chip in the horizontal direction proposed in the embodiment of the present application;

[0036] Figure 2 Shows a schematic diagram of the end-face signal coupling of the optical chip proposed in the embodiment of the present application;

[0037] Figure 3 Shows a schematic diagram of the intermediate layer and the bottom layer proposed in the embodiment of the present application, where (a) is a schematic diagram of the connection layer, (b) is a schematic diagram of the intermediate layer, and (c) is a schematic diagram of the bottom layer;

[0038] Figure 4 Shows a schematic diagram of the calculation process of the input signal by the cross-waveguide region proposed in the embodiment of the present application;

[0039] Figure 5 Shows a schematic diagram of the optical chip proposed in the embodiment of the present application, where (a) is a schematic diagram of the multi-layer photonic integrated circuit, and (b) is a schematic diagram of the interconnection pins of the electronic integrated circuit;

[0040] Figure 6 Shows a schematic diagram of the optical chip proposed in the embodiment of the present application, where (a) is a schematic diagram of the connection layer, (b) is a schematic diagram of the intermediate layer and the bottom layer, and (c) is a schematic diagram of the interconnection between the electronic basic circuit and the multi-layer photonic integrated circuit;

[0041] Figure 7 The figure shows a schematic diagram proposed in an embodiment of the present application. (a) is a schematic diagram of multi-layer input type signal coupling, and (b) is a schematic diagram of multi-layer input type signal filter coupling;

[0042] Figure 8 The figure shows a schematic diagram of a microring computing unit arranged in an array proposed in an embodiment of the present application;

[0043] Figure 9 The figure shows a schematic diagram of a Mach-Zehnder unit arranged in a cascade structure proposed in an embodiment of the present application. Detailed implementation manners

[0044] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following describes in detail the specific implementation manners, structures, features, and effects thereof according to the present invention in combination with the accompanying drawings and preferred embodiments.

[0045] The reference numerals in the accompanying drawings of the specification include: compact splitter 111, coupled waveguide 112, optoelectronic interconnection electrode 113, input end face coupled amplification waveguide 211, output end face coupled amplification waveguide 212, and cross waveguide 311.

[0046] An optical chip, as shown in the embodiments Figure 1 and Figure 2 as follows:

[0047] The optical chip includes a multi-layer photonic integrated circuit and an electronic integrated circuit. The multi-layer photonic integrated circuit includes, from top to bottom and bonded in sequence:

[0048] A connection layer for transmitting optical signals;

[0049] An intermediate layer for amplifying optical signals;

[0050] A bottom layer for parallel transmission and calculation of optical signals;

[0051] The connection layer, the intermediate layer, and the bottom layer are all photonic integrated circuit layers. Optical paths for vertical interconnection of optical signals are formed between the connection layer and the intermediate layer, and between the intermediate layer and the bottom layer. The connection layer is interconnected with the electronic integrated circuit.

[0052] As shown in Figure 1 and Figure 2 In this embodiment, the multi-layer photonic integrated circuit includes three photonic integrated circuit layers stacked and bonded in sequence. The vertical interconnection manner of optical signals between layers is completed by the optical paths. Under the action of the evanescent field, the input optical signal will be coupled into the waveguide of the adjacent layer, thereby completing the vertical transmission of the optical signal and the output process. In Figure 1 and Figure 2Among them, the dashed line with an arrow represents the propagation direction of the optical signal input, and the curved dashed line between layers represents the coupling of the optical signal from the upper layer to the lower layer during the input process. The solid line with an arrow represents the propagation direction of the optical signal output, and the curved solid line between layers represents the coupling of the optical signal from the lower layer to the upper layer during the output process.

[0053] The multi-layer photonic integrated circuit includes, in sequence and bonded together:

[0054] A connection layer, that is, the first layer of the photonic integrated circuit, the topmost layer, as Figure 3 shown in (a) of the figure, is provided with a first waveguide layer including a modulator coupling fabricated on a silicon material, a compact splitter 111, a coupled waveguide 112 arranged in a matrix, and an optoelectronic interconnection electrode 113 respectively connected between the coupled waveguide 112 and the electronic integrated circuit. The compact splitter 111 includes two groups of splitters respectively arranged on both sides of the connection layer, and are arranged in horizontal and vertical directions respectively.

[0055] Among them, the output optical fibers of the splitter are vertically arranged, and in this embodiment, each splitter is equipped with four output optical fibers. The coupled waveguide 112 includes a horizontal coupled waveguide 112 and a vertical coupled waveguide 112 connected to one end of the horizontal coupled waveguide 112. The optoelectronic interconnection electrodes are respectively connected to the non-coupled ends of the horizontal coupled waveguide 112 and the vertical coupled waveguide 112.

[0056] When outputting data to the next layer, the modulator coupling converts the electrical signal into an optical signal, the optical signal is transmitted based on the input optical fiber of the splitter, and the optical signal is coupled into the next layer by the output optical fiber, thus completing the preliminary output process of the optical signal. When receiving the optical signal input from the next layer, the input optical signal is led out from the corresponding end-face coupled amplification waveguide, received by the vertical coupled waveguide 112 and propagated by the horizontal coupled waveguide 112 to the corresponding optoelectronic interconnection electrode 113 for optoelectronic response, thus completing the calculation and storage in the electronic integrated circuit.

[0057] An intermediate layer, that is, the second layer of the photonic integrated circuit, as Figure 3 shown in (b) of the figure, is provided with a second waveguide layer including an input end-face coupled amplification waveguide 211 and an output end-face coupled amplification waveguide 212 fabricated on a silicon-based material.

[0058] The input end-face coupled amplification waveguide 211 includes a horizontal signal coupling section one and vertical signal coupling sections one respectively connected to both ends of the horizontal signal coupling section one;

[0059] The output end-face coupled amplification waveguide 212 includes a horizontal signal coupling section two and vertical signal coupling sections two respectively connected to both ends of the horizontal signal coupling section two.

[0060] Among them, the arrangement position of the input end-face coupled amplifying waveguide 211 is aligned with the position of the output optical fiber of the splitter, and the arrangement position of the output end-face coupled amplifying waveguide 212 is aligned with the vertical coupling waveguide 112 in the coupling waveguide 112.

[0061] After obtaining the optical signal output from the connection layer in the middle layer, by means of the signal amplification mechanism of the end-face coupling waveguide 112, the signal loss caused by the coupling process is reduced, so as to amplify the input signal and the output signal through the middle layer, and then couple the corresponding signals to the corresponding end-face coupling waveguide 112 area. In this embodiment, the end-face coupling waveguide 112 area refers to the coupling area for coupling the optical signal of the upper layer to the lower layer or coupling the optical signal of the lower layer to the upper layer.

[0062] The bottom layer, that is, the third layer of the photonic integrated circuit layer, as Figure 3 shown in (c) of, is provided with a waveguide layer three including a matrix of cross waveguides 311 made on a silicon-based material and several straight waveguides. The matrix of cross waveguides 311 includes several cross waveguides 311 arranged in a matrix and adjacent ends of which are interconnected, and the straight waveguides are arranged at the connection points of the cross waveguides 311.

[0063] In this embodiment, there are vertically interconnected light input paths between the splitter, the end-face coupled amplifying waveguide, and the matrix of cross waveguides 311, and there are vertically interconnected light output paths between the matrix of cross waveguides 311, the end-face coupled amplifying waveguide, and the coupling waveguide 112.

[0064] The input end-face coupled amplifying waveguide 211 realizes the connection between the first vertical signal coupling section and the end of the corresponding matrix of cross waveguides 311, and the output end-face coupled amplifying waveguide 212 realizes the connection between the end of the corresponding matrix of cross waveguides 311 and the vertical coupling waveguide 112. Specifically, the first vertical signal coupling section at both ends of the input end-face coupled amplifying waveguide 211 is respectively used to connect the first vertical signal coupling section and the input end of the corresponding matrix of cross waveguides 311 to form a light input path, and the second vertical signal coupling section of the output end-face coupled amplifying waveguide 212 is respectively used to connect the vertical coupling waveguide 112 and the output end of the corresponding matrix of cross waveguides 311 to form a light output path.

[0065] The bottom layer receives the optical signal transmitted from the middle layer and performs data multi-dimensional input response in the corresponding cross waveguides 311 along the horizontal and vertical transmission directions. The specific input signal calculation process is as Figure 4 shown. When the input signal is 1, according to the total input dimension, the corresponding output signal is 1 / n of the corresponding serial number.

[0066] The output response of the first column: C1 = 1 × 1 / n;

[0067] The output response of the second column: C2 = 1 × 1 / (n - 1);

[0068] Output response of the third column: C3 = 1 × 1 / (n - 2); .....

[0069] Output response of the nth column: Cn = 1;

[0070] The response effect of the vertical input signal is the same as that of the horizontal input signal. The input signal obtains the corresponding output response signal through the designed n-dimensional output circuit, and the output response signal is transmitted along the end-face coupled amplification waveguide, the vertical coupling waveguide 112, and the horizontal coupling waveguide 112 to the optoelectronic interconnection electrode 113 on the connection layer for electrical signal conversion, and finally the calculation is completed in the electronic integrated circuit.

[0071] The basic solution of this application also provides a manufacturing method of an optical chip for manufacturing the above-mentioned optical chip, including the following steps:

[0072] Step S01: According to Figure 6 the pattern shown in (a) of , deposit a BOX layer, a first waveguide layer, and a first cladding layer on the silicon wafer in sequence, integrate the pre-designed coupling waveguide 112, modulator coupling, and optoelectronic interconnection electrode 113 in the waveguide layer, and then remove the base layer by grinding and polishing to obtain a connection layer;

[0073] Step S02: According to Figure 6 the pattern shown in (b) of , deposit a BOX layer, a third waveguide layer, a third cladding layer, a second waveguide layer, and a second cladding layer on the silicon-based wafer in sequence. And the thickness of the oxide layer needs to be consistent with the designed end-face gap (coupling width) to obtain the connected intermediate layer and bottom layer;

[0074] Step S03: According to Figure 6 the pattern shown in (c) of , bond the connection layer and the intermediate layer through the end-face bonding technology to obtain a multi-layer photonic integrated circuit. The multi-layer chip design allows reducing the output coverage area and loss, and its structural schematic diagram is as shown in Figure 5 the pattern shown in (a) of . Among them, the bending waveguide radius of the splitter is designed to be 9 - 14 μm, the waveguide width is designed to be 1 - 6 μm, and the thickness is designed to be 0.4 - 4 μm.

[0075] Step S04: Connect the connection points of the electronic integrated circuit and the optoelectronic interconnection electrode 113 on the connection layer of the multi-layer photonic integrated circuit to realize the interconnection of the electronic integrated circuit and the multi-layer photonic integrated circuit as shown in Figure 6 the pattern shown in (c) of , and obtain an optical chip. Among them, the schematic diagram of the interconnection pins of the electronic integrated circuit is as shown in Figure 5 the pattern shown in (b) of .

[0076] When the above solution is used, the connection layer receives optical signals, including input response signals and weight signals, and couples them into the silicon-based chip of the middle layer along the horizontal and vertical directions respectively. With the help of the input end-face coupling and amplifying waveguide 211 in the middle layer, the power is amplified, and the amplified signal is end-face coupled along the middle layer to the bottom layer;

[0077] In the bottom layer, the input signals are matrixed and output by means of the cross waveguide 311. The completed optical signal matrix is propagated and amplified to the silicon-based chip of the middle layer. After the signal is amplified by the output end-face coupling and amplifying waveguide 212 in the middle layer, it is propagated to the vertical coupling waveguide 112 and the horizontal coupling waveguide 112 of the connection layer. Finally, the connection layer performs the optical-to-electrical signal conversion process on the received optical signals by means of the optoelectronic interconnection electrode 113 structure, and accumulates and stores the obtained output optical signals in the electronic integrated circuit.

[0078] In some embodiments, as Figure 7 shown in (a) of, the connection layer has a 3D stacked structure and is provided with multiple layers of extended waveguides as output response structures. In this output response structure, the output signals are not limited to single-layer input responses. Multiple signal outputs can also be designed according to different layers by means of multiple layers of extended waveguides, so as to achieve data calculation tasks with higher output density.

[0079] As Figure 7 shown in the schematic diagram shown in (a) of, the signal output layer is provided with a total of 3 layers of silicon waveguides, including the connection layer and two layers of extended waveguide layers connected below the connection layer. The extended waveguide layers are also photon integrated circuit layers. Of course, in other embodiments, they can also be any other number of layers.

[0080] Through the interlayer network, the original single-layer n-dimensional output can be extended to a 3×n-dimensional output to improve the signal output and input accommodation capabilities of the entire optical chip. Moreover, adjacent levels are arranged in a staggered manner to avoid signal crosstalk generated during single-layer high-density layout, avoid crosstalk defects, and achieve high-fidelity and high-density signal output. And, as Figure 7 shown in (a) of, a trapezoidal optical via is used between adjacent levels to form an optical channel, thereby completing the optical coupling process. Specifically, the area of the coupling surface in the input direction of the trapezoidal optical via is larger than the area of the coupling surface in the output direction.

[0081] In some embodiments, a staggered design is also adopted between adjacent levels in other photon integrated circuit layers to achieve high-integration response of input signals and calculation signals and achieve high computing performance.

[0082] In some embodiments, other layer photon integrated circuits may also be successively stacked and bonded between the connection layer and the intermediate layer, including successively stacking and bonding other photon integrated circuits for realizing data input, optical computing unit coupling, and having multifunctional transmission functions.

[0083] In some embodiments, a parallel optical computing unit is further provided on the bottom layer and is made on a silicon-based material.

[0084] In some embodiments, the parallel optical computing unit is a plurality of microring computing units arranged in an array. As Figure 8 shown, the microring computing units are arranged in an array between the cross-waveguide 311 matrices. Each microring computing unit includes a microring coupling waveguide 112 and a phase change material region provided in the middle section of the microring coupling waveguide 112. The two ends of the microring coupling waveguide 112 are arranged in horizontal and vertical directions respectively. During the parallel optical computing process, when the optical signal passes through the microring, it will be affected by the phase change material and thus undergo phase modulation. The phase-modulated optical signal is the corresponding matrix calculation result, and the output optical signal is the collection of these phases. Accumulating the collections of different phases is the final output result of the optical parallel computing, which is stored and displayed in the electronic integrated circuit.

[0085] After the horizontal input signal is input, a part (1 / n, 1 / (n - 1), …, 1) will be calculated in the corresponding microring computing unit. After the calculation is completed, it will be transmitted along the vertical direction, and the optical signal will be accumulated and output in the electronic integrated circuit after being output.

[0086] In some embodiments, the parallel optical computing unit is a Mach-Zehnder unit arranged in a cascade structure. A plurality of Mach-Zehnder units arranged in a cascade structure are arranged in a multi-level cascade manner in the horizontal direction and in a cross-interconnection manner in the vertical direction. Specifically, the Mach-Zehnder unit includes a Mach-Zehnder coupling element and a thermal phase modulation unit. As Figure 9 shown, the Mach-Zehnder coupling element divides the optical signal into two paths and recombines them after passing through the thermal phase modulation unit. Among them, φ and 2θ are the introduced phase offsets respectively.

[0087] In the bottom layer, with the help of a photomultiplier composed of a microring computing unit arranged in an array or a Mach-Zehnder unit arranged in a cascade structure, etc., the input optical signal completes multiplication calculation in the bottom layer. After the calculation is completed, the optical signal is output to the optoelectronic converter and is interconnected, stored, and displayed in the electronic integrated circuit.

[0088] At the same time, a 3D packaging technology is used to realize high-speed optical interconnection between the multi-layer photon integrated circuit and the electronic integrated circuit to reduce the crosstalk effect, thereby realizing high-speed optoelectronic conversion response and obtaining high-speed interconnection.

[0089] The optical chip of the present invention reduces data movement and memory hierarchy through a multi-layer stacking design, thereby improving critical path delay and system energy efficiency. It has high scalability characteristics, operates at a higher speed and lower energy per MAC operation, and has relatively minimal output energy, further improving computational accuracy. The chip has the characteristics of high integration and hybrid interconnection, as well as the hybrid use of extended optical computing units, with high design freedom. The chip has a coupled amplification gain characteristic, which can effectively reduce the optical power loss defect during transmission.

[0090] The optical chip provided by the present invention is a high-density and low-loss 3D photon transmission chip that realizes free transmission and interconnection of optical signals through multi-layer dielectric waveguides, and realizes vertical interconnection of light through multi-layer dielectric optical waveguides and structures, including optical paths and optical vias (stepped optical vias).

[0091] The above are only the preferred embodiments of the present invention, and there is no any form of limitation to the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the equivalent embodiments by using the above-disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. An optical chip, characterized in that, It includes a multi-layer photonic integrated circuit and an electronic integrated circuit. The multi-layer photonic integrated circuit includes, from top to bottom, sequentially bonded: A connection layer for transmitting optical signals; An intermediate layer for amplifying optical signals; A bottom layer for parallel transmission and calculation of optical signals; The connection layer, the intermediate layer, and the bottom layer are all photonic integrated circuit layers. Optical paths for vertical interconnection of optical signals are formed between the connection layer and the intermediate layer, and between the intermediate layer and the bottom layer. The connection layer is interconnected with the electronic integrated circuit; The connection layer is provided with a modulator coupling, a compact splitter, a coupled waveguide, and an optoelectronic interconnection electrode for optical signal input / output and optoelectronic conversion; The intermediate layer is provided with an input end face coupled amplification waveguide and an output end face coupled amplification waveguide for optical signal amplification and transmission; The bottom layer is provided with a cross waveguide matrix and a straight waveguide for parallel transmission and calculation of optical signals; There are vertically interconnected light input paths between the compact splitter, the input end face coupled amplification waveguide, and the cross waveguide matrix, and vertically interconnected light output paths between the cross waveguide matrix, the output end face coupled amplification waveguide, and the coupled waveguide; The compact splitter includes two groups of splitters respectively arranged on both sides of the connection layer, and are arranged in horizontal and vertical directions respectively. The coupled waveguide includes a horizontal coupled waveguide and a vertical coupled waveguide connected to one end of the horizontal coupled waveguide. The optoelectronic interconnection electrodes are respectively connected to the non-coupled ends of the horizontal coupled waveguide and the vertical coupled waveguide; The input end face coupled amplification waveguide includes a horizontal signal coupling section one and vertical signal coupling sections one connected to both ends; The output end face coupled amplification waveguide includes a horizontal signal coupling section two and vertical signal coupling sections two connected to both ends; One end of the vertical signal coupling section one is respectively vertically interconnected with the output optical fiber, and one end of the vertical signal coupling section two is respectively vertically interconnected with the vertical coupled waveguide.

2. A photonic chip according to claim 1, characterized in that, The cross waveguide matrix includes a plurality of cross waveguides arranged in a matrix and having adjacent ends interconnected, and the straight waveguide is provided at the connection of the cross waveguides; The input ends of the cross waveguide matrix are respectively vertically interconnected with the remaining vertical signal coupling sections one, and the output ends of the cross waveguides are respectively vertically interconnected with the remaining vertical signal coupling sections two.

3. A photonic chip according to claim 1, wherein There are several extended waveguide layers, all of which are photonic integrated circuit layers, connected between the connection layer and the intermediate layer. Optical coupling is performed between adjacent extended waveguide layers using trapezoidal optical vias and they are arranged in a staggered manner. The area of the input direction coupling surface of the trapezoidal optical via is larger than the area of the output direction coupling surface.

4. A optical chip according to claim 1, wherein The bottom layer is further provided with a parallel optical computing unit. The parallel optical computing unit is a plurality of micro-ring computing units arranged in an array. The micro-ring computing unit includes a micro-ring coupled waveguide and a phase change material region provided therein for performing phase modulation on optical signals.

5. A photonic chip according to claim 1, characterized in that The bottom layer is further provided with a parallel optical computing unit. The parallel optical computing unit is a plurality of Mach-Zehnder units arranged in a cascaded structure. The Mach-Zehnder unit includes a Mach-Zehnder coupling element and a thermal phase modulation unit for performing phase shift calculation on optical signals.

6. A manufacturing method of an optical chip, for manufacturing an optical chip as described in claim 1, characterized in that, It includes the following steps: Step S01: Deposit a BOX layer, a first waveguide layer, and a first cladding layer on a silicon wafer substrate layer in sequence. Integrate pre-designed coupled waveguides, modulator couplings, and optoelectronic interconnection electrodes in the waveguide layer. Then, remove the substrate layer by grinding and polishing to obtain a connection layer. Step S02: Deposit a BOX layer, a third waveguide layer, a third cladding layer, a second waveguide layer, and a second cladding layer on a silicon-based wafer substrate layer in sequence. Step S03: Bond the connection layer and the intermediate layer through an end-face bonding technique to obtain a multi-layer photonic integrated circuit. Step S04: Connect the connection points of the electronic integrated circuit and the optoelectronic interconnection electrodes on the connection layer of the multi-layer photonic integrated circuit to achieve the interconnection between the electronic integrated circuit and the multi-layer photonic integrated circuit, and obtain an optical chip.

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