On-chip optical half adder arithmetic unit

Abstract

The invention discloses an on-chip optical half adder arithmetic unit, and belongs to the field of optical devices, the on-chip optical half adder arithmetic unit comprises a substrate and an optical waveguide structure arranged on the substrate, the optical waveguide structure comprises an input port connected with an optical signal input end, a multimode diffraction region containing three diffraction layers, and an output port connected with an optical signal output end; incident light signals enter the multimode diffraction region through the input port to be diffracted and propagated to the first diffraction layer, after the incident light signals are emitted from the third diffraction layer, the light propagates for a certain distance to reach the three specific detector regions of the output port, and the propagation of the light in the diffraction region is changed by changing the length of the diffraction grooves, so that a preset arithmetic result is achieved. The on-chip optical diffraction half adder arithmetic unit has the advantages of being small in size, simple in structure, easy to manufacture and the like, has good expansibility and is suitable for large-scale integration.

Description

Technical Field

[0001] The present invention relates to the technical field of optical devices, and particularly relates to an on-chip optical half adder arithmetic unit. Background Art

[0002] As the process of electronic transistors gradually approaches the limit and the quantum effect is significant, processors based on electrons have encountered an unsustainable bottleneck in performance growth. In addition, different from traditional computing, more than 80% of the computing volume in artificial neural networks comes from calculations such as matrix transformation and logical operations. In an electronic integrated chip, the implementation forms of these operations are relatively complex, and simple operations require a large number of transistors to complete, resulting in high power consumption of electronic computing, and at the same time, the computing speed, fidelity, etc. are greatly reduced. In addition, due to the separation of the storage unit and the computing unit in the existing von Neumann architecture processors, tidal data loads will occur during large-scale data operations, which have problems such as high power consumption, slow speed, and low bandwidth, and can no longer meet the needs of large-scale artificial neural networks for ultra-high-speed and low-latency massive data processing.

[0003] Compared with traditional integrated circuits, optical computing performs calculations with photons instead of electrons, and calculations such as dense matrix multiplication and logical operations, which are the most energy-consuming and time-consuming in artificial neural networks, can be carried out at the speed of light. In addition, optical computing also has the advantages of low power consumption, low latency, high bandwidth, and high parallelism. Facing the continuously upgraded computing power requirements in deep learning, optical computing is expected to become a training execution platform for a new generation of artificial intelligence technologies, and is regarded as one of the effective ways to break through Moore's law in the field of artificial intelligence, and is one of the important development directions in the future of the field of artificial intelligence and high-performance computing. Summary of the Invention

[0004] The present invention provides an on-chip optical half adder arithmetic unit, which realizes the function of half adder arithmetic. The on-chip optical diffraction half adder arithmetic unit has the advantages of small volume, simple structure, easy manufacturing, etc., and at the same time has good scalability and is suitable for large-scale integration.

[0005] An embodiment of the present invention provides an on-chip optical half adder arithmetic unit, including: a substrate and an optical waveguide structure disposed on the substrate. The optical waveguide structure includes three optical input ports connected in sequence, a multimode diffraction region, and three optical output ports. The three optical output ports are connected to the end of the multimode diffraction region through three reverse tapers;

[0006] The three optical input ports are respectively defined as the input port of the augend of the optical half adder, the input port of a constant reference bias signal, and the input port of the addend of the optical half adder;

[0007] The multimode diffraction region includes three diffraction layers, which are arranged one after another in the diffraction region of the optical waveguide structure in the forward propagation direction of the optical signal. Each diffraction layer contains multiple diffraction slots, and the continuous phase adjustment of the incident light phase from 0 to 2π is achieved by adjusting the length of the diffraction slots.

[0008] The three optical output ports are respectively defined as the logic 0 port, the logic 1 port, and the high-order carry output port of the optical half adder and the number output terminal. When there is an optical signal input to the high-order carry port, it represents logic 1, and when there is no optical signal input, it represents logic 0.

[0009] Optionally, in an embodiment of the present invention, among the optical input signals of the three optical input ports, according to the truth table of the half adder function, the phase of the optical input signal is modulated. The logic 0 of the addend input port and the addend input port is mapped to phase 0, and the logic 1 is mapped to phase π. The input port of the reference constant bias signal is constantly logic 1, that is, phase π.

[0010] Optionally, in an embodiment of the present invention, the particle swarm optimization algorithm is used to determine the length of the diffraction slot, so as to realize the continuous phase adjustment of the input light phase from 0 to 2π, thereby controlling the propagation direction of the input light and making the input light reach the corresponding output port to realize the corresponding arithmetic operation function.

[0011] Optionally, in an embodiment of the present invention, the optimization process of the particle swarm optimization algorithm includes:

[0012] Initialization setting: Randomly generate a number of particles, and randomly initialize the particle positions and movement speeds.

[0013] Particle fitness calculation and speed update: Calculate the fitness according to the current position of the particle, recalculate the particle movement speed and update the particle position.

[0014] Optimal position update: Compare the fitness of the particle at the current position with the historical optimal fitness, and update the optimal position.

[0015] Optimal solution return: When the performance of the on-chip optical half adder operation unit converges to the expected range or the algorithm reaches the maximum number of iterations, the iteration stops, and the historical optimal position is returned as the optimal solution to obtain the length of the diffraction slot.

[0016] Optionally, in an embodiment of the present invention, the wavelength of the optical input signal is 1550 nm.

[0017] Optionally, in an embodiment of the present invention, each diffraction layer contains 18 diffraction slots.

[0018] The on-chip optical half adder arithmetic unit according to the embodiment of the present invention realizes the half adder function by presetting the output results under different input optical signals. Through the particle swarm optimization algorithm, by changing the length of the diffraction slots in the multimode diffraction region, the propagation direction of the incident light is controlled and made to reach the corresponding output port, thereby realizing the corresponding arithmetic operation function. And gradually optimize and improve the effective output power difference, and finally realize the design of the optical half adder arithmetic unit with high contrast.

[0019] Additional aspects and advantages of the present invention will be given in part in the following description, will become apparent in part from the following description, or will be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the drawings, in which:

[0021] Figure 1 Schematic structural diagram of an on-chip optical half adder arithmetic unit according to an embodiment of the present invention;

[0022] Figure 2 Top view of the on-chip optical half adder arithmetic unit according to an embodiment of the present invention;

[0023] Figure 3 Schematic diagram of the input port and output port according to an embodiment of the present invention;

[0024] Figure 4 Schematic diagram of the particle swarm algorithm according to an embodiment of the present invention;

[0025] Figure 5 Schematic diagram of the truth table of the structure of the on-chip optical half adder arithmetic unit according to an embodiment of the present invention;

[0026] Figure 6 GDS layout of the structure of the on-chip optical half adder arithmetic unit according to an embodiment of the present invention.

[0027] Description of reference numerals: substrate - 1, optical waveguide structure - 2, optical input port - 3, multimode diffraction region - 4, optical output port - 5, reverse cone - 6. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the drawings, in which the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0029] Figure 1 Schematic structural diagram of an on-chip optical half adder arithmetic unit according to an embodiment of the present invention.

[0030] As Figure 1 shown, the on-chip optical half adder arithmetic unit includes: a substrate 1 and an optical waveguide structure 2 disposed on the substrate 1. The optical waveguide structure 2 includes three optical input ports 3, a multimode diffraction region 4, and three optical output ports 5 that are connected in sequence. The three optical output ports 5 are connected to the end of the multimode diffraction region 4 through three reverse tapers 6. As Figure 2 shown, it is a top view of this structure.

[0031] As Figure 3 shown, the three optical input ports are respectively defined as the addend input port of the optical half adder, the input port of the constant reference bias signal, and the addend input port of the optical half adder.

[0032] The multimode diffraction region includes three diffraction layers. The three diffraction layers are arranged one after another in the diffraction region of the optical waveguide structure in the forward propagation direction of the optical signal. Each diffraction layer contains a plurality of diffraction slots, and the incident light phase is continuously adjusted from 0 to 2π by adjusting the diffraction slot length.

[0033] The three optical output ports are respectively defined as the logic 0 port, the logic 1 port, and the high-order carry output port of the sum output terminal of the optical half adder. When there is an optical signal input to the high-order carry port, it represents logic 1, and when there is no optical signal input, it represents logic 0, reducing beam splitting and improving the resolution of the output. The arithmetic result of the output is confirmed by the light intensity of the optical signal at the output port.

[0034] The three optical input ports are connected to the optical signal input, and the three optical output ports are connected to the optical signal output. The incident optical signal enters the multimode diffraction region through the optical input port and diffracts and propagates to the first diffraction layer. A plurality of diffraction slots are included on one diffraction layer. When the incident light exits from the first diffraction layer, the incident light is preliminarily phase and amplitude modulated. The exiting light serves as a new wavelet source and is connected to other diffraction slots of the second diffraction layer through diffraction. After exiting from the second diffraction layer, the exiting light serves as a new wavelet source and is connected to other diffraction slots of the third diffraction layer through diffraction. After exiting from the third diffraction layer, the exiting light is directionally output to ensure that it has a high light intensity in a specific direction, and the light propagates a certain distance to reach three specific detector regions of the output port. A balanced photodiode (BPD) is connected to the output port to obtain the output power of the corresponding port. By changing the length of the diffraction slot, the propagation of light in the diffraction region is changed, so as to achieve a preset arithmetic result, and further improve the effective output power difference of the mode field of the output light through an improved particle swarm optimization algorithm.

[0035] The present invention adopts two judgment methods at the output port. For the judgment of the local bit and sum, two ports are respectively used to represent the output of logic 0 and logic 1 for judgment, while for the carry output, a single port is used for output. The presence of an optical signal input represents logic 1, and the absence of an optical signal input represents logic 0. At the same time, when the present invention outputs results of 00, 01, and 10, there is only one output port with an optical signal, which can effectively reduce beam splitting and improve the resolution of the output port. The on-chip optical diffraction half adder arithmetic unit can realize the arithmetic operation function of the half adder. The on-chip optical diffraction half adder arithmetic unit has the advantages of small volume, simple structure, and easy manufacturing. At the same time, it has good scalability and is suitable for large-scale integration.

[0036] In an embodiment of the present invention, a diffraction layer contains 18 diffraction grooves. By means of an appropriate number of diffraction grooves, the brightness of the sub-wave sources after diffraction is higher, so as to improve the light intensity of the final output port. It is prepared by etching on the top layer of silicon. In this structure, the length of the diffraction groove is an adjustable parameter, while the height and width are fixed parameters, and the phase of the incident light can be continuously adjusted from 0 to 2π. By changing the length of the diffraction groove, the propagation of light in the diffraction region is changed, the propagation direction of the incident light is controlled, and it is made to reach the corresponding output port, thereby realizing the corresponding arithmetic operation function. Through the regulation of the length of the diffraction groove, the arithmetic operation of the half adder can be realized.

[0037] In an embodiment of the present invention, the wavelength of the input optical signal is 1550 nm.

[0038] In an embodiment of the present invention, among the optical input signals at the three optical input ports, according to the truth table of the half adder function, the phases of the optical input signals are modulated. The logic 0 of the addend input port and the augend input port are mapped to phase 0, and the logic 1 is mapped to phase π. The input port with a constant reference bias signal is constantly at logic 1, that is, phase π.

[0039] In an embodiment of the present invention, as Figure 4 shown, the particle swarm optimization algorithm is used to determine the length of the diffraction groove, so as to realize the continuous phase adjustment of the input light phase from 0 to 2π, thereby controlling the propagation direction of the input light and making the input light reach the corresponding output port, and realizing the corresponding arithmetic operation function. By using the particle swarm optimization algorithm to adjust the length of the diffraction groove in this structure and gradually optimize and improve the effective output power difference, the design of the on-chip optical diffraction half adder arithmetic unit with high contrast is finally realized. The truth table of the realized function is as Figure 5 shown.

[0040] Specifically, the implementation of the half - adder function is achieved by presetting the output results under different input optical signals. Using the particle swarm optimization algorithm, by adjusting the diffraction slot length in this structure, continuous phase adjustment of the incident light from 0 to 2π can be performed, thereby controlling the propagation direction of the incident light and making it reach the corresponding output port, thus realizing the corresponding arithmetic operation function. And gradually optimize and improve the effective output power difference, and finally realize the design of the on - chip optical diffraction half - adder operation unit with high contrast.

[0041] In the embodiment of the present invention, the optimization process of the particle swarm optimization algorithm includes:

[0042] Initialization setting: Randomly generate a number of particles, and randomly initialize the particle positions and movement speeds;

[0043] Particle fitness calculation and speed update: Calculate the fitness according to the current particle position, recalculate the particle movement speed and update the particle position;

[0044] Optimal position update: Compare the fitness of the particle at the current position with the historical optimal fitness, and update the optimal position;

[0045] Optimal solution return: When the performance of the on - chip optical half - adder operation unit converges to the expected range or the algorithm reaches the maximum number of iterations, the iteration stops, and the historical optimal position is returned as the optimal solution to obtain the diffraction slot length.

[0046] In a specific embodiment of the present invention, to implement the 0 + 1 operation in the half - adder function, an optical signal with a wavelength of 1550 nm and a phase of 0 is incident on the input port of the augend. An optical signal with a wavelength of 1550 nm and a phase of π is incident on the input port of the addend. A constant reference bias signal is constantly incident on the input port with a wavelength of 1550 nm and a phase of π. The optical signal carrying the phase information is input through the input port and propagates forward to the multimode diffraction region in the optical waveguide structure, first reaching the first diffraction layer. When the incident light exits from the first diffraction layer, the exiting light serves as a new wave source and is connected to other diffraction slots in the second diffraction layer through diffraction. After exiting from the second diffraction layer, the exiting light serves as a new wave source and is connected to other diffraction slots in the third diffraction layer through diffraction. After exiting from the third diffraction layer, the light propagates a certain distance to reach three specific detector regions at the output port. A balanced photodiode (BPD) is connected to the output port to obtain the output power of the corresponding port. According to the comparison of the output powers of different output ports, it can be judged whether the operation result is correct. By analogy, for the remaining three input cases, the optical signals can be input in sequence according to this logic. The GDS layout of the on - chip optical half - adder operation unit structure is as Figure 6 shown.

[0047] The on-chip optical half adder arithmetic unit proposed according to the embodiments of the present invention has the advantages of small volume, simple structure, easy manufacturing, etc. At the same time, it has good scalability and is suitable for large-scale integration.

[0048] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or N embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0049] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0050] Any process or method description shown in the flowchart or described in other ways herein can be understood as representing a module, segment, or part of code including one or N executable instructions for implementing a customized logic function or process, and the scope of the preferred embodiments of the present invention includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in the reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

Claims

1. An on-chip optical half adder computing unit, characterized in that: The invention comprises: a substrate and an optical waveguide structure arranged on the substrate, wherein the optical waveguide structure comprises three optical input ports, a multimode diffraction region and three optical output ports connected in sequence, wherein the three optical output ports are connected to the ends of the multimode diffraction region through three reverse cones; The three optical input ports are respectively defined as a summand input port of the optical half adder, an input port of a constant reference bias signal, and an addend input port of the optical half adder; The multimode diffraction region includes three diffraction layers, which are arranged in a tandem in the diffraction region of the optical waveguide structure according to the direction of forward propagation of the optical signal, and each diffraction layer contains a plurality of diffraction grooves, and the phase of the incident light is continuously adjusted from 0 to 2π by adjusting the length of the diffraction grooves; The three optical output ports are defined as a logic 0 port, a logic 1 port and a high-order carry output port of an optical half adder and a digital output port, respectively. The high-order carry port indicates logic 1 when there is an optical signal input, and indicates logic 0 when there is no optical signal input.

2. The on-chip optical half adder computing unit according to claim 1, characterized in that: In the optical input signals of the three optical input ports, the phases of the optical input signals are modulated according to the half adder function truth table, the logic 0 of the addend input port and the addend input port is mapped to phase 0, the logic 1 is mapped to phase π, and the input port of the constant reference bias signal is constantly at logic 1, that is, phase π.

3. The on-chip optical half adder computing unit according to claim 1, characterized in that: The length of the diffraction slot is determined by the particle swarm optimization algorithm, so that the input light phase can be continuously adjusted from 0 to 2π, thereby controlling the propagation direction of the input light and making the input light reach the corresponding output port, realizing the corresponding arithmetic operation function.

4. The on-chip optical half adder computing unit according to claim 1, characterized in that: The optimization process of particle swarm optimization algorithm includes: Initialization settings: randomly generate a number of particles, and randomly initialize the particle positions and movement speeds; Particle fitness calculation and speed update: Calculate the fitness according to the current position of the particle, recalculate the particle movement speed and update the particle position; Optimal position update: compare the particle fitness at the current position with the historical optimal fitness and update the optimal position; Optimal solution return: When the performance of the on-chip optical half-adder operation unit converges to the expected range or the algorithm reaches the maximum number of iterations, the iteration stops and returns the historical optimal position as the optimal solution to obtain the diffraction slot length.

5. The on-chip optical half adder computing unit according to claim 1, characterized in that: The wavelength of the optical input signal is 1550nm.

6. The on-chip optical half adder computing unit according to claim 1, characterized in that: Each diffraction layer contains 18 diffraction grooves.

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