Reconfiguration system with multiple storage modes, access method, equipment, medium and product

Abstract

The invention discloses a reconstruction system of multiple storage modes, an access method, equipment, a medium and a product, relates to the technical field of electronic information, and compared with the condition that the conventional different storage modes correspond to different storage spaces, so that the storage resource overhead is relatively large, multiple storage modes share one preset storage space, and the storage efficiency is improved. And the storage resource overhead is reduced while the storage space is saved. The current data storage state of the preset storage space can be determined in real time through hardware design adjustment by adopting a corresponding connection mode of the comparator, the phase inverter and the buffer group, so that the judgment accuracy is improved, the transmission delay is reduced, and the system reliability is improved. Different access storage modes can be selected by the multiple storage modes through selection signals, and meanwhile, the two access storage modes can be switched randomly, so that different storage modes can be realized, and the flexibility of data storage access can be improved.

Description

Technical Field

[0001] The present application relates to the field of electronic information technology, and in particular to a reconstruction system, access method, device, medium and product of multiple storage modes. Background Art

[0002] In the field of digital circuit design, data is stored in storage modes corresponding to various volatile storage units (such as random access memory (RAM), first in first out memory (FIFO), etc.). At the same time, the storage space of various volatile storage units is set to meet the use requirements of different storage modes, that is, each volatile storage unit occupies a storage space, which means that when data is stored in the corresponding storage space according to storage mode A at the same time, the storage space stored according to storage mode B will be idle and wasted, resulting in a large storage overhead.

[0003] Therefore, how to reduce storage overhead to save storage space is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] The present application provides a reconstruction system, access method, device, medium and product of multiple storage modes to at least solve the problem of large storage overhead of multiple storage modes occupying different storage spaces in the related art.

[0005] The present application provides a reconstruction system of multiple storage modes, including a storage module with a counting unit, wherein the counting unit includes a comparator, an inverter and a buffer group; the multiple storage modes include at least a random access storage mode and a sequential access storage mode: the random access storage mode and the sequential access storage mode share the same preset storage space; The input end of the buffer group is connected to the comparator, and the enable end is connected to the inverter, for outputting a data count mark of a current access operation; the comparator receives a storage quantity signal of a preset storage space and a threshold signal to determine a current access operation; the inverter receives a storage mode selection signal; The buffer group corresponds to the random access storage mode when in a blocked state; and corresponds to the sequential access storage mode when in a conducting state, so that the access device can access and process the target data according to the current access operation and the data counting mark.

[0006] This application provides a data access method in multiple storage modes, including: Get the current access operation and target data; In the sequential access storage mode, access processing is performed on the target data according to the current access operation and the data count mark; wherein, the logical circuit function corresponding to the data count mark is implemented by the reconstruction system of the multiple storage modes.

[0007] This application also provides a true random number access method, including: Obtain a true random number; When the true random number causes data congestion, suspend access processing on the true random number; When the true random numbers are not continuous, obtain an alternative data source to replace the true random numbers, and perform access processing using the replaced true random numbers; wherein, the process of the true random number access processing is completed according to the steps of the data access method of the multiple storage modes.

[0008] This application also provides a plaintext data access method, including: Obtain plaintext data; When the first data format for encrypting the plaintext data is different from the second data format of the plaintext data, perform format conversion processing on the plaintext data according to the second data format to obtain target plaintext data; Perform access processing on the target plaintext data to encrypt the plaintext data; wherein, the access processing process is completed according to the steps of the data access method of the multiple storage modes.

[0009] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of the data access method of the multiple storage modes, or the true random number access method, or the plaintext data access method as described when executing the computer program.

[0010] This application also provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program implements the steps of the data access method of the multiple storage modes, or the true random number access method, or the plaintext data access method as described when executed by a processor.

[0011] This application also provides a computer program product, including a computer program, which implements the steps of the data access method of the multiple storage modes, or the true random number access method, or the plaintext data access method as described when executed by a processor.

[0012] Through this application, since the multiple storage modes are mainly divided into a random access storage mode and a sequential access storage mode, on the one hand, regardless of the storage mode, the access and processing of target data are carried out in a shared preset storage space. Compared with the situation where different storage modes in the conventional case correspond to different storage spaces, resulting in a relatively large storage resource overhead of the storage space, this application shares a preset storage space for multiple storage modes, saving the storage space and reducing the storage resource overhead at the same time. On the other hand, in this application, the connection modes corresponding to the comparator, inverter, and buffer bank are adopted. Through hardware design adjustment, the current data storage state of the preset storage space can be determined in real time, improving the judgment accuracy while reducing the transmission delay and enhancing the reliability of the system. The buffer bank corresponds to the random access storage mode when in a blocked state and corresponds to the sequential access storage mode when in a conducting state, that is, the output is valid when the storage mode is the sequential access storage mode. The access process accesses and processes the target data in the preset storage space according to the current access operation and the data count mark corresponding to the preset storage space output by the buffer bank. Considering the different storage characteristics of the two storage modes, during the access process of the sequential access storage mode, the data storage state of the preset storage space is viewed based on the data count mark to facilitate subsequent access processing and improve the access efficiency. On the third hand, multiple storage modes are selected through a selection signal to achieve the selection of different access storage modes. At the same time, the random switching between the two access storage modes is also realized to achieve different storage methods of different modes. The access process of the sequential access storage mode, compared with the access process of the random access storage mode, considering the overwrite and read characteristics of the random access storage mode, can achieve normal reading and writing even when the data storage state of the preset storage space is full. Before the actual access of the sequential access storage mode, it is necessary to view the data count mark to save the access process of writing when the data storage is full and reading when the data storage is empty. By sharing a preset storage space for the random access storage mode and the sequential access storage mode through this application, the flexibility of data storage access is improved.

[0013] Therefore, it is possible to solve the problem of relatively large storage overhead corresponding to different storage spaces in the conventional multiple storage modes, and achieve the effect of realizing the access processing of the sequential access storage mode through the connection of each logic device of the counting unit. At the same time, multiple storage modes share a preset storage space, reducing the storage overhead to save the storage space. Brief Description of the Drawings

[0014] In order to more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0015] Figure 1 Structural diagram of a reconstruction system with multiple storage modes provided by an embodiment of the present application; Figure 2 Schematic structural diagram of a random access storage mode provided by an embodiment of the present application; Figure 3 Schematic structural diagram of a sequential access storage mode provided by an embodiment of the present application; Figure 4 Schematic diagram of an access operation between a control module and a client provided by an embodiment of the present application; Figure 5 Schematic diagram of two access operations between a control module and a client provided by an embodiment of the present application; Figure 6 Circuit diagram of a read / write operation logic circuit for a storage module by a control module and a client respectively provided by an embodiment of the present application; Figure 7 Flowchart of a data access method with multiple storage modes provided by an embodiment of the present application; Figure 8 Another storage schematic diagram based on a sequential access storage mode provided by an embodiment of the present application; Fig. 9 Flowchart of a data movement provided by an embodiment of the present application; Fig.10 Schematic diagram of interface connections between modules in an FPGA provided by an embodiment of the present application; Fig.11 State transition diagram of a control module state machine provided by an embodiment of the present application; Fig.12 State transition diagram of a data receiving module state machine provided by an embodiment of the present application; Fig.13 Flowchart of a true random number access method provided by an embodiment of the present application; Fig.14 Schematic diagram of a true random number scenario provided by an embodiment of the present application; Fig.15 Flowchart of a plaintext data access method provided by an embodiment of the present application; Fig.16 Data conversion diagram of a cryptographic module provided by an embodiment of the present application; Fig.17 Flowchart of data format conversion processing provided by an embodiment of the present application; Fig.18 Structural diagram of a data access device with multiple storage modes provided by an embodiment of the present application. Detailed implementation manners

[0016] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0017] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0018] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the data access method for multiple storage modes depends, the specific application environment architecture or specific hardware architecture will be described herein. In the field of digital circuit design, multiple volatile storage units are used as the data storage area. After the power-off of the Field-Programmable Gate Array (FPGA), the data stored in the volatile storage unit will be lost. Therefore, the volatile storage unit only serves as a temporary buffer for data. Since the storage modes of each volatile storage unit are different and each has its own advantages and disadvantages, multiple storage modes of volatile storage units are simultaneously adopted in the design process to meet the usage requirements. However, the storage spaces corresponding to each of the multiple volatile storage units are relatively large, and thus there is a defect of relatively large storage resource overhead. The reconstruction system for multiple storage modes provided by the present application can solve the above technical problems.

[0020] Implementing the reconstruction of multiple storage modes in a system is to control the volatile storage unit by designing the state machines of the control module, data receiving module, and storage module, so that the storage module can implement the functions of multiple storage modes according to the user's settings.

[0021] Figure 1 The structure diagram of a reconstruction system for multiple storage modes provided by the embodiments of the present application is as Figure 1As shown, it includes a storage module with a counting unit. The counting unit includes a comparator 11, an inverter 12, and a buffer bank 13; the multiple storage modes at least include a random access storage mode and a sequential access storage mode: the random access storage mode and the sequential access storage mode share the same preset storage space; The input end of the buffer bank 13 is connected to the comparator 11, and the enable end is connected to the inverter 12, which is used to output the data counting mark of the current access operation; the comparator 11 receives the storage quantity signal and the threshold signal of the preset storage space to determine the current access operation; the inverter 12 receives the storage mode selection signal; The buffer bank 13 corresponds to the random access storage mode when in a blocked state; and corresponds to the sequential access storage mode when in a conducting state, so that the access control device can perform access processing on the target data according to the current access operation and the data counting mark.

[0022] Specifically, the reconstruction system includes a storage module, which has a counting unit. Here, the counting unit is mainly used to count the data quantity of the storage module. The counting process combines a comparator and an inverter, and outputs the data counting mark of the current access operation through the output end of the buffer bank. The input end of the buffer bank is connected to the comparator, and the enable end is connected to the inverter. The comparator receives the storage quantity signal and the threshold signal of the preset storage space to determine the read operation or write operation corresponding to the current access operation. The inverter receives the storage mode selection signal, such as CS = 0 or 1. When CS = 1, the subsequent access is performed according to the random access storage mode. When CS = 0, the subsequent access is performed according to the sequential access storage mode. Regarding the setting of the storage mode selection signal, it can be an instruction issued by the host computer or set by the control module. This application does not make specific limitations on the conversion between the two storage modes, and can be set according to the conventional setting or based on which task to determine which storage mode to select. This application mainly focuses on the setting of the access processing process under different storage modes. The current access operation can be a read operation or a write operation. In this embodiment, considering the read and write operations between the control module, the storage module, and the data receiving module, it is possible to implement that only one access operation can be performed between any two modules, or it is possible to implement two access operations between any two modules. This is not limited here and can be set according to the actual situation.

[0023] The buffer bank corresponds to the random access storage mode when in a blocked state, and corresponds to the sequential access storage mode when in a conducting state. The blocked state is due to the enable end inputting a low level, and the corresponding enable end inputs a high level in the conducting state. Considering the setting of the inverter, when it receives the random access storage mode, a low level is output after passing through the inverter, which corresponds to the invalidity of the random access storage mode. On the contrary, the sequential access storage mode is valid.

[0024] Considering the conventional random access storage mode, the present application can implement the overwrite feature. If the storage space is full during a write operation, overwrite writing can be achieved, so there is no need for a counting unit. Regarding the sequential access storage mode, the overwrite feature cannot be implemented. When the storage space is full, writing can only be performed after there is a free address. Therefore, a counting unit is used to obtain information about whether the storage space is full or not, that is, the data counting mark is known. So, the access control device only needs to perform access processing on the target data according to the current access operation and the data counting mark during access processing.

[0025] The multiple storage modes at least include the random access storage mode and the sequential access storage mode. The random access storage mode only corresponds to the same type here. Specifically, it can be a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), or a Random Access Memory (RAM), etc. It allows users to randomly access any location in the memory and can quickly read or write data at any address without the need to access in sequence. Figure 2 As shown in the following figure, it is a schematic structural diagram of a random access storage mode provided by an embodiment of the present application. Figure 2 As shown, addressing needs to be performed before the operation. Data writing / reading operations are performed on the storage units according to the address. For example, write data Data1 to the unit at address 0x0001 and read data Data3 from the unit at address 0x0003. The advantage of RAM is that the data has a relatively long lifetime. After reading the data in a certain address unit, the data still exists in the storage unit until it is overwritten by new data. The disadvantage is that in the case of a large amount of data, the data access speed is slow. Before data operation, addressing is required. After giving the address of each storage unit to be written / read, data can be written / read to / from the storage unit.

[0026] The sequential access storage mode is mainly FIFO, based on a data structure, and is read in the order of writing, that is, the earliest written data is read first. Figure 3 As shown in the following figure, it is a schematic structural diagram of a sequential access storage mode provided by an embodiment of the present application. Figure 3As shown, data can be continuously operated and written into the FIFO in the order of data entry; when reading data, the data at the bottom of the FIFO is read sequentially, and the data that enters the FIFO first is read first. For example, Data0 enters the FIFO first and is read out first. The advantage of the FIFO is that it does not require complex address management and can continuously realize data reading and writing. Therefore, the data access efficiency is high and it is suitable for scenarios of high-speed data processing; the disadvantage is that data can only be processed sequentially and is not suitable for situations where certain specific data needs to be processed preferentially.

[0027] Regarding when to perform the corresponding storage mode, the storage mode selection signal can be read. If CS = 1, subsequent accesses are performed according to the random access storage mode. When CS = 0, subsequent accesses are performed according to the sequential access storage mode. The specific values of the marker bits can change and are not limited here. They can be set according to the actual situation.

[0028] When the current storage mode is the random access storage mode, the target data in the preset storage space is accessed and processed according to the current access operation. Here, it includes the access process of writing the target data into the preset storage space and the access process of reading the target data from the preset storage space. This is not limited here and can be the same or different from the conventional access processing.

[0029] When the current storage mode is the sequential access storage mode, the target data is accessed and processed according to the current access operation and the data count marker. In addition to the same access types as the read and write operations in the above embodiments, the data count marker is added. This is because the sequential access storage mode cannot achieve the overwrite write feature, and the data count marker represents the data storage state of the preset storage space.

[0030] Regarding the storage in the preset storage space, if the storage space is full, subsequent continuous writing will not be performed. Therefore, the data count marker is used to mark when writing can be performed in order to write the target data into the preset storage space. If the storage space is empty, subsequent continuous reading will not be performed. The data count marker is used to mark when reading can be performed to read the target data from the preset storage space.

[0031] Regarding the output of the data count marker, it is implemented through the logic circuit of the counting unit corresponding to the preset storage space, and the output value depends on the number of data in each storage unit of the preset storage space, that is, the counting unit records and accumulates.

[0032] Compared with directly receiving a flag bit to represent the data count flag in the conventional technical solution, the present embodiment adopts the hardware design of a logic circuit, which can achieve real-time response and avoid the delay in the middle transmission caused by the possible accumulation in software form and transmission to the controller or data receiving module in the conventional technical solution. The logic circuit of the present embodiment is closely integrated with other hardware parts of the system to reduce external intervention and improve the overall performance of the system.

[0033] Through the embodiments of the present application, since the multiple storage modes are mainly divided into a random access storage mode and a sequential access storage mode. On the one hand, regardless of the storage mode, a common preset storage space is used to access and process the target data. Compared with the situation in the conventional case where different storage modes correspond to different storage spaces, resulting in a large storage resource overhead of the storage space, the present application shares a common preset storage space for multiple storage modes, saving storage space and reducing the storage resource overhead at the same time. On the other hand, in the present application, the corresponding connection modes of a comparator, an inverter, and a buffer bank are adopted. Through hardware design adjustment, the current data storage state of the preset storage space can be determined in real time, improving the judgment accuracy while reducing the transmission delay and enhancing the reliability of the system. The buffer bank corresponds to the random access storage mode when in a blocked state and corresponds to the sequential access storage mode when in a conducting state, that is, it outputs validly in the sequential access storage mode. The access process is to access and process the target data in the preset storage space according to the current access operation and the data count flag corresponding to the preset storage space output by the buffer bank. Considering the different storage characteristics of the two storage modes, during the access process of the sequential access storage mode, the data storage state of the preset storage space is checked based on the data count flag to facilitate subsequent access processing and improve the access efficiency. On the third hand, multiple storage modes are selected through a selection signal to achieve the selection of different access storage modes. At the same time, the random switching between the two access storage modes is also realized to achieve different storage methods. The access process of the sequential access storage mode, compared with the access process of the random access storage mode, considering the overwrite and read characteristics of the random access storage mode, normal reading and writing can be achieved even when the data storage state of the preset storage space is full. Before the actual access in the sequential access storage mode, it is necessary to check the data count flag to save the access process of writing when the data storage is full and reading when the data storage is empty. By sharing a common preset storage space for the random access storage mode and the sequential access storage mode in the present application, the flexibility of data storage access is improved.

[0034] Therefore, it is possible to solve the problem of large storage overhead corresponding to different storage spaces in conventional multiple storage modes, and achieve access processing in sequential access storage mode through the connection of each logic device of the counting unit. At the same time, multiple storage modes share a preset storage space, reducing the storage overhead to save storage space.

[0035] In some embodiments, the buffer group includes a first buffer group, and the first buffer group includes a first buffer and a second buffer; The input ends of the first buffer and the second buffer are respectively connected to the comparator, and the enable ends are respectively connected to the inverter; the first buffer is used to output a write flag, and the second buffer is used to output a read flag.

[0036] Specifically, in this embodiment, considering that the access operation includes a read operation and a write operation, which respectively correspond to different flags. In the random access storage mode, the write flag and the read flag signals are in a high impedance state. In the sequential access storage mode, it presents the writing (Full = 0) or prohibited writing (Full = 1) of the write flag Full, and the reading (Empty = 0) or prohibited reading (Empty = 1) of the read flag (Empty).

[0037] The write flag is output through the output end of the first buffer, and the read flag is output through the output end of the second buffer, so as to be used as a reference for the sequential access storage mode to access the target data.

[0038] The connection relationship between the first buffer and the second buffer provided in this embodiment is targeted in the sequential access storage mode. By setting the write flag and the read flag, the accuracy of writing and reading during the access process of the sequential access storage mode is ensured, preventing data blockage or data discontinuity.

[0039] In some embodiments, the comparator includes a first comparator and a second comparator, and the inverter includes a first inverter and a second inverter; The first ends of the first comparator and the second comparator respectively receive the storage quantity signal; the second end of the first comparator receives the total storage quantity signal of the threshold signal, and the output end is connected to the input end of the first buffer; the second end of the second comparator receives the numerical signal of the threshold signal, and the output end is connected to the input end of the second buffer; The input ends of the first inverter and the second inverter respectively receive the storage mode selection signal; the output end of the first inverter is connected to the enable end of the first buffer; the output end of the second inverter is connected to the enable end of the second buffer.

[0040] Specifically, as Figure 1As shown, the first buffer group (Tri_1~Tri2): When the enable terminal (en) of the buffer is at a high level, the buffer conducts and can output data; when the enable terminal is at a low level, the buffer blocks and data cannot be output. At this time, the output terminal is in a high-impedance state.

[0041] Regarding the storage quantity signal, it can be directly obtained here or determined by an accumulator (ADD). When using the accumulator, the number of data in each storage unit in the storage area is counted, and the count value cnt (0 ≤ cnt ≤ M) is output.

[0042] The first comparator, that is, the equality checker (JMP), compares the input terminals 1 and 2. When the value of input terminal 1 = the value of input terminal 2, JMP outputs a high level; when the value of input terminal 1 ≠ the value of input terminal 2, JMP outputs a low level.

[0043] The second comparator compares the input terminals 1 and 2. When the value of input terminal 1 < the value of input terminal 2, the comparator outputs a high level; when the value of input terminal 1 ≥ the value of input terminal 2, the comparator outputs a low level.

[0044] The first inverter (NOT_1) and the second inverter (NOT_2) are implemented by NOT gates and output after inverting the input value.

[0045] The input terminal of the accumulator (ADD) is connected to the output port of the storage unit of the preset storage space, and the output terminal is connected to the respective first ends of the first comparator and the second comparator to output the storage quantity signal. The second end of the first comparator receives the total storage quantity signal (M) of the threshold signal, and the output terminal is connected to the input terminal of the first buffer. The second end of the second comparator receives the numerical signal "1" of the threshold signal, and the output terminal is connected to the input terminal of the second buffer.

[0046] The storage mode selection signal is input to the respective input terminals of the first inverter and the second inverter. The output terminal of the first inverter is connected to the enable terminal of the first buffer, and the output terminal of the second inverter is connected to the enable terminal of the second buffer. The output terminal of the first buffer outputs a write mark (Full), and the output terminal of the second buffer outputs a read mark (Empty).

[0047] Based on the connection relationship between the various logic devices provided in this embodiment, by comparing the number of counting units, the data storage status of the storage space is responded to in real time to improve the accuracy of judgment.

[0048] In some embodiments, the state output process of the first buffer and the second buffer includes: When the storage mode selection signal is in the random access storage mode, and after both the first inverter and the second inverter output the second level, it is determined that the first buffer and the second buffer are in a blocked state; When the storage mode selection signal is the sequential access storage mode, after passing through the first inverter and the second inverter, both output the first level, then it is determined that the first buffer and the second buffer are in the conducting state.

[0049] Specifically, when the storage mode selection signal is the random access storage mode, after passing through the first inverter and the second inverter, both output the second level, then it is determined that the signals at the enable terminals of the first buffer and the second buffer are the second level, corresponding to the first buffer and the second buffer being in the blocking state.

[0050] When the storage mode selection signal is the sequential access storage mode, after passing through the first inverter and the second inverter, both output the first level, then it is determined that the signals at the enable terminals of the first buffer and the second buffer are the first level, corresponding to the first buffer and the second buffer being in the conducting state.

[0051] Combined with the above embodiments, in the case of using an accumulator, the count values cnt of the accumulator (ADD) are respectively output to the terminal 1 of the first comparator and the terminal 1 of the second comparator; the storage quantity signal can also be directly obtained and input to the corresponding terminal 1 of the first comparator and the second comparator. The value at the input terminal 2 of the first comparator is M, and the value at the input terminal 2 of the second comparator is '1'; the output of the first comparator is connected to the input terminal of the first buffer, and the output of the second comparator is connected to the input terminal of the second buffer; the mode selection signal CS is respectively connected to the input terminals of the first inverter and the second inverter, the output terminal of the first inverter is connected to the enable terminal en of the first buffer, and the output terminal of the second inverter is connected to the en terminal of the second buffer; the output terminal of the first buffer is the Full signal, and the output terminal of the second buffer is the Empty signal.

[0052] When the mode selection signal is 1, it corresponds to selecting the random access storage mode. After CS passes through the first inverter and the second inverter, it becomes '0'. At this time, the en terminals of the first buffer and the second buffer are at a low level, the tri-state buffer is in the blocking state, and the Full and Empty signals are in the high-impedance state; When the mode selection signal is 0, it corresponds to selecting the sequential access storage mode. After CS passes through the first inverter and the second inverter, it becomes '1'. At this time, the en terminals of the first buffer and the second buffer are at a high level, the tri-state buffer is in the conducting state, and the output of the Full and Empty signals at this time depends on the count value cnt of the ADD.

[0053] The state output process of the first buffer and the second buffer provided in this embodiment, in combination with the random access storage mode and the sequential access storage mode, is effective for the sequential access storage mode, improving the flexible switching between the sequential access storage mode and the random access storage mode and realizing the access processing of different storage modes when sharing the same preset storage space.

[0054] In some embodiments, the output process of the data count flag includes: When the storage quantity signal is 0, the first comparator outputs a second level, and after passing through the first buffer, the write flag is output as write; the second comparator outputs a first level, and after passing through the second buffer, the read flag is output as prohibited from reading; Or, when the storage quantity signal is greater than or equal to 1 and less than the total storage quantity signal, the first comparator outputs a second level, and after passing through the first buffer, the write flag is output as write; the second comparator outputs a second level, and after passing through the second buffer, the read flag is output as read; Or, when the storage quantity signal is equal to the total storage quantity signal, the first comparator outputs a first level, and after passing through the first buffer, the write flag is output as prohibited from writing; the second comparator outputs a second level, and after passing through the second buffer, the read flag is output as read.

[0055] Specifically, when cnt = 0: After the inputs 1 and 2 of the first comparator are compared, since 0 ≠ M, the first comparator outputs a low level. After passing through the first buffer, the Full signal becomes '0'; correspondingly, the input 1 (value 0) of the second comparator < input 2 (value 1), the second comparator outputs a high level. After passing through the second buffer, the Empty signal becomes '1'; at this time, it means that the input is not full and the output is empty; Or, when 1 ≤ cnt < M: The Full signal is '0'. Since the input 1 of the second comparator ≥ input 2, the second comparator outputs a low level, making the Empty signal '0'; at this time, it means that the input is not full and the output is not empty; Or, when cnt = M: Since the input 1 = input 2 of the first comparator, the first comparator outputs a high level, making the Full signal '1'; since the input 1 > input 2 of the second comparator, the Empty signal remains '0'; at this time, it means that the input is full and the output is not empty.

[0056] The logical relationship between the logical devices of the logic circuit provided in this embodiment can determine the current data storage state of the preset storage space in real time, improving the judgment accuracy while reducing the transmission delay and improving the reliability of the system.

[0057] In some embodiments, the access control device includes a control module and a data receiving module; wherein, ports corresponding to write operations and read operations are provided between every two of the control module, the storage module, and the data receiving module to implement the access processing procedures of read and write operations between the control module and the storage module, and between the storage module and the data receiving module.

[0058] It should be noted that the access control device includes a control module and a data receiving module. The basic operation is that the control module writes target data to the storage module, and the data receiving module reads data from the storage module. The data receiving module of the access control device in this embodiment can be in the reconstruction system or corresponding to the client, which is not limited herein and can be set according to the actual situation. That is to say, the access control device can be located in the reconstruction system or not.

[0059] Figure 4 This is a schematic diagram of an access operation between a control module and a client provided by an embodiment of the present application. As Figure 4 shown, the control module controls the storage module to implement the reconstruction of the random access storage mode or the sequential access storage mode; the control module receives the data sent by an external data source (host computer) or uses the data in the control module and writes the data to the storage module. The data receiving module, as the client, reads data from the storage module; the data receiving module can be located outside the FPGA, such as an independent chip or module; the data receiving module can also be located inside the FPGA as a sub-module of the FPGA. In this example, 2 groups of ports are set. The control module writes data to the storage module through the write operation port, and the data receiving module reads data from the storage module through the read operation port. By setting 2 groups of ports, the control module and the data receiving module can operate on the storage module simultaneously. As long as the control module writes data to the storage module, the data receiving module can read it, without having to wait until all the data is written to the storage module and then read by the data receiving module, thereby improving the data processing speed.

[0060] Compared with the conventional technical solutions where there are random access storage modes or sequential access storage modes, corresponding storage spaces are set, and there are two ways to set the storage module corresponding to the control module and the client, that is, two write operation ports are set between the control module and the storage module. One write operation port is connected to the storage module a accessed according to the random access storage mode, and the other write operation port is connected to the storage module b accessed according to the sequential access storage mode. Two read operation ports are set between the storage module and the client. One read operation port reads from the storage module a according to the random access storage mode, and the other read operation port reads from the storage module b according to the sequential access storage mode. Compared with the conventional method of setting two storage modules, the present application only sets one storage module for reading, realizing the reuse of functions of different storage modes in the same storage module, saving storage space. In addition, setting 2 groups of ports can realize the access operation on the storage module simultaneously, improving the data processing speed.

[0061] In addition, in this embodiment, Figure 5 is a schematic diagram of two access operations between the control module and the client provided by the embodiment of the present application. As Figure 5 shown, in this embodiment, the operations of independently writing to and reading from the storage module between the control module and the client are realized.

[0062] In this embodiment, corresponding to the port settings where there are write operations and read operations between two-by-two modules, each module independently writes to and reads from the storage module, thereby improving the data processing speed and flexibility.

[0063] In some embodiments, the buffer group further includes a second buffer group; The output end of the first buffer group is connected to the input end of the second buffer group; The enable end of the second buffer group receives the register value; The output end of the second buffer group outputs a data count mark. When the register value is 1, the second buffer group is in a conducting state, and when the register value is 0, the second buffer group is in a blocking state.

[0064] Specifically, Figure 6 is a circuit diagram of the read and write operation logic circuit of the control module and the client respectively for the storage module provided by the embodiment of the present application. As Figure 6 shown, by adding an additional second buffer group and an additional register value, any access control device can realize the access processing of read operations and write operations in the sequential access storage mode.

[0065] In some embodiments, the second buffer group includes a third buffer, a fourth buffer, a fifth buffer, and a sixth buffer; the register value includes a first register value and a second register value; The input terminals of the third buffer and the fourth buffer are each connected to the output terminal of the first buffer, and are used for the write marks output corresponding to the control module and the data receiving module; The input terminals of the fifth buffer and the sixth buffer are each connected to the output terminal of the second buffer, and are used for the read marks output corresponding to the control module and the data receiving module; The enable terminals of the third buffer and the fifth buffer each receive the first register value; the enable terminals of the fourth buffer and the sixth buffer each receive the second register value.

[0066] Specifically, as Figure 6 shown, a second buffer group (Tri_3~Tri_6) with 1 bit is added, and at the same time, the first register value and the second register value of the register are also added. When CS = '0', the Full and Empty signals are each divided into 2 groups, Full_A and Empty_A are provided to the control module, and Full_B and Empty_B are provided to the data receiving module. By setting the register (Prio), the query of the data storage state in the FIFO mode is realized, and the conflict during the read and write operations of the storage unit by the control module and the data receiving module is avoided. The initial value of Prio is A = '0' and B = '0'. At this time, Tri_3~Tri_6 are in the blocked state and output high-impedance signals. It should be noted that A and B in this embodiment respectively represent the first register value and the second register value.

[0067] The input terminals of the third buffer and the fourth buffer are each connected to the output terminal of the first buffer, and their corresponding outputs are the write mark (Full_A) of the control module and the write mark (Full_B) corresponding to the data receiving module. The input terminals of the fifth buffer and the sixth buffer are each connected to the output terminal of the second buffer, and the corresponding outputs are the read mark (Empty_A) of the control module and the read mark (Empty_B) corresponding to the data receiving module.

[0068] The enable terminals of the third buffer and the fifth buffer each receive the first register value. When the first register value is 1, corresponding to the read and write operations of the control module, the read mark or the write mark is output accordingly. At this time, when the first register is set to 1, the second register is set to 0, and the data receiving module corresponding to the output terminals of the fourth buffer and the sixth buffer is invalid.

[0069] The enable terminals of the fourth buffer and the sixth buffer each receive the second register value. When the second register value is 1, corresponding to the read and write operations of the data receiving module, the read mark or the write mark is output accordingly. At this time, when the second register is set to 1, the first register value is set to 0, and the control module corresponding to the output terminals of the third buffer and the fifth buffer is invalid.

[0070] When the control module and the data receiving module provided in this embodiment perform read operations on the storage module respectively, they output corresponding to the data count mark, so as to improve the data processing efficiency and the flexibility of access operations at the same time.

[0071] In some embodiments, the output process of the data count mark of the second buffer group includes: When the control module performs a read operation or a write operation, set the first register value to 1 and the second register value to 0, then it is determined that the output ends of the third buffer and the fifth buffer respectively output a read mark or a write mark; Or, when the data receiving module performs a read operation or a write operation, set the first register value to 0 and the second register value to 1, then it is determined that the output ends of the fourth buffer and the sixth buffer respectively output a read mark or a write mark.

[0072] Specifically, based on the logic principle of the above logic circuit, when the control module needs to read / write the storage area, set A = '1' and B = '0' to turn on the third buffer and the fifth buffer, so that the Full_A and Empty_A signals can be obtained; after the control module finishes reading / writing the storage area, set A = '0' and B = '0' to release the control right of the signal; that is, reset the first register value and the second register value.

[0073] When the data receiving module needs to read / write the storage area, set A = '0' and B = '1' to turn on the fourth buffer and the sixth buffer, so that the Full_B and Empty_B signals can be obtained; after the data receiving module finishes reading / writing the storage area, set A = '0' and B = '0' to release the control right of the signal.

[0074] After the access is completed in this embodiment, the control right of the signal is released to facilitate the access processing of subsequent other access operations, and further improve the data processing efficiency.

[0075] In some embodiments, it further includes a seventh buffer; The input end of the seventh buffer is connected to the first data output port of the control module, the enable end is connected to the write enable port, and the output end is connected to the write data port of the storage module; The seventh buffer is used to conduct when the write enable port outputs a first level and write the target data into the storage module.

[0076] Such as Figure 6As shown in the figure, the input end of the seventh buffer is connected to the first data output port (DATA_A_out[7...0]) of the control module, the enable end is connected to the write enable port (A_wren), and the output end is connected to the write data port (D_in[7...0]) of the storage module. The write enable signal (wren) is connected to the en end. When wren = '1', the data can pass through the seventh buffer from the first data output port (DATA_A_out[7...0]) and be output to the storage area; when wren = '0', the data from the first data output port (DATA_A_out[7...0]) is blocked by the seventh buffer and cannot be written into the storage area.

[0077] The settings of the ports of the seventh buffer, the control module, and the storage module provided in this embodiment enable the control module to successfully write the target data into the storage module to ensure the accuracy of data circulation.

[0078] In some embodiments, an eighth buffer, a ninth buffer, and a tenth buffer are further included; The output end of the eighth buffer is connected to the first data input port of the control module, the enable end is connected to the read enable port, and the input end is connected to the read data port of the storage module; The input end of the ninth buffer is connected to the second data output port of the data receiving module, the enable end is connected to the write enable port of the data receiving module, and the output end is connected to the write data port of the storage module; The output end of the tenth buffer is connected to the second data input port of the data receiving module, the enable end is connected to the read enable port of the data receiving module, and the input end is connected to the read data port of the storage module.

[0079] As Figure 6 shown, 8-bit buffers (the eighth buffer, the ninth buffer, and the tenth buffer) are added, and a first data input port (DATA_A_in[7...0]) and a read enable port (A_rden) are added to the control module. When the control module sets A_rden = '1', the storage unit can be read, and when A_rden = '0', the data of the storage unit cannot be read. The data receiving module is added with a second data output port (DATA_B_out[7...0]), a write enable port (B_wren), and a read enable port (B_rden).

[0080] The output end of the eighth buffer is connected to the first data input port (DATA_A_in[7...0]) of the control module, the enable end is connected to the read enable port (A_rden), and the input end is connected to the read data port (A_D_out[7...0]) of the storage module; The input end of the ninth buffer is connected to the second data output port (DATA_B_out [7...0]) of the data receiving module, the enable end is connected to the write enable port (B_wden) of the data receiving module, and the output end is connected to the write data port (B_D_in[7...0]) of the storage module; The output end of the tenth buffer is connected to the second data input port (DATA_B _in[7...0]) of the data receiving module, the enable end is connected to the read enable port (B_rden) of the data receiving module, and the input end is connected to the read data port (B_D_out[7...0]) of the storage module.

[0081] When the control module and the data receiving module operate on the storage module respectively in this embodiment, corresponding buffers are set to conduct or block at corresponding ports to ensure the smooth progress of data reading operations and improve the orderliness of access operations.

[0082] Furthermore, the present application also provides a data access method for multiple storage modes. Figure 7 It is a flowchart of a data access method for multiple storage modes provided by an embodiment of the present application, as Figure 7 shown, the method includes: S11: Obtain the current access operation and target data; S12: In the sequential access storage mode, access and process the target data according to the current access operation and the data count flag; wherein, the logical circuit function corresponding to the data count flag is implemented by a reconstruction system for multiple storage modes.

[0083] Specifically, it should be noted in this embodiment that in the random access storage mode, in combination with the situation described in the above embodiment, it can be the same as or different from the conventional access processing, and it is not limited here. In the sequential access storage mode, the target data is accessed and processed based on the current access operation and the data count flag, which is the same as the implementation manner of the corresponding embodiment in the above embodiment, and will not be elaborated here.

[0084] For the description of the features in the embodiments corresponding to the data access method for multiple storage modes, reference can be made to the relevant description of the embodiments corresponding to the reconstruction system for multiple storage modes, which will not be elaborated one by one here.

[0085] In some embodiments, when performing access processing in the sequential access storage mode, storage addresses are set in advance for the stored data of the storage units in the preset storage space to achieve access processing according to the storage addresses.

[0086] Specifically, compared with accessing address information in sequence in the conventional random access storage mode, in this embodiment, a corresponding storage address is added to each storage unit so that when writing data, any address of a certain storage unit and the number of data to be written are given arbitrarily, and the address automatically increments after each data write to achieve the writing of multiple consecutive data. For example, starting from address 0x0001, 3 data items Data1 to Data3 are continuously written, thereby improving the deficiency of the prior art that data can only be written sequentially from the top of the FIFO; and the overwrite writing mode of data can be achieved, that is, when there is data in a certain storage unit, the old data can be overwritten with new data.

[0087] When the sequential access storage mode provided by this embodiment performs access processing, the storage addresses of the stored data in the storage units of the preset storage space are set in advance to achieve access processing according to the storage addresses, improving the flexibility and diversity of the addressing method for accessing the preset storage space in the sequential access storage mode, and also improving the efficiency of data reading and writing.

[0088] In some embodiments, when the current access operation is a read operation and the target data is multiple consecutive data items, the access processing of the target data includes: Obtaining the first target sub-data of the storage unit and the corresponding data address; Controlling the access control device to read the first target sub-data according to the data address; Moving the next second target sub-data of the first target sub-data to the data address as the new first target sub-data for reading until all the target data is read.

[0089] Specifically, Figure 8 FIG. is another storage schematic diagram based on the sequential access storage mode provided by the embodiments of the present application. As Figure 8 shown, taking the FIFO as an example, when reading data, multiple consecutive data items can be continuously read starting from any certain storage unit. After each data item is read, the data in the subsequent unit automatically moves forward, improving the deficiency of the prior art that data can only be read sequentially from the bottom of the FIFO. For example, after reading a data item Data1 from the unit at address 0x0001, Data2 moves to the 0x0001 address unit, Data3 moves to the 0x0002 address unit...

[0090] The state machine 3 of the storage module reads the specific address value ADDR_B[n...0] sent by the data receiving module and the value len2 of register 2 when CS = '0'. After the data receiving module reads one data each time, the state machine 3 moves the data after the Addr unit forward in sequence, that is, realizes the data flow function of the FIFO. For example, if Addr = 0x0001 and len2 = 2, after the data receiving module reads the data Data_1 in 0x0001, the state machine 3 moves the data Data_2 in 0x0002 to 0x0001 in sequence, and moves the data Data_3 in 0x0003 to 0x0002...; then, when the data receiving module continues to read the data Data_2 in 0x0001, the state machine 3 moves the data Data_3 in 0x0002 to 0x0001...

[0091] Specific reading method: Obtain the first target sub-data of the storage unit and the corresponding data address, and control the access control device to read the first target sub-data according to the data address. Here, the access control device can be the data receiving module or the control module, which is not limited here. When reading the target data of the storage module based on the data receiving module, control the data receiving module to read the first target sub-data from the data address through the read data port (D_out[7...0]) of the data receiving module, and receive it to the second data input port (DATA_B_in[7...0]) corresponding to the second port (ADDR_B[n...0]). Leave the address information of the first target sub-data empty, and migrate the next second target sub-data of the first target sub-data to the data address of the first target sub-data as the new first target sub-data, and return to the step of controlling the data receiving module to read the first target sub-data from the data address through the read data port until the target data is read completely.

[0092] Regarding the volatile storage area of the storage module, the size of the storage area and the data width of each storage unit can be set by the administrator / user. For example, set 8bit×M, each storage unit is 8bit, corresponding to the data output interface width of the control module; among them , it is related to the width of the address interface (ADDR_A[n...0]) of the control module: for example, when n = 7, it is an 8-bit address [7...0], , so the storage area contains 256 storage units, and the storage area size is 256×8bit. It can also be set that the storage unit is 16bit, 32bit, etc., which is not specifically limited in this application.

[0093] The implementation process of the state machine 3 in the storage module: When the data receiving module gives the address of the storage unit through the ADDR_B[n...0] interface, it enters the start state, and the state machine sets the temporary variables ptr and len; (2) len stores the value len2 of register 2 read; (3) ptr stores the address value Addr read from the ADDR_B[n...0] interface; (4) The state machine delays for one clock cycle Clk, waiting for the data receiving module to read 1 data from the storage unit at address Addr; (5) Then it is judged whether the address unit of Addr + 1 is empty. If it is empty, it means there is no data and the process ends; if it is not empty, it means there is data. Move the data in the address unit of Addr + 1 to the address unit of Addr, that is, Data[ptr]=Data[ptr + 1], and increment the value of ptr to process the next data, so that the data after the address of Addr + 1 moves forward in turn until the last storage unit is processed or an empty storage unit is detected; At this point, the data receiving module has read one data from the address of Addr, and the state machine 3 has completed the forward movement of the data after the address of Addr; (6) It is judged whether the data receiving module has read len data. If not, it jumps to step (3) to reassign Addr to ptr and then repeats steps (4) and (5) until the data receiving module has read len data.

[0094] Fig. 9 It is a flowchart of data movement provided by an embodiment of the present application, as Fig. 9 shown, including: S21: Read the register value of register 2 of the data receiving module; S22: The temporary variable of state machine 3 of the storage module stores the address value read from the second port; S23: State machine 3 delays for one clock cycle, waiting for the data receiving module to read one data from the storage unit of the address value; S24: Judge whether the address unit corresponding to the address value plus 1 is empty; if it is empty, end, if not, enter step S25; S25: Move the data in the address unit corresponding to the address value plus 1 to the storage unit corresponding to the address value, increment the temporary variable by 1, and decrement the register value of register 2 to process the next data, so that the data after the address unit corresponding to the address value plus 1 moves forward, and return to step S24 until the register value is equal to 0 and end.

[0095] When the data receiving module gives the address of the storage unit through the ADDR_B[n...0] interface, it enters the start state, and the state machine sets the temporary variables ptr and len; len stores the value len2 of register 2 read; ptr stores the address value Addr read from the ADDR_B[n...0] interface; the state machine 3 delays for one clock cycle Clk, waiting for the data receiving module to read 1 data from the storage unit at address Addr; then it judges whether the address unit of Addr+1 is empty. If it is empty, it means there is no data and the process ends; if it is not empty, it means there is data. Move the data in the address unit of Addr+1 to the address unit of Addr, that is, Data[ptr]=Data[ptr+1], and increment the value of ptr by 1 to process the next data, and move the data after the address of Addr+1 forward in turn until the last storage unit is processed or an empty storage unit is detected; at this time, the data receiving module has read one data from address Addr, and the state machine 3 has completed the forward movement of the data after address Addr; judge whether the data receiving module has read len data. If not, jump to step (3) to reassign Addr to ptr and repeat the execution.

[0096] In the data movement in this embodiment, after each data is read, the data of the subsequent unit is automatically migrated. The automatic migration mechanism ensures that after each data is read, the subsequent data is immediately filled in, reducing the waiting time for data reading, thereby improving the efficiency of data processing, ensuring the continuity of the data stream, and avoiding processing delays caused by data interruption. Automatic migration ensures that data can be read and processed in a timely manner, avoiding overflow problems caused by data accumulation in a data structure with a sequential access storage mode, and also preventing the "starvation" phenomenon caused by insufficient data at the reading end.

[0097] In some other embodiments, when the current access operation is a read operation and the target data is multiple consecutive data, the access processing of the target data includes: Obtain multiple consecutive data and the corresponding data addresses; Control the access control device to read multiple consecutive data according to the data addresses; Correspondingly, after the reading access of the target data is completed, it further includes: Migrate the data at the next data address of the data address of the target data in the storage unit to the data address.

[0098] Specifically, obtain the first target sub-data to the Nth target sub-data of the storage unit and the corresponding data addresses respectively; Control the data receiving module to read the target data from the data address through the read data port to receive it to the second data input port corresponding to the second port; Correspondingly, after the read access to the target data is completed, it further includes: Vacate the address information of the first target sub-data to the Nth target sub-data, and migrate the data at the next address information of the address information of the first target sub-data to the Nth target sub-data in the storage unit to the address information of the first target sub-data to the Nth target sub-data.

[0099] Specifically, compared with the above embodiments, the automatic migration in this embodiment is performed every time N data are read. When the target data are multiple sub-target data, a continuous multiple of sub-target data are read at one time for reception by the data receiving module.

[0100] The data movement in this embodiment can reduce the number of read operations each time multiple data are read, thereby improving the efficiency of data processing. Batch reading reduces the waiting time between each read operation, making the data stream more continuous. By reducing the frequency of read operations, the error rate that may be caused by frequent operations is reduced.

[0101] In some embodiments, when the current access operation is a write operation and is written to the storage module by the control module, the target data is accessed and processed according to the current access operation and the data count flag, including: When the write status information of the control module is a write operation and the data count flag is a write flag, enter the write data state of the target data; Write the target data from the first data output port corresponding to the first port of the control module to the write data port of the storage module; Decrease the register flag value of the control module by 1 and increase the address information by 1 to enter the waiting state; When the updated register flag value is greater than 0 and the data count flag is a write flag, write the next target data until the register flag value is 0 to complete the writing process of all target data.

[0102] Specifically, obtain the write status information and the first port corresponding to the control module; use the data stored in the first port as the target data; when the write status information is a write operation and the data count flag is a write flag, enter the write data state of the target data; obtain the write data port corresponding to the storage module; write the target data from the first data output port corresponding to the first port to the write data port; decrease the register flag value of the control module by 1, and increase the address information of the control module by 1, and enter the waiting state of the control module; when the updated register flag value is greater than 0 and the data count flag is a write flag, and return to the step of entering the write data state of the target data to write the next target data until the register flag value is 0, completing the access process of all target data of the control module to the preset storage space.

[0103] Fig.10 It is a schematic diagram of the interface connection between modules in an FPGA provided by an embodiment of this application. As Fig.10 shown, there is a set of write operation ports between the control module and the storage module, including a mode selection signal interface (CS), a first port (ADDR_A[n……0]), a first data output port (DATA_A_out[7……0]), a write enable port (wren) corresponding to the write operation instruction, and a data count flag bit port (Full). The left interfaces of the control module are a clock signal interface (Clk) and a reset signal interface (Reset) respectively. In the interface setting of the FPGA, subsequent normal access processing is carried out by connecting to a clock module, a reset module, and a power supply. Clock module: It can be a clock source such as a crystal oscillator to provide the system clock signal CLK for the FPGA. Reset module: After the FPGA is powered on, it provides the system reset signal RST. Power supply: It provides the working voltage for the FPGA.

[0104] Clk: Clock signal, connected to the system clock signal of the FPGA; Reset: Reset signal, connected to the system reset signal of the FPGA; CS: Mode selection signal for random access storage mode and sequential access storage mode. When the control module or the host computer sets CS = '1', the storage module implements the random access storage mode function; when CS = '0', the sequential access storage mode function is implemented; ADDR_A[n……0]: Address output interface, used to address the storage unit of the storage module. For example, when n = 7, it is an 8-bit address [7……0], and the addressing range at this time is storage units; DATA_A_out[7……0]: Data output interface, used to write data to the storage unit of the storage module; wren: Write enable signal, active high. After setting wren = '1', the storage unit can be written. When wren = '0', data cannot be written to the storage unit; Full: This signal is valid when CS = '0' (sequential access storage mode), indicating whether the storage space in the sequential access storage mode is full. Full = '1' means that the data input to the storage area has been stored full and data cannot be written to the storage unit anymore; Full = '0' means that the data is not full and data can continue to be written to the storage unit.

[0105] State machine 1: Write the acquired external data to the storage area; Register 1: Store the data quantity len1 written to the storage module. The specific value is set and modified by the control module; it can also be set by the external host computer software.

[0106] Fig.11 This is a state transition diagram of a control module state machine provided by an embodiment of the present application. As Fig.11 shown, it includes an idle IDLE state, a write length WR_LEN state, a RAM mode (write address WR_ADDR, write data WR_DATA, wait WAIT), a FIFO mode (write address WR_ADDR, write data WR_DATA, wait WAIT), and an end FINAL state.

[0107] In the sequential access storage mode, during the access operation where the control module accesses the storage module for writing, it is necessary to obtain the corresponding write status information of the control module and the corresponding first port (ADDR_A[n...0]). In this application, the data in the address of the first port is used as the target data. When the write status is a write operation and the data count flag is a write flag, it enters the write data state. That is, in the case of the write address state (WR_ADDR) and the data count flag being a write flag (Full = 0), it enters the write data state (WR_DATA). At this time, the corresponding write data port of the storage module (D_in[7...0]) is obtained, and the target data is written from the first data output port (DATA_A_out[7...0]) corresponding to the first port to the storage address of the write data port. After writing one data, the register flag value (len1) of register 1 of the control module is decremented by 1, and the address information of the control module is incremented by 1 (Addr + 1), and it enters the wait state (WAIT).

[0108] In the wait state, the state machine 1 of the control module jumps according to the register flag value. When the updated register flag value is greater than 0 and the data count flag is a write flag, it again goes to the write data state for execution until all the target data is written to the storage module. At this time, the register flag value is 0, and it enters the end state (FINAL).

[0109] In the FINAL state, the state machine 1 ends the current data writing process and returns to IDLE, and can start the next data writing process.

[0110] Before selecting between the random access storage mode and the sequential access storage mode, when the FPGA is powered on and reset, the state machine enters the idle state (IDLE); after the reset ends, it enters the write length state (WR_LEN), writes the number of data to register 1, and sets the value of CS to determine which storage mode to use for access processing.

[0111] Similarly, during the write access operation in the random access storage mode, when CS = '1', the random access storage mode is entered; enter the write address state (WR_ADDR), and give a specific address value through the port ADDR_A[n...0] to address the corresponding storage unit in the storage area, and then enter the write data state (WR_DATA); in the WR_DATA state, write data to the storage unit with the storage area address ADDR_A[n...0] of the write data port (D_in[7...0]) through the first data output port (DATA_A_out[7...0]), and decrement the len1 value in register 1 by 1, and then enter the wait state WAIT; in the WAIT state, the state machine jumps according to the len1 value. When len1 > 0, it jumps back to the WR_ADDR state to execute, gives the address of the next storage unit and then performs the write data operation until all the data is written into the storage unit. At this time, len1 becomes 0, and the state machine enters the end state FINAL.

[0112] The write operation access processing based on the sequential access storage mode provided in this embodiment enables data to complete the write operation according to the sequential access storage mode through the combined control of the state machine of the control module and the register, so as to improve the flexibility and diversity of the write access processing process.

[0113] In some embodiments, when the current access operation is a read operation and the data receiving module reads the storage module, the target data is accessed and processed according to the current access operation and the data count flag, including: When the read state information of the data receiving module is a read operation and the data count flag is a read flag, enter the read data state of the target data; Read the target data from the read data port of the storage module to the second data input port corresponding to the second port of the data receiving module; Decrement the register flag value of the data receiving module by 1 and enter the wait state; When the updated register flag value is greater than 0 and the data count flag is a read flag, read the next target data until the register flag value is 0 to complete the reading process of all target data.

[0114] Specifically, obtain the read status information corresponding to the data receiving module and the second port; when the read status information is a read operation and the data count flag is a read flag, enter the read data status of the target data; obtain the read data port corresponding to the storage module; use the data of the read data port as the target data; read the target data from the read data port to the second data input port corresponding to the second port; decrement the register flag value of the data receiving module by 1, and enter the waiting state of the data receiving module; when the updated register flag value is greater than 0 and the data count flag is a read flag, return to the step of entering the read data status of the target data to read the next target data until the register flag value is 0, completing the access process of all target data of the data receiving module to the preset storage space.

[0115] As Fig.10 shown, there is a set of read operation ports between the storage module and the data receiving module, including a clock signal interface (Clk), a reset signal interface (Reset), a mode selection signal interface (CS), a second port (ADDR_B[n……0]), a second data input port (DATA_B_in[7……0]), and a data count flag bit port (Empty).

[0116] Clk: Connected to the system clock signal of the FPGA; Reset: Connected to the reset signal of the FPGA; CS: Connected to the CS of the control module; ADDR_B[n……0]: Address output interface for addressing the storage unit of the storage module; similarly, n corresponds to the number M of storage units, ; DATA_B_in[7……0]: Data input interface for reading data from the storage unit of the storage module; Empty: This signal is valid when CS = '0' (sequential access storage mode), indicating whether the storage space in the sequential access storage mode is empty. Empty = '1' means there is no data in the storage area, in an empty state, and data cannot be read from the storage area; Empty = '0' means there is data in the storage area, in a non-empty state, and data can be read.

[0117] State machine 2: Read data from the storage area; Register 2: Store the number of data len2 read from the storage area, and the specific value is set and modified by the data receiving module.

[0118] Fig.12 This is the state transition diagram of a data receiving module state machine provided by an embodiment of the present application. As Fig.12As shown, it includes states such as IDLE, write length (WR_LEN), RAM mode (read address (RD_ADDR), read data (RD_DATA), wait (WAIT)), FIFO mode (read address (RD_ADDR), read data (RD_DATA), wait (WAIT)), and FINAL.

[0119] In the sequential access storage mode, during the access operation where the data receiving module accesses the storage module for reading, it is necessary to obtain the corresponding read status information of the data receiving module and the corresponding second port (ADDR_B[n...0]). When the read status information is a read operation and the data count flag is a read flag, it enters the read data state. That is, in the case of the read address state (RD_ADDR) and the data count flag being a read flag (Empty = 0), it enters the read data state (RD_DATA). At this time, the corresponding read data port of the storage module (D_out[7...0]) is obtained, and the target data is read from the read data port to the second data input port corresponding to the second port (DATA_B_in[7...0]), that is, a target data is read from the storage unit at the storage area address Addr, the register flag value (len2) of register 2 of the data receiving module is decremented by 1, and it enters the wait state (WAIT).

[0120] In the wait state, the state machine 2 of the data receiving module jumps according to the register flag value. When the updated register flag value is greater than 0 and the data count flag is a read flag, it turns back to the read data state for execution, that is, continues to read the next data from the Addr address until all the target data is written to the data receiving module. At this time, the register flag value is 0, and it enters the end state (FINAL).

[0121] In the FINAL state, the state machine 2 ends this data reading process, returns to IDLE, and can start the next data reading process.

[0122] Before selecting the random access storage mode and the sequential access storage mode, when the FPGA is powered on and reset, it enters the idle state (IDLE); after the reset ends, it enters the write length (WR_LEN), writes the number of data to be read to register 2; and reads the CS signal to determine whether it is the random access storage mode or the sequential access storage mode.

[0123] Similarly, during the read access operation in the random access storage mode, when CS='1' is read, the random access storage mode is entered: enter the read address state (RD_ADDR), and give the specific address value through the port ADDR_B[n...0] to address the corresponding storage unit in the storage area, and then enter the read data state (RD_DATA); in the RD_DATA state, read a data from the unit with the address ADDR_B[n...0] in the storage area through the data port D_out[7...0], and decrement the len2 value in register 2 by 1, and then enter the wait state WAIT; in the WAIT state, the state machine jumps according to the len2 value. When len2>0, it jumps back to RD_ADDR to execute, that is, after giving the address of the next storage unit, perform the read data operation until len2 data are read and the len2 value becomes 0, and enter the end state FINAL.

[0124] The read operation access processing based on the sequential access storage mode provided in this embodiment enables data to complete the read operation according to the sequential access storage mode through the combined control of the state machine and registers of the data receiving module, so as to improve the flexibility and diversity of the read access processing process.

[0125] Furthermore, the present application also provides a true random number access method. Fig.13 As shown in the flowchart of a true random number access method provided by an embodiment of the present application, as Fig.13 shown, the method includes: S31: Obtain a true random number; S32: When the true random number causes a data blocking mechanism, suspend the access processing of the true random number; S33: When the true random numbers are not continuous, obtain an alternative data source to replace the true random numbers, and use the replaced true random numbers for access processing; Among them, the process of true random number access processing is completed according to the steps of the data access methods of multiple storage modes.

[0126] Specifically, Fig.14 As shown in the schematic diagram of a true random number scenario provided by an embodiment of the present application, as Fig.14 shown, random numbers are often used data in cryptographic applications. When the generation speed of true random numbers is relatively fast and the control module transfers the data to the storage area, if the client reads slowly, it will cause problems such as the mismatch between the data writing and reading speeds, resulting in the loss of written data, which also causes the occurrence of the data blocking mechanism. When the generation speed of the external true random number module is slow, or in case of abnormal situations such as failures or resets, if the client reads fast, at this time the data sending end cannot normally provide data for the client, and there is a problem that the client reads an empty data from the storage area, resulting in discontinuous data, which also causes the occurrence of the data continuity mechanism.

[0127] When the above data blocking mechanism occurs, the access processing of true random numbers will be paused to wait for consistent reading and then resume data transmission. When data discontinuity occurs, a backup data source needs to be used to replace the true random numbers and continue the access processing.

[0128] It should be noted that when the true random numbers in this embodiment are accessed and processed using the above data access method, the true random numbers only need to correspond to the target data.

[0129] The true random number access method provided in this embodiment, in addition to achieving the beneficial effects of the above data access methods for various storage modes, also realizes the interaction between the client and the random number generator, as well as the blocking and synchronization mechanisms of random numbers.

[0130] In some embodiments, it further includes: Presetting a third register value and a fourth register value; When the true random numbers received by the control module cause data blockage, set the third register value to 1 and set the write enable signal corresponding to the control module to 0 to pause the access processing; When the true random numbers received by the data receiving module are discontinuous, set the fourth register value to 1, use a backup data source to replace the true random numbers, and use the replaced true random numbers for access processing.

[0131] Specifically, when to pause accessing data and when to use a backup data source need to be set through registers, that is, the settings of the third register value and the fourth register value.

[0132] Data blocking mechanism: Set a register Busy in the storage module. When the data receiving module sets Busy = '1' indicating a busy state, at this time, after the control module detects Busy = '1', set the write enable signal A_wren = '0' to pause data transmission; resume data transmission after Busy becomes '0'.

[0133] Improvement of the data continuity mechanism. Set a register Req in the storage module. When Empty_B = '1', the data receiving module sets Req = '1' indicating that empty data has been read and there is a need to continue reading data. At this time, after the control module detects Req = '1', use a backup data source (pseudo-random numbers through software) module to continue the data transmission process; pause data transmission after Req becomes '0'.

[0134] The marker setting based on the third register value and the fourth register value provided in this embodiment improves data recognition efficiency and also realizes the data synchronization mechanism between the client and the random number generation module.

[0135] Further, the present application also provides a method for accessing plaintext data. Fig.15 FIG. is a flowchart of a method for accessing plaintext data provided by an embodiment of the present application. As Fig.15 shown, the method includes: S41: Obtain plaintext data; S42: When the first data format for encrypting the plaintext data is different from the second data format of the plaintext data, perform format conversion processing on the plaintext data according to the second data format to obtain target plaintext data; S43: Perform access processing on the target plaintext data to encrypt the plaintext data; Wherein, the process of the access processing is completed as per the steps of the data access method of multiple storage modes.

[0136] Specifically, Fig.16 FIG. is a data conversion diagram of a password module provided by an embodiment of the present application. As Fig.16 shown, taking the Data Encryption Standard (DES) algorithm password module as an example for illustration. DES performs data encryption processing in units of 64-bit data groups. The data organization method in the host computer has a big-endian mode (Big-Endian, high bytes are stored at low addresses) and a little-endian mode (Little-Endian, low bytes are stored at low addresses); the DES module also has a big-endian mode or a little-endian mode. If the data organization method adopted by the host computer is different from that of the password module, the DES module will have a problem of encryption error, and thus correct data cannot be obtained.

[0137] When the first data format for encrypting the plaintext data is the same as the second data format of the plaintext data, after directly reading the plaintext data through the storage module, encryption can be performed, and there is no need to adjust the data format.

[0138] When the first data format for encrypting the plaintext data is different from the second data format of the plaintext data, format conversion is required before transmitting it to the password module, that is, the data receiving module. The transmission process here is the same as the access processing process of the data access method of the above-mentioned multiple storage modes, and will not be elaborated here.

[0139] The method for accessing plaintext data provided in this embodiment, in addition to achieving the beneficial effects of the above data access method, also realizes the automatic big-endian-little-endian matching of the data between the host computer and the password module, ensuring the correctness of the password data.

[0140] In some embodiments, the comparison process of the first data format and the second data format includes: Pre-set the value of the fifth register; Use the plaintext data that has been transmitted to the corresponding encryption module as the first data; Encrypt the first sub-data of the first data; If an error occurs during the encryption process, set the value of the fifth register to 1, and determine that the first data format of the encrypted plaintext data is different from the second data format of the plaintext data; If the encryption process is correct, set the value of the fifth register to 0, and determine that the first data format of the encrypted plaintext data is the same as the second data format of the plaintext data.

[0141] Specifically, during this process, set the value of the fifth register (i.e., the Error register value) in the storage module. When the password module (data receiving module) receives the first sub-data of the first data, perform encryption processing. If an error occurs during the encryption process, set the value of the fifth register to 1, and at this time, determine that the processing formats are different. If the encryption process is correct, set the value of the fifth register to 0, then determine that the processing formats are the same.

[0142] When the password module processes data in the Little-Endian format and the data in the host computer is in the Little-Endian format, the data formats of the password module and the host computer are consistent. At this time, the password module can obtain the correct result when encrypting the data, and at this time, there is no need to set the Error register; the control module reads Error = '0' and does not need to adjust the data format.

[0143] When the password module processes data in the Little-Endian format and the data in the host computer is in the Big-Endian format, after the password module receives the first Big-Endian format data from the host computer, an error will occur during the data encryption process and the expected result cannot be generated; at this time, the password module sets the Error register to '1'. The data format conversion module reads Error = '1' and starts from the second data, reverses the order of each 64-bit data of the host computer, converts the received Big-Endian format to the Little-Endian format, and then transfers it to the storage module after the conversion. Thus, it is ensured that the DES password module can obtain the correct encrypted data after the second data.

[0144] Similarly, when the password module processes data in Big-Endian format, the processing procedure of the data format conversion module is the same as that in the above embodiment. When it detects that Error = '0', it does not need to reverse the byte order in the 64-bit data. For each 64-bit data received from the host computer, it sequentially outputs Data[7...0], Data[15...8],..., Data[63...56], and transmits them to the storage module at address units 0x(k), 0x(k + 1),..., 0x(k + 7) (k ≥ 0) correspondingly; when it detects that Error = '1', it needs to reverse the byte order in the 64-bit data. For each 64-bit data received from the host computer, it sequentially outputs Data[63...56], Data[55...48],..., Data[7...0], and transmits them to the storage module at address units 0x(k), 0x(k + 1),..., 0x(k + 7) (k ≥ 0) correspondingly.

[0145] Fig.17 FIG. is a flowchart of data format conversion processing provided by an embodiment of the present application. As Fig.17 shown, it includes: S44: Determine whether the value of the fifth register is 1; if so, go to step S45, if not, go to step S48; S45: Determine that the data interval is 7; S46: Reverse-process the current first data to obtain the processed first data; S47: Decrease the reverse-processed data packet by 1 to obtain the next second data as the new current first data, and return to step S46; until the reverse-processed data packet is 0; S48: Output the processed data packets one by one.

[0146] The comparison process of the processing format provided in this embodiment simplifies the result presented by the comparison process and improves the data processing efficiency.

[0147] An embodiment of the present application further provides a data access device with multiple storage modes. Fig.18 FIG. is a structural diagram of a data access device with multiple storage modes provided by an embodiment of the present application. As Fig.18 shown, the device includes: An acquisition module 21 that acquires the current access operation and target data; An access module 22 that, in the sequential access storage mode, processes the target data according to the current access operation and the data count flag; wherein, the logical circuit function corresponding to the data count flag is implemented by a reconstruction system with multiple storage modes.

[0148] For the description of the features in the embodiments corresponding to the data access device with multiple storage modes, reference can be made to the relevant descriptions in the embodiments corresponding to the data access method with multiple storage modes, which will not be elaborated here one by one.

[0149] Furthermore, an embodiment of the present application also provides a true random number access device. For the description of the features in the embodiments corresponding to the true random number access device, reference can be made to the relevant descriptions in the embodiments corresponding to the true random number access method, which will not be elaborated here one by one.

[0150] Furthermore, an embodiment of the present application also provides a plaintext data access device. For the description of the features in the embodiments corresponding to the plaintext data access device, reference can be made to the relevant descriptions in the embodiments corresponding to the plaintext data access method, which will not be elaborated here one by one.

[0151] An embodiment of the present application also provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute any one of the above-mentioned data access methods with multiple storage modes, or, such as the true random number access method, or, such as the steps of the plaintext data access method.

[0152] An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute any one of the above-mentioned data access methods with multiple storage modes, or, such as the true random number access method, or, such as the steps of the plaintext data access method when running.

[0153] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs and other various media that can store computer programs.

[0154] An embodiment of the present application also provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, it implements any one of the above-mentioned data access methods with multiple storage modes, or, such as the true random number access method, or, such as the steps of the plaintext data access method.

[0155] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements any one of the above-mentioned data access methods with multiple storage modes, or, such as the true random number access method, or, such as the steps of the plaintext data access method.

[0156] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0157] The above has introduced in detail a data access method, an electronic device, a medium, and a product provided by this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A reconstruction system for multiple storage modes, characterized in that: A storage module including a counting unit, wherein the counting unit includes a comparator, an inverter and a buffer group; the multiple storage modes include at least a random access storage mode and a sequential access storage mode; the random access storage mode and the sequential access storage mode share the same preset storage space; The input end of the buffer group is connected to the comparator, and the enable end is connected to the inverter, for outputting a data count mark of a current access operation; the comparator receives a storage quantity signal of a preset storage space and a threshold signal to determine a current access operation; the inverter receives a storage mode selection signal; The buffer group corresponds to the random access storage mode when in a blocking state, and corresponds to the sequential access storage mode when in a conducting state, so that the access control device can access the target data according to the current access operation and the data counting mark.

2. The reconstruction system of multiple storage modes according to claim 1, characterized in that: The buffer group includes a first buffer group, the first buffer group includes a first buffer and a second buffer; The input terminals of the first buffer and the second buffer are connected to the comparator, and the enable terminals are connected to the inverter; the first buffer is used to output a write mark, and the second buffer is used to output a read mark.

3. The reconstruction system of multiple storage modes according to claim 2, characterized in that: The comparator includes a first comparator and a second comparator, and the inverter includes a first inverter and a second inverter; The first comparator and the second comparator each receive the storage quantity signal at a first end; the first comparator receives the total storage quantity signal of the threshold signal at a second end, and the output end is connected to the input end of the first buffer; the second comparator receives the numerical value signal of the threshold signal at a second end, and the output end is connected to the input end of the second buffer; The first inverter and the second inverter each receive the storage mode selection signal at an input terminal; The output end of the first inverter is connected to the enable end of the first buffer; the output end of the second inverter is connected to the enable end of the second buffer.

4. The reconstruction system of multiple storage modes according to claim 3, characterized in that: The state output process of the first buffer and the second buffer includes: When the storage mode selection signal is a random access storage mode, the first inverter and the second inverter both output a second level, and it is determined that the first buffer and the second buffer are in a blocking state; When the storage mode selection signal is a sequential access storage mode, the first inverter and the second inverter both output a first level, and it is determined that the first buffer and the second buffer are in a conducting state.

5. The reconstruction system of multiple storage modes according to claim 4, characterized in that: The output process of the data counting mark includes: When the storage quantity signal is 0, the first comparator outputs the second level, and the write mark is output as write through the first buffer; the second comparator outputs the first level, and the read mark is output as read-prohibited through the second buffer; Alternatively, when the storage quantity signal is greater than or equal to 1 and less than the total storage quantity signal, the first comparator outputs a second level, and after passing through the first buffer, the write mark is output as write; the second comparator outputs a second level, and after passing through the second buffer, the read mark is output as read; Alternatively, when the storage quantity signal is equal to the total storage quantity signal, the first comparator outputs a first level, and after passing through the first buffer, the write mark is output as write-prohibited; the second comparator outputs a second level, and after passing through the second buffer, the read mark is output as read.

6. The reconstruction system of multiple storage modes according to claim 3, characterized in that: The access control device includes a control module and a data receiving module; wherein ports corresponding to write operations and read operations are set between each of the control module, the storage module and the data receiving module to implement the access processing process of read and write operations between the control module and the storage module and between the storage module and the data receiving module.

7. The reconstruction system of multiple storage modes according to claim 6, characterized in that: The buffer group also includes a second buffer group; The output end of the first buffer group is connected to the input end of the second buffer group; An enable terminal of the second buffer group receives a register value; The output end of the second buffer group outputs the data counting mark. When the register value is 1, the second buffer group is in a conducting state. When the register value is 0, the second buffer group is in a blocking state.

8. The reconstruction system of multiple storage modes according to claim 7, characterized in that: The second buffer group includes a third buffer, a fourth buffer, a fifth buffer and a sixth buffer; the register value includes a first register value and a second register value; The input ends of the third buffer and the fourth buffer are connected to the output end of the first buffer, respectively, for writing mark outputs corresponding to the control module and the data receiving module; The input ends of the fifth buffer and the sixth buffer are connected to the output end of the second buffer respectively, and are used for the read mark output corresponding to the control module and the data receiving module; The third buffer and the fifth buffer each enable end to receive the first register value; the fourth buffer and the sixth buffer each enable end to receive the second register value.

9. The reconstruction system of multiple storage modes according to claim 8, characterized in that: The output process of the data count mark of the second buffer group includes: When the control module performs a read operation or a write operation, the first register value is set to 1, and the second register value is set to 0, and it is determined that the output ends of the third buffer and the fifth buffer correspond to outputting a read mark or a write mark; Alternatively, when the data receiving module performs a read operation or a write operation, the first register value is set to 0 and the second register value is set to 1, and the output ends of the fourth buffer and the sixth buffer are determined to output a read mark or a write mark correspondingly.

10. The reconstruction system of multiple storage modes according to claim 5, characterized in that: Also included is a seventh buffer; The input end of the seventh buffer is connected to the first data output port of the control module, the enable end is connected to the write enable port, and the output end is connected to the write data port of the storage module; The seventh buffer is used to be turned on when the write enable port outputs a first level, and write the target data into the storage module.

11. The reconstruction system of multiple storage modes according to claim 9, characterized in that: Also included is an eighth buffer, a ninth buffer and a tenth buffer; The output end of the eighth buffer is connected to the first data input port of the control module, the enable end is connected to the read enable port, and the input end is connected to the read data port of the storage module; The input end of the ninth buffer is connected to the second data output port of the data receiving module, the enable end is connected to the write enable port of the data receiving module, and the output end is connected to the write data port of the storage module; The output end of the tenth buffer is connected to the second data input port of the data receiving module, the enable end is connected to the read enable port of the data receiving module, and the input end is connected to the read data port of the storage module.

12. A data access method in multiple storage modes, characterized in that: include: Get the current access operation and target data; In a sequential access storage mode, the target data is accessed and processed according to the current access operation and the data counting mark; wherein the logic circuit function corresponding to the data counting mark is implemented by a reconstruction system of multiple storage modes as described in any one of claims 1 to 11.

13. The data access method of multiple storage modes according to claim 12, characterized in that: During the access processing in the sequential access storage mode, a storage address is pre-set for the storage data of the storage unit of the preset storage space to implement access processing according to the storage address.

14. The data access method of multiple storage modes according to claim 13, characterized in that: When the current access operation is a read operation and the target data is a plurality of continuous data, access processing is performed on the target data, including: Acquire the first target sub-data of the storage unit and the corresponding data address; Controlling the access control device to read the first target sub-data according to the data address; The next second target sub-data of the first target sub-data is migrated to the data address as new first target sub-data for reading, until the target data is completely read.

15. The data access method of multiple storage modes according to claim 13, characterized in that: When the current access operation is a read operation and the target data is a plurality of continuous data, access processing is performed on the target data, including: Get multiple continuous data and corresponding data addresses; Controlling the access control device to read a plurality of continuous data according to the data address; Correspondingly, after completing the read access of the target data, the method further includes: The data of the target data at a data address next to the data address of the storage unit is migrated to the data address.

16. The data access method of multiple storage modes according to claim 12, characterized in that: When the current access operation is a write operation and is written to the storage module by the control module, access processing is performed on the target data according to the current access operation and the data count mark, including: When the write state information of the control module is a write operation and the data count mark is a write mark, entering a write data state of the target data; Writing the target data from the first data output port corresponding to the first port of the control module to the write data port of the storage module; The register mark value of the control module is reduced by 1, and the address information is increased by 1 to enter the waiting state; When the updated register mark value is greater than 0 and the data count mark is a write mark, the next target data is written until the register mark value is 0, so as to complete the writing process of all target data.

17. The data access method of multiple storage modes according to claim 12, characterized in that: When the current access operation is a read operation and the storage module is read by the data receiving module, access processing is performed on the target data according to the current access operation and the data counting mark, including: When the read state information of the data receiving module is a read operation and the data counting mark is a read mark, entering a read data state of the target data; Reading the target data from the data read port of the storage module to the second data input port corresponding to the second port of the data receiving module; Decrease the register mark value of the data receiving module by 1 and enter the waiting state; When the updated register mark value is greater than 0 and the data count mark is a read mark, the next target data is read until the register mark value is 0, so as to complete the reading process of all target data.

18. A true random number access method, characterized in that: include: Get true random numbers; When the true random number causes data congestion, suspending access processing to the true random number; When the true random number is discontinuous, an alternative data source is obtained to replace the true random number, and the replaced true random number is used for access processing; wherein the true random number access processing process is completed according to the steps of the data access method of multiple storage modes as described in any one of claims 12 to 17.

19. The true random number access method according to claim 18, characterized in that: Also includes: Presetting a third register value and a fourth register value; When the true random number received by the control module causes data congestion, the third register value is set to 1, and the write enable signal corresponding to the control module is set to 0 to suspend access processing; When the true random numbers received by the data receiving module are discontinuous, the fourth register value is set to 1, the standby data source is used to replace the true random numbers, and the replaced true random numbers are used for access processing.

20. A method for accessing plaintext data, characterized in that: include: Get plaintext data; When the first data format of encrypting the plaintext data is different from the second data format of the plaintext data, performing format conversion processing on the plaintext data according to the second data format to obtain target plaintext data; Access processing is performed on the target plaintext data to encrypt the plaintext data; wherein the access processing process is completed according to the steps of the data access method with multiple storage modes as described in any one of claims 12 to 17.

21. The plaintext data access method according to claim 20, characterized in that: The comparison process of the first data format and the second data format includes: Presetting the fifth register value; The plaintext data transmitted to the encryption module is used as the first data; encrypting the first sub-data of the first data; If an error occurs in the encryption process, the fifth register value is set to 1, and it is determined that the first data format for encrypting the plaintext data is different from the second data format for the plaintext data; If the encryption process is correct, the fifth register value is set to 0, and it is determined that the first data format for encrypting the plaintext data is the same as the second data format for the plaintext data.

22. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the data access method of multiple storage modes as described in any one of claims 12 to 17, or the true random number access method as described in claim 18 or 19, or the steps of the plaintext data access method as described in claim 20 or 21 when executing the computer program.

23. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the data access method of multiple storage modes as described in any one of claims 12 to 17, or the true random number access method as described in claim 18 or 19, or the steps of the plaintext data access method as described in claim 20 or 21.

24. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, it implements the data access method of multiple storage modes as described in any one of claims 12 to 17, or the true random number access method as described in claim 18 or 19, or the steps of the plaintext data access method as described in claim 20 or 21.

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