A chip testing platform and system based on FPGA

Abstract

The present application relates to an FPGA-based chip testing platform and system, wherein the testing platform is characterized by including: a first instruction execution module configured to decode a first instruction from a host computer; and a second instruction execution module configured to read and parse a second instruction, wherein the type of the second instruction corresponds to different operations during the chip testing process. The FPGA-based chip testing platform proposed in this application can pre-cache the second instruction in the FPGA and transfer some operations originally performed in the host computer to the FPGA. The FPGA has a faster clock frequency and does not have unnecessary structures such as bus transmission, thereby reducing delays during the testing process.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a chip testing platform and system based on FPGA. Background Art

[0002] Against the backdrop of the rapid development of contemporary electronic technology, the demand for hardware testing is showing an unprecedented growth trend. With the continuous advancement of technology, the complexity and integration of integrated circuits have increased dramatically, which has put forward more stringent requirements for testing technology.

[0003] Programmable hardware architectures, such as FPGAs, bring unprecedented flexibility and customization to the testing world. They can dynamically adjust test plans based on the needs of specific devices and functional modules, significantly improving test coverage and efficiency.

[0004] In existing platforms that use FPGAs to test chips, operations such as data parsing and instruction conversion are typically performed by the host computer. This host computer contains structures such as bus transmissions that are not required by the test chip, and its long clock cycle results in significant delays during testing. When testing high-speed chips, the chip sends data quickly, while the host computer reads data more slowly. This can cause the host computer to miss important information sent by the chip, making it unable to accurately determine whether the chip under test is functioning properly. Summary of the Invention

[0005] In response to the technical problems existing in the prior art, the present application proposes an FPGA-based chip testing platform, characterized in that it includes: a first instruction execution module, configured to decode a first instruction from a host computer, wherein the type of the first instruction includes at least a write instruction and an execute instruction, the first instruction execution module includes a first state machine, configured to set the first instruction execution module to a corresponding state according to the type of the first instruction, and in the first instruction recognition state, when the first state machine determines that the first instruction is a write instruction, it jumps to the state of receiving the second instruction to store the high-order address, the state of receiving the second instruction to store the low-order address, the state of receiving each byte of the content written in the second instruction, and the write state in sequence; a second instruction execution module, coupled to the first instruction execution module, when the first instruction type is an execute instruction, the first instruction execution module is configured to send a control signal to the second instruction execution module, and the second instruction execution module is configured to read and parse the second instruction, wherein the type of the second instruction corresponds to different operations in the chip testing process; a storage module, configured to provide storage space for the second instruction; the first instruction includes a synchronization byte to represent a new first instruction, and when the first instruction execution module receives the synchronization byte, the first instruction execution module and the second instruction execution module stop executing the current operation and start executing the new first instruction.

[0006] In particular, the test platform proposed in this application is characterized in that the second instruction execution module is configured to send data to the chip to be tested; the type of the second instruction includes a data sending instruction, the content of which includes an instruction type mark; the content of the data to be sent and the data length.

[0007] In particular, the test platform proposed in this application is characterized in that the second instruction execution module is configured to read data from the chip to be tested; the type of the second instruction includes a data reading instruction, the content of which includes an instruction type tag; and the length of the data to be read.

[0008] In particular, the test platform proposed in this application is characterized in that the second instruction execution module is also configured to send specific data to the chip to be tested while reading data from the chip to be tested when testing an abnormal situation; in this case, the second instruction content also includes the data sent to the chip to be tested.

[0009] In particular, the test platform proposed in the present application is characterized in that the second instruction execution module includes a counting module; the type of the second instruction includes a jump instruction, the content of which includes an instruction type tag; a jump address; and a number of loops; when the second instruction execution module reads a jump instruction, it is configured to obtain the second instruction at the corresponding position according to the jump address and execute it, and the count value of the counting module is increased by one until the count value of the counting module meets the number of loops in the jump instruction.

[0010] In particular, the test platform proposed in this application is characterized in that the second instruction execution module includes a timing module; the type of the second instruction includes a delay instruction, and its content includes an instruction type mark; delay time; when the second instruction execution module reads the delay instruction, the timing module starts timing and waits until the time specified in the delay instruction is reached before reading the next second instruction.

[0011] In particular, the test platform proposed in the present application is characterized in that the second instruction execution module includes a second state machine configured to set the second instruction execution module to a corresponding state according to the type of the second instruction.

[0012] In particular, the test platform proposed in this application is characterized in that it also includes an interface protocol driver module, coupled to the second instruction execution module and the chip to be tested, configured to be controlled by the second instruction execution module, receive data from the second instruction execution module, and send it to the chip to be tested; and read data from the chip to be tested and send it to the second instruction execution module.

[0013] In particular, the test platform proposed in the present application is characterized by further comprising a read-back cache module coupled to the second instruction execution module and configured to cache the data read back by the chip under test in sequence.

[0014] In particular, the present application also proposes a chip testing system, which is characterized by including a host computer and the above-mentioned chip testing platform.

[0015] The FPGA-based chip testing platform and system proposed in this application can pre-cache the second instruction in the FPGA and transfer some operations originally performed in the host computer to the FPGA. The FPGA has a faster clock frequency and does not have unnecessary structures such as bus transmission, thereby reducing the delay in the testing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0017] Figure 1 is a module diagram of a chip testing system according to an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of a first instruction structure after communication encoding according to an embodiment of the present application;

[0019] Figure 3 is a flowchart of a test platform processing a first instruction according to an embodiment of the present application;

[0020] Figure 4 is a schematic diagram of states and jump modes of a first state machine according to an embodiment of the present application;

[0021] Figure 5 is a schematic diagram of states and jump modes of a second state machine according to an embodiment of the present application;

[0022] Figure 6 This is a schematic diagram of the operation steps executed by the second instruction execution module during the chip testing process according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0025] Technologies, methods, and devices known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. The lines between the elements in the drawings are merely for ease of explanation, indicating that at least the elements at both ends of the line are communicating with each other, and are not intended to limit the unconnected elements from being unable to communicate. Furthermore, the number of lines between two elements is intended to indicate at least the number of signals involved in the communication between the two elements or at least the number of outputs provided, and is not intended to limit the two elements to communicating only with the signals shown in the figure.

[0026] Figure 1 3 is a module diagram of a chip testing system according to an embodiment of the present application.

[0027] According to one embodiment, the chip testing system may include a host computer 10 and a test platform 11. A user uses the test platform 11 to directly test a chip under test 12. According to one embodiment, the host computer 10 may send a first instruction to the test platform, and the test platform 11 may perform an internal operation based on the first instruction.

[0028] According to one embodiment, the host computer 10 may include a test process storage module 101 for storing all detailed process step information related to the test of the chip to be tested.

[0029] According to one embodiment, the host computer 10 may further include a chip register related information storage module 102 for storing information such as detailed length, address, and function of the chip register.

[0030] According to one embodiment, the host computer 10 may further include an instruction encoding module 103, which may generate a first instruction recognizable by the test platform 11 or perform first instruction encoding based on information stored in the test process storage module 101 and the chip register related information storage module 102.

[0031] According to one embodiment, the host computer 10 may further include a communication module 104 for performing communication encoding on the first instruction generated by the instruction encoding module 103. According to one embodiment, the communication encoding may include inserting a synchronization byte and inserting an escape byte.

[0032] According to one embodiment, the communication module 104 can communicate with the test platform 11 in a serial manner. Due to the serial manner, data can be transmitted between the host computer 10 and the test platform 11 through only one serial bus, simplifying the line connection of the test system.

[0033] Figure 2 This is a schematic diagram of a first instruction structure after communication encoding according to an embodiment of the present application.

[0034] According to one embodiment, the first instructions may include at least two types, namely, write instructions and execute instructions. Of course, more types of first instructions may be included according to user needs and the type of the chip to be tested.

[0035] According to one embodiment, the first instruction may include a write control word or an execute control word, which is used to distinguish whether the instruction type is a write instruction or an execute instruction.

[0036] According to one embodiment, when the first instruction is a write instruction, it may include the content of the second instruction. According to one embodiment, the test platform 11 may perform a detection operation on the chip to be tested according to the second instruction.

[0037] According to one embodiment, when the first instruction is a write instruction, its content may include second instruction storage address information, for example, the second instruction stores a high-order address and the second instruction stores a low-order address.

[0038] According to one embodiment, the first instruction content may also include a synchronization byte and an escape byte, two specific bytes specified during the communication encoding process. The synchronization byte marks the beginning of a new first instruction. During the communication encoding process, the contents of the synchronization byte and the escape byte are first specified. Then, the escape byte is inserted before each byte whose content is the same as the synchronization byte or the escape byte. Finally, the synchronization byte is added before each first instruction. The position of the escape byte is not fixed and varies depending on the situation. This embodiment illustrates only one example.

[0039] According to one embodiment, the test platform 11 may include a receiving module 111 coupled to the host computer 10. The receiving module 111 receives a first instruction in the form of a serial signal from the host computer 10 and converts it into a parallel signal. Using a parallel signal can improve the efficiency of data processing by the test platform 11.

[0040] According to one embodiment, the test platform 11 may further include a first instruction execution module 112 coupled to the receiving module 111 . The first instruction execution module 112 receives the parallel signal from the receiving module 111 .

[0041] According to one embodiment, the first instruction execution module 112 may include a first state machine 1121. According to one embodiment, the first state machine 1121 may have seven states and jump in a certain manner. In different states, the first state machine 1121 can identify the first instruction, synchronize communication frames, perform byte escapes, and decode the first instruction.

[0042] According to one embodiment, the test platform 11 may further include a storage module 113 coupled to the first instruction execution module 112 , and the storage module 113 is configured to store the second instruction.

[0043] Existing platforms using FPGA test chips typically perform operations such as data parsing and instruction conversion in a host computer. The communication delay between the host computer and the FPGA is long and variable, resulting in significant delays during the test process. The storage module 113 can store a second instruction, thereby pre-caching the second instruction in the FPGA and transferring some operations previously performed in the host computer to the FPGA. The FPGA has a relatively fast clock frequency and does not require unnecessary structures such as bus transmission, thus reducing delays during the test process.

[0044] According to one embodiment, the test platform 11 may further include a second instruction execution module 114 coupled to the first instruction execution module 112, the storage module 113, and the chip under test 12. The second instruction execution module 114 may read a second instruction from the storage module 113 and perform chip test-related operations such as sending data and reading data.

[0045] According to one embodiment, the second instruction execution module 114 may include a second state machine 1141 and a timing module 1142. According to one embodiment, the second state machine 1141 may involve eight states and jump in a certain manner. According to one embodiment, in a specific state, the timing module 1142 may cooperate with the second state machine 1141 to implement the state jump.

[0046] According to one embodiment, the second instruction execution module 114 may further include a data sending control module 1143 configured to send data to the chip under test 12 .

[0047] According to one embodiment, the second instruction execution module 114 may further include a data reading control module 1144 configured to read data from the chip under test 12 .

[0048] According to one embodiment, the second instruction execution module 114 may further include a counting module 1145. During chip testing, some types of instructions need to be repeatedly executed a certain number of times. The counting module 1145 may be configured to count the number of repeated executions.

[0049] According to one embodiment, the test platform 11 may further include an interface protocol driver module 115, coupled between the second instruction execution module 114 and the chip under test 12. According to one embodiment, the interface protocol driver module 115 may be controlled by the second instruction execution module 114, receive a signal from the second instruction execution module 114, and send it to the chip under test 12, or receive a signal from the chip under test 12 and send it to the second instruction execution module 114. According to one embodiment, the operating clock frequency of the test platform 11 is higher, while the operating clock frequency of the chip under test 12 is lower. The interface protocol driver module 115 is capable of performing frequency division processing so that the operating clock frequency of the test platform 11 meets the required range of the chip under test 12.

[0050] According to one embodiment, the test platform 11 may further include a readback cache module 116 coupled to the second instruction execution module 114. According to one embodiment, the readback cache module 116 may include a first-in-first-out queue 1161, capable of sequentially caching the signals read back from the chip under test 12 by the second instruction execution module 114.

[0051] According to one embodiment, the test platform 11 may further include a data sending module 117 coupled to the readback buffer module 116 and the host computer 10. According to one embodiment, the readback buffer module 116 is configured to send data to the data sending module 117 in the order of readback. The data sending module 117 is configured to convert parallel data into serial data and send the serial data to the host computer 10.

[0052] According to one embodiment, when the first instruction is a write instruction, the first state machine 1121 in the first instruction execution module 112 can parse the first instruction and write the second instruction into a corresponding address in the storage module 113 according to the address therein.

[0053] According to one embodiment, when the first instruction is an execution instruction, the first instruction execution module 112 may send a control signal to control the second instruction execution module 114 to obtain and execute the second instruction.

[0054] According to one embodiment, the second instruction may include multiple types such as sending data, reading data, waiting for transmission completion, waiting for a specific signal, configuring a specific signal, jumping, delaying, and ending.

[0055] According to one embodiment, when the type of the second instruction is to send data, its content may include an instruction type tag, content of the sent data, and length of the sent data.

[0056] According to one embodiment, when the type of the second instruction is to read data, its content may include an instruction type tag, the length of the data, and the content of the data. According to one embodiment, in some special cases, data needs to be sent at the same time as reading data, so the content of sending data is included in the read data instruction.

[0057] According to one embodiment, when the type of the second instruction is to wait for transfer completion, its content may include an instruction type tag.

[0058] According to one embodiment, when the type of the second instruction is to wait for a specific signal, its content may include an instruction type tag and a code of the wait signal. The signal to be waited for is a signal in the chip under test 12.

[0059] According to one embodiment, when the type of the second instruction is to configure a specific signal, its content may include an instruction type tag, a target level of the configuration signal, and an encoding of the configuration signal. The signal to be configured is a signal in the second instruction execution module 114.

[0060] According to one embodiment, when the type of the second instruction is a jump, its content may include an instruction type tag, a predetermined jump number, and a second instruction storage address to jump to.

[0061] According to one embodiment, when the second instruction is a delay instruction, its content may include an instruction type tag and the number of clock cycles of the delay.

[0062] According to one embodiment, when the second instruction is an end, its content may include an instruction type tag.

[0063] Figure 3 This is a flowchart of a test platform processing a first instruction according to an embodiment of the present application.

[0064] Step 301: The test platform 11 receives a first instruction from a host computer. According to one embodiment, this step may further include converting the first instruction from a serial instruction to a parallel instruction.

[0065] Step 302: Decode the first instruction and determine whether the first instruction is a write instruction or an execute instruction according to the control word in the first instruction.

[0066] Step 303: When the first instruction is a write instruction, the write content in the first instruction is stored as the second instruction based on the second instruction storage high address and the second instruction storage low address in the first instruction.

[0067] Step 304: When the first instruction is an execution instruction, the test platform 11 starts to execute the second instruction.

[0068] Figure 4This is a schematic diagram of the states and jump modes of a first state machine according to an embodiment of the present application.

[0069] According to one embodiment, after the test platform is started, the first state machine 1121 is in the default state 401 .

[0070] According to one embodiment, when the first instruction execution module 112 receives the first instruction and detects the synchronization byte, the first state machine 1121 jumps to the synchronization state 402 .

[0071] According to one embodiment, when the first instruction execution module 112 receives the first instruction control word, the first state machine 1121 jumps to the first instruction recognition state 403. According to one embodiment, the first instruction control word can include two types: a write control word and an execute control word. In the first instruction recognition state 403, the first state machine 1121 identifies the type of the first instruction control word.

[0072] According to one embodiment, if the first instruction control word is a write control word, the first instruction is determined to be a write instruction, and the process jumps to the receive second instruction storage high address state 405 , where the first instruction execution module 112 receives the second instruction storage high address.

[0073] According to one embodiment, after receiving the second instruction storage high address, the first state machine 1121 jumps to the receive second instruction storage low address state 406, and the first instruction execution module 112 receives the second instruction storage low address.

[0074] According to one embodiment, after receiving the second instruction to store the low-order address, the first state machine 1121 sequentially jumps to the state of receiving the first byte of the written content, the state of receiving the second byte of the written content, the state of receiving the third byte of the written content, and the state of receiving the fourth byte of the written content. The first instruction execution module 112 sequentially receives the first to fourth bytes of the written content. According to one embodiment, different specifications of the written content or second instruction can be determined according to user needs.

[0075] According to one embodiment, after receiving the fourth byte of the write content, the first state machine 1121 may jump to the write state 411 to write the second instruction content to the specified address in the storage module 113. After the write is completed, it jumps to the default state 401.

[0076] According to one embodiment, in the first instruction recognition state 403, if the first instruction control word is recognized as an execution control word, the first instruction is determined to be an execution instruction, and the process jumps to the control state 404 of the second instruction execution module to start execution. The first state machine 1121 controls the second instruction execution module 114 to execute the second instruction, and then jumps to the default state 401.

[0077] According to one embodiment, when the first instruction execution module 112 receives an escape byte, it regards the next byte as a normal byte, even if the next byte appears to be a synchronization byte or an escape byte.

[0078] According to one embodiment, the synchronization byte marks the beginning of a new instruction. Therefore, regardless of the current state of the first state machine 1121, upon receiving a synchronization byte without an escape byte, the first state machine 1121 jumps to the synchronization state 402. The first instruction may be interrupted during transmission. In this case, the host computer 10 only needs to send the synchronization byte without the escape byte to start a new first instruction from the beginning.

[0079] Figure 5 This is a schematic diagram of the states and jump methods of the second state machine according to an embodiment of the present application.

[0080] According to one embodiment, before receiving the control signal from the first instruction execution module 112 , the second state machine 1141 is in the default state 501 .

[0081] According to one embodiment, after receiving a control signal from the first instruction execution module 112, the second state machine 1141 jumps to the second instruction reading state 502. In this state, the second instruction execution module 114 reads and parses an instruction from the storage module 113. According to one embodiment, the second instruction execution module 114 may also pre-increase the storage index address of the second instruction to be read next by 1 to ensure that the next second instruction is read from the new address.

[0082] According to one embodiment, when the second instruction execution module 114 finds that the second instruction it has read is an end instruction after parsing, the second state machine 1141 jumps back to the default state 501 .

[0083] According to one embodiment, when the second instruction execution module 114 finds that the second instruction it has read is a non-termination instruction after parsing, the second state machine 1141 jumps to a corresponding state according to the specific instruction type.

[0084] According to one embodiment, when the second instruction is a data transmission instruction, the second state machine 1141 jumps from the second instruction reading state 502 to the data transmission state 503. In this state, the data transmission control module 1143 performs an operation of sending data to the interface protocol driver module 115, and after the operation is completed, the second state machine 1141 jumps back to the second instruction reading state 502.

[0085] According to one embodiment, when the second instruction is a data read instruction, the second state machine 1141 jumps from the second instruction read state 502 to the data read state 504. In this state, the data read control module 1144 reads data from the interface protocol driver module 115 and sends the read data to the read back buffer module 116. After the operation is completed, the second state machine 1141 jumps back to the second instruction read state 502.

[0086] According to one embodiment, when the second instruction is to wait for a specific signal, the second state machine 1141 jumps from the second instruction reading state 502 to the waiting signal state 505. In this state, the second state machine 1141 performs a waiting operation until the specific signal is valid, and jumps back to the second instruction reading state 502 after the operation is completed.

[0087] According to one embodiment, when the second instruction is to configure a specific signal, the second state machine 1141 jumps from the second instruction reading state 502 to the configuration signal state 506. In this state, the second state machine 1141 performs an operation to configure the specific signal to a specified level, and after the operation is completed, the second state machine 1141 jumps back to the second instruction reading state 502.

[0088] According to one embodiment, when the second instruction is a jump instruction, second state machine 1141 jumps from second instruction read state 502 to second instruction address change state 507. In this state, second state machine 1141 performs an operation to change the second instruction storage index address to a specified address. After the operation is completed, it jumps back to second instruction read state 502. During chip testing, some operations need to be repeated until a certain number of times are reached. Counting module 1145 is configured to count the number of repeated executions.

[0089] According to one embodiment, when the second instruction is a delay instruction, the second state machine 1141 jumps from the second instruction read state 502 to the delay state 508. In this state, the timing module 1142 starts counting until the count of the timing module 1142 reaches a specified value. After the count is completed, the second state machine 1141 jumps back to the second instruction read state 502.

[0090] According to one embodiment, when the second instruction is finished, the second state machine 1141 jumps from the second instruction reading state 502 to the default state 501 .

[0091] Figure 6 This is a schematic diagram of the operation steps executed by the second instruction execution module during the chip testing process according to an embodiment of the present application.

[0092] According to one embodiment, during the chip testing process, the second instructions stored in the storage module 113 are as shown in Table 1.

[0093] Table 1

[0094] address Second Instruction Address 1 Send data 0xFF Address 2 Delay 1 millisecond Address 3 Configure a specific signal to be valid Address 4 Waiting for the completion signal to be valid Address 5 Send data 0x44 Address 6 Reading Data Address 7 Change the second instruction storage index address to address 4 until the set number of repetitions is reached Address 8 Finish

[0095] According to one embodiment, during the chip test process, the second state machine 1141 performs the following operations: Figure 6 shown.

[0096] Step 601 : The second instruction execution module 114 receives a control signal from the first instruction execution module 112 and starts executing a second instruction.

[0097] Step 602 : The second instruction execution module 114 reads the second instruction for sending data 0xFF from address 1 of the storage module 113 , and the data sending control module 1143 executes the operation of sending the data 0xFF.

[0098] Step 603: The second instruction execution module 114 reads the second instruction with a delay of 1 millisecond from address 2 of the storage module 113, and the timing module 1142 executes the operation of delaying 1 millisecond.

[0099] Step 604 : The second instruction execution module 114 reads the second instruction for configuring the specific signal to be valid from address 3 of the storage module 113 , and the second state machine 1141 executes the operation of configuring the specific signal to be valid.

[0100] Step 605: The second instruction execution module 114 reads the second instruction of the wait completion signal from address 4 of the storage module 113. The completion signal indicates that the chip has completed the data conversion. The second state machine 1141 executes the operation of waiting for the signal to be valid.

[0101] Step 606 : the second instruction execution module 114 reads the second instruction for sending data 0x44 from address 5 of the storage module 113 , and the data sending control module 1143 executes the operation of sending the data 0x44.

[0102] Step 607 : The second instruction execution module 114 reads the second instruction for reading data from address 6 of the storage module 113 , and the data read control module 1144 executes the data reading operation.

[0103] Step 608: Second instruction execution module 114 reads the second instruction to jump to from address 7 of storage module 113, and second state machine 1141 changes the storage index address of the second instruction. According to one embodiment, during chip testing, steps 605 to 608 are repeated until a set number of repetitions is reached. Therefore, when executing step 608, if the count of counting module 1145 does not reach the set number of repetitions, second state machine 1141 changes the storage index address of the second instruction to address 4, returning to step 605.

[0104] Step 609 : When the count of the counting module 1145 reaches the set number of repetitions, the second instruction execution module 114 reads the second instruction to the end from address 8 of the storage module 113 .

[0105] This application uses a method of pre-caching instructions to the FPGA, transferring some operations originally completed in the host computer to the FPGA for completion, and utilizing every clock cycle as much as possible. Compared with existing FPGA chip test platforms, this invention reduces latency, allowing the chip under test to accurately enter a specified state and complete the test of a specified function. The interface protocol driver module proposed in this application can perform frequency division processing, so that the operating clock frequency of the test platform meets the required range of the chip under test.

[0106] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A chip testing platform based on FPGA, characterized in that: include: A first instruction execution module is configured to decode a first instruction from a host computer, wherein the type of the first instruction includes at least a write instruction and an execute instruction, and the first instruction execution module includes a first state machine, configured to set the first instruction execution module to a corresponding state according to the type of the first instruction. In a first instruction recognition state, when the first state machine determines that the first instruction is a write instruction, it jumps to a state of receiving a second instruction to store a high-order address, a state of receiving a second instruction to store a low-order address, a state of receiving each byte of content written in the second instruction, and a write state in sequence; a second instruction execution module, coupled to the first instruction execution module, wherein when the first instruction type is an execution instruction, the first instruction execution module is configured to send a control signal to the second instruction execution module, and the second instruction execution module is configured to read and parse the second instruction, wherein the type of the second instruction corresponds to different operations in the chip test process; a storage module configured to provide a storage space for the second instruction; The first instruction includes a synchronization byte to represent a new first instruction. When the first instruction execution module receives the synchronization byte, the first instruction execution module and the second instruction execution module stop executing current operations and start executing the new first instruction.

2. The test platform according to claim 1, wherein: The second instruction execution module is configured to send data to the chip under test; the type of the second instruction includes a data sending instruction, the content of which Including instruction type tag; data content and data length to be sent.

3. The test platform according to claim 1, wherein: The second instruction execution module is configured to read data from the chip under test; the type of the second instruction includes a data read instruction, the content of which Including instruction type tag and length of data to be read.

4. The test platform according to claim 1, wherein: The second instruction execution module is further configured to send specific data to the chip under test while reading data from the chip under test when testing an abnormal situation; in this case, the second instruction content also includes the data sent to the chip under test.

5. The test platform according to claim 1, wherein: The second instruction execution module includes a counting module; the type of the second instruction includes a jump instruction, and the content of the second instruction includes an instruction type tag; Jump address; and the number of cycles; When the second instruction execution module reads a jump instruction, it is configured to obtain the second instruction at the corresponding position according to the jump address and execute it, and the counting module count value is increased by one until the counting module count value meets the number of loops in the jump instruction.

6. The test platform according to claim 1, wherein: The second instruction execution module includes a timing module; the type of the second instruction includes a delay instruction, and its content includes an instruction type mark; a delay time; when the second instruction execution module reads the delay instruction, the timing module starts timing and waits until the time specified in the delay instruction is reached before reading the next second instruction.

7. The test platform according to claim 1, wherein: The second instruction execution module includes a second state machine configured to set the second instruction execution module to a corresponding state according to the type of the second instruction.

8. The test platform according to claim 1, characterized in that It also includes an interface protocol driver module, coupled to the second instruction execution module and the chip to be tested, configured to be controlled by the second instruction execution module, receive data from the second instruction execution module, and send it to the chip to be tested; and read data from the chip to be tested and send it to the second instruction execution module.

9. The test platform according to claim 1, characterized in that It also includes a read-back cache module, coupled to the second instruction execution module, and configured to cache the data read back by the chip to be tested in sequence.

10. A chip testing system, characterized by The chip testing platform comprises a host computer and any one of claims 1 to 9.

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