Simulation integrated circuit test stimulus generation method based on multi-stage bayesian optimization

Abstract

The application discloses a simulation integrated circuit test excitation generation method based on multi-stage Bayesian optimization. Defect modeling is performed on a to-be-tested analog integrated circuit to obtain a defect simulation analog integrated circuit. Then, a search space is set and discretized according to an excitation source of the to-be-tested analog integrated circuit. An initial point is sampled in the search space. Then, a multi-stage Bayesian optimization is used to search for a test excitation set. In the search, a combination of detectable fault sets of the initial point is taken as a combination fault detection set, the number of the combination fault detection set is taken as a target function of each initial point, and an initial historical excitation set is formed. Finally, the multi-stage Bayesian optimization is used to search for a test excitation set required by the analog integrated circuit. The application uses the characteristics of the Bayesian optimization, designs a multi-stage Bayesian optimization algorithm, improves the search efficiency of the test excitation, reduces the simulation time, and improves the generation efficiency of the analog integrated circuit test excitation.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of analog integrated circuit test, and more specifically relates to a method for generating test excitation of analog integrated circuit based on multi-stage Bayesian optimization. BACKGROUND

[0002] The test of analog and mixed-signal circuits is still a challenge in the industry, especially the functional test based on the specified specifications in the post-silicon test link may introduce significant test cost to the integrated circuit. Functional test can generally obtain high-quality test results, but it needs to test all the key specifications of the circuit one by one, which may cause the test time to be too long. In addition, the completion of functional test requires expensive automatic test equipment (ATE), which is usually equipped with high-resolution analog instruments, digital signal processing (DSP) capabilities and a large amount of storage space to save test response data.

[0003] With the growing demand of the Internet of Things (IoT) market for short-range communication systems, it is increasingly necessary to develop low-cost test methods for analog and radio frequency modules. Low-complexity production test techniques are required for low-cost integrated circuits (ICs), which can also be applied to wafer screening tests to avoid packaging of faulty parts. Therefore, fault-oriented analog test (Fault-Oriented Test) may provide a low-cost alternative for test engineers to avoid or at least reduce the complexity of developing and applying specification-based tests.

[0004] In fault-oriented analog test (Fault-Oriented Test), each voltage source voltage and each current source current are used as input excitation. To evaluate the test excitation, fault injection and simulation of the circuit are required. The simulation of the circuit is completed by SPICE (Simulation program with integrated circuit emphasis) by solving the matrix to obtain the numerical solution of the circuit node voltage and other indicators. Unlike digital circuit test excitation generation, the voltage of each node is a real number, which cannot be evaluated by simple 0, 1 logic combination.

[0005] In the test process of analog and mixed-signal circuits, the combination of test excitation (real number combination in a certain interval) needs to evaluate the number of test excitation compared with the combination of test excitation (0 and 1 logic combination) of pure digital circuits, which is from 2 n to m n(wherein, m is the value number of each analog power supply after the introduction of the step length, and n is the number of analog power supplies), is exponentially rising. In the testing process of analog and digital-analog hybrid circuits, the "unit" that occurs a fault is reduced from the gate circuit level to the original element level, and the number of "units" that need to be fault injected is also increased by 2-15 times.

[0006] Therefore, in the process of evaluating the test stimulus, if all the stimuli are evaluated one by one, the evaluation time will be greatly increased from the evaluation method and the number of test stimulus combinations. Therefore, search algorithms such as random search and heuristic search need to be used to reduce the evaluation times.

[0007] Meanwhile, from the number of "units" that need to be fault injected and the fault types, the cost of each evaluation of the stimulus is also high. In the search algorithm, obtaining the information that guides the next search is itself one of the optimization goals, so the number of stimuli that need to be evaluated needs to be reduced as much as possible. That is, the stimulus that needs to be evaluated next needs to be selected under the condition of limited current information, and the cost of each evaluation is very high. Therefore, a balance needs to be found between exploring unknown areas and utilizing the high-value areas that have been evaluated. SUMMARY

[0008] The purpose of the present application is to overcome the shortcomings of the prior art and provide a multi-stage Bayesian optimization-based analog integrated circuit test stimulus generation method. The multi-stage Bayesian optimization algorithm is designed by utilizing the characteristics of Bayesian optimization, the search efficiency of the test stimulus is improved, the simulation time is reduced, and the generation efficiency of the analog integrated circuit test stimulus is improved.

[0009] In order to achieve the above-mentioned application purpose, the multi-stage Bayesian optimization-based analog integrated circuit test stimulus generation method of the present application comprises the following steps:

[0010] S1: For the analog integrated circuit to be tested, all elements in the circuit netlist are identified, fault models are established for all elements except power supplies, a fault list is generated, each fault model is equivalently compressed, and is injected into the analog integrated circuit to be tested one by one to obtain a fault simulation analog integrated circuit;

[0011] S2: According to the number M of stimulus sources of the analog integrated circuit to be tested and the voltage interval of each stimulus source, an M-dimensional search space is established; then, according to the actual needs, the test stimulus step length is set, and the search space is discretized to obtain the coordinates of each search grid point;

[0012] S3: Sampling in the search space to obtain D initial points start d , d = 1, 2, …, D, performing fault simulation on each initial point start d in the analog integrated circuit and recording the detectable fault set f d of each initial point start startd ;

[0013] S4: Searching for a test stimulus set based on multi-stage Bayesian optimization, including the following steps:

[0014] S4.1: Obtaining the union of the detectable fault sets f d of the D initial points start startd as a combined fault detection set F1, taking the number of detectable faults in the combined fault detection set F1 as a combined fault detection number V1, and then taking the combined fault detection number V1 as the objective function value of each initial point start d , thereby obtaining a historical stimulus set E1;

[0015] S4.2: Setting up a surrogate model according to actual needs, and pre-training the surrogate model using the historical stimulus set E1;

[0016] S4.3: Letting the Bayesian optimization round s = 1;

[0017] S4.4: Performing the s-th round of Bayesian optimization, specifically as follows:

[0018] S4.4.1: Letting the search round r = 1;

[0019] S4.4.2: Setting a sampling function according to actual needs, and selecting a stimulus p s in the search space according to the maximum value of the sampling function in the complement of the historical stimulus set E s,r ;

[0020] S4.4.3: Simulating the analog integrated circuit to obtain the detectable fault set f s,r of the stimulus p s,r ; obtaining the union of the detectable fault set f s,r and the combined fault detection set F s , and taking the number of detectable faults in the union as the combined fault detection number V s,r corresponding to the stimulus p s,r ;

[0021] S4.4.4: Updating the surrogate model using the stimulus p s,r and the combined fault detection number V s,r corresponding thereto;

[0022] S4.4.5: Determine whether r < R, where R represents the search round of each Bayesian optimization round. If yes, proceed to step S4.4.6; otherwise, end the current round of Bayesian optimization.

[0023] S4.4.6: Let the search round number r = r + 1, and return to step S4.4.2;

[0024] S4.5: Determine whether the Bayesian optimization termination condition has been met. If yes, proceed to step S4.6; otherwise, proceed to step S4.8.

[0025] S4.6: Obtain the R incentives p obtained from the Bayesian optimization in this round. s,r The set of detectable faults f s,r and combined fault detection set F s The collection of, as the combined fault detection set F s+1 The number of detectable faults in this set is taken as the combined fault detection quantity V. s+1 Then, the number of combined fault detections, V, will be increased. s+1 The R incentives p obtained in this round of Bayesian optimization are... s,r and historical inspiration set E s Given the original objective function value, we obtain the historical stimulus set E. s+1 ;

[0026] S4.7: Let the Bayesian optimization round s = s + 1, and return to step S4.4;

[0027] S4.8: The historical stimulus set E S The test stimulus set E serves as the final analog circuit test set.

[0028] This invention relates to a method for generating test stimuli for analog integrated circuits based on multi-stage Bayesian optimization. The method involves performing defect modeling on the analog integrated circuit under test to obtain a defect-simulated analog integrated circuit. Then, a search space is set and discretized according to the excitation sources of the analog integrated circuit under test. Initial points are sampled in the search space, and a multi-stage Bayesian optimization is used to search for the test stimuli set. During the search, the set of detectable faults at the initial points is used as the combined fault detection set, and the number of combined fault detections is used as the objective function for each initial point, forming an initial historical stimuli set. Finally, the required test stimuli set for the analog integrated circuit is obtained through multiple rounds of Bayesian optimization search.

[0029] This invention proposes a multi-stage Bayesian optimization method. In each stage, the location of the next stimulus to be evaluated is determined through a sampling function and a surrogate model. It takes into account both "exploration-exploitation" and the ability of a single stimulus to detect more faults and multiple stimulus combinations to detect as many faults as possible. It exhibits better performance than grid search and random search. It can greatly reduce simulation time in the process of selecting test stimulus combinations, which has important practical significance for reducing the testing cost of analog integrated circuits. Attached Figure Description

[0030] Figure 1 This is a flowchart illustrating a specific implementation of the analog integrated circuit test stimulus generation method based on multi-stage Bayesian optimization of the present invention.

[0031] Figure 2 It is the component hard fault model information table specified in IEEE P2427;

[0032] Figure 3 This is an example diagram of MOS transistor fault injection in this embodiment;

[0033] Figure 4 This is an example diagram of the search space;

[0034] Figure 5 This is a flowchart of the multi-stage Bayesian optimization search test stimulus set in this invention;

[0035] Figure 6 This is a flowchart of Bayesian optimization in this invention;

[0036] Figure 7 This is a flowchart of the test incentive optimization based on the Pareto genetic algorithm in this embodiment;

[0037] Figure 8 This is a structural diagram of the bandgap reference circuit in this embodiment. Detailed Implementation

[0038] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0039] To better illustrate the technical solution of the present invention, the technical principles of the present invention will be briefly explained first.

[0040] In analog integrated circuit testing, fault coverage and detectable fault coverage are two very important metrics. Fault coverage (defect_coverage) is equal to the number of detectable faults (defect) divided by the total number of injected faults (defectall), and can be used to evaluate the performance of current fault detection algorithms.

[0041]

[0042] Because some circuit components were added during the design of analog integrated circuits to mitigate the impact of process variations. Simultaneously, as analog integrated circuits become larger and more complex, some circuit faults become undetectable. Therefore, if undetectable faults exist, detectable fault coverage should be added as one of the metric for evaluating current fault detection algorithms, in addition to fault coverage rate. The formula for calculating detectable_defect_coverage is:

[0043]

[0044] Here, detectable_defect represents the number of detectable defects.

[0045] In the design-for-test (DFT) process of analog integrated circuits, it is often necessary to ensure the quality of the integrated circuit by bringing out internal test points with high measurable fault coverage in advance. However, bringing out internal test points is very costly in terms of design. Therefore, without changing the number of internal test points, each test point of the analog integrated circuit is modeled as a system of nonlinear equations about the input stimulus:

[0046]

[0047] Among them, i m Let m represent the m-th stimulus, where m = 1, 2, ..., M, and M represents the number of stimuli. n This represents the nth measurement point, where n = 1, 2, ..., N, and N represents the number of measurement points. j Let j represent the i-th fault state, j = 0 indicates that the analog integrated circuit is fault-free, j = 1, 2, ..., K, and K represents the number of faults. Indicates the current fault status. j The algebraic relationship between the next node response and the test stimulus.

[0048] Therefore, under different fault conditions, the algebraic relationship between the measurement point response and the test stimulus of the analog integrated circuit is different, that is... Different. By comparing the output of the same measuring point under the same excitation in different fault states, if the output exceeds the set threshold, it can be determined that the fault is measurable.

[0049] While considerable expertise exists in Test Vector Generation (ATPG) for digital integrated circuits, progress in ATPG for analog integrated circuits has been relatively slow. Furthermore, unlike digital integrated circuit ATPG where the excitation type is a simple binary 0 or 1 code representing digital voltage, analog integrated circuit test excitations can be complex, such as continuous-time signals, multi-tone / multi-frequency signals, single-frequency single-amplitude sine waves, or even single-amplitude DC excitations.

[0050] However, the evaluation of test stimuli depends on fault coverage. To obtain fault coverage, the aforementioned nonlinear equations need to be solved, which involves performing SPICE (Simulation Program with Integrated Circuit Emphasis) simulations. More complex stimuli require longer simulation times, but consequently, they become more capable of reflecting differences in algebraic relationships.

[0051] With the increasing complexity of analog integrated circuits (ICs), especially mixed-signal circuits, the time cost of using complex excitation signals during simulation has increased significantly. To address this challenge, this invention proposes a test method based on DC excitation. This method utilizes the SPICE tool to perform optimally fast DC analysis to evaluate fault coverage, thereby effectively shortening the test cycle.

[0052] In traditional analog IC design, there are typically one or two voltage sources. However, as the number of voltage sources increases, the potential combinations of test stimuli grow exponentially. For example, for a single voltage source, if there are 20 different effective voltage levels within its operating range, there are 20 possible test stimuli. With two voltage sources, the number of different voltage combinations reaches 400; and with three voltage sources, this number jumps to 8,000. Even with rapid simulation of each combination in SPICE DC simulation mode, the cumulative time overhead is still significant.

[0053] Therefore, selecting a single test stimulus or combination of test stimuli that can achieve sufficiently high fault coverage without a comprehensive evaluation of all potential test stimuli is a challenging task.

[0054] One challenge in evaluating test stimuli is that their exact fault coverage cannot be known until these tests are actually performed. Therefore, the selection of the next test stimuli to evaluate must rely on prior experience and existing information. In other words, it is necessary to determine, based on currently available information, which test stimuli should be evaluated next to optimize fault detection efficiency.

[0055] The test stimulus generation process presents a classic "exploration-exploitation" problem: on the one hand, it requires exploring uncertain areas that haven't yet been evaluated but may offer higher fault coverage; on the other hand, it also needs to focus on areas that, based on existing information, show promise for good results. To achieve optimal fault detection efficiency, a reasonable balance must be found between these two aspects. Specifically, based on the information provided by currently evaluated test stimuli, strategies can be developed to determine which test stimulus should be evaluated next, ensuring that potentially better test points are not missed while fully utilizing proven and effective resources.

[0056] Bayesian optimization is one method used to solve such problems. It is a sequential design strategy for global optimization, particularly suitable for situations where the objective function is costly to evaluate, non-differentiable, or noisy. Unlike traditional gradient-based methods, Bayesian optimization approximates the unknown objective function by constructing a surrogate model (usually a Gaussian process) and uses this model to guide the search process. The Bayesian optimization process can be briefly described as follows:

[0057] 1) Select a set of initial observation points and evaluate the objective function values ​​at these points. This data will be used to train the initial surrogate model.

[0058] 2) Based on existing observation data, a statistical model, such as a Gaussian process, is used as a surrogate model to model the objective function. This model can not only predict the output values ​​of unvisited locations but also provide an estimate of the uncertainty of the prediction. This step embodies the "prior" in Bayesian methods, that is, our assumptions about the objective function when there is no new information.

[0059] 3) Define an acquisition function, which is a function of the posterior distribution of the surrogate model. The acquisition function measures the value of potential evaluation points, taking into account both exploration and exploitation. Select the points that maximize the acquisition function as candidate points for the next objective function to be evaluated.

[0060] 4) Evaluate the objective function value at the selected new point and add this new observation to the existing dataset. Then, based on all available data, update the parameters of the surrogate model using Bayes' theorem to obtain the "posterior" distribution of the objective function. This update reflects a more accurate understanding of the objective function as new information becomes available.

[0061] By employing Bayesian optimization algorithms to explore and select optimal test stimuli, fault coverage can be maximized within a limited number of evaluations. However, in this process, fault coverage depends not only on the number of faults that the test stimuli can diagnose, but also on the overlap characteristics between test stimuli. Some test stimuli with low fault coverage may be able to detect unique faults that test stimuli with high fault coverage fail to detect.

[0062] Therefore, to utilize all test stimuli more efficiently during the exploration process, a comprehensive evaluation approach is needed. This involves a thorough analysis of all evaluated test stimuli to select a combination that maximizes overall fault coverage. This goes beyond simply choosing the test stimuli with the highest individual fault coverage; rather, it involves constructing a set of test stimuli where each member contributes its unique fault coverage capability, ensuring that as many potential faults as possible are diagnosed.

[0063] Furthermore, this phenomenon suggests that if the selection of test stimuli with high fault coverage is simply used as the goal of Bayesian optimization during the test stimulus generation process, it may lead to insufficient overall fault coverage of the final test stimulus combination. To address this issue, this invention proposes a test stimulus generation strategy based on multi-stage Bayesian optimization.

[0064] In multi-stage Bayesian optimization, each stage has a fixed number of evaluations. At the beginning of each stage, the algorithm selects a new test stimulus that yields the highest fault coverage when combined with the currently selected test stimuli. At the end of the stage, all test stimuli that participated in the selection process are added to the pool of selected test stimuli. Simultaneously, the fault detection rates and stimulus point information of these test stimuli are fed into a Gaussian model for pre-learning to better guide the selection in subsequent stages.

[0065] Meanwhile, as more and more faults are covered, the uncovered faults will concentrate on some singularities. These singularities are almost unrelated to the number of detectable faults in the surrounding points. In other words, as the number of rounds increases, the role of prior experience becomes smaller and smaller. Therefore, this invention gradually increases the randomness of the algorithm as the number of rounds increases, choosing exploration more than relying on prior experience in the "exploration-exploitation" balance.

[0066] In this way, at each new stage, the optimization objective is to select new test stimuli that, when combined with the test stimuli evaluated in previous stages, achieve the highest fault coverage. This process continues until the pre-set maximum number of evaluations or the expected fault coverage is reached. Once the optimization process stops, a subset of all evaluated test stimuli is selected, ensuring that the minimum number of test stimuli is used while maintaining the same level of fault coverage.

[0067] This approach not only improves the efficiency of fault diagnosis but also ensures the diversity of test stimulus combinations, avoiding the limitations that may arise from solely pursuing high fault coverage. Through multi-stage optimization and pre-learning of Gaussian models, the most effective test stimuli can be identified and selected more accurately, thereby achieving comprehensive and efficient fault coverage.

[0068] Based on the above analysis, this invention proposes a test stimulus generation method for analog integrated circuits based on multi-stage Bayesian optimization, aiming to find the test stimulus combination with the highest fault coverage within a limited number of evaluations. Figure 1 This is a flowchart illustrating a specific implementation of the analog integrated circuit test stimulus generation method based on multi-stage Bayesian optimization according to the present invention. Figure 1 As shown, the specific steps of the analog integrated circuit test stimulus generation method based on multi-stage Bayesian optimization of the present invention include:

[0069] S101: Component Fault Modeling and Injection

[0070] For the analog integrated circuit under test, all components in the circuit netlist are identified, fault models are established for all components except the power supply, and a fault list is generated. Each fault model is equivalently compressed and injected into the analog integrated circuit under test one by one to obtain the fault simulation integrated circuit.

[0071] This approach simulates faults that may occur during actual manufacturing processes due to various failure mechanisms (such as additional metal deposition). This embodiment uses the Fault 10 model provided by the IEEE P2427 standard proposal. According to the definition in the IEEE P2427 draft standard, a fault is considered an unexpected permanent change in a circuit element or its connection that is not within the component's manufacturing specifications. Device-level faults in integrated circuits are generally divided into two categories: parametric faults and hard faults. Hard faults are usually caused by problems in the silicon manufacturing process, such as dust particles or insufficient etching, which can lead to changes in the topology of the manufactured circuit.

[0072] Defect-Oriented Testing (DOT) relies on precisely defined fault models to achieve a quantitative assessment of fault coverage. Although fault modeling in analog integrated circuits has not yet reached the same level of standardization as in digital circuits, an emerging draft standard proposed by the IEEE P2427 working group is working to address the standardization of hard fault modeling in analog integrated circuits and power electronics. Figure 2 This is the component hard fault model information table specified in IEEE P2427. For example... Figure 2 As shown, for two-port components (such as resistors and capacitors), two basic fault modes are defined: open circuit and short circuit. For three-port components (such as MOSFETs and transistors), an open circuit condition and a short circuit condition between any two ports are defined for each port, for a total of six fault modes. In this embodiment, to improve simulation efficiency and avoid unnecessary computational overhead, short circuit faults are not injected into components with the same ports.

[0073] In this embodiment, fault injection is accomplished by generating code blocks for different devices in the SPICE netlist. The netlist structure is modified using the SPICE ".alter" statement to modify and simulate the netlist describing a fault-free circuit. Here, code block generation is implemented using Python, while the actual netlist modification and simulation are performed using HSPICE software. This simulates circuits with various faults and obtains circuit performance parameters. By comparing the response of the faulty circuit with the baseline response of the fault-free circuit, the fault detection results can be analyzed. Figure 3 This is an example diagram of MOSFET fault injection in this embodiment. Figure 3 As shown in the figure, Figure (a) illustrates the injection methods for short-circuit fault, open-circuit fault, and open-gate fault of three-terminal device, and Figure (b) illustrates the fault models for short-circuit fault, open-circuit fault, and open-gate fault of three-terminal device.

[0074] S102: Establish the search space:

[0075] Based on the number M of excitation sources of the analog integrated circuit under test and the voltage range of each excitation source, an M-dimensional search space is established. Since modifying the excitation source value within a specific granularity does not change the circuit response, this invention introduces the concept of an excitation step size. The test excitation step size (i.e., search accuracy) is set according to actual needs, and then the search space is discretized to obtain the coordinates of each search grid point.

[0076] Figure 4 This is an example diagram of the search space. For example... Figure 4As shown, in this embodiment, 0.1V is selected as the excitation step size. Furthermore, since it is a CMOS circuit, the voltage range is generally [0, 2.5V]. If there are two excitation sources, the search space is a two-dimensional search space, where the blue points correspond to the acceptable excitation points. If there are three excitation sources, the search space is a three-dimensional search space, where the red points are the acceptable excitation points.

[0077] S103: Initial sampling point:

[0078] D initial points (start) are obtained by sampling in the search space. d d = 1, 2, ..., D, in analog integrated circuits, for each initial point start d Perform fault simulation and record each initial point (start). d Detectable fault set

[0079]

[0080] In this embodiment, the Latin hypercube sampling method is used to obtain the initial point. Latin hypercube sampling (LHS) is a random sampling technique used in multidimensional space, commonly employed in computer experiments and Monte Carlo simulations. It aims to uniformly cover the multidimensional parameter space, improving sampling efficiency and accuracy. The core idea of ​​LHS is to divide the range of each dimension into equally probable intervals, ensuring that each interval is sampled once in each dimension. This ensures a uniform distribution of each parameter in the high-dimensional space while avoiding sample point clustering. The specific method of Latin hypercube sampling is as follows:

[0081] The interval of each dimension in the search space is uniformly divided into L smaller intervals. For each dimension m, the corresponding excitation value space is normalized to the interval [0,1], and then divided into L sub-intervals of equal length:

[0082]

[0083] For each dimension, randomly select a point from these sub-intervals, ensuring that each sub-interval is selected once in each dimension. This guarantees a uniform distribution across each dimension. Combine the random points in each dimension to form D initial points in M ​​dimensions.

[0084] S104: Test stimulus set based on multi-stage Bayesian optimization search:

[0085] Next, we optimize the search test incentive set based on multi-stage Bayesian optimization. Figure 5 This is a flowchart illustrating the multi-stage Bayesian optimization search for the test stimulus set in this invention. (For example...) Figure 5As shown, the specific steps of searching the test stimulus set based on multi-stage Bayesian optimization in this invention include:

[0086] S501: Initialize the historical stimulus set:

[0087] Find D initial points start d Detectable fault set The set of all faults is taken as the combined fault detection set F1. The number of detectable faults in the combined fault detection set F1 is taken as the combined fault detection quantity V1. Then, the combined fault detection quantity V1 is taken as the starting point for each fault. d The objective function value is obtained, thus yielding the historical stimulus set E1.

[0088] S502: Pre-trained surrogate model:

[0089] The proxy model is set up according to actual needs, and the historical stimulus set E1 is used to pre-train the proxy model.

[0090] In Bayesian optimization, the surrogate model not only predicts the output values ​​at unvisited locations but also provides an estimate of the uncertainty of the prediction. This step embodies the "prior" in Bayesian optimization methods, namely, the assumptions made about the objective function in the absence of new information. The surrogate model can be set according to actual needs; in this embodiment, a Gaussian process model is used.

[0091] S503: Let the Bayesian optimization round s = 1.

[0092] S504: Bayesian optimization:

[0093] Perform Bayesian optimization in the s-th round. Figure 6 This is a flowchart of Bayesian optimization in this invention. For example... Figure 6 As shown, the specific steps of Bayesian optimization in this invention include:

[0094] S601: Let the number of search rounds r = 1.

[0095] S602: Selecting the stimulus:

[0096] Set the sampling function according to actual needs, in the historical excitation set E s The excitation p is selected in the search space based on the maximum value of the sampling function in the complement set. s,r .

[0097] In Bayesian optimization, the most crucial technique is the acquisition function, which is a function of the posterior distribution of the surrogate model, typically denoted by α(x). In this embodiment, the acquisition function used is the probability of improvement (PI) function, and its calculation formula is as follows:

[0098] α PI (x)=P(f(x)≥(f(x + )+∈)) (2)

[0099] Where, α PI (x) represents the probability of improvement, and P(·) represents the probability, x + Is it in the first t steps that f(x) is made? i The largest point x i , where i∈[1,t]. ∈ is a very small positive number used to balance the "exploitation-exploitation" process.

[0100] Since the surrogate model used in this embodiment is a Gaussian process model, the formula for improving probability PI can be expressed as:

[0101]

[0102] Where Φ(·) is the cumulative distribution function (CDF), and μ t (x) is the mean of the t points that have been evaluated, σ t (x) is the standard deviation of the t points that have been evaluated.

[0103] Φ(x)=P(X≤x) (4)

[0104] When searching, according to formula (3), x t It is a known optimal value, and its vicinity is higher than μ. t The CDF value of (x) will be relatively large, x t+1 The position will be x t This reflects the "utilization" of existing optimal values. Since the goal of Bayesian optimization is not to simulate the entire curve using a Gaussian process, but to find the best possible value with the fewest possible samplings, it is necessary to add ∈ as a constant to balance the exploration utilization. Due to the unexplored region, σ... t Since (x) is relatively large, the CDF of the unexplored region is relatively large after appropriately increasing ∈. In summary, increasing the value of ∈ helps to explore unknown regions, while decreasing the value of ∈ helps to utilize existing regions.

[0105] S603: Simulation yields a set of detectable faults:

[0106] The analog acquisition circuit is simulated to obtain the excitation p. s,r The set of detectable faults f s,r Find the set of detectable faults f. s,r and combined fault detection set F s The set of detectable faults in the set is used as the excitation p.s,r The corresponding number of combined fault detections V s,r .

[0107] S604: Update the proxy model:

[0108] Using excitation p s,r and the corresponding number of combined fault detections V s,r Update the proxy model.

[0109] By updating the parameters of the surrogate model using the incentives selected in each search and the corresponding objective function values, the "posterior" distribution of the objective function can be obtained. This update reflects a more accurate understanding of the objective function as new information becomes available.

[0110] S605: Determine whether r < R, where R represents the search round of each Bayesian optimization round. If yes, proceed to step S606; otherwise, end the current round of Bayesian optimization.

[0111] S606: Let the search round number r = r + 1, and return to step S602.

[0112] S505: Determine whether the Bayesian optimization termination condition has been met. If yes, proceed to step S506; otherwise, proceed to step S508. The Bayesian optimization termination condition can be set according to actual needs. It can be set to the maximum number of Bayesian optimization rounds or the number of detectable faults reaching the total number of faults.

[0113] S506: Update historical stimulus set:

[0114] Find the R incentives p obtained by the Bayesian optimization in this round. s,r The set of detectable faults f s,r and combined fault detection set F s The collection of, as the combined fault detection set F s+1 The number of detectable faults in this set is taken as the combined fault detection quantity V. s+1 Then, the number of combined fault detections, V, is calculated. s+1 The R incentives p obtained in this round of Bayesian optimization are... s,r and historical inspiration set E s Given the original objective function value, we obtain the historical stimulus set E. s+1 .

[0115] S507: Let the Bayesian optimization round s = s + 1, and return to step S504.

[0116] S508: Obtain the test stimulus set:

[0117] Historical incentive set E S The test stimuli in the test stimulus set E are used as the final test stimulus set for the analog integrated circuit test.

[0118] The test stimulus set obtained above covers all simulated stimuli in the search process. While this ensures comprehensive testing, it inevitably introduces a large number of redundant test stimuli. To more effectively control testing costs and improve testing efficiency, after the defect coverage of the test stimulus set reaches the expected target, the test stimuli can be screened and optimized to achieve the highest possible defect detection rate with the fewest possible test stimuli. Since simultaneously satisfying the two objectives of low testing cost and high testing performance is a multi-objective optimization problem, and multi-objective optimization problems usually have multiple Pareto optimal solutions, finding and determining the Pareto optimal solution set is the key to solving multi-objective problems. Based on the above principle, this embodiment uses the Pareto genetic algorithm to further optimize the test stimulus set E, aiming to find a series of Pareto optimal solutions, thereby providing a diverse selection set that allows for a more reasonable decision-making process that balances cost and performance based on actual conditions and needs. Figure 7 This is a flowchart illustrating the optimal test incentive based on the Pareto genetic algorithm in this embodiment. For example... Figure 7 As shown, the specific steps for test incentive optimization based on the Pareto genetic algorithm in this embodiment include:

[0119] S701: Define the optimization objective:

[0120] Determine the optimization objective for the test stimulus selection based on actual needs, denoted as B for the number of optimization objectives, and set the optimization objective function g for the test stimulus selection scheme. b (X), b = 1, 2, ..., B, the smaller the objective function value, the better the test plan. In this embodiment, there are two optimization objectives: the number of test stimulus vectors and the defect detection rate. The number of test stimulus vectors is related to the testing cost; generally, the larger the number of test stimulus vectors, the higher the testing cost. Therefore, it is necessary to minimize the number of test stimulus vectors. The objective function expression for optimizing the number of test stimulus vectors is:

[0121]

[0122] Where X = [x1, x2, ..., x D ] represents the test stimulus vector selection scheme, x d Let x be a binary variable. d =0 indicates that the d-th test stimulus vector was not selected in the test stimulus vector selection scheme for the individual. d =1 indicates that the d-th test stimulus vector is selected in the test plan corresponding to the individual, where d = 1, 2, ..., D, and D represents the number of test stimulus vectors in the test stimulus set E.

[0123] Regarding defect detection rate, a higher defect detection rate allows for a better selection of test stimulus schemes. Therefore, the objective function expression for optimizing the defect detection rate is:

[0124] g2(X)=1-fdr(X) (6)

[0125] Where fdr(X) represents the defect detection rate of the test stimulus vector selection scheme. Defect coverage equals the number of detectable defects divided by the total number of injected defects. all The calculation formula is as follows:

[0126]

[0127] Therefore, the multi-objective function expression in this embodiment is as follows:

[0128]

[0129] S702: Generate the initial population.

[0130] Generating the initial population is the first step in a genetic algorithm, and its quality directly affects the effectiveness of subsequent evolution. In practical applications, a random method is usually used to generate the initial population. In this embodiment, H individuals X are randomly generated. h =[x h,1 ,x h,2 ,…,x h,D ], h = 1, 2, ..., H, where each individual represents a test stimulus vector selection scheme, x h,d =0 indicates that the d-th test stimulus vector was not selected in the test stimulus vector selection scheme for the individual. h,d =1 indicates that the d-th test stimulus vector is selected in the test scheme corresponding to the individual, where d = 1, 2, ..., D, and D represents the number of test stimulus vectors in the test stimulus set E. The H randomly generated individuals form the initial population P.

[0131] S703: Set the iteration count t = 1.

[0132] S704: Generate a new population:

[0133] Select, crossover, and mutate individuals in population P to generate a new population Q.

[0134] Since each individual in this embodiment is a binary encoded vector, the classic single-point crossover method is used for individual crossover, and the classic single-point mutation method is used for individual mutation.

[0135] S705: Merging populations:

[0136] The populations P and Q are merged to obtain the population S = P∪Q.

[0137] S706: Individual optimization based on Pareto optimality:

[0138] Calculate the B optimization objective function values ​​for each individual in population S. Determine the Pareto dominance relationship between any two individuals based on the optimization objective function values. Count the number of times each individual is dominated. Sort all individuals in ascending order of the number of times they are dominated. Select the top H individuals to form the preferred population P′.

[0139] S707: Determine if the iteration count t < t max , t max This indicates the preset maximum number of iterations. If so, proceed to step S708; otherwise, proceed to step S709.

[0140] S708: Let the iteration number t = t + 1, let the population P = P′, and return to step S704.

[0141] S709: Optimal solution for obtaining test stimulus vectors:

[0142] Non-dominated individuals in the preferred population P′ are selected based on Pareto dominance, and the test incentive vector selection schemes corresponding to these non-dominated individuals are considered as the preferred schemes. It is evident that by selecting non-dominated individuals, decision-makers are provided with the information needed to weigh multiple objectives.

[0143] To better illustrate the technical solution of this invention, specific examples are used to experimentally verify the invention. In this embodiment, the bandgap reference circuit provided by the IEEE P2427 working group is used to verify the feasibility of this invention. Figure 8 This is a structural diagram of the bandgap reference circuit in this embodiment. (See diagram below.) Figure 8 As shown, the Bandgap reference circuit contains a total of 102 components, including 43 three-terminal components and 59 two-terminal components. A detailed analysis of the test stimulus generation for the Bandgap reference circuit is performed using the Python scripting language and Hspice simulation software.

[0144] Based on the fault simulation framework described in the IEEE standard proposal, fault models were constructed for all components in the circuit. Open-circuit faults were simulated as a 1GΩ resistor in series with the fault terminal, while short-circuit faults were modeled as a 200Ω resistor in parallel between the fault terminals. A total of 376 complete faults were generated; after redundancy reduction, 340 faults were generated for the Bandgap circuit. Verification showed that using all test stimuli, 274 of the 340 faults could be detected. This means that 66 faults were undetectable.

[0145] The IEEE bandgap reference circuit contains three nominally 2.5V excitation sources, but only two are actually connected to the circuit, thus limiting the voltage range to [0, 2.5V]. A two-dimensional search space can be established. Twelve MOS transistor gate nodes and one output node, for a total of thirteen nodes, are used as measurement points. Table 1 shows the number of combined fault detections corresponding to the initial point of the Latin hypercube sampling and the four points of the first round of Bayesian optimization in this embodiment.

[0146]

[0147] Table 1

[0148] At this point, the historical stimulus pool is empty, so the number of combined fault detections is the same as the number of fault detections selected from the stimuli. Eight stimuli were selected in this round, with (0, 1.9) detecting the most faults. Using these test vectors, a total of 254 faults can be detected.

[0149] All selected incentives in this round are added to the historical incentive pool. In the next round of Bayesian optimization, all incentives are combined with incentives in the historical incentive pool and the combined fault detection number is evaluated. This process is repeated until the expected fault detection number is reached.

[0150] In this experiment, the expected number of fault detections was 272 (out of 274). In the first round of Bayesian optimization, 8 stimuli were evaluated, resulting in the diagnosis of 254 faults, a fault coverage rate of 74.7%, and a detectable fault coverage rate of 92.7%. In the third round of Bayesian optimization, 16 stimuli were evaluated, resulting in the diagnosis of 256 faults, a fault coverage rate of 75.3%, and a detectable fault coverage rate of 93.4%. In the ninth round of Bayesian optimization, 60 stimuli were evaluated, resulting in the diagnosis of 269 faults, a fault coverage rate of 79.1%, and a detectable fault coverage rate of 98.2%. In the fifteenth round of Bayesian optimization, 64 stimuli were evaluated, resulting in the diagnosis of 272 faults, achieving a fault coverage rate of 80% and a detectable fault detection rate of 100%.

[0151] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A method for generating test stimuli for analog integrated circuits based on multi-stage Bayesian optimization, characterized in that, Includes the following steps: S1: For the analog integrated circuit under test, identify all components in the circuit netlist, establish fault models for all components except the power supply, generate a fault list, perform equivalent compression on each fault model, and inject them one by one into the analog integrated circuit under test to obtain the fault simulation integrated circuit. S2: Based on the number M of excitation sources of the analog integrated circuit under test and the voltage range of each excitation source, establish an M-dimensional search space; set the test excitation step size according to actual needs, and then discretize the search space to obtain the coordinates of each search grid point; S3: Sample D initial points (start) from the search space. d d = 1, 2, ..., D, in analog integrated circuits, for each initial point start d Perform fault simulation and record each initial point (start). d Detectable fault set S4: Optimize the search test incentive set based on multi-stage Bayesian methods, including the following steps: S4.1: Find D initial points start d Detectable fault set The set of all faults is taken as the combined fault detection set F1. The number of detectable faults in the combined fault detection set F1 is taken as the combined fault detection quantity V1. Then, the combined fault detection quantity V1 is taken as the starting point for each fault. d The objective function value is obtained, thus yielding the historical stimulus set E1; S4.2: Set up the proxy model according to actual needs, and pre-train the proxy model using the historical stimulus set E1; S4.3: Let the Bayesian optimization round s = 1; S4.4: Perform Bayesian optimization in the s-th round, the specific method is as follows: S4.4.1: Let the number of search rounds r = 1; S4.4.2: Set the sampling function according to actual needs, in the historical excitation set E s The excitation p is selected in the search space based on the maximum value of the sampling function in the complement set. s,r ; S4.4.3: Simulate the analog acquisition circuit to obtain the excitation p. s,r The set of detectable faults f s,r ; Obtain the set of detectable faults f s,r and combined fault detection set F s The set of detectable faults in the set is used as the excitation p. s,r The corresponding number of combined fault detections V s,r ; S4.4.4: Using excitation p s,r and the corresponding number of combined fault detections V s,r Update the proxy model; S4.4.5: Determine whether r < R, where R represents the search round of each Bayesian optimization round. If yes, proceed to step S4.4.6; otherwise, end the current round of Bayesian optimization. S4.4.6: Let the search round number r = r + 1, and return to step S4.4.2; S4.5: Determine whether the Bayesian optimization termination condition has been met. If yes, proceed to step S4.6; otherwise, proceed to step S4.

8. S4.6: Obtain the R incentives p obtained from the Bayesian optimization in this round. s,r The set of detectable faults f s,r and combined fault detection set F s The collection of, as the combined fault detection set F s+1 The number of detectable faults in this set is taken as the combined fault detection quantity V. s+1 Then, the number of combined fault detections, V s+1 The R incentives p obtained in this round of Bayesian optimization are... s,r and historical inspiration set E s Given the original objective function value, we obtain the historical stimulus set E. s+1 ; S4.7: Let the Bayesian optimization round s = s + 1, and return to step S4.4; S4.8: The historical stimulus set E S The test stimulus set E serves as the final analog circuit test set.

2. The analog integrated circuit test stimulus generation method according to claim 1, characterized in that, The initial point in step S3 is obtained by sampling using the Latin hypercube sampling method.

3. The analog integrated circuit test stimulus generation method according to claim 1, characterized in that, In step S4.2, the proxy model adopts the Gaussian process model.

4. The method for generating test stimuli for analog integrated circuits according to claim 1, characterized in that, The sampling function in step S4.4.2 adopts an improved probability function.

5. The method for generating test stimuli for analog integrated circuits according to claim 1, characterized in that, Step S4.8 also includes test incentive optimization based on the Pareto genetic algorithm for the current test incentive set E. The specific method is as follows: S4.8.1: Determine the optimization objective for the test stimulus selection based on actual needs, denoted as B for the number of optimization objectives, and set the optimization objective function g for the test stimulus selection scheme. b (X), b = 1, 2, ..., B, the smaller the value of the objective function, the better the test plan; S4.8.2: Randomly generate H individuals X h =[x h,1 ,x h,2 ,…,x h,D ], h = 1, 2, ..., H, where each individual represents a test stimulus vector selection scheme, x h,d =0 indicates that the d-th test stimulus vector was not selected in the test stimulus vector selection scheme for the individual. h,d =1 indicates that the d-th test stimulus vector is selected in the test scheme corresponding to the individual, where d = 1, 2, ..., D, and D represents the number of test stimulus vectors in the test stimulus set E; the H randomly generated individuals form the initial population P; S4.8.3: Set the iteration count t = 1; S4.8.4: Perform selection, crossover, and mutation operations on individuals in population P to generate a new population Q; S4.8.5: Merge population P and population Q to obtain population S = P∪Q; S4.8.6: Calculate the B optimization objective function values ​​corresponding to each individual in the population S, determine the Pareto dominance relationship between any two individuals based on the optimization objective function values, count the number of times each individual is dominated, sort all individuals in ascending order of the number of times they are dominated, and select the top H individuals to form the preferred population P′. S4.8.7: Determine if the iteration count t < t max , t max This indicates the preset maximum number of iterations. If so, proceed to step S4.8.8; otherwise, proceed to step S4.8.

9. S4.8.8: Let the iteration number t = t + 1, let the population P = P′, and return to step S4.8.4; S4.8.9: Select non-dominated individuals from the preferred population P′ based on the Pareto dominance relationship, and use the test incentive vector selection scheme corresponding to these non-dominated individuals as a preferred scheme.

6. The method for generating test stimuli for analog integrated circuits according to claim 5, characterized in that, The optimization objective function in step S4.8.1 includes an optimization objective function for the number of test stimulus vectors and an optimization objective function for the defect detection rate. The expression for the optimization objective function for the number of test stimulus vectors is: Where X = [x1, x2, ..., x D ] represents the test stimulus vector selection scheme, x d Let x be a binary variable. d =0 indicates that the d-th test stimulus vector was not selected in the test stimulus vector selection scheme for the individual. d =1 indicates that the d-th test stimulus vector is selected in the test plan corresponding to the individual, where d = 1, 2, ..., D, and D represents the number of test stimulus vectors in the test stimulus set E; The objective function for optimizing the defect detection rate is expressed as follows: g2(X)=1-fdr(X) Where fdr(X) represents the defect detection rate of the test stimulus vector selection scheme.

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