Display device and method of driving the same

Abstract

The invention discloses a display device and a method of driving the same. The display device includes: a first pixel connected to a first data line and a first scan line; a second pixel connected to the first data line and the second scan line; a first scan driver connected to the first scan start line and the first scan line; and a second scan driver connected to the second scan start line and the second scan line. In a first frame period, after a first period has elapsed after a first scan start signal having a turn-on level is supplied to a first scan start line, a second scan start line is supplied with a second scan start signal having a turn-on level. In a second frame period, a difference between a time at which a first scan start signal having an on level is supplied and a time at which a second scan start signal having an on level is supplied corresponds to a second period. The second period is shorter than the first period.

Description

[0001] This application is a divisional application of the invention with the application date of November 9, 2020, application number 202011238560.2, and title "Display device and method for driving a display device".

[0002] Cross-reference to related applications

[0003] This application claims the priority and benefits of Korean Patent Application No. 10-2019-0173279, filed with the Korean Intellectual Property Office on December 23, 2019, the entire disclosure of which is incorporated herein by reference. Technical field

[0004] The present disclosure generally relates to a display device and a method for driving the same. Background art

[0005] With the development of information technology, the importance of display devices as a connection medium between users and information has increased. Accordingly, display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices are increasingly utilized.

[0006] Each pixel of a display device may emit light having a luminance corresponding to a data voltage supplied through a data line. The display device may display an image frame by using a combination of light emitted from the pixels.

[0007] A plurality of pixels may be connected to each data line. Accordingly, a scan driver is required to provide a scan signal for selecting a pixel to which a data voltage is to be supplied among the plurality of pixels. The scan driver is configured in the form of a shift register to sequentially provide a scan signal having a conductive level in units of scan lines.

[0008] A clock signal may be provided to control the scan driver. As the frequency of the clock signal increases, more power consumption is required. Summary of the invention

[0009] Aspects of embodiments relate to a display device in which the frequency of a clock signal is controlled according to the type of a frame such that power consumption can be reduced, and a method for driving the display device.

[0010] According to an embodiment of the present disclosure, a display device is provided. The display device includes: a first pixel connected to a first data line and a first scan line; a second pixel connected to the first data line and a second scan line; a first scan driver connected to a first scan start line and the first scan line; and a second scan driver connected to a second scan start line and the second scan line. Wherein, in a first frame period, after a first period has elapsed after a first scan start signal having a conductive level is supplied to the first scan start line, the second scan start line is supplied with a second scan start signal having a conductive level. Wherein, in a second frame period, the difference between the time when the first scan start signal having a conductive level is supplied and the time when the second scan start signal having a conductive level is supplied corresponds to a second period. Wherein, the second period is shorter than the first period.

[0011] In the first frame period, the first scan clock signal supplied to the first scan driver may have a first period. In the second frame period, the first scan clock signal may have a second period longer than the first period.

[0012] In the first frame period, the second scan clock signal supplied to the second scan driver may have a first period. In the second frame period, the second scan clock signal may have a second period.

[0013] The display device may further include: a first emission driver connected to a first emission stop line and a first emission line; and a second emission driver connected to a second emission stop line and a second emission line. The first pixel may be connected to the first emission line, and the second pixel may be connected to the second emission line. In the first frame period, after a third period has elapsed after a first emission stop signal having a cut-off level is supplied to the first emission stop line, the second emission stop line may be supplied with a second emission stop signal having a cut-off level. In the second frame period, the difference between the time when the first emission stop signal having a cut-off level is supplied and the time when the second emission stop signal having a cut-off level is supplied may correspond to a fourth period. The fourth period may be shorter than the third period.

[0014] In the first frame period, the first emission clock signal supplied to the first emission driver may have a third period. In the second frame period, the first emission clock signal may have a fourth period longer than the third period.

[0015] In the first frame period, the second emission clock signal supplied to the second emission driver may have a third period. In the second frame period, the second emission clock signal may have a fourth period.

[0016] The display device may further include a third pixel connected to the first data line and a third scan line that is the next scan line of the first scan line. The third scan line may be connected to the first scan driver. In the first frame period, the difference between the time when the first scan signal having a conductive level is applied to the first scan line and the time when the third scan signal having a conductive level is applied to the third scan line may correspond to the third period. In the second frame period, the difference between the time when the first scan signal having a conductive level is applied and the time when the third scan signal having a conductive level is applied may correspond to the fourth period. The fourth period may be longer than the third period.

[0017] The display device may further include a fourth pixel connected to the first data line and a fourth scan line that is the next scan line of the second scan line. The fourth scan line may be connected to the second scan driver. In the first frame period, the difference between the time when the second scan signal having a conductive level is applied to the second scan line and the time when the fourth scan signal having a conductive level is applied to the fourth scan line may correspond to the third period. In the second frame period, the difference between the time when the second scan signal having a conductive level is applied and the time when the fourth scan signal having a conductive level is applied may correspond to the fourth period.

[0018] The display device may further include a fifth pixel connected to the first data line and a fifth scan line that is the previous scan line of the second scan line. The fifth scan line may be connected to the first scan driver. In the first frame period, the time when the fifth scan signal having a conductive level is applied to the fifth scan line may be earlier than the time when the second scan signal having a conductive level is applied. In the second frame period, the time when the fifth scan signal having a conductive level is applied may be later than the time when the second scan signal having a conductive level is applied.

[0019] The minimum value of the second period may be 0 seconds, and the maximum value of the second period may correspond to the vertical blanking period.

[0020] When the number of pixels connected to the first data line between the first pixel and the second pixel is X and the horizontal period is Y, the first period may correspond to (X + 1) × Y.

[0021] According to another embodiment of the present disclosure, a method of driving a display device is provided. The method includes: in a first frame period, supplying a first scan start signal having a conductive level to a first scan start line connected to a first scan driver; in the first frame period, after a first period has elapsed after the first scan start signal having a conductive level is supplied, supplying a second scan start signal having a conductive level to a second scan start line connected to a second scan driver; and in a second frame period that is the next frame period of the first frame period, supplying the first scan start signal having a conductive level and the second scan start signal having a conductive level with a time difference of a second period, where the second period is shorter than the first period.

[0022] In the first frame period, the first scan clock signal supplied to the first scan driver may have a first period. In the second frame period, the first scan clock signal may have a second period that is longer than the first period.

[0023] In the first frame period, the second scan clock signal supplied to the second scan driver may have a first period. In the second frame period, the second scan clock signal may have a second period.

[0024] The method may further include: in the first frame period, supplying a first emission stop signal having a cut-off level to a first emission stop line connected to a first emission driver; in the first frame period, after a third period has elapsed after the first emission stop signal having a cut-off level is supplied, supplying a second emission stop signal having a cut-off level to a second emission stop line connected to a second emission driver; and in the second frame period, supplying the first emission stop signal having a cut-off level and the second emission stop signal having a cut-off level with a time difference of a fourth period. The fourth period may be shorter than the third period.

[0025] In the first frame period, the first emission clock signal supplied to the first emission driver may have a third period. In the second frame period, the first emission clock signal may have a fourth period that is longer than the third period.

[0026] In the first frame period, the second emission clock signal supplied to the second emission driver may have a third period. In the second frame period, the second emission clock signal may have a fourth period.

[0027] The method may further include: in a first frame period, supplying, by a first scan driver, a first scan signal having a conductive level to a first scan line; in the first frame period, after a third period has elapsed after the first scan signal having the conductive level is supplied, supplying, by the first scan driver, a second scan signal having the conductive level to a second scan line that is a next scan line of the first scan line; and in a second frame period, supplying, by the first scan driver, the first scan signal having the conductive level and the second scan signal having the conductive level with a time difference of a fourth period. The fourth period may be longer than the third period.

[0028] The method may further include: in a first frame period, supplying, by a second scan driver, a third scan signal having a conductive level to a third scan line; in the first frame period, after a third period has elapsed after the third scan signal having the conductive level is supplied, supplying, by the second scan driver, a fourth scan signal having the conductive level to a fourth scan line that is a next scan line of the third scan line; and in a second frame period, supplying, by the second scan driver, the third scan signal having the conductive level and the fourth scan signal having the conductive level with a time difference.

[0029] The method may further include: in a first frame period, supplying, by the first scan driver, a fifth scan signal having a conductive level to a fifth scan line that is a previous scan line of the third scan line. In the first frame period, the time when the fifth scan signal having the conductive level is supplied may be earlier than the time when the third scan signal having the conductive level is supplied. In the second frame period, the time when the fifth scan signal having the conductive level is supplied may be later than the time when the third scan signal having the conductive level is supplied. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. However, the subject matter of the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0031] In the drawings, the dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals refer to the same elements throughout.

[0032] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0033] Figure 2 is a diagram illustrating a pixel according to an embodiment of the present disclosure.

[0034] Figure 3 It is a diagram showing a high-frequency driving method according to an embodiment of the present disclosure.

[0035] Figure 4 It is a diagram showing a data writing period according to an embodiment of the present disclosure.

[0036] Figure 5 It is a diagram showing a data writing period according to another embodiment of the present disclosure.

[0037] Figure 6 It is a diagram showing a low-frequency driving method according to an embodiment of the present disclosure.

[0038] Figure 7 It is a diagram showing a bias refresh period according to an embodiment of the present disclosure.

[0039] Figure 8 It is a diagram showing a bias refresh period according to another embodiment of the present disclosure.

[0040] Figure 9 It is a diagram showing a scan driver according to an embodiment of the present disclosure.

[0041] Figure 10 It is a diagram showing a third scan driver according to an embodiment of the present disclosure.

[0042] Figure 11 It shows Figure 10 a diagram of the scan levels of the third scan driver shown in

[0043] Figure 12 It shows Figure 11 a diagram of the driving method of the scan levels shown in

[0044] Figure 13 It is a diagram showing a first scan driver according to an embodiment of the present disclosure.

[0045] Figure 14 It shows Figure 13 a diagram of the scan levels of the first scan driver shown in

[0046] Figure 15 It shows Figure 14 a diagram of the driving method of the scan levels shown in

[0047] Figure 16 It is a diagram showing a second scan driver according to an embodiment of the present disclosure.

[0048] Figure 17 It is a diagram showing a transmission driver according to an embodiment of the present disclosure.

[0049] Figure 18FIG. is a diagram showing a first emission driver according to an embodiment of the present disclosure.

[0050] Figure 19 is a diagram showing Figure 18 the emission stage of the first emission driver shown in

[0051] Figure 20 is a diagram showing Figure 19 the driving method of the emission stage shown in

[0052] Figure 21 FIG. is a diagram showing a second emission driver according to an embodiment of the present disclosure.

[0053] Figure 22 and Figure 23 is a diagram showing a case where data write frames are consecutive.

[0054] Figures 24 to 26 is a diagram showing a case where data write frames and bias refresh frames are consecutive. DETAILED DESCRIPTION

[0055] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings so that those skilled in the art can practice the present disclosure. The present disclosure may be implemented in various suitable and different forms and is not limited to the example embodiments described in this specification. As used herein, when describing embodiments of the present disclosure, the use of the term "may" means "one or more embodiments of the present disclosure".

[0056] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than degree terms and are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art. It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to" or "adjacent to" another element or layer, it can be directly on, directly connected to, directly coupled to or directly adjacent to the other element or layer, or there may be one or more intervening elements or layers.

[0057] Parts that are not relevant to the description may be omitted (for example, elements and / or processes that may be involved in practicing the present disclosure but are not relevant to the present disclosure) to clearly describe the present disclosure, and throughout the specification, the same or similar constituent elements will be denoted by the same reference numerals. Accordingly, the same reference numerals may be used in different drawings to identify the same or similar elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0058] In addition, for better understanding and ease of description, the dimensions and thicknesses of each component shown in the drawings may be exaggerated, and the present disclosure is not limited thereto. For clear expression or description, the thicknesses of some parts and regions may be exaggerated.

[0059] Figure 1 is a diagram showing a display device according to an embodiment of the present disclosure.

[0060] Referring Figure 1 , the display device 9 may include a timing controller 10, a data driver 20, a scan driver 30, a transmission driver 40, and a pixel unit 50.

[0061] The timing controller 10 may receive an external input signal from an external processor. The external input signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and an RGB data signal (e.g., a red, green, and blue data signal), etc.

[0062] The vertical synchronization signal may include a plurality of pulses. As used herein, a pulse may refer to, for example, a voltage pulse or a current pulse. When each pulse of the vertical synchronization signal is generated, this may indicate that, relative to the time when the pulse is generated, the previous frame period ends and the current frame period begins. The interval between adjacent pulses of the vertical synchronization signal may correspond to one frame period. The horizontal synchronization signal may include a plurality of pulses. When each pulse of the horizontal synchronization signal is generated, this may indicate that, relative to the time when the pulse is generated, the previous horizontal period ends and a new horizontal period begins. The interval between adjacent pulses of the horizontal synchronization signal may correspond to one horizontal period. The data enable signal may have an enable level in one or more horizontal periods (e.g., a specific horizontal period), and a disable level in other periods. When the data enable signal has an enable level, this may indicate that the RGB data signal is supplied in the corresponding horizontal period. The RGB data signal may be supplied in each of the corresponding horizontal periods in units of pixel rows. The timing controller 10 may generate a grayscale value based on the RGB data signal to correspond to the specifications of the display device 9. The timing controller 10 may generate control signals to be supplied to the data driver 20, the scan driver 30, the transmission driver 40, etc., to correspond to the specifications of the display device 9.

[0063] The data driver 20 may generate data voltages to be provided to the data lines DL1, DL2, ……, and DLm by using the grayscale value and the control signal received from the timing controller 10. For example, the data driver 20 may sample the grayscale value by using a clock signal, and supply data voltages corresponding to the grayscale value to the data lines DL1, DL2, ……, and DLm in units of pixel rows (e.g., pixels connected to the same scan line). Here, m may be an integer greater than 0.

[0064] The scan driver 30 may generate scan signals to be provided to scan lines GIL1, GWNL1, GWPL1, GBL1, ……, GILn, GWNLn, GWPLn, and GBLn by receiving a clock signal, a scan start signal, etc. from the timing controller 10. Here, n may be an integer greater than 0.

[0065] The scan driver 30 may include a plurality of sub-scan drivers. In an example, the first sub-scan driver may provide scan signals for scan lines GIL1, ……, and GILn, the second sub-scan driver may provide scan signals for scan lines GWNL1, ……, and GWNLn, the third sub-scan driver may provide scan signals for scan lines GWPL1, ……, and GWPLn, and the fourth sub-scan driver may provide scan signals for scan lines GBL1, ……, and GBLn. Each of the sub-scan drivers may include a plurality of scan stages connected in the form of a shift register. For example, the scan driver 30 may generate scan signals in such a manner that a scan start signal having a conductive level (e.g., conductive amplitude) supplied to the scan start line is sequentially transmitted to the next scan stage.

[0066] In another example, the first sub-scan driver and the second sub-scan driver may be integrated to provide scan signals for scan lines GIL1, GWNL1, ……, GILn, and GWNLn, and the third sub-scan driver and the fourth sub-scan driver may be integrated to provide scan signals for scan lines GWPL1, GBL1, ……, GWPLn, and GBLn. For example, the previous scan line of the nth scan line GWNLn (e.g., the (n - 1)th scan line) may be connected to the same electrical node as the nth scan line GILn. In addition, for example, the next scan line of the nth scan line GWPLn (e.g., the (n + 1)th scan line) may be connected to the same electrical node as the nth scan line GBLn.

[0067] The first sub-scan driver and the second sub-scan driver may supply scan signals having pulses of a first polarity to scan lines GIL1, GWNL1, ……, GILn, and GWNLn. Additionally, the third sub-scan driver and the fourth sub-scan driver may supply scan signals having pulses of a second polarity to scan lines GWPL1, GBL1, ……, GWPLn, and GBLn. The first polarity and the second polarity may be opposite polarities to each other.

[0068] In the following, the polarity may represent the logic level of a pulse. For example, when a pulse has a first polarity, the pulse may have a high level. A pulse with a high level may be referred to as a rising pulse. When a rising pulse is supplied to the gate electrode of an N-type (e.g., N-class) transistor, the N-type transistor may conduct. For example, the rising pulse may be the conduction level with respect to the N-type transistor. Assume a case where a voltage having a level sufficiently lower than the level of the gate electrode of the N-type transistor (e.g., lower than the voltage applied to the gate electrode) is applied to the source electrode of the N-type transistor. For example, the N-type transistor may be an NMOS transistor.

[0069] In addition, when a pulse has a second polarity, the pulse may have a low level. A pulse with a low level may be referred to as a falling pulse. When a falling pulse is supplied to the gate electrode of a P-type (e.g., P-class) transistor, the P-type transistor may conduct. For example, the falling pulse may be the conduction level with respect to the P-type transistor. Assume a case where a voltage having a level sufficiently higher than the level of the gate electrode of the P-type transistor (e.g., higher than the voltage applied to the gate electrode) is applied to the source electrode of the P-type transistor. For example, the P-type transistor may be a PMOS transistor.

[0070] The emission driver 40 may generate emission signals to be provided to the emission lines EL1, EL2, …, and ELn by receiving a clock signal, an emission stop signal, etc. from the timing controller 10. For example, the emission driver 40 may sequentially provide emission signals of pulses having a cutoff level (e.g., cutoff amplitude) to the emission lines EL1, EL2, …, and ELn. For example, the emission driver 40 may be configured in the form of a shift register and may generate emission signals in such a way that an emission stop signal of a pulse having a cutoff level is sequentially transmitted to the next emission stage under the control of the clock signal.

[0071] The pixel unit 50 includes pixels. For example, the pixel PXnm may be connected to a corresponding data line DLm, corresponding scan lines GILn, GWNLn, GWPLn, and GBLn, and a corresponding emission line ELn.

[0072] Figure 2 is a diagram showing a pixel according to an embodiment of the present disclosure.

[0073] Reference Figure 2 , the pixel PXnm according to an embodiment of the present disclosure may include transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a light-emitting diode LD.

[0074] The first electrode of transistor T1 can be connected to the first electrode of transistor T2, the second electrode of transistor T1 can be connected to the first electrode of transistor T3, and the gate electrode of transistor T1 can be connected to the second electrode of transistor T3. Transistor T1 can be referred to as the driving transistor.

[0075] The first electrode of transistor T2 can be connected to the first electrode of transistor T1, the second electrode of transistor T2 can be connected to data line DLm, and the gate electrode of transistor T2 can be connected to scan line GWPLn. Transistor T2 can be referred to as the scanning transistor.

[0076] The first electrode of transistor T3 can be connected to the second electrode of transistor T1, the second electrode of transistor T3 can be connected to the gate electrode of transistor T1, and the gate electrode of transistor T3 can be connected to scan line GWNLn. Transistor T3 can be referred to as the diode-connected transistor.

[0077] The first electrode of transistor T4 can be connected to the second electrode of storage capacitor Cst, the second electrode of transistor T4 can be connected to initialization line VINTL, and the gate electrode of transistor T4 can be connected to scan line GILn. Transistor T4 can be referred to as the gate initialization transistor.

[0078] The first electrode of transistor T5 can be connected to power supply line ELVDDL, the second electrode of transistor T5 can be connected to the first electrode of transistor T1, and the gate electrode of transistor T5 can be connected to emission line ELn. Transistor T5 can be referred to as the first emission transistor.

[0079] The first electrode of transistor T6 can be connected to the second electrode of transistor T1, the second electrode of transistor T6 can be connected to the anode of light-emitting diode LD, and the gate electrode of transistor T6 can be connected to emission line ELn. Transistor T6 can be referred to as the second emission transistor.

[0080] The first electrode of transistor T7 can be connected to the anode of light-emitting diode LD, the second electrode of transistor T7 can be connected to initialization line VINTL, and the gate electrode of transistor T7 can be connected to scan line GBLn. Transistor T7 can be referred to as the anode initialization transistor.

[0081] The first electrode of storage capacitor Cst can be connected to power supply line ELVDDL, and the second electrode of storage capacitor Cst can be connected to the gate electrode of transistor T1.

[0082] The anode of the light-emitting diode LD can be connected to the second electrode of the transistor T6, and the cathode of the light-emitting diode LD can be connected to the power supply line ELVSSL. The voltage applied to the power supply line ELVSSL can be set to be lower than the voltage applied to the power supply line ELVDDL. The light-emitting diode LD can be an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot light-emitting diode, or the like.

[0083] The transistors T1, T2, T5, T6, and T7 can be implemented with P-type (e.g., P-class) transistors (e.g., can be P-type (e.g., P-class) transistors). The channels of the transistors T1, T2, T5, T6, and T7 can be configured with polysilicon (e.g., can include or can be polysilicon). The polysilicon transistors can be low-temperature polysilicon (LTPS) transistors. The polysilicon transistors have a high electron mobility and fast driving characteristics according to the high electron mobility.

[0084] The transistors T3 and T4 can be implemented with N-type (e.g., N-class) transistors (e.g., can be N-type (e.g., N-class) transistors). The channels of the transistors T3 and T4 can be configured with an oxide semiconductor (e.g., can include or can be an oxide semiconductor). The oxide semiconductor transistors can be formed by a low-temperature process and have a charge mobility lower than that of the polysilicon transistors. Thus, the oxide semiconductor transistors have a current leakage amount generated in the off state, which is smaller than the current leakage amount of the polysilicon transistors.

[0085] In some embodiments, the transistor T7 can be configured with an N-type (e.g., N-class) oxide semiconductor transistor instead of a polysilicon transistor. Instead of the scan line GBLn, one of the scan lines GWNLn and GILn can be connected to the gate electrode of the transistor T7.

[0086] Figure 3 It is a diagram showing a high-frequency driving method according to an embodiment of the present disclosure.

[0087] When the pixel unit 50 displays a frame at a first driving frequency, it can be said that the display device 9 is in the first display mode. In addition, when the pixel unit 50 displays a frame at a second driving frequency lower than the first driving frequency, it can be said that the display device 9 is in the second display mode.

[0088] In the first display mode, the display device 9 can display an image frame at a frequency of 20 Hz or higher (e.g., 60 Hz).

[0089] The second display mode may be a low - power display mode. In the second display mode, the display device 9 may display image frames at a frequency less than 20 Hz (e.g., 1 Hz). For example, during normal use, the case of only displaying time and date in the "always - on mode" may correspond to the second display mode.

[0090] The time period 1TP may include a plurality of frame periods 1FP. The time period 1TP is an arbitrarily defined time period for comparing the first display mode and the second display mode. The time period 1TP may represent the same time interval in the first display mode and the second display mode. For ease of description, it is assumed that the frame period 1FP has the same time interval in the first display mode and the second display mode. Thus, the time period 1TP in the first display mode and the second display mode may include the same number of frame periods 1FP.

[0091] In the first display mode, each frame period 1FP may include a data - writing period WP and a transmission period EP. For ease of description, in Figure 3 it is shown, based on the first pixel row, that the data - writing period WP is at the initial stage of the frame period 1FP and the transmission period EP is after the data - writing period WP. However, in the case of pixel rows other than the first pixel row, the data - writing period WP may be in the middle or at the later stage of the frame period 1FP.

[0092] Thus, the pixel PXnm may display a plurality of image frames corresponding to the plurality of frame periods 1FP during the time period 1TP, based on the data voltage received during the data - writing period WP.

[0093] Figure 4 FIG. is a diagram showing a data - writing period according to an embodiment of the present disclosure. Figure 5 FIG. is a diagram showing a data - writing period according to another embodiment of the present disclosure.

[0094] First, a transmission signal En having a cut - off level (high level) may be supplied to the transmission line ELn during the data - writing period WP. Thus, during the data - writing period WP, the transistors T5 and T6 may be in a cut - off state.

[0095] Next, a first pulse of a conductive level (high level), e.g., the first pulse of the scan signal GIn, is supplied to the scan line GILn. In some embodiments, after the emission signal En starts to be supplied to the emission line ELn, the first pulse of the scan signal GIn may start to be supplied to the scan line GILn. Thus, the transistor T4 is turned on, and the gate electrode of the transistor T1 and the initialization line VINTL are connected to each other. Accordingly, the voltage of the gate electrode of the transistor T1 is initialized to the initialization voltage of the initialization line VINTL and is held by the storage capacitor Cst. For example, the initialization voltage of the initialization line VINTL may be a voltage sufficiently lower than the voltage of the power supply line ELVDDL. For example, the initialization voltage may be a voltage having a level equal to or similar to the level of the voltage of the power supply line ELVSSL. Thus, the transistor T1 may be turned on.

[0096] Next, a first pulse of a conductive level (e.g., the low level of the first pulse of the scan signal GWPn and the high level of the first pulse of the scan signal GWNn), e.g., the first pulse of each of the scan signals GWPn and GWNn, is supplied to the scan lines GWPLn and GWNLn, and the corresponding transistors T2 and T3 are turned on. Accordingly, the data voltage Dm applied to the data line DLm is written (e.g., applied to or stored in) the storage capacitor Cst through the transistors T2, T1, and T3. However, the data voltage Dm corresponds to the gray value G(n - 4) of the pixel four horizontal periods (e.g., the earlier four horizontal periods) before. The data voltage Dm is not used for the emission of the pixel PXnm but is used to apply a conduction bias voltage to the transistor T1. When the conduction bias voltage is applied before writing the set data voltage Dm to the transistor T1, hysteresis can be minimized or reduced.

[0097] Next, a first pulse of a conductive level (low level), e.g., the first pulse of the scan signal GBn, is supplied to the scan line GBLn, and the transistor T7 is turned on. Accordingly, the anode voltage of the light-emitting diode LD is initialized.

[0098] A second pulse of a conductive level (high level), e.g., the second pulse of the scan signal GIn, is supplied to the scan line GILn, and the above-described driving process is performed again. For example, the conduction bias voltage is applied to the transistor T1 again, and the anode voltage of the light-emitting diode LD is initialized.

[0099] By repeating the above process, when a third pulse of a conductive level is supplied to the scan lines GWPLn and GWNLn, the data voltage Dm corresponding to the gray value Gn of the pixel PXnm is written to the storage capacitor Cst. The data voltage Dm written to the storage capacitor Cst is a voltage obtained by reflecting a decrease (e.g., reduction) in the threshold voltage of the transistor T1.

[0100] Finally, when the emission signal En becomes the conductive level (low level), transistors T5 and T6 are in (e.g., return to) the conductive state. Accordingly, a drive current path connecting the power supply line ELVDDL, transistors T5, T1, and T6, the light-emitting diode LD, and the power supply line ELVSSL is formed, and a drive current flows through the drive current path. The amount of the drive current corresponds to the data voltage Dm stored in the storage capacitor Cst. Since the drive current flows through transistor T1, a decrease in the threshold voltage of transistor T1 is reflected. Accordingly, the reflection of the threshold voltage to the decrease in the data voltage Dm stored in the storage capacitor Cst and the reflection of the threshold voltage to the decrease in the drive current cancel each other out, and thus, a drive current corresponding to the data voltage Dm can flow regardless of the threshold voltage of transistor T1.

[0101] The light-emitting diode LD emits light having a set luminance according to the amount of the drive current.

[0102] In the present embodiment, the case where each scan signal (e.g., GIn, GWPn, GWNn, and GBn) includes three pulses has been described. However, in another embodiment, each scan signal may include two or more than four pulses. In still another embodiment, each scan signal may include one pulse, and thus, the process of applying the conduction bias voltage to transistor T1 is omitted (see Figure 5 ). Hereinafter, for ease of description, the data writing period WP will be described based on Figure 5 .

[0103] In addition, the interval between adjacent pulses of the horizontal synchronization signal Hsync may correspond to one horizontal period. For example, one horizontal period may correspond to the time difference between the start of one pulse of the horizontal synchronization signal Hsync and the start of an adjacent pulse of the horizontal synchronization signal Hsync. Although the case where the pulse of the horizontal synchronization signal Hsync has a low level is shown in Figure 4 , in another embodiment, the pulse of the horizontal synchronization signal Hsync may have a high level.

[0104] Figure 6 is a diagram illustrating a low-frequency driving method according to an embodiment of the present disclosure.

[0105] In the second display mode, the first frame period 1FP during the period 1TP may include a data writing period WP and an emission period EP, and each of the other frame periods 1FP during the period 1TP may include a bias refresh period BP and an emission period EP.

[0106] The transistors T3 and T4 of the pixel PXnm remain in the off state during other frame periods 1FP in the period 1TP (e.g., the frame period 1FP after the first frame period 1FP during the period 1TP), and thus, the storage capacitor Cst maintains the same data voltage during a plurality of image frames. For example, the transistors T3 and T4 are configured as oxide semiconductor transistors, and thus, current leakage can be minimized or reduced.

[0107] Thus, the pixel PXnm can display the same single image frame during the period 1TP based on the data voltage supplied during the data writing period WP.

[0108] Figure 7 FIG. is a diagram showing a bias refresh period according to an embodiment of the present disclosure. Figure 8 FIG. is a diagram showing a bias refresh period according to another embodiment of the present disclosure.

[0109] Reference Figure 7 , in the bias refresh period BP, a scan signal GIn and GWNn having a cut-off level (low level) are supplied. Thus, as described above, the data voltage written into the storage capacitor Cst remains unchanged during the bias refresh period BP. A reference data voltage Vref can be applied to the data line DLm.

[0110] However, in the bias refresh period BP, an emission signal En and scan signals GWPn and GBn having the same waveform as the waveform in the data writing period WP can be supplied. Thus, in a plurality of frame periods 1FP of the period 1TP, the light emitted from the light emitting diode LD has a similar waveform, so that under low-frequency driving, the user sees little or no flicker.

[0111] Reference Figures 1 to 7 The pixel PXnm described with reference to is an embodiment suitable for high-frequency driving and low-frequency driving. The embodiments described later can also be applied to pixels having another circuit that can be driven at high frequency and low frequency. For example, all of the transistors T1 to T7 of the pixel PXnm can be configured as only P-type (e.g., P-class) transistors. Thus, the scan driver 30 only includes a sub-scan driver of P-type transistors, and thus, the configuration of the scan driver 30 can be simplified. For example, the pixel PXnm may not include the emission transistors T5 and T6. Thus, the emission driver 40 may be unnecessary.

[0112] In this embodiment, a case where each of the scan signals GWPn and GBn includes three pulses is described. However, in another embodiment, each of the scan signals GWPn and GBn may include two or more than four pulses. In still another embodiment, each of the scan signals GWPn and GBn may include one pulse. Thus, the process of applying the conduction bias voltage to the transistor T1 is omitted (see Figure 8 ). Hereinafter, for convenience of description, the bias refresh period BP will be described based on Figure 8 .

[0113] Figure 9 FIG. is a diagram showing a scan driver according to an embodiment of the present disclosure.

[0114] Referring to Figure 9 , the scan driver 30 according to an embodiment of the present disclosure may include a first scan driver 30P1, a second scan driver 30P2, and a third scan driver 30N.

[0115] As described with reference to Figure 1 , in some embodiments, the scan signals of the scan lines GIL1 to GILn may be provided by the third scan driver 30N. In another embodiment, the scan signals of the scan lines GIL1 to GILn may be provided from a separate scan driver. Additionally, in some embodiments, the scan signals of the scan lines GBL1 to GBLn may be provided by the first scan driver 30P1 and the second scan driver 30P2. In another embodiment, the scan signals of the scan lines GBL1 to GBLn may be provided from a separate scan driver.

[0116] The first scan driver 30P1 may be connected to a first scan start line FLML1, a scan clock line PCKLS, and scan lines GWPL1, GWPL2, GWPL3, ……, and GWPLp. Here, p may be an integer greater than 0. At least one of the scan clock signals supplied to the first scan driver 30P1 through the scan clock line PCKLS may be defined as a first scan clock signal.

[0117] The second scan driver 30P2 may be connected to a second scan start line FLML2, a scan clock line PCKLS, and scan lines GWPL(p + 1), GWPL(p + 2), …, and GWPLq. Here, q may be an integer greater than p. At least one of the scan clock signals supplied to the second scan driver 30P2 through the scan clock line PCKLS may be defined as a second scan clock signal. The second scan driver 30P2 may be connected to the same scan clock line PCKLS as the first scan driver 30P1. For example, the first scan clock signal and the second scan clock signal may be the same. However, the embodiments are not limited thereto, and for example, the second scan driver 30P2 may be connected to a different scan clock line from the first scan driver 30P1, and the first scan clock signal and the second scan clock signal may be different. In some embodiments, the second scan driver 30P2 may be connected to a second scan start line FLML2 that is independent of the first scan start line FLML1 of the first scan driver 30P1. The first scan line GWPL(p + 1) of the second scan driver 30P2 may correspond to the next scan line of the last scan line GWPLp of the first scan driver 30P1.

[0118] The third scan driver 30N may be connected to a third scan start line FLML3, a scan clock line NCKLS, and scan lines GWNL1, GWNL2, GWNL3, ..., GWNLp, GWNL(p + 1), GWNL(p + 2), ..., and GWNLq.

[0119] Figure 10 FIG. is a diagram illustrating a third scan driver according to an embodiment of the present disclosure.

[0120] Figure 10 The third scan driver 30N shown in FIG. may correspond to the first sub-scan driver described with reference to Figure 1 Those skilled in the art may implement the first sub-scan driver described with reference to Figure 10 by replacing the scan lines GWNL1, GWNL2, GWNL3, GWNL4, …, and GWNLn shown in FIG. with scan lines GIL1 to GILn. For example, in some embodiments, in addition to replacing the scan lines GWNL1 to GWNLn with the scan lines GIL1 to GILn, the first sub-scan driver described with reference to Figure 1 may have the same structure or configuration as the third scan driver 30N described with reference to Figure 1 FIG. Figure 10 FIG.

[0121] Reference Figure 10, the third scan driver 30N may include scan stages NST1, NST2, NST3, NST4, ……, NSTn. Each of the scan stages NST1 to NSTn may be connected to a previous scan line (or carry line) through the first input terminal 201. However, since the first scan stage NST1 does not have a previous scan line connected to the first scan stage NST1, the first scan stage NST1 may be connected to the third scan start line FLML3 through the first input terminal 201.

[0122] Each of the odd scan stages NST1, NST3, …… may include a second input terminal 202 connected to the clock line NCKL1 and a third input terminal 203 connected to the clock line NCKL2. Each of the even scan stages NST2, NST4, ……, NSTn may include a second input terminal 202 connected to the clock line NCKL2 and a third input terminal 203 that may be connected to the clock line NCKL1.

[0123] In some embodiments, each of the odd scan stages NST1, NST3, …… may include a second input terminal 202 connected to the clock line NCKL2 and a third input terminal 203 connected to the clock line NCKL1. Each of the even scan stages NST2, NST4, ……, NSTn may include a second input terminal 202 connected to the clock line NCKL1 and a third input terminal 203 connected to the clock line NCLK2.

[0124] The scan stages NST1 to NSTn may be respectively connected to the corresponding scan lines GWNL1 to GWNLn through the output terminals 204.

[0125] The scan stages NST1 to NSTn may be connected to each other in the form of a shift register. For example, each of the scan stages NST1 to NSTn may generate a scan signal in such a way that a third scan start signal having a conductive level, which will be supplied to the third scan start line FLML3, is sequentially transmitted to the next scan stage.

[0126] Figure 11 is a diagram showing Figure 10 the scan stages of the third scan driver shown in

[0127] Referring to Figure 11 , the Figure 10 first scan stage NST1 of the scan driver N30 shown in Figure 10 is shown as an exemplary embodiment. The other scan stages NST2, NST3, NST4, …… and NSTn shown in

[0128] The scan-level NST1 may include transistors P1 to P12 and capacitors CN1 to CN3. The transistors P1 to P12 may be P-type (e.g., P-class) transistors.

[0129] The first electrode of transistor P2 may be connected to the second electrode of transistor P1, the second electrode of transistor P2 may be connected to the third scan start line FLML3, and the gate electrode of transistor P2 may be connected to the clock line NCKL1.

[0130] The first electrode of transistor P3 may be connected to node NN3, the second electrode of transistor P3 may be connected to the clock line NCKL1, and the gate electrode of transistor P3 may be connected to the first electrode of transistor P2.

[0131] In some embodiments, transistor P3 may include a first sub-transistor and a second sub-transistor connected in series. The first electrode of the first sub-transistor may be connected to node NN3, the second electrode of the first sub-transistor may be connected to the first electrode of the second sub-transistor, and the gate electrode of the first sub-transistor may be connected to the first electrode of transistor P2. The first electrode of the second sub-transistor may be connected to the second electrode of the first sub-transistor, the second electrode of the second sub-transistor may be connected to the clock line NCKL1, and the gate electrode of the second sub-transistor may be connected to the first electrode of transistor P2. According to this embodiment, current leakage can be reduced, and an excessive source-drain voltage can be divided. Therefore, the stress applied to transistor P3 can be reduced.

[0132] The first electrode of transistor P4 may be connected to node NN3, the second electrode of transistor P4 may be connected to the power supply line VLNL, and the gate electrode of transistor P4 may be connected to the clock line NCKL1.

[0133] The first electrode of transistor P5 may be connected to node NN4, the second electrode of transistor P5 may be connected to the clock line NCKL2, and the gate electrode of transistor P5 may be connected to node NN2.

[0134] The first electrode of transistor P6 may be connected to the power supply line VHNL, the second electrode of transistor P6 may be connected to node NN4, and the gate electrode of transistor P6 may be connected to node NN3.

[0135] The first electrode of transistor P7 may be connected to the first electrode of capacitor CN3, the second electrode of transistor P7 may be connected to the clock line NCKL2, and the gate electrode of transistor P7 may be connected to the second electrode of capacitor CN3.

[0136] The first electrode of transistor P8 can be connected to node NN1, the second electrode of transistor P8 can be connected to the first electrode of capacitor CN3, and the gate electrode of transistor P8 can be connected to clock line NCKL2.

[0137] The first electrode of transistor P9 can be connected to power supply line VHNL, the second electrode of transistor P9 can be connected to node NN1, and the gate electrode of transistor P9 can be connected (e.g., through transistor P1) to node NN2.

[0138] The first electrode of transistor P10 can be connected to power supply line VHNL, the second electrode of transistor P10 can be connected to scan line GWNL1, and the gate electrode of transistor P10 can be connected to node NN1.

[0139] The first electrode of transistor P11 can be connected to scan line GWNL1, the second electrode of transistor P11 can be connected to power supply line VLNL, and the gate electrode of transistor P11 can be connected to node NN2.

[0140] The first electrode of transistor P12 can be connected to the second electrode of capacitor CN3, the second electrode of transistor P12 can be connected to node NN3, and the gate electrode of transistor P12 can be connected to power supply line VLNL.

[0141] The first electrode of transistor P1 can be connected to node NN2, the second electrode of transistor P1 can be connected to the first electrode of transistor P2, and the gate electrode of transistor P1 can be connected to power supply line VLNL.

[0142] The first electrode of capacitor CN1 can be connected to power supply line VHNL, and the second electrode of capacitor CN1 can be connected to node NN1.

[0143] The first electrode of capacitor CN2 can be connected to node NN4, and the second electrode of capacitor CN2 can be connected to node NN2.

[0144] The first electrode of capacitor CN3 can be connected to the first electrode of transistor P7, and the second electrode of capacitor CN3 can be connected to the gate electrode of transistor P7.

[0145] Figure 12 is a diagram showing Figure 11 the driving method of the scan stage shown in.

[0146] Reference Figure 12, which shows the timing diagram of the third scan start signal FLM3 applied to the third scan start line FLML3, the clock signal NCK2 applied to the clock line NCKL2, the clock signal NCK1 applied to the clock line NCKL1, the node voltage VNN2 of the node NN2, the node voltage VNN3 of the node NN3, the node voltage VNN1 of the node NN1, and the scan signal GWN1 applied to the scan line GWNL1. The horizontal sync signal Hsync is shown as a reference signal for the timing. The interval between the pulses of the horizontal sync signal Hsync can be referred to as one horizontal period.

[0147] A voltage with a high level can be applied to the power supply line VHNL, and a voltage with a low level can be applied to the power supply line VLNL. For example, the voltage applied to the power supply line VHNL can be higher than the voltage applied to the power supply line VLNL. In the description of the driving method, both the transistors P12 and P1 have gate electrodes connected to the power supply line VLNL and are in an on state during most periods (e.g., during most of the time), and thus, the description of the transistors P12 and P1 can be omitted.

[0148] First, at time t1a, the third scan start signal FLM3 with a cut-off level (high level) is supplied, and the clock signal NCK1 with a low level is supplied. Therefore, the transistors P2 and P4 are turned on.

[0149] When the transistor P2 is turned on, the third scan start signal FLM3 with a high level is transmitted to the node NN2, and the node voltage VNN2 has a high level. The transistors P3, P5, P9, and P11 are turned off by the node voltage VNN2 with a high level.

[0150] When the transistor P4 is turned on, the node NN3 and the power supply line VLNL are connected to each other, and thus, the node voltage VNN3 has a low level. The transistors P6 and P7 are turned on by the node voltage VNN3 with a low level.

[0151] When the transistor P6 is turned on, the node NN4 and the power supply line VHNL are connected to each other. Therefore, the power supply line VHNL supports one end (e.g., the first electrode of the capacitor CN2) of the capacitor CN2, and thus, the node voltage VNN2 of the node NN2 can be stably maintained.

[0152] When the transistor P7 is turned on, the first electrode of the capacitor CN3 and the clock line NCKL2 are connected to each other. Since the clock signal NCK2 with a high level is applied to the gate electrode of the transistor P8, the transistor P8 is in an off state, and thus, the node voltage VNN1 remains unchanged (e.g., the node voltage VNN1 has a high level).

[0153] At time t2a, a clock signal NCK2 having a low level is supplied.

[0154] The clock signal NCK2 having a low level is supplied to the first electrode of a capacitor CN3 through a transistor P7. Due to the coupling of the capacitor CN3, a voltage having a level lower than the low level is applied to the gate electrode of the transistor P7. Thus, the transistor P7 can stably maintain an on state and has improved driving characteristics.

[0155] According to this embodiment, due to the transistor P12, the node voltage VNN3 is not affected by the coupling of the capacitor CN3. When a voltage having a level lower than the low level is applied to the first electrode of the transistor P12 due to the coupling of the capacitor CN3, the first electrode of the transistor P12 serves as a drain electrode. Therefore, the node NN3 corresponding to the second electrode of the transistor P12 serves as a source electrode (e.g., the source electrode of the transistor P12). Additionally, since a voltage having a low level is applied to the gate electrode of the transistor P12 through a power supply line VLNL, a voltage having a level higher than the low level is applied to the source electrode of the transistor P12, rendering the transistor P12 conductive. At the current time, the node voltage VNN3 of the node NN3 has a low level, and thus, the transistor P12 is in an off state.

[0156] Thus, according to this embodiment, the node voltage VNN3 is held by the transistor P12, and thus, an excessive bias voltage is prevented or blocked from being applied to the transistors P3 and P4, enabling the lifespan of the transistors P3 and P4 to be extended.

[0157] Additionally, the transistor P8 is turned on by the clock signal NCK2 having a low level. Thus, the nodes NN1 and the clock line NCKL2 are connected to each other through the transistors P7 and P8. Therefore, the transistor P10 is turned on by the node voltage VNN1 having a low level. The transistor P9 remains in an off state due to the node voltage VNN2 having a high level.

[0158] The power supply line VHNL and the scan line GWNL1 are connected to each other through the transistor P10 in an on state. Thus, a voltage having a high level is supplied as a scan signal GWN1 having a high level to the scan line GWNL1.

[0159] At time t3a, a clock signal NCK1 having a low level is supplied. Accordingly, the transistor P4 is turned on, and the node NN3 is connected to the power supply line VLNL. Thus, the node voltage VNN3 is maintained at a low level. In addition, the transistor P2 is turned on, and a third scan start signal FLM3 having a low level is supplied to the node NN2. Accordingly, the transistors P3, P5, P9, and P11 are turned on. Accordingly, the transistor P10 is diode-connected, and thus, a voltage having a high level applied to the power supply line VHNL is not transmitted to the scan line GWNL1. The voltage having a low level applied to the power supply line VLNL is transmitted to the scan line GWNL1 through the transistor P11 in the on state.

[0160] At time t4a, a clock signal NCK1 having a high level is supplied. Since the transistor P3 is in the on state, the node voltage VNN3 increases. Accordingly, the transistors P6 and P7 are turned off.

[0161] At time t5a, a clock signal NCK2 having a low level is provided. Since the transistor P5 is in the on state, due to the coupling of the capacitor CN2, the node voltage VNN2 decreases to a level lower than the low level. Thus, the transistor P11 can stably maintain the on state and has improved driving characteristics.

[0162] According to the present embodiment, due to the transistor P1, the node corresponding to the second electrode of the transistor P1 is not affected by the coupling of the capacitor CN2. When a voltage having a level lower than the low level is applied to the node NN2, which is the first electrode of the transistor P1, due to the coupling of the capacitor CN2, the first electrode of the transistor P1 serves as a drain electrode. Accordingly, the node corresponding to the second electrode of the transistor P1 serves as a source electrode. In addition, since a voltage having a low level is applied to the gate electrode of the transistor P1 through the power supply line VLNL, a voltage having a level higher than the low level is applied to the source electrode of the transistor P1, so that the transistor P1 is turned on. At the current time, a voltage having a low level is applied to the source electrode of the transistor P1, and thus, the transistor P1 is in the off state.

[0163] Accordingly, according to the present embodiment, the transistor P1 maintains the voltage of the node corresponding to the second electrode of the transistor P1, so that an excessive bias voltage is prevented or blocked from being applied to the transistors P2 and P3. Thus, the lifetimes of the transistors P2 and P3 can be extended.

[0164] Figure 13 FIG. is a diagram showing a first scan driver according to an embodiment of the present disclosure.

[0165] Reference Figure 13, the first scan driver 30P1 may include scan stages PST11 to PST14. The scan stages PST11 to PST14 may be connected to corresponding scan lines GWPL1 to GWPL4 and a scan clock line PCKLS. The scan stages PST11 to PST14 may be implemented with the same circuit.

[0166] Each of the scan stages PST11 to PST14 may include a first input terminal 1001, a second input terminal 1002, a third input terminal 1003, and an output terminal 1004.

[0167] The first input terminal 1001 of the first scan stage PST11 may be connected to the first scan start line FLML1. The first input terminal 1001 of each of the other scan stages PST12 to PST14 may be connected to the scan line (or carry line) of the previous scan stage. In the example, a first scan start signal is supplied to the first input terminal 1001 of the first scan stage PST11, and an output signal (e.g., a scan signal or a carry signal) of the previous scan stage is supplied to the first input terminal 1001 of each of the other scan stages PST12 to PST14.

[0168] The second input terminal 1002 of the j-th (j is odd or even) scan stage may be connected to the clock line PCKL1, and the third input terminal 1003 of the j-th scan stage may be connected to the clock line PCKL2. The second input terminal 1002 of the (j + 1)-th scan stage may be connected to the clock line PCKL2, and the third input terminal 1003 of the (j + 1)-th scan stage may be connected to the clock line PCKL1.

[0169] The pulses of the clock signals PCK1 and PCK2 applied to the clock lines PCKL1 and PCKL2 have the same period (e.g., two horizontal periods), but have different phases. Therefore, the pulses of the clock signals PCK1 and PCK2 may not overlap with each other (see Figure 15 ).

[0170] Moreover, each of the scan stages PST11 to PST14 may be connected to a power supply line VHPL and a power supply line VLPL. The voltage of the power supply line VHPL may be set to a cut-off level (gate cut-off voltage or a voltage with a high level). Additionally, the voltage of the power supply line VLPL may be set to a conduction level (gate conduction voltage or a voltage with a low level).

[0171] Figure 14 is a diagram showing Figure 13 the scan stages of the first scan driver shown in

[0172] For ease of description, in Figure 14The first scan stage PST11 and the second scan stage PST12 are shown. Refer to Figure 14 , the first scan stage PST11 may include a first driver 1210, a second driver 1220, and an output unit (buffer) 1230.

[0173] The output unit 1230 corresponds to (e.g., according to) the voltages of the node NP1 and the second node NP2, and controls the voltage supplied to the output terminal 1004. To this end, the output unit 1230 includes a transistor M5 and a transistor M6.

[0174] The transistor M5 is located between the power supply line VHPL and the output terminal 1004, and the gate electrode of the transistor M5 is connected to the node NP1. The transistor M5 corresponds to (e.g., according to) the voltage applied to the node NP1, and controls the connection between the power supply line VHPL and the output terminal 1004.

[0175] The transistor M6 is located between the output terminal 1004 and the third input terminal 1003, and the gate electrode of the transistor M6 is connected to the node NP2. The transistor M6 corresponds to (e.g., according to) the voltage applied to the node NP2, and controls the connection between the output terminal 1004 and the third input terminal 1003. The output unit 1230 is driven as a buffer. Additionally, the output unit 1230 can be configured by connecting multiple transistors in parallel. For example, in some embodiments, each of the transistors M5 and M6 can be implemented as multiple transistors connected in parallel.

[0176] The first driver 1210 corresponds to (e.g., according to) the signals supplied to the first input terminal 1001 to the third input terminal 1003, and controls the voltage of the node NP3. To this end, the first driver 1210 includes transistors M2 to transistors M4 (e.g., transistors M2, M3, and M4).

[0177] The transistor M2 is located between the first input terminal 1001 and the node NP3, and the gate electrode of the transistor M2 is connected to the second input terminal 1002. The transistor M2 corresponds to (e.g., according to) the signal supplied to the second input terminal 1002, and controls the connection between the first input terminal 1001 and the node NP3.

[0178] The transistors M3 and M4 are connected in series between the node NP3 and the power supply line VHPL. The transistor M3 is located between the transistor M4 and the node NP3, and the gate electrode of the transistor M3 is connected to the third input terminal 1003. The transistor M3 corresponds to (e.g., according to) the signal supplied to the third input terminal 1003, and controls the connection between the transistor M4 and the node NP3.

[0179] The transistor M4 is located between the transistor M3 and the power supply line VHPL, and the gate electrode of the transistor M4 is connected to the node NP1. The transistor M4 corresponds to (e.g., according to) the voltage of the node NP1, and controls the connection between the transistor M3 and the power supply line VHPL.

[0180] The second driver 1220 corresponds to (e.g., according to) the voltages of the second input terminal 1002 and the node NP3, and controls the voltage of the node NP1. To this end, the second driver 1220 includes a transistor M1, a transistor M7, a transistor M8, a capacitor CP1, and a capacitor CP2.

[0181] The capacitor CP1 is connected between the node NP2 and the output terminal 1004. The capacitor CP1 is charged with a voltage corresponding to (e.g., according to) the on state (e.g., conducting state) and the off state (e.g., non-conducting state) of the transistor M6.

[0182] The second capacitor CP2 is connected between the node NP1 and the power supply line VHPL. The capacitor CP2 is charged with the voltage applied to the node NP1.

[0183] The transistor M7 is located between the node NP1 and the second input terminal 1002, and the gate electrode of the transistor M7 is connected to the node NP3. The transistor M7 corresponds to (e.g., according to) the voltage of the node NP3, and controls the connection between the node NP1 and the second input terminal 1002.

[0184] The transistor M8 is located between the node NP1 and the power supply line VLPL, and the gate electrode of the transistor M8 is connected to the second input terminal 1002. The transistor M8 corresponds to (e.g., according to) the voltage of the second input terminal 1002, and controls the connection between the node NP1 and the power supply line VLPL.

[0185] The transistor M1 is located between the node NP3 and the node NP2, and the gate electrode of the transistor M1 is connected to the power supply line VLPL. While maintaining (e.g., having) the on state of the transistor M1, the transistor M1 maintains (e.g., provides) the electrical connection between the node NP3 and the node NP2. Additionally, the transistor M1 limits the voltage drop width of the node NP3 corresponding to the voltage of the node NP2. For example, although the voltage of the node NP2 drops to a voltage lower than the voltage of the power supply line VLPL, the voltage of the node NP3 is not lower than the voltage obtained by subtracting the threshold voltage of the transistor M1 from the voltage of the power supply line VLPL.

[0186] Meanwhile, in addition to the signals supplied to the first input terminal 101, the second input terminal 102, and the third input terminal 103, the configuration of the second scan stage PST12 can have substantially the same configuration as that of the first scan stage PST11. Therefore, the overlapping description of the second scan stage PST12 can be omitted.

[0187] Figure 15 is a diagram showing Figure 14 the driving method of the scan stage shown in

[0188] For ease of description, the operation process using the first scan stage PST11 will be described in Figure 15 what follows.

[0189] Referring to Figure 15 , the clock signal PCK1 and the clock signal PCK2 have a period of two horizontal periods 2H and are supplied in different horizontal periods. For example, the clock signal PCK2 is set to a signal shifted by half a period (i.e., one horizontal period 1H) relative to the clock signal PCK1. In addition, the first scan start signal FLM1 supplied to the first input terminal 1001 can be synchronized with the clock signal PCK1 supplied to the second input terminal 1002.

[0190] The supply of a signal can mean that the signal has a conductive level (here, a low level). The suspension of the signal supply can mean that the signal has a cutoff level (here, a high level).

[0191] In addition, when the first scan start signal FLM1 is supplied, the first input terminal 1001 can be set to a voltage with a low level, and when the first scan start signal FLM1 is not supplied, the first input terminal 1001 can be set to a voltage with a high level. In addition, when the clock signal is supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 can be set to a voltage with a low level, and when the clock signal is not supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 can be set to a voltage with a high level.

[0192] The operation process will be described in more detail. First, the first scan start signal FLM1 is supplied in synchronization with the clock signal PCK1.

[0193] When the clock signal PCK1 is supplied, the transistors M2 and M8 are turned on. When the transistor M2 is turned on, the first input terminal 1001 and the node NP3 are electrically connected to each other. Since the transistor M1 is set to the on state for most of the period (e.g., during most of the time), the node NP2 remains electrically connected to the node NP3.

[0194] When the first input terminal 1001 and the node NP3 are electrically connected to each other, the voltage VNP2 of the node NP2 and the voltage VNP3 of the node NP3 are set to a low level by the first scan start signal FLM1 supplied to the first input terminal 1001. When the voltage VNP2 of the node NP2 and the voltage VNP3 of the node NP3 are set to a low level, the transistors M6 and M7 are turned on.

[0195] When the transistor M6 is turned on, the third input terminal 1003 and the output terminal 1004 are electrically connected to each other. The third input terminal 1003 is set to have a high-level voltage (for example, the clock signal PCK2 is not supplied), and thus, a high-level voltage is also output to the output terminal 1004. When the transistor M7 is turned on, the second input terminal 1002 and the node NP1 are electrically connected to each other. According to the clock signal PCK1 supplied to the second input terminal 1002, the voltage VNP1 of the node NP1 is set to a low level.

[0196] In addition, when the clock signal PCK1 is supplied, the transistor M8 is turned on. When the transistor M8 is turned on, the voltage of the power supply line VLPL is supplied to the node NP1. The voltage of the power supply line VLPL is set to be equal to (or approximately equal to) the voltage of the low level of the clock signal PCK1, and thus, the node NP1 stably holds a voltage with a low level.

[0197] When the node NP1 is set to have a low-level voltage, the transistors M4 and M5 are turned on. When the transistor M4 is turned on, the power supply line VHPL and the transistor M3 are electrically connected to each other. Since the transistor M3 is set to an off state, even when the transistor M4 is turned on, the node NP3 stably holds a voltage with a low level. When the transistor M5 is turned on, the voltage of the power supply line VHPL is supplied to the output terminal 1004. The voltage of the power supply line VHPL is set to be equal to (or approximately equal to) the voltage of the high level supplied to the third input terminal 1003, and thus, the output terminal 1004 stably holds a voltage with a high level.

[0198] Subsequently, the supply of the first scan start signal FLM1 and the clock signal PCK1 is aborted. When the supply of the clock signal PCK1 is aborted, the transistors M2 and M8 are turned off. The transistors M6 and M7 corresponding to the voltage stored in the capacitor CP1 remain in an on state. For example, the voltage stored in the capacitor CP1 is applied to the gate electrodes of the transistor M6 and the transistor M7. For example, due to the voltage stored in the capacitor CP1, the nodes NP2 and NP3 remain at a low level voltage.

[0199] When the transistor M6 remains in the on state, the electrical connection between the output terminal 1004 and the third input terminal 1003 is maintained. When the transistor M7 remains in the on state, the node NP1 remains electrically connected to the second input terminal 1002. Corresponding to the time when the supply of the clock signal PCK1 is suspended, the voltage of the second input terminal 1002 is set to a voltage having a high level, and thus, the node NP1 is also set to a voltage having a high level. When a voltage having a high level is supplied to the node NP1, the transistors M4 and M5 are turned off.

[0200] Subsequently, the clock signal PCK2 is supplied to the third input terminal 1003. Since the transistor M6 is set to the on state, the clock signal PCK2 supplied to the third input terminal 1003 is supplied to the output terminal 1004. The output terminal 1004 outputs the clock signal PCK2 as a scan signal GWP1 having a conductive level to the first scan line GWPL1.

[0201] At the same time, when the clock signal PCK2 is supplied to the output terminal 1004, due to the coupling of the capacitor CP1, the voltage VNP2 of the node NP2 drops to a voltage lower than the voltage of the power supply line VLPL, and thus, the transistor M6 stably remains in the on state.

[0202] At the same time, although the voltage VNP2 of the node NP2 drops, the node NP3 can approximately maintain the voltage of the power supply line VLPL (for example, the voltage obtained by subtracting the threshold voltage of the transistor M1 from the voltage of the power supply line VLPL).

[0203] After the scan signal GWP1 having a conductive level is output to the first scan line GWPL1, the supply of the clock signal PCK2 is suspended. When the supply of the clock signal PCK2 is suspended, the output terminal 1004 outputs a voltage having a high level. In addition, corresponding to the voltage having a high level, the voltage VNP2 of the node NP2 increases to approximately the voltage of the power supply line VLPL.

[0204] Subsequently, the clock signal PCK1 is supplied. When the clock signal PCK1 is supplied, the transistors M2 and M8 are turned on. When the transistor M2 is turned on, the first input terminal 1001 and the node NP3 are electrically connected to each other. The first scan start signal FLM1 is not supplied to the first input terminal 1001, and thus, is set to a voltage having a high level. Thus, when the transistor M1 is turned on, a voltage having a high level is supplied to the node NP3 and the node NP2, and thus, the transistors M6 and M7 are turned off.

[0205] When the transistor M8 is turned on, the voltage of the power supply line VLPL is supplied to the node NP1, and thus, the transistors M4 and M5 are turned on. When the transistor M5 is turned on, the voltage of the power supply line VHPL is supplied to the output terminal 1004. Subsequently, corresponding to the voltage charged in the capacitor CP2, the transistors M4 and M5 remain in the on state, and thus, the voltage of the power supply line VHPL is stably supplied to the output terminal 1004.

[0206] In addition, when the clock signal PCK2 is supplied, the transistor M3 is turned on. Since the transistor M4 is set in the on state, the voltage of the power supply line VHPL is supplied to the nodes NP3 and NP2. The transistors M6 and M7 are stably kept in the off state.

[0207] The output signal (e.g., scan signal) of the first scan stage PST11 is supplied to the second scan stage PST12 in synchronization with the clock signal PCK2. The second scan stage PST12 outputs a scan signal GWP2 having a conductive level to the second scan line GWPL2 in synchronization with the clock signal PCK1. By repeating the above process, the scan stages PST11 to PST14 sequentially output scan signals having a conductive level to the scan lines GWPL1 to GWPL4.

[0208] Figure 16 is a diagram showing a second scan driver according to an embodiment of the present disclosure.

[0209] Reference Figure 16 , the second scan driver 30P2 may include scan stages PST21 to PST24. The scan stages PST21 to PST24 may be connected to the corresponding scan lines GWPL(p + 1) to GWPL(p + 4) and the scan clock line PCKLS. The scan stages PST21 to PST24 may be implemented with the same circuit.

[0210] Each of the scan stages PST21 to PST24 may include a first input terminal 1001, a second input terminal 1002, a third input terminal 1003, and an output terminal 1004.

[0211] The first input terminal 1001 of the first scan stage PST21 may be connected to the second scan start line FLML2. The first input terminal 1001 of each of the other scan stages PST22 to PST24 may be connected to the scan line (or carry line) of the previous scan stage. In the example, a first scan start signal is supplied to the first input terminal 1001 of the first scan stage PST21, and the output signal (e.g., scan signal or carry signal) of the previous scan stage is supplied to the first input terminal 1001 of each of the other scan stages PST22 to PST24.

[0212] The second input terminal 1002 of the k-th (where k is odd or even) scan stage can be connected to the clock line PCKL1, and the third input terminal 1003 of the k-th scan stage can be connected to the clock line PCKL2. For example, as Figure 16 shown, the digital k is odd. The second input terminal 1002 of the (k + 1)-th scan stage can be connected to the clock line PCKL2, and the third input terminal 1003 of the (k + 1)-th scan stage can be connected to the clock line PCKL1.

[0213] The pulses of the clock signals PCK1 and PCK2 applied to the clock lines PCKL1 and PCKL2 have the same period (e.g., two horizontal periods 2H), but have different phases. Therefore, the pulses of the clock signals PCK1 and PCK2 may not overlap with each other.

[0214] Moreover, each of the scan stages PST21 to PST24 can be connected to the power supply lines VHPL and VLPL. The voltage of the power supply line VHPL can be set to the cut-off level. Additionally, the voltage of the power supply line VLPL can be set to the conduction level.

[0215] The circuit configurations of the scan stages PST21 to PST24 can be the same as those of the scan stages PST11 to PST14 described above, and thus, the description of overlapping can be omitted.

[0216] Figure 17 is a diagram showing a transmission driver according to an embodiment of the present disclosure.

[0217] Refer to Figure 17 , the transmission driver 40 according to an embodiment of the present disclosure can include a first transmission driver 41 and a second transmission driver 42.

[0218] The first transmission driver 41 can be connected to the first emission stop line ELML1, the emission clock line ECKLS, and the emission lines EL1, EL2, EL3, …… and ELp. At least one of the emission clock signals supplied to the first transmission driver 41 through the emission clock line ECLKS can be referred to as the first emission clock signal.

[0219] The second transmission driver 42 may be connected to a second transmission stop line ELML2, a transmission clock line ECKLS, and transmission lines EL(p + 1), EL(p + 2), ……, ELq. At least one of the transmission clock signals supplied to the second transmission driver 42 through the transmission clock line ECKLS may be referred to as a second transmission clock signal. The second transmission driver 42 may be connected to the same transmission clock line ECKLS as the first transmission driver 41. In some embodiments, the second transmission driver 42 may be connected to a second transmission stop line ELML2 independent of the first transmission stop line ELML1 of the first transmission driver 41. For example, the second transmission driver 42 may be connected to a different transmission stop line from the first transmission driver 41, and the first transmission stop signal and the second transmission stop signal may be different. The first transmission line EL(p + 1) of the second transmission driver 42 may correspond to the next transmission line of the last transmission line ELp of the first transmission driver 41.

[0220] Figure 18 FIG. is a diagram illustrating a first transmission driver according to an embodiment of the present disclosure.

[0221] Reference Figure 18 , the first transmission driver 41 may include a plurality of transmission stages EST11 to EST14. For ease of description, four transmission stages EST11 to EST14 are shown in Figure 18 . The transmission stages EST11 to EST14 may be respectively connected to corresponding transmission lines EL1 to EL4, and may be commonly connected to the transmission clock line ECKLS. The transmission stages EST11 to EST14 may have substantially the same circuit structure.

[0222] Each of the transmission stages EST11 to EST14 may include a first input terminal 101, a second input terminal 102, a third input terminal 103, and an output terminal 104.

[0223] The first input terminal 101 may receive an output signal (e.g., a transmission signal or a carry signal) of a previous transmission stage or a first transmission stop signal. In an example, the first input terminal 101 of the first transmission stage EST11 may be connected to the first transmission stop line ELML1, and the first input terminal 101 of each of the other transmission stages EST12 to EST14 may be connected to the transmission line of the previous transmission stage.

[0224] The second input terminal 102 of the l-th (l is odd or even) transmission stage may be connected to the clock line ECKL1, and the third input terminal 103 of the l-th transmission stage may be connected to the clock line ECKL2. For example, as Figure 18As shown, l can be an odd number. Additionally, the second input terminal 102 of the (l + 1)-th emission stage can be connected to the clock line ECKL2, and the third input terminal 103 of the (l + 1)-th emission stage can be connected to the clock line ECKL1. For example, the clock line ECKL1 and the clock line ECKL2 can be alternately connected to the second input terminal 102 and the third input terminal 103 of each emission stage.

[0225] The pulse of the clock signal ECK1 applied to the clock line ECKL1 and the pulse of the clock signal ECK2 applied to the clock line ECKL2 do not overlap with each other in time (see Figure 20 ). Each pulse can have a conductive level.

[0226] The emission stages EST11 to EST14 can be connected to the power supply line VDDL and the power supply line VSSL. The voltage of the power supply line VDDL can be set to a cut-off level, and the voltage of the power supply line VSSL can be set to a conductive level. The voltage level of the emission signal can be set based on the voltage of one of the power supply line VDDL and the power supply line VSSL.

[0227] Figure 19 is a diagram showing Figure 18 the emission stages of the first emission driver shown in

[0228] Refer to Figure 19 , the emission stage EST11 can include an input unit 210, an output unit 220, a first signal processor 230, a second signal processor 240, a third signal processor 250, and a first stabilizer 260.

[0229] The output unit 220 can supply the voltage of the power supply line VDDL or the power supply line VSSL to the output terminal 104 corresponding to (e.g., according to) the voltages of the node NE1 and the node NE2. To this end, the output unit 220 can include a transistor Q10 and a transistor Q11.

[0230] The transistor Q10 can be connected between the power supply line VDDL and the output terminal 104. Additionally, the gate electrode of the transistor Q10 can be connected to the node NE1. The transistor Q10 can be turned on or off corresponding to (e.g., according to) the voltage of the node NE1. The voltage of the power supply line VDDL supplied to the output terminal 104 when the transistor Q10 is turned on can be output as an emission signal having a cut-off level through the emission line EL1.

[0231] The transistor Q11 can be connected between the output terminal 104 and the power supply line VSSL. Additionally, the gate electrode of the transistor Q11 can be connected to the node NE2. The transistor Q11 can be turned on or off corresponding to the voltage of the node NE2. When the transistor Q11 is turned on, the voltage of the power supply line VSSL supplied to the output terminal 104 can be output as a transmission signal having a conductive level through the transmission line EL1.

[0232] The input unit 210 can control the voltages of the node NE3 and the node NE4 corresponding to (e.g., according to) the signals supplied to the first input terminal 101 and the second input terminal 102. For this purpose, the input unit 210 can include the transistor Q7, the transistor Q8, and the transistor Q9.

[0233] The transistor Q7 can be connected between the first input terminal 101 and the node NE4. Additionally, the gate electrode of the transistor Q7 can be connected to the second input terminal 102. When a clock signal having a conductive level is supplied to the second input terminal 102, the transistor Q7 can be turned on to electrically connect the first input terminal 101 and the node NE4.

[0234] The transistor Q8 can be connected between the node NE3 and the second input terminal 102. Additionally, the gate electrode of the transistor Q8 can be connected to the node NE4. The transistor Q8 can be turned on or off corresponding to (e.g., according to) the voltage of the node NE4.

[0235] The transistor Q9 can be connected between the node NE3 and the power supply line VSSL. Additionally, the gate electrode of the transistor Q9 can be connected to the second input terminal 102. When a clock signal having a conductive level is supplied to the second input terminal 102, the transistor Q9 can be turned on to supply the voltage of the power supply line VSSL to the node NE3.

[0236] The first signal processor 230 can control the voltage of the node NE1 corresponding to (e.g., according to) the voltage of the node NE2. For this purpose, the first signal processor 230 can include the transistor Q12 and the capacitor CE3.

[0237] The transistor Q12 can be connected between the power supply line VDDL and the node NE1. Additionally, the gate electrode of the transistor Q12 can be connected to the node NE2. The transistor Q12 can be turned on or off corresponding to (e.g., according to) the voltage of the node NE2.

[0238] The capacitor CE3 can be connected between the power supply line VDDL and the node NE1. The capacitor CE3 can hold the voltage applied to the node NE1.

[0239] The second signal processor 240 may be connected to node NE5 and may control the voltage of node NE1 corresponding to (e.g., according to) the signal supplied to the third input terminal 103. To this end, the second signal processor 240 may include transistor Q5, transistor Q6, capacitor CE1, and capacitor CE2.

[0240] Capacitor CE1 may be connected between node NE2 and the third input terminal 103. Capacitor CE1 may maintain the voltage difference between the third input terminal 103 and node NE2.

[0241] The first electrode of capacitor CE2 may be connected to node NE5, and the second electrode of capacitor CE2 may be connected to transistor Q5.

[0242] Transistor Q5 may be connected between the second electrode of capacitor CE2 and node NE1. Additionally, the gate electrode of transistor Q5 may be connected to the third input terminal 103. When a clock signal is supplied to the third input terminal 103, transistor Q5 may be turned on to electrically connect the second electrode of capacitor CE2 and node NE1.

[0243] Transistor Q6 may be connected between the second electrode of capacitor CE2 and the third input terminal 103. Additionally, the gate electrode of transistor Q6 may be connected to node NE5.

[0244] The third signal processor 250 may control the voltage of node NE4 corresponding to (e.g., according to) the voltage of node NE3 and the signal supplied to the third input terminal 103. To this end, the third signal processor 250 may include transistor Q3 and transistor Q4.

[0245] Transistor Q3 and transistor Q4 may be connected in series between the power supply line VDDL and node NE4. The gate electrode of transistor Q3 may be connected to node NE3. Additionally, the gate electrode of transistor Q4 may be connected to the third input terminal 103.

[0246] The first stabilizer 260 may be connected between the second signal processor 240 and the input unit 210. The first stabilizer 260 may limit the voltage drop width of node NE3 and node NE4. The first stabilizer 260 may include transistor Q1 and transistor Q2.

[0247] Transistor Q1 may be connected between node NE3 and node NE1. Additionally, the gate electrode of transistor Q1 may be connected to the power supply line VSSL. Transistor Q2 may be connected between node NE2 and node NE4. Additionally, the gate electrode of transistor Q2 may be connected to the power supply line VSSL.

[0248] Meanwhile, except for the signals supplied to the first input terminal 101, the second input terminal 102, and the third input terminal 103, the configuration of the second emitter EST12 can be substantially the same as that of the first emitter EST11. Therefore, the overlapping description of the second emitter EST12 can be omitted.

[0249] Figure 20 is a diagram showing Figure 19 the driving method of the emitter shown in.

[0250] In Figure 20 the operation process will be described based on the first emitter EST11.

[0251] Referring to Figure 20 , each of the pulses of the clock signal ECK1 and the pulses of the clock signal ECK2 has a period of two horizontal periods 2H, and the pulses of the clock signal ECK1 and the pulses of the clock signal ECK2 are generated in different horizontal periods. For example, the pulses of the clock signal ECK2 can be a signal shifted by half a period (e.g., one horizontal period 1H) relative to the pulses of the clock signal ECK1.

[0252] The first emission stop signal ELM1 having a cut-off level (high level) supplied to the first input terminal 101 is set to overlap at least once with the clock signal ECK1 of the pulse having a conduction level (low level) supplied to the second input terminal 102. To this end, the first emission stop signal ELM1 can be supplied during a width (e.g., longer time) wider than the width of the clock signal ECK1. For example, the first emission stop signal ELM1 can be supplied within four horizontal periods 4H. In addition, the first emission signal E1 of the pulse having a cut-off level (high level) supplied to the first input terminal 101 of the second emitter EST12 can overlap at least once with the clock signal ECK2 of the pulse having a conduction level (low level) supplied to the second input terminal 102 of the second emitter EST12.

[0253] First, at time t1b, the clock signal ECK1 having a low level is supplied to the second input terminal 102. For example, a pulse can be generated in the clock signal ECK1. Therefore, the transistor Q7 and the transistor Q9 can be turned on.

[0254] When the transistor Q7 is turned on, the first input terminal 101 and the node NE4 can be electrically connected to each other. Since the transistor Q2 remains turned on, the first input terminal 101 can be electrically connected to the node NE2 via the node NE4. At time t1b, the start pulse having a high level is not supplied to the first input terminal 101, and therefore, the voltage VNE4 of the node NE4 and the voltage VNE2 of the node NE2 can be set to a low level.

[0255] When a voltage with a low level is supplied to node NE2 and node NE4, transistors Q8, Q11, and Q12 can be turned on.

[0256] When transistor Q12 is turned on, the voltage of power supply line VDDL can be supplied, such that the voltage VNE1 of node NE1 is set to a high level. Therefore, transistor Q10 can be turned off.

[0257] When transistor Q11 is turned on, the voltage of power supply line VSSL can be supplied to output terminal 104. Therefore, at time t1b, a transmission signal E1 with a conductive level (low level) can be supplied to transmission line EL1.

[0258] When transistor Q8 is turned on, clock signal ECK1 is supplied to node NE3. Since transistor Q1 remains turned on, clock signal ECK1 can be supplied to node NE5 via node NE3.

[0259] Meanwhile, when transistor Q9 is turned on, the voltage of power supply line VSSL is supplied to node NE3 and node NE5. Clock signal ECK1 can have a low level, and thus, the voltage VNE3 of node NE3 and the voltage VNE5 of node NE5 can be set to a low level. Therefore, transistors Q3 and Q6 are turned on.

[0260] When transistor Q6 is turned on, a clock signal ECK2 with a high level is supplied from the third input terminal 103 to the second electrode of capacitor CE2. Since transistor Q5 is in the off state, node NE1 can maintain the voltage of power supply line VDDL regardless of the voltages of node NE5 and the second electrode of capacitor CE2.

[0261] When transistor Q3 is turned on, the voltage of power supply line VDDL can be supplied to transistor Q4. Transistor Q4 can be in the off state, and thus, node NE4 can maintain a low level.

[0262] At time t2b, a clock signal ECK1 with a high level is supplied to the second input terminal 102. For example, a pulse can disappear in clock signal ECK1. Therefore, transistors Q7 and Q9 can be turned off. The previous voltages of node NE2 and node NE1 can be maintained by capacitors CE1 and CE3, and transistors Q8, Q11, and Q12 can remain turned on.

[0263] When transistor Q8 is turned on, a clock signal ECK1 with a high level is supplied from the second input terminal 102 to node NE3 and node NE5. Therefore, transistors Q3 and Q6 are set to the off state.

[0264] At time t3b, a clock signal ECK2 having a low level is supplied to the third input terminal 103. For example, a pulse is generated in the clock signal ECK2. Accordingly, the transistors Q4 and Q5 are turned on.

[0265] When the transistor Q5 is turned on, the second electrode of the capacitor CE2 and the node NE1 are electrically connected to each other. Since the transistor Q12 is in the on state, the node NE1 holds the voltage of the power supply line VDDL.

[0266] When the transistor Q4 is turned on, the second electrode of the transistor Q3 and the node NE2 are electrically connected to each other. Since the transistor Q3 is in the off state, the voltage of the power supply line VDDL is not supplied to the nodes NE4 and NE2.

[0267] When a clock signal ECK2 having a low level is supplied to the third input terminal 103, due to the coupling of the capacitor CE1, the node NE2 drops to a voltage lower than the voltage of the power supply line VSSL. Accordingly, the voltages of the gate electrodes of the transistors Q11 and Q12 are lower than the voltage of the power supply line VSSL, so that the driving characteristics of these transistors can be improved.

[0268] Regardless of the voltage drop of the node NE2, due to the transistor Q2, the node NE4 can approximately hold the voltage of the power supply line VSSL. For example, since the voltage of the power supply line VSSL is continuously applied to the gate electrode of the transistor Q2, the voltage of the node NE4 corresponding to the source electrode of the transistor Q2 does not drop to a value lower than the value obtained by adding the threshold voltage value to the voltage of the power supply line VSSL. Accordingly, the voltage difference between the first electrode and the second electrode of the transistor Q7 is minimized or reduced, so that the change in the characteristics of the transistor Q7 can be prevented, or the change in the characteristics of the transistor Q7 can be reduced or minimized.

[0269] At time t4b, a first emission stop signal ELM1 having a cut-off level (high level) is supplied to the first input terminal 101, and a clock signal ECK1 having a low level is supplied to the second input terminal 102. For example, a pulse is generated in the clock signal ECK1. Accordingly, the transistors Q7 and Q9 are turned on.

[0270] When the transistor Q7 is turned on, the first input terminal 101 is electrically connected to the nodes NE4 and NE2. Accordingly, the nodes NE4 and NE2 are charged with a high-level voltage, and the transistors Q8, Q11, and Q12 are turned off.

[0271] When transistor Q9 is turned on, the voltage of power supply line VSSL is supplied to node NE3 and node NE5, and transistors Q3 and Q6 are turned on. Since transistor Q4 is turned off even when transistor Q3 is turned on, the voltage of node NE4 is maintained.

[0272] When transistor Q6 is turned on, the second electrode of capacitor CE2 and the third input terminal 103 are electrically connected to each other. Since transistor Q5 is in the off state, node NE1 remains at a high level.

[0273] At time t5b, a clock signal ECK2 with a low level is supplied to the third input terminal 103. For example, a pulse is generated in the clock signal ECK2. As a result, transistors Q4 and Q5 are turned on. Since nodes NE3 and NE5 are in a state where they are charged with the voltage of power supply line VSSL, transistors Q3 and Q6 are in the on state.

[0274] The clock signal ECK2 with a low level is applied to node NE1 via the turned-on transistors Q5 and Q6, and transistor Q10 is turned on. When transistor Q10 is turned on, the voltage of power supply line VDDL is supplied as the transmission signal E1 to the output terminal 104. Thus, a transmission signal E1 with a cut-off level (high level) can be supplied to the transmission line EL1.

[0275] When transistors Q3 and Q4 are turned on, the voltage of power supply line VDDL is supplied to node NE4 and node NE2. Thus, transistors Q8 and Q11 can be stably maintained in the off state.

[0276] At the same time, when a clock signal ECK2 with a low level is supplied to the second electrode of capacitor CE2, due to the coupling of capacitor CE2, the voltage of node NE5 drops to a voltage lower than the voltage of power supply line VSSL. As a result, the voltage applied to the gate electrode of transistor Q6 drops to a voltage lower than the voltage of power supply line VSSL, and the driving characteristics of transistor Q6 can be improved.

[0277] Regardless of the voltage of node NE5, the voltage of node NE3 can approximately maintain the voltage of power supply line VSSL through transistor Q1. For example, since the voltage of power supply line VSSL is continuously applied to the gate electrode of transistor Q1, the voltage of node NE3 corresponding to the source electrode of transistor Q1 does not drop below the value obtained by adding the threshold voltage value (e.g., the threshold voltage value of transistor Q1) to the voltage of power supply line VSSL. Therefore, regardless of the voltage drop of node NE5, node NE3 can approximately maintain the voltage of power supply line VSSL. The voltage difference between the source electrode and the drain electrode of transistor Q8 is minimized or reduced, so that the change of the characteristics of transistor Q8 can be prevented, or the change of the characteristics of transistor Q8 can be reduced or minimized.

[0278] At time t6b, a clock signal ECK1 with a low level is supplied to the second input terminal 102. For example, a pulse can be generated in the clock signal ECK1. Therefore, transistors Q7 and Q9 are turned on.

[0279] When transistor Q7 is turned on, node NE4 and node NE2 are electrically connected to the first input terminal 101, and thus, a voltage with a low level is supplied from the first input terminal 101 to node NE4 and node NE2. Therefore, transistors Q8, Q11, and Q12 are turned on.

[0280] When transistor Q8 is turned on, a clock signal ECK1 with a low level is supplied to node NE3 and node NE5.

[0281] When transistor Q12 is turned on, the voltage of power supply line VDDL is supplied to node NE1, and transistor Q10 is turned off.

[0282] When transistor Q11 is turned on, the voltage of power supply line VSSL is supplied to the output terminal 104. Therefore, an emission signal E1 with a conductive level (low level) can be supplied to the emission line EL1.

[0283] Meanwhile, by repeating the above process, the second emission stage EST12, which is supplied with the emission signal E1 with a cut-off level from the output terminal 104 of the first emission stage EST11, supplies the emission signal E2 with a cut-off level to the emission line EL2. For example, by repeating the above process, the emission stages EST11 to EST14 according to the embodiments of the present disclosure can supply emission signals to the emission lines EL1 to EL4.

[0284] Figure 21 It is a diagram showing a second emission driver according to an embodiment of the present disclosure.

[0285] Reference Figure 21, the second emission driver 42 may include a plurality of emission stages EST21 to EST24. For ease of description, four emission stages EST21 to EST24 are shown in Figure 21 . The emission stages EST21 to EST24 may be respectively connected to corresponding emission lines EL(p + 1) to EL(p + 4), and may be commonly connected to the emission clock line ECKLS. The emission stages EST21 to EST24 may have substantially the same circuit structure.

[0286] Each of the emission stages EST21 to EST24 may include a first input terminal 101, a second input terminal 102, a third input terminal 103, and an output terminal 104.

[0287] The first input terminal 101 may receive an output signal (e.g., an emission signal or a carry signal) of the previous emission stage or the second emission stop signal ELM2. In an example, the first input terminal 101 of the first emission stage EST21 may be connected to the second emission stop line ELML2, and the first input terminal 101 of each of the other emission stages EST22 to EST24 may be connected to the emission line of the previous emission stage.

[0288] The second input terminal 102 of the h-th (h is odd or even) emission stage may be connected to the clock line ECKL1, and the third input terminal 103 of the h-th emission stage may be connected to the clock line ECKL2. For example, as shown in Figure 21 , h may be odd. Additionally, the second input terminal 102 of the (h + 1)-th emission stage may be connected to the clock line ECKL2, and the third input terminal 103 of the (h + 1)-th emission stage may be connected to the clock line ECKL1. For example, the clock line ECKL1 and the clock line ECKL2 may be alternately connected to the second input terminal 102 and the third input terminal 103 of each emission stage.

[0289] The pulse of the clock signal ECK1 applied to the clock line ECKL1 and the pulse of the clock signal ECK2 applied to the clock line ECKL2 do not overlap with each other in time. Each pulse may have a conductive level.

[0290] The emission stages EST21 to EST24 may be connected to the power supply line VDDL and the power supply line VSSL. The voltage of the power supply line VDDL may be set to a cut-off level, and the voltage of the power supply line VSSL may be set to a conductive level. The voltage level of the emission signal may be set based on the voltage of one of the power supply line VDDL and the power supply line VSSL.

[0291] The circuit configuration of the emission stages EST21 to EST24 may be the same as that of Figure 18The circuit configurations of the emission stages EST11 to EST14 shown in [figure] are the same or substantially the same, and thus, the overlapping descriptions may not be repeated.

[0292] Figure 22 and Figure 23 are diagrams showing the case where data write frames are consecutive.

[0293] Referring to Figure 22 , for ease of description, a plurality of pixels PX1 to PX6 connected to the first data line DL1 are shown as an example. For ease of description, the plurality of pixels PX1 to PX6 are described based on the scan lines GWPL1, GWPL2, GWPLp, GWPL(p + 1), GWPL(p + 2), and GWPLq among the scan lines connected to the respective pixels PX1 to PX6 and connected to the gate electrodes of the transistors T2 of the respective pixels PX1 to PX6. For example, the pixels PX1 to PX6 are described based on the scan lines GWPL1 to GWPLq connected to the first scan driver 30P1 and the second scan driver 30P2.

[0294] Hereinafter, the "first scan line" may represent a scan line among the scan lines connected to the first scan driver 30P1 that supplies a scan signal having a first conduction level after the generation of the first scan start signal FLM1 having a conduction level. In the Figure 22 embodiment shown in [figure], the first scan line may represent the first scan line GWPL1. Additionally, the "last scan line" may represent a scan line among the scan lines connected to the second scan driver 30P2 that supplies a scan signal having a last conduction level after the generation of the second scan start signal FLM2. In the Figure 22 embodiment shown in [figure], the last scan line may represent the sixth scan line GWPLq. The "next scan line" of a reference scan line may represent a scan line that supplies a scan signal having a conduction level at the closest time after (e.g., at the next time among the times when the scan signal is supplied to the scan line) a scan signal having a conduction level is supplied to the reference scan line. The "previous scan line" of a reference scan line may represent a scan line that supplies a scan signal having a conduction level at the closest time before (e.g., at the previous time among the times when the scan signal is supplied to the scan line) a scan signal having a conduction level is supplied to the reference scan line. The above description is based on the case where one conduction level pulse is supplied to the scan line in one frame including the data write period WP. When two or more pulses having a conduction level are continuously supplied to the scan line in each frame, the above description may be applied based on the last pulse.

[0295] The first pixel PX1 can be connected to a first data line DL1, a first scan line GWPL1, a first emission line EL1, and scan lines GIL1, GWNL1, and GBL1. The first scan line GWPL1 can be connected to a first scan driver 30P1. The first scan line GWPL1 can be the first scan line.

[0296] The second pixel PX2 can be connected to the first data line DL1, a second scan line GWPL(p + 1), a second emission line EL(p + 1), and scan lines GIL(p + 1), GWNL(p + 1), and GBL(p + 1). The second scan line GWPL(p + 1) can be connected to a second scan driver 30P2.

[0297] The third pixel PX3 can be connected to the first data line DL1, a third scan line GWPL2, a third emission line EL2, and scan lines GIL2, GWNL2, and GBL2. The third scan line GWPL2 can be connected to the first scan driver 30P1. The third scan line GWPL2 can be the next scan line of the first scan line GWPL1.

[0298] The fourth pixel PX4 can be connected to the first data line DL1, a fourth scan line GWPL(p + 2), a fourth emission line EL(p + 2), and scan lines GIL(p + 2), GWNL(p + 2), and GBL(p + 2). The fourth scan line GWPL(p + 2) can be connected to the second scan driver 30P2. The fourth scan line GWPL(p + 2) can be the next scan line of the second scan line GWPL(p + 1).

[0299] The fifth pixel PX5 can be connected to the first data line DL1, a fifth scan line GWPLp, a fifth emission line ELp, and scan lines GILp, GWNLp, and GBLp. The fifth scan line GWPLp can be connected to the first scan driver 30P1. The fifth scan line GWPLp can be the previous scan line of the second scan line GWPL(p + 1).

[0300] The sixth pixel PX6 can be connected to the first data line DL1, a sixth scan line GWPLq, a sixth emission line ELq, and scan lines GILq, GWNLq, and GBLq. The sixth scan line GWPLq can be connected to the second scan driver 30P2. The sixth scan line GWPLq can be the last scan line.

[0301] The emission lines EL1, EL2, and ELp can be connected to a first emission driver 41. The emission lines EL(p + 1), EL(p + 2), and ELq can be connected to a second emission driver 42. The scan lines GWNL1, GWNL2, GWNLp, GWNL(p + 1), GWNL(p + 2), and GWNLq can be connected to a third scan driver 30N.

[0302] Reference Figure 23 shows example two frame periods when driving a display device in a first display mode. The first frame period may sequentially include a first vertical blanking period and a first active data period ADPN. A second frame period, which is the next frame period of the first frame period, may sequentially include a second vertical blanking period VBP(N + 1) and a second active data period ADP(N + 1).

[0303] The "active data period" may be a supply period of gray values constituting an image frame to be displayed by the pixel units 50. The "vertical blanking period" may be a transition period between the active data period of the previous image frame and the active data period of the current image frame. Clock training, frame setting, and pseudo data supply may be performed during the vertical blanking period. Pulses of the above vertical synchronization signal may be generated during the vertical blanking period and may not be generated during the active data period. Pulses of the above horizontal synchronization signal may be generated in both the vertical blanking period and the active data period.

[0304] Before a first data writing period WPN, pixels PX1 to PX6 may emit light based on data voltages written in the previous data writing period during a emission period EP(N - 1). The data writing period and the emission period may be changed in units of pixel rows.

[0305] Based on each pixel row, the first active data period ADPN may sequentially include a first data writing period WPN and a first emission period EPN. In the first data writing period WPN, data voltages may be sequentially written into pixels PX1 to PX6. During the first emission period EPN, pixels PX1 to PX6 may emit light based on the data voltages written in the first data writing period WPN.

[0306] Clock training, frame setting, and pseudo data supply may be performed during the second vertical blanking period VBP(N + 1). In the second vertical blanking period VBP(N + 1), pixels PX1 to PX6 may maintain an emission state based on the data voltages written in the first data writing period WPN.

[0307] Based on each pixel row, the second active data period ADP(N + 1) may include a second data writing period WP(N + 1) and a second emission period EP(N + 1). In the second data writing period WP(N + 1), data voltages may be sequentially written into pixels PX1 to PX6. During the second emission period EP(N + 1), pixels PX1 to PX6 may emit light based on the data voltages written in the second data writing period WP(N + 1).

[0308] The scan clock signal PCKS may represent being applied to Figure 9The scan clock signal of the clock line in the scan clock line PCKLS shown in. The scan clock signal PCKS may correspond to the first scan clock signal or the second scan clock signal described above. Figure 23 The scan clock signal PCKS shown in is simply shown to describe the first period PP1, and may have a waveform different from the actual waveform (e.g., different from Figure 23 the waveform shown in).

[0309] The scan clock signal NCKS may represent the scan clock signal of the clock line applied to the Figure 9 scan clock line NCKLS shown in. Figure 23 The scan clock signal NCKS shown in is simply shown to describe whether to supply the scan clock signal NCKS, and may have a waveform different from the actual waveform (e.g., Figure 23 the waveform shown in). Since it is necessary for the third scan driver 30N to sequentially supply scan signals with a conductive level during the data write periods WPN and WP(N + 1), the scan clock signal NCKS with a conductive level may also be supplied in a specific period.

[0310] The emission clock signal ECKS may represent the emission clock signal of the clock line applied to the Figure 17 emission clock line ECKLS shown in. The emission clock signal ECKS may correspond to the first emission clock signal or the second emission clock signal described above. Figure 23 The emission clock signal ECKS shown in is simply shown to describe the third period EP1, and may have a waveform different from the actual waveform (e.g., different from Figure 23 the waveform shown in).

[0311] At time t1c, the first scan start signal FLM1 with a conductive level may be supplied. Synchronized with the supply of the first scan start signal FLM1 with a conductive level, the third scan start signal FLM3 with a conductive level and the first emission stop signal ELM1 with a cut-off level may be supplied.

[0312] At time t2c, the scan stage PST11 may supply the first scan signal GWP1 with a conductive level (low level).

[0313] At time t3c, the second scan start signal FLM2 with a conductive level may be supplied. Synchronized with the supply of the second scan start signal FLM2 with a conductive level, the second emission stop signal ELM2 with a cut-off level may be supplied.

[0314] At time t4c, the scan stage PST21 may supply the second scan signal GWP(p + 1) with a conductive level.

[0315] The operations of the scan driver 30 and the emission driver 40 at the times t1c, t2c, t3c, and t4c in the first frame period are the same as the operations of the scan driver 30 and the emission driver 40 at the times t5c, t6c, t7c, and t8c in the second frame period, and thus, the overlapping descriptions may not be repeated.

[0316] In the first frame period and the second frame period, the scan clock signal PCKS may have a first period PP1. Additionally, in the first frame period and the second frame period, the emission clock signal ECKS may have a third period EP1.

[0317] Figures 24 to 26 is a diagram showing the case where a data write frame and a bias refresh frame are consecutive.

[0318] Reference Figure 24 , shows an example of two frame periods when a display device is displayed in the second display mode. The first frame period may sequentially include a first vertical blanking period and a first active data period ADPN. The second frame period, which is the next frame period of the first frame period, may sequentially include a second vertical blanking period VBP(N + 1) and a second dummy data period DDP(N + 1).

[0319] The "dummy data period" may correspond to the "active data period". For example, the length of the "dummy data period" may be equal to the length of the "active data period" (e.g., equal to the length of the first active data period ADPN). However, the gray scale values constituting the image frame may not be supplied during the "dummy data period".

[0320] The operations of the scan driver 30 and the emission driver 40 at the times t1d, t2d, t3d, and t4d in the first frame period in the second display mode may be the same as the operations of the scan driver 30 and the emission driver 40 at the times t1c, t2c, t3c, and t4c in the first frame period in the first display mode, and thus, the overlapping descriptions may not be repeated. The difference between the time t3d when the second scan start signal FLM2 having a conductive level is supplied and the time t1d when the first scan start signal FLM1 having a conductive level is supplied may be defined as a first period.

[0321] When the number of pixels connected to the first data line DL1 between the first pixel PX1 and the second pixel PX2 is X and the horizontal period is Y, the first period may correspond to (X + 1) × Y.

[0322] According to an embodiment of the present disclosure, in the second frame period, the difference between the time t5d at which the first scan start signal FLM1 having a conductive level is supplied and the time t5d at which the second scan start signal FLM2 having a conductive level is supplied may correspond to the second period. The second period may be shorter than the first period.

[0323] In Figure 24 the embodiment shown, the first scan start signal FLM1 having a conductive level and the second scan start signal FLM2 having a conductive level may be supplied concurrently or simultaneously. For example, in Figure 24 the second frame period shown, the first scan start signal FLM1 and the second scan start signal FLM2 may be supplied concurrently or simultaneously. Accordingly, the second period may be 0 (0 seconds).

[0324] Based on each pixel row connected to the first scan driver 30P1, the second pseudo data period DDP(N+1) may sequentially include a first bias refresh period BP1(N+1) and a first emission period EP1(N+1). Additionally, based on each pixel row connected to the second scan driver 30P2, the second pseudo data period DDP(N+1) may sequentially include a second bias refresh period BP2(N+1) and a second emission period EP2(N+1).

[0325] According to this embodiment, at least a portion of the first bias refresh period BP1(N+1) and the second bias refresh period BP2(N+1) may overlap each other. In Figure 24 the embodiment shown, the first bias refresh period BP1(N+1) and the second bias refresh period BP2(N+1) may be the same. Accordingly, the first emission period EP1(N+1) and the second emission period EP2(N+1) may be the same.

[0326] For example, according to this embodiment, the first scan driver 30P1 and the second scan driver 30P2 may operate concurrently or simultaneously, and accordingly, the scan clock signal PCKS may have a second period PP2. The second period PP2 may be longer than the first period PP1. For example, the frequency of the scan clock signal PCKS in the second frame period may be lower than the frequency of the scan clock signal PCKS in the first frame period, and accordingly, power consumption may be reduced.

[0327] Referring to Figure 7 and Figure 8 the driving method shown, the supply of the first emission stop signal ELM1 having a cut-off level must be synchronized with the supply of the first scan start signal FLM1 having a conductive level. Additionally, the supply of the second emission stop signal ELM2 having a cut-off level must be synchronized with the supply of the second scan start signal FLM2 having a conductive level.

[0328] In the first frame period, the difference between the time when the second emission stop signal ELM2 having a cut-off level is supplied and the time when the first emission stop signal ELM1 having a cut-off level is supplied may be defined as a third period. Additionally, in the second frame period, the difference between the time when the second emission stop signal ELM2 having a cut-off level is supplied and the time when the first emission stop signal ELM1 having a cut-off level is supplied may be defined as a fourth period. The fourth period may be shorter than the third period.

[0329] For example, according to this embodiment, the first emission driver 41 and the second emission driver 42 may operate concurrently or simultaneously, and thus, the emission clock signal ECKS may have a fourth period EP2. The fourth period EP2 may be longer than the third period EP1. For example, the frequency of the emission clock signal ECKS in the second frame period may be lower than the frequency of the emission clock signal ECKS in the first frame period, and thus power consumption may be reduced.

[0330] Reference Figure 7 and Figure 8 In the driving method shown, the third scan driver 30N does not supply a scan signal having a conductive level during the second frame period. Therefore, the third scan driver 30N does not have to supply a scan clock signal NCKS having a conductive level at a specific period during the second frame period. Moreover, the third scan driver 30N does not supply a third scan start signal FLM3 having a conductive level during the second frame period.

[0331] Reference Figure 25 In the second display mode, a part of the valid data period ADPN and a part of the dummy data period DDP(N + 1) are compared with each other. For example, the valid data period ADPN and the dummy data period DDP(N + 1) may be compared based on the times t2d and t6d when the first scan signal GWP1 having a conductive level is supplied.

[0332] In the first frame period, the difference between the time t2d when the first scan signal GWP1 having a conductive level is applied to the first scan line GWPL1 and the time t2.1d when the third scan signal GWP2 having a conductive level is applied to the third scan line GWPL2 may be defined as a third period.

[0333] Additionally, in the second frame period, the difference between the time t6d when the first scan signal GWP1 having a conductive level is applied and the time t6.1d when the third scan signal GWP2 having a conductive level is applied may be defined as a fourth period. The fourth period may be longer than the third period.

[0334] This driving characteristic is a phenomenon that occurs because the second period PP2 of the scan clock signal PCKS supplied to the first scan driver 30P1 and the second scan driver 30P2 is longer than the first period PP1.

[0335] Meanwhile, referring to Figure 22 and Figure 24 In the first frame period, the time when the fifth scan signal GWPp having a conductive level is applied to the fifth scan line GWPLp can be earlier than the time t4d when the second scan signal GWP(p + 1) having a conductive level is applied. Meanwhile, in the second frame period, the time when the fifth scan signal GWPp having a conductive level is applied can be later than the time t6d when the second scan signal GWP(p + 1) having a conductive level is applied.

[0336] Referring to Figure 26 it shows the following situation: in the second frame period, the second period PSD, which is the difference between the time when the first scan start signal FLM1 having a conductive level is supplied and the time when the second scan start signal FLM2' having a conductive level is supplied, is not 0 (0 seconds).

[0337] For example, at least part of the first bias refresh period BP1(N + 1) and the second bias refresh period BP2(N + 1)' can overlap with each other, but the first bias refresh period BP1(N + 1) and the second bias refresh period BP2(N + 1)' may not be exactly the same (for example, may not completely overlap). Therefore, at least part of the emission periods EP1(N + 1) and EP2(N + 1)' can overlap with each other, but the emission periods EP1(N + 1) and EP2(N + 1)' may not be exactly the same (for example, may not completely overlap).

[0338] For example, the minimum value of the second period PSD can be 0 (0 seconds), and the maximum value of the second period PSD can correspond to the second vertical blanking period VBP(N + 1). The second period PSD is set to be equal to or less than the maximum value so that the bias refresh periods BP1(N + 1) and BP2(N + 1)' do not overlap with the adjacent data writing period WPN.

[0339] Similarly, in the second frame period, the fourth period ESD, which is the difference between the time when the first emission stop signal ELM1 having a cut-off level is supplied and the time when the second emission stop signal ELM2' having a cut-off level is supplied, can be not 0 (0 seconds).

[0340] In Figure 26In this case, a situation is shown where the time when the second scan start signal FLM2' having a conductive level is supplied in the second frame period is earlier than the time when the first scan start signal FLM1 having a conductive level is supplied. However, in another embodiment, the time when the first scan start signal FLM1 having a conductive level is supplied is earlier than the time when the second scan start signal FLM2' having a conductive level is supplied. For example, the time when the first scan start signal FLM1 having a conductive level is supplied may occur during the second vertical blanking period VBP(N + 1).

[0341] Similarly, in Figure 26 a situation is shown where the time when the second emission stop signal ELM2' having a cut-off level is supplied in the second frame period is earlier than the time when the first emission stop signal ELM1 having a cut-off level is supplied. However, in another embodiment, the time when the first emission stop signal ELM1 having a cut-off level is supplied may be earlier than the time when the second emission stop signal ELM2' having a cut-off level is supplied. For example, the time when the first emission stop signal ELM1 having a cut-off level is supplied may occur during the second vertical blanking period VBP(N + 1).

[0342] In the display device and its driving method according to the present disclosure, the frequency of the clock signal is controlled according to the type of frame, so that power consumption can be reduced.

[0343] Example embodiments have been disclosed herein, and although example terms are used, they are used and interpreted only in a general and descriptive sense and are not for the purpose of limitation. In some cases, as will be apparent to those of ordinary skill in the art at the time of effective filing of this application, features, characteristics, and / or elements described in connection with one embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with another embodiment, unless specifically stated otherwise. Therefore, those skilled in the art will understand that various suitable changes can be made in form and detail without departing from the spirit and scope of the present disclosure set forth in the appended claims and their equivalents.

Claims

1. A display device, comprising: a first scan driver connected to a first scan start line and a first scan line; a second scan driver connected to a second scan start line and a second scan line; and pixels connected to the first scan line and the second scan line, each of the pixels including a P-type transistor connected to one of the first scan lines and an N-type transistor connected to one of the second scan lines, wherein, in a first period of a low-frequency driving mode, the second scan start line is supplied with a second scan start signal having a conductive level, and the first scan start signal having the conductive level is supplied to the first scan start line, wherein, in a second period of the low-frequency driving mode, the second scan start line is supplied with the second scan start signal maintaining a cut-off level, and the first scan start signal having the conductive level is supplied to the first scan start line, and wherein the second period is after the first period.

2. The display device according to claim 1, wherein, in the first period, the first scan clock signal supplied to the first scan driver has a first period, and wherein, in the second period, the first scan clock signal has a second period longer than the first period.

3. The display device according to claim 2, wherein, in the first period, the second scan clock signal supplied to the second scan driver has the first period, and wherein, in the second period, the second scan clock signal maintains a cut-off level.

4. The display device according to claim 3, further comprising: a first emission driver connected to a first emission stop line and a first emission line; and a second emission driver connected to a second emission stop line and a second emission line, wherein each of the pixels further includes a transistor connected to one of the first emission line and the second emission line, wherein, in the first period, after a third period elapses after the first emission stop signal having a cut-off level is supplied to the first emission stop line, the second emission stop line is supplied with a second emission stop signal having a cut-off level, wherein, in the second period, the difference between the time when the first emission stop signal having the cut-off level is supplied and the time when the second emission stop signal having the cut-off level is supplied corresponds to a fourth period, and wherein the fourth period is shorter than the third period.

5. The display device according to claim 4, wherein, in the first period, the first emission clock signal supplied to the first emission driver has a third period, and wherein, in the second period, the first emission clock signal has a fourth period longer than the third period.

6. The display device according to claim 5, wherein, in the first period, the second emission clock signal supplied to the second emission driver has the third period, and wherein, in the second period, the second emission clock signal has the fourth period.

7. A method for driving a display device, the method comprising: In a first period of a low-frequency driving mode, supplying a first scan start signal having a conductive level to a first scan start line connected to a first scan driver; In the first period, supplying a second scan start signal having a conductive level to a second scan start line connected to a second scan driver; and In a second period of the low-frequency driving mode, supplying the first scan start signal having the conductive level and the second scan start signal maintaining a cut-off level, wherein the second period is after the first period.

8. The method according to claim 7, wherein, In the first period, a first scan clock signal supplied to the first scan driver has a first period, and wherein, in the second period, the first scan clock signal has a second period longer than the first period.

9. The method according to claim 8, wherein, In the first period, a second scan clock signal supplied to the second scan driver has the first period, and wherein, in the second period, the second scan clock signal maintains a cut-off level.

10. The method according to claim 9, further comprising: In the first period, supplying a first emission stop signal having a cut-off level to a first emission stop line connected to a first emission driver; In the first period, after a third period has elapsed after the first emission stop signal having the cut-off level is supplied, supplying a second emission stop signal having a cut-off level to a second emission stop line connected to a second emission driver; and In the second period, supplying the first emission stop signal having the cut-off level and the second emission stop signal having the cut-off level with a time difference of a fourth period, wherein the fourth period is shorter than the third period.

11. The method according to claim 10, wherein, In the first period, a first emission clock signal supplied to the first emission driver has a third period, and wherein, in the second period, the first emission clock signal has a fourth period longer than the third period.

12. The method according to claim 11, wherein, In the first period, a second emission clock signal supplied to the second emission driver has the third period, and wherein, in the second period, the second emission clock signal has the fourth period.

13. A display device, comprising: A first scan driver connected to a first scan start line and a first scan line; A second scan driver connected to a second scan start line and a second scan line; and Pixels connected to the first scan line and the second scan line, wherein each of the pixels includes: A first transistor; A second transistor including a first electrode connected to a data line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a corresponding one of the first scan lines; and A third transistor, including a first electrode connected to the gate electrode of the first transistor, a second electrode connected to the second electrode of the first transistor, and a gate electrode connected to a corresponding one of the second scan lines, wherein, in a first period of a low-frequency driving mode, the second scan start line is supplied with a second scan start signal having a conductive level, and a first scan start signal having a conductive level is supplied to the first scan start line, wherein, in a second period of the low-frequency driving mode, the second scan start line is supplied with the second scan start signal maintaining a cut-off level, and the first scan start signal having the conductive level is supplied to the first scan start line, and wherein the second period is after the first period.

14. The display device according to claim 13, wherein, the second transistor is a polysilicon transistor, and wherein the third transistor is an oxide semiconductor transistor.

15. The display device according to claim 13, wherein, each of the pixels further includes: a light-emitting diode; a fourth transistor, including a first electrode connected to the gate electrode of the first transistor, a second electrode connected to an initialization line, and a gate electrode connected to a third scan line; a fifth transistor, including a first electrode connected to a first power supply line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to an emission line; a sixth transistor, including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the anode of the light-emitting diode, and a gate electrode connected to the emission line; and a seventh transistor, including a first electrode connected to the initialization line, a second electrode connected to the anode of the light-emitting diode, and a gate electrode connected to a fourth scan line.

16. The display device according to claim 15, wherein, the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor are polysilicon transistors, and wherein the third transistor and the fourth transistor are oxide semiconductor transistors.

17. The display device according to claim 15, further including: a third scan driver, connected to a third scan start line and a third scan line including the third scan line; and a fourth scan driver, connected to a fourth scan start line and a fourth scan line including the fourth scan line.

18. The display device according to claim 13, wherein, in the first period, a first scan clock signal supplied to the first scan driver has a first period, and wherein, in the second period, the first scan clock signal has a second period longer than the first period.

19. The display device according to claim 18, wherein, in the first period, a second scan clock signal supplied to the second scan driver has the first period, and wherein, in the second period, the second scan clock signal maintains a cut-off level.

20. The display device according to claim 19, further including: A first emission driver, connected to a first emission stop line and a first emission line; and a second emission driver, connected to a second emission stop line and a second emission line, wherein each of the pixels further includes a transistor connected to a corresponding one of the first emission line and the second emission line, wherein, in the first period, after a third period has elapsed after a first emission stop signal having a cut-off level is supplied to the first emission stop line, the second emission stop line is supplied with a second emission stop signal having a cut-off level, wherein, in the second period, the difference between the time when the first emission stop signal having the cut-off level is supplied and the time when the second emission stop signal having the cut-off level is supplied corresponds to a fourth period, and wherein the fourth period is shorter than the third period.

21. The display device according to claim 20, wherein, in the first period, the first emission clock signal supplied to the first emission driver has a third period, and wherein, in the second period, the first emission clock signal has a fourth period longer than the third period.

22. The display device according to claim 21, wherein, in the first period, the second emission clock signal supplied to the second emission driver has the third period, and wherein, in the second period, the second emission clock signal has the fourth period.

Images