Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. According to the display panel, part of the signal input lines are electrically connected with the two data lines, the control transistors are arranged between the signal input lines and the two corresponding data lines, and the grid electrodes of the control transistors are connected with the signal control lines, so that one signal input line can be electrically connected with the multiple data lines, and the number of channels of a driving chip is reduced; grid electrodes of a plurality of control transistors connected with a plurality of data lines connected with the sub-pixel units with the same light emitting color are connected with the same signal control line, so that the sub-pixel units with the same light emitting color are controlled by the same signal control line, and the sub-pixel units with the same light emitting color can be charged at the same time; vertical stripes caused by different charging time are avoided, and the yield of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] With the development of display technologies, the refresh rate of display devices is getting higher and higher. Correspondingly, the number of signal lines required in display devices is increasing. However, the channels of driving chips are limited. Increasing the signal lines correspondingly requires adding driving chips, which will lead to problems such as increased costs and increased borders. To solve the above problems, existing display devices have proposed a mux (multiplexing) technology, that is, two signal lines are connected to a channel of a driving chip under the control of a multiplexing line. Thus, when the frequency increases and the number of signal lines increases, there is no need to add a driving chip, reducing costs and reducing the border. However, in actual use, it is found that using the multiplexing technology will cause vertical stripes to appear in the display device, resulting in abnormal display.

[0003] Therefore, existing display devices using the multiplexing technology are prone to technical problems of vertical stripes during display, resulting in poor display. Summary of the Invention

[0004] Embodiments of the present application provide a display panel and a display device to solve the technical problem that existing display devices using the multiplexing technology are prone to vertical stripes during display, resulting in poor display.

[0005] To achieve the above object, according to the first aspect of the present application, a display panel is provided. The display panel includes a plurality of pixel units arranged in an array, and each of the pixel units includes a plurality of sub-pixel units of different light-emitting colors; the display panel includes:

[0006] Multiple data lines;

[0007] Multiple signal input lines, some of the signal input lines are electrically connected to two of the data lines, and a control transistor is provided between the signal input line and the corresponding two data lines. The gate of the control transistor is connected to a signal control line;

[0008] Wherein, each of the sub-pixel units is connected to one of the data lines, and the gates of the multiple control transistors connected to the multiple data lines connected by the sub-pixel units of the same light-emitting color are connected to the same signal control line.

[0009] According to the second aspect of the present application, a display device is provided. The display device includes the display panel according to any one of the above embodiments.

[0010] An embodiment of the present application provides a display panel and a display device. By electrically connecting some signal input lines to two data lines, and providing a control transistor between the signal input line and the corresponding two data lines, with the gate of the control transistor connected to the signal control line, one signal input line can be electrically connected to multiple data lines, reducing the number of channels of the driving chip. Moreover, the gates of the multiple control transistors connected to the multiple data lines to which the sub-pixel units of the same emission color are connected are connected to the same signal control line, such that the sub-pixel units of the same emission color are controlled by the same signal control line, and the sub-pixel units of the same emission color can be charged simultaneously, avoiding vertical stripes caused by different charging times and improving the yield of the display panel.

[0011] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0013] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, where the same reference numerals in the following description represent the same parts.

[0014] Figure 1 Schematic diagram of the first comparative display device provided by the embodiment of the present application.

[0015] Figure 2 Schematic diagram of the second comparative display device provided by the embodiment of the present application.

[0016] Figure 3 Schematic diagram of the third comparative display device provided by the embodiment of the present application.

[0017] Figure 4 Schematic diagram of the pixel arrangement of the display panel provided by the embodiment of the present application.

[0018] Figure 5 First schematic diagram of the connection manner of the sub-pixel unit, data line, signal input line, signal control line, and control transistor of the display panel provided by the embodiment of the present application.

[0019] Figure 6 Second schematic diagram of the connection manner of the sub-pixel unit, data line, signal input line, signal control line, and control transistor of the display panel provided by the embodiment of the present application.

[0020] Figure 7 The third schematic diagram of the connection manner of the sub-pixel unit, data line, signal input line, signal control line, and control transistor of the display panel provided by the embodiment of the present application.

[0021] Figure 8 The fourth schematic diagram of the connection manner of the sub-pixel unit, data line, signal input line, signal control line, and control transistor of the display panel provided by the embodiment of the present application.

[0022] Figure 9 For Figure 6 and Figure 8 the timing diagram of the signal control line of the display panel in Detailed implementation manners

[0023] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0024] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "connection" and "electrical connection" should be understood in a broad sense. For example, they can be directly connected or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0025] To illustrate the principle of the technical problems generated in the embodiments of the present application, some comparative display devices are provided. It can be understood that these comparative display devices cannot be used as the prior art in the embodiments of the present application. As Figure 1 shown, a comparative display device is provided. Taking the comparative display device as a liquid crystal display device as an example, the comparative display device includes a red sub-pixel 111, a green sub-pixel 112, and a blue sub-pixel 113. Each sub-pixel is connected to a data trace, and each data input trace is connected to two data traces through a multiplexing transistor 12, and it can be seen from Figure 1 that Figure 1 in

[0026] From Figure 1As can be seen, the comparison display device includes a first data input trace S01, a second data input trace S02, a third data input trace S03, a fourth data input trace S04, a fifth data input trace S05, and a sixth data input trace S06. The polarities of the signals output from the first data input trace S01, the third data input trace S03, and the fifth data input trace S05 are positive, and the polarities of the signals output from the second data input trace S02, the fourth data input trace S04, and the sixth data input trace S06 are negative.

[0027] From Figure 1 As can be seen, the comparison display device further includes a first data trace D1, a second data trace D2, a third data trace D3, a fourth data trace D4, a fifth data trace D5, a sixth data trace D6, a seventh data trace D7, an eighth data trace D8, a ninth data trace D9, a tenth data trace D10, an eleventh data trace D11, and a twelfth data trace D12. The polarities of the signals output from the first data trace D1, the third data trace D3, the fifth data trace D5, the seventh data trace D7, the ninth data trace D9, and the eleventh data trace D11 are positive, and the polarities of the signals output from the second data trace D2, the fourth data trace D4, the sixth data trace D6, the eighth data trace D8, the tenth data trace D10, and the twelfth data trace D12 are negative.

[0028] From Figure 1 As can be seen, the first data trace D1 and the third data trace D3 are connected to the first data input trace S01 through a multiplexing transistor 12, the second data trace D2 and the fourth data trace D4 are connected to the second data input trace S02 through a multiplexing transistor 12, the fifth data trace D5 and the seventh data trace D7 are connected to the third data input trace S03 through a multiplexing transistor 12, the sixth data trace D6 and the eighth data trace D8 are connected to the fourth data input trace S04 through a multiplexing transistor 12, the ninth data trace D9 and the eleventh data trace D11 are connected to the fifth data input trace S05 through a multiplexing transistor 12, and the tenth data trace D10 and the twelfth data trace D12 are connected to the sixth data input trace S06 through a multiplexing transistor 12.

[0029] From Figure 1 As can be seen, the first data trace D1, the fourth data trace D4, the seventh data trace D7, and the tenth data trace D10 are connected to the red sub-pixel 111, the second data trace D2, the fifth data trace D5, the eighth data trace D8, and the eleventh data trace D11 are connected to the green sub-pixel 112, and the third data trace D3, the sixth data trace D6, the ninth data trace D9, and the twelfth data trace D12 are connected to the blue sub-pixel.

[0030] But from Figure 1It can be seen that the gates of the multiplexing transistors connected to multiple data lines connected to sub-pixels of the same emission color are connected to different multiplexing lines. Taking the red sub-pixel 111 as an example, it can be seen that the two multiplexing transistors connected to the first data trace D1 and the tenth data trace D10 are connected to the first multiplexing line MUX01, and the two multiplexing transistors connected to the fourth data trace D4 and the seventh data trace D7 are connected to the second multiplexing line MUX02. Since the first multiplexing line MUX01 and the second multiplexing line MUX02 do not receive signals simultaneously, the charging start times of the respective red sub-pixels 111 are different, and thus the charging rates of the respective red sub-pixels 111 are different, resulting in vertical stripes during display. Therefore, existing display devices using multiplexing technology are prone to the technical problem of vertical stripes causing poor display during display.

[0031] As Figure 2 shown, another comparative display device is provided. Taking the comparative display device as an OLED (Organic Light-Emitting Diode) as an example, the comparative display device does not require polarity inversion. At the same time, in order to prevent the signals of the data traces from being switched when the comparative display device displays a pure color screen, the first data trace D1 and the fourth data trace D4 are connected to the first data input trace S01 through the multiplexing transistor 12, the second data trace D2 and the fifth data trace D5 are connected to the second data input trace S02 through the multiplexing transistor 12, the third data trace D3 and the sixth data trace D6 are connected to the third data input trace S03 through the multiplexing transistor 12, the seventh data trace D7 and the tenth data trace D10 are connected to the fourth data input trace S04 through the multiplexing transistor 12, the eighth data trace D8 and the eleventh data trace D11 are connected to the fifth data input trace S05 through the multiplexing transistor 12, and the ninth data trace D9 and the twelfth data trace D12 are connected to the sixth data input trace S06 through the multiplexing transistor 12.

[0032] However, it can be seen from Figure 2 that there will still be a situation where the gates of the multiplexing transistors connected to multiple data lines connected to sub-pixels of the same emission color are connected to different multiplexing lines. Taking the red sub-pixel 111 as an example, it can be seen that the two multiplexing transistors connected to the first data trace D1 and the fourth data trace D4 are connected to the first multiplexing line MUX01, and the two multiplexing transistors connected to the seventh data trace D7 and the tenth data trace D10 are connected to the second multiplexing line MUX02. Since the first multiplexing line MUX01 and the second multiplexing line MUX02 do not receive signals simultaneously, the charging start times of the respective red sub-pixels 111 are different, and thus the charging rates of the respective red sub-pixels 111 are different, resulting in vertical stripes during display. Therefore, existing display devices using multiplexing technology are prone to the technical problem of vertical stripes causing poor display during display.

[0033] In view of the above technical problems, embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0034] Figure 4 It is a schematic diagram of the pixel arrangement of the display panel provided by an embodiment of the present application. Figure 5 It is a first schematic diagram of the connection manner of the sub-pixel unit, data line, signal input line, signal control line, and control transistor of the display panel provided by an embodiment of the present application. Figure 6 It is a second schematic diagram of the connection manner of the sub-pixel unit, data line, signal input line, signal control line, and control transistor of the display panel provided by an embodiment of the present application. Figure 7 It is a third schematic diagram of the connection manner of the sub-pixel unit, data line, signal input line, signal control line, and control transistor of the display panel provided by an embodiment of the present application. Figure 8 It is a fourth schematic diagram of the connection manner of the sub-pixel unit, data line, signal input line, signal control line, and control transistor of the display panel provided by an embodiment of the present application. Figure 9 is Figure 6 and Figure 8 The timing diagram of the signal control line of the display panel in.

[0035] As Figures 4 to 9 shown, embodiments of the present application provide a display panel. The display panel 2 includes a plurality of pixel units 21 arranged in an array, and each pixel unit 21 includes a plurality of sub-pixel units 201 of different light-emitting colors; the display panel 2 includes a plurality of data lines Data and a plurality of signal input lines SL. Some of the signal input lines SL are electrically connected to two of the data lines Data, and a control transistor 22 is provided between the signal input line SL and the corresponding two data lines Data. The gate of the control transistor 22 is connected to the signal control line MUX;

[0036] Among them, each sub-pixel unit 201 is connected to one data line Data, and the gates of the plurality of control transistors 22 connected to the plurality of data lines Data connected by the sub-pixel units 201 of the same light-emitting color are connected to the same signal control line MUX.

[0037] An embodiment of the present application provides a display panel. By electrically connecting some signal input lines SL to two data lines Data, and providing a control transistor 22 between the signal input line SL and the corresponding two data lines Data, and connecting the gate of the control transistor 22 to the signal control line MUX, one signal input line SL can be electrically connected to two data lines Data, reducing the number of channels of the driving chip; and enabling the gates of multiple control transistors 22 connected to multiple data lines Data connected to sub-pixel units 201 of the same emission color to be connected to the same signal control line MUX, so that the sub-pixel units 201 of the same emission color are controlled by the same signal control line, and the sub-pixel units 201 of the same emission color can be charged simultaneously, avoiding vertical stripes caused by different charging times and improving the yield of the display panel.

[0038] Specifically, that some signal input lines SL are electrically connected to two data lines Data, and a control transistor 22 is provided between the signal input line SL and the corresponding two data lines Data means that when a signal input line SL is electrically connected to two data lines Data, at least one control transistor is provided between this signal input line SL and the two data lines Data to which it is electrically connected; for example, as Figure 5 shown, the signal input line SL includes a first input sub-line S1, the data line Data includes a first data sub-line Data1 and a second data sub-line Data2, and the control transistor 22 includes a first sub-transistor T11 and a ninth sub-transistor T31. The first input sub-line S1 is electrically connected to the first data sub-line Data1 and the second data sub-line Data2, a first sub-transistor T11 is provided between the first input sub-line S1 and the first data sub-line Data1, and a ninth sub-transistor T31 is provided between the first input sub-line S1 and the second data sub-line Data2.

[0039] Specifically, that the gates of multiple control transistors connected to multiple data lines Data connected to the sub-pixel units 201 of the same emission color are connected to the same signal control line means that the sub-pixel units 201 of the same emission color are connected to multiple data lines Data, these data lines Data are respectively connected to multiple control transistors 22, and the gates of these control transistors 22 are connected to the same signal control line MUX; for example, as Figure 5 shown, taking the first sub-pixel unit 201a as an example, the data line Data includes a first data sub-line Data1, a fourth data sub-line Data4, a seventh data sub-line Data7, and a tenth data sub-line Data10, and the control transistor 22 includes a first sub-transistor T11, a second sub-transistor T12, a third sub-transistor T13, and a fourth sub-transistor T14. Figure 5Among them, the four first sub-pixel units 201a will be respectively connected to the first data sub-line Data1, the fourth data sub-line Data4, the seventh data sub-line Data7, and the tenth data sub-line Data10. The first data sub-line Data1, the fourth data sub-line Data4, the seventh data sub-line Data7, and the tenth data sub-line Data10 will be respectively connected to the first sub-transistor T11, the second sub-transistor T12, the third sub-transistor T13, and the fourth sub-transistor T14. The gates of the first sub-transistor T11, the second sub-transistor T12, the third sub-transistor T13, and the fourth sub-transistor T14 are all connected to the first control sub-line MUX1.

[0040] Specifically, it can be understood that the gates of the multiple control transistors 22 connected to the multiple data lines Data connected to the sub-pixel units 201 of the same emission color are connected to the same signal control line MUX, which is based on the fact that the data lines are connected to the control transistors. For the case where the data line Data is directly connected to the signal input line SL, this feature does not exist. For example, as Figure 5 shown, the sub-pixel unit 201 includes a second sub-pixel unit 201b. The data line Data includes a second data sub-line Data2 and a fifth data sub-line Data5. The signal input line SL includes a second input sub-line S2 and a fourth input sub-line S4. The second data sub-line Data2 is directly connected to the second input sub-line S2, and the fifth data sub-line Data5 and the fourth input sub-line S4 are directly connected. The second data sub-line Data2 and the fifth data sub-line Data5 will not be connected to the control transistor, so there will be no control transistor connected to the second data sub-line and the fifth data sub-line Data5. However, it can be understood that since the data lines connected to the second sub-pixel unit 201b are directly connected to the signal input line, data can be input simultaneously, and there will be no problem of vertical stripes caused by different charging times of each second sub-pixel unit 201b.

[0041] Specifically, as Figures 4 to 8 shown, the display panel 2 further includes a source driver chip 31. The data input line SL is connected to the source driver chip 31. It can be understood that the source driver chip 31 includes multiple output channels, and each data input line SL can be connected to each output channel. In addition, since the number of channels of different source driver chips 31 is different and the resolutions of different display panels are different, there may be a situation where a display panel 2 requires a large number of channels and the number of channels of a single source driver chip 31 is insufficient. In this case, multiple source driver chips 31 can be set.

[0042] Specifically, for multiple control transistors connected to multiple data lines connected to the sub-pixel units of the same emission color, connecting their gates to the same signal control line can be achieved in the following two ways: within multiple sub-pixel units in the same row, for the sub-pixel units of the same emission color, the gates of multiple control transistors connected to multiple data lines are connected to the same signal control line; or within the display panel, for all sub-pixel units of the same emission color, the gates of multiple control transistors connected to multiple data lines are connected to the same signal control line.

[0043] In some embodiments, as Figures 4 to 8 shown, the sub-pixel unit 201 includes a first sub-pixel unit 201a, a second sub-pixel unit 201b, and a third sub-pixel unit 201c with different emission colors. The second sub-pixel unit 201b is disposed between the first sub-pixel unit 201a and the third sub-pixel unit 201c.

[0044] Among them, within one pixel unit 21, two of the data lines Data connected to the first sub-pixel unit 201a, the data lines Data connected to the second sub-pixel unit 201b, and the data lines Data connected to the third sub-pixel unit 201c are electrically connected to the same signal input line SL. By making two of the data lines Data connected to the first sub-pixel unit 201a, the data lines Data connected to the second sub-pixel unit 201b, and the data lines Data connected to the third sub-pixel unit 201c electrically connected to the same signal input line SL within one pixel unit, one signal input line SL can be electrically connected to two data lines Data, reducing the number of signal input lines, the number of required channels, the border of the display panel, and the cost.

[0045] Specifically, the emission colors of the first sub-pixel unit 201a, the second sub-pixel unit 201b, and the third sub-pixel unit 201c are red, green, and blue respectively, but the embodiments of the present application are not limited thereto. For example, the emission colors of the first sub-pixel unit 201a, the second sub-pixel unit 201b, and the third sub-pixel unit 201c are red, blue, and green respectively, or the emission colors of the first sub-pixel unit 201a, the second sub-pixel unit 201b, and the third sub-pixel unit 201c are green, blue, and red respectively, or the emission colors of the first sub-pixel unit 201a, the second sub-pixel unit 201b, and the third sub-pixel unit 201c are blue, green, and red respectively, or the emission colors of the first sub-pixel unit 201a, the second sub-pixel unit 201b, and the third sub-pixel unit 201c are blue, red, and green respectively.

[0046] Specifically, as Figure 5 、 Figure 6As shown, the data line Data connected to the first sub-pixel unit 201a and the data line Data connected to the third sub-pixel unit 201c can be electrically connected to the same signal input line SL; as Figure 7 , Figure 8 shown, the data line Data connected to the first sub-pixel unit 201a and the data line Data connected to the second sub-pixel unit 201b can be electrically connected to the same signal input line SL.

[0047] In some embodiments, as Figure 5 , Figure 6 shown, the data line Data connected to the first sub-pixel unit 201a and the data line Data connected to the third sub-pixel unit 201c are electrically connected to the same signal input line SL; the signal control line MUX includes a first control sub-line MUX1 and a second control sub-line MUX2;

[0048] Among them, the gates of the plurality of control transistors 22 connected to the data lines Data connected to the plurality of first sub-pixel units 201a are connected to the first control sub-line MUX1, and the gates of the plurality of control transistors 22 connected to the data lines Data connected to the plurality of third sub-pixel units 201c are connected to the second control sub-line MUX2. By connecting the gates of the plurality of control transistors 22 connected to the data lines Data connected to the plurality of first sub-pixel units 201a to the first control sub-line MUX1, the plurality of first sub-pixel units can be charged simultaneously, so that the charging times of the first sub-pixel units are close or even the same, avoiding the appearance of vertical stripes; by connecting the gates of the plurality of control transistors 22 connected to the data lines Data connected to the plurality of third sub-pixel units 201c to the second control sub-line MUX2, the plurality of third sub-pixel units can be charged simultaneously, so that the charging times of the third sub-pixel units are close or even the same, avoiding the appearance of vertical stripes.

[0049] In some embodiments, as Figure 5 shown, the data line Data connected to the second sub-pixel unit 201b is directly connected to the signal input line SL. By directly connecting the data line Data connected to the second sub-pixel unit to the signal input line SL, the second sub-pixel units can be charged simultaneously, so that the charging times of the second sub-pixel units are close or even the same, avoiding the appearance of vertical stripes.

[0050] Specifically, as Figures 5 to 8As shown, the data line Data includes a first data sub-line Data1, a second data sub-line Data2, a third data sub-line Data3, a fourth data sub-line Data4, a fifth data sub-line Data5, a sixth data sub-line Data6, a seventh data sub-line Data7, an eighth data sub-line Data8, a ninth data sub-line Data9, a tenth data sub-line Data10, an eleventh data sub-line Data11, and a twelfth data sub-line Data12;

[0051] The signal input line SL includes a first input sub-line S1, a second input sub-line S2, a third input sub-line S3, a fourth input sub-line S4, a fifth input sub-line S5, a sixth input sub-line S6, a seventh input sub-line S7, and an eighth input sub-line S8.

[0052] Specifically, as Figure 5 shown, the control transistor 22 includes a first sub-transistor T11, a second sub-transistor T12, a third sub-transistor T13, a fourth sub-transistor T14, a ninth sub-transistor T31, a tenth sub-transistor T32, an eleventh sub-transistor T33, and a twelfth sub-transistor T34; the signal control line MUX includes a first control sub-line MUX1 and a second control sub-line MUX2.

[0053] Specifically, as Figure 5 、 Figure 6 shown, it can be seen that four first sub-pixel units 201a are respectively connected to the first data sub-line Data1, the fourth data sub-line Data4, the seventh data sub-line Data7, and the tenth data sub-line Data10. The first data sub-line Data1, the fourth data sub-line Data4, the seventh data sub-line Data7, and the tenth data sub-line Data10 are respectively connected to the second electrodes of the first sub-transistor T11, the second sub-transistor T12, the third sub-transistor T13, and the fourth sub-transistor T14. The gates of the first sub-transistor T11, the second sub-transistor T12, the third sub-transistor T13, and the fourth sub-transistor T14 are all connected to the first control sub-line MUX1. The first electrodes of the first sub-transistor T11, the second sub-transistor T12, the third sub-transistor T13, and the fourth sub-transistor T14 are respectively connected to the first input sub-line S1, the third input sub-line S3, the fifth input sub-line S5, and the seventh input sub-line S7.

[0054] Specifically, as Figure 5 、 Figure 6As shown, it can be seen that four third sub-pixel units 201c are respectively connected to a third data sub-line Data3, a sixth data sub-line Data6, a ninth data sub-line Data9, and a twelfth data sub-line Data12. The third data sub-line Data3, the sixth data sub-line Data6, the ninth data sub-line Data9, and the twelfth data sub-line Data12 are respectively connected to the second electrodes of a ninth sub-transistor T31, a tenth sub-transistor T32, an eleventh sub-transistor T33, and a twelfth sub-transistor T34. The gates of the ninth sub-transistor T31, the tenth sub-transistor T32, the eleventh sub-transistor T33, and the twelfth sub-transistor T34 are all connected to a second control sub-line MUX2. The first electrodes of the ninth sub-transistor T31, the tenth sub-transistor T32, the eleventh sub-transistor T33, and the twelfth sub-transistor T34 are respectively connected to a first input sub-line S1, a third input sub-line S3, a fifth input sub-line S5, and a seventh input sub-line S7.

[0055] Specifically, as Figure 5 shown, it can be seen that four second sub-pixel units 201b are respectively connected to a second data sub-line Data2, a fifth data sub-line Data5, an eighth data sub-line Data8, and a twelfth data sub-line Data12. The second data sub-line Data2, the fifth data sub-line Data5, the eighth data sub-line Data8, and the twelfth data sub-line Data12 are respectively connected to a second input sub-line S2, a fourth input sub-line S4, a sixth input sub-line S6, and an eighth input sub-line S8.

[0056] Specifically, as Figure 5 、 Figure 6 shown, taking the display panel as a liquid crystal display panel as an example, in order to achieve signal inversion, the signals output by a signal input line SL and a data line Data will carry polarities. Figure 5 、 Figure 6 In , “+” is used to represent that the polarity of the output signal is positive, and “-” is used to represent that the polarity of the output signal is negative. However, the embodiments of the present application are not limited thereto. When the display panel is an OLED display panel, the signals output by the signal input line SL and the data line Data can be non-polar.

[0057] Specifically, as Figure 5 shown, it can be seen that through two signal control lines, it is possible to connect the gates of multiple control transistors connected to multiple data lines of sub-pixel units of the same emission color to the same signal control line. Compared with the design using three signal control lines, it saves space, and the charging time is longer than that of the design using three signal control lines.

[0058] Specifically, when the bandwidth of the source driver chip 31 is insufficient but the number of channels of the source driver chip 31 is sufficient, for example, when the display panel has a resolution of 16 inches, 2.8K, and a refresh rate of 300 Hz, there are 2880 columns of pixel units in the display panel. Correspondingly, the number of columns of sub-pixel units in the display panel is 2880 * 3 = 8640, that is, there are 8640 data lines. If the mux technology of the comparative display device shown in Figure 1 is adopted, the number of channels required is 8640 / 2 = 4320. For a source driver chip with 1440 channels, the number of source driver chips required is 4320 / 1440 = 3, that is, three source driver chips need to be used. However, due to the influence of the bandwidth, the bandwidth of the three source driver chips is insufficient, so 4 source driver chips need to be used. In the embodiment of the present application, within one pixel unit, the data lines connected to two sub-pixel units are electrically connected to the same signal input line, and the data line connected to the other sub-pixel unit is electrically connected to another signal input line. The number of channels required is 2880 + 2880 = 5760, and the number of source driver chips required is 5760 / 1440 = 4. Exactly 4 source driver chips can meet the above design. Therefore, the number of driver chips will not be increased.

[0059] In some embodiments, as shown in Figure 6 and Figure 9 , a control transistor 22 is provided between the data line Data connected to the second sub-pixel unit 201b and the signal input line SL. The signal control line MUX further includes a third control sub-line MUX3. The gates of the multiple control transistors 22 connected to the data lines Data connected to the multiple second sub-pixel units 201b are connected to the third control sub-line MUX3;

[0060] Among them, the phase of the signal of the third control sub-line MUX3 is the same as that of one of the first control sub-line MUX1 and the second control sub-line MUX2.

[0061] Specifically, the timing of the third control sub-line MUX3 is the same as that of one of the first control sub-line MUX1 and the second control sub-line MUX2.

[0062] Specifically, considering that among the sub-pixel units with different emission colors, for some sub-pixel units, a control transistor is provided between the data line and the signal input line they are connected to, while for some sub-pixel units, no control transistor is provided between the data line and the signal input line they are connected to. There will be certain differences in the signals due to different voltage drops, resulting in poor display uniformity. Therefore, although the data lines Data connected to the second sub-pixel units 201b and the signal input lines SL are in one-to-one correspondence, a control transistor is still provided between the data lines Data connected to the second sub-pixel units 201b and the signal input lines SL, so that the voltage drops of the signals received by the sub-pixel units with different emission colors are similar or even the same, improving the display uniformity.

[0063] Meanwhile, considering that adding signal control lines may lead to a shortened charging time, the phase of the signal on the third control sub-line can be made the same as that of the signal on one of the first control sub-line and the second control sub-line, so that the charging time will not be shortened.

[0064] Specifically, as Figure 6 shown, the control transistor 22 further includes a fifth control transistor T21, a sixth control transistor T22, a seventh control transistor T23, and an eighth control transistor T24, and the signal control line MUX further includes a third control sub-line MUX3.

[0065] Specifically, as Figure 6 shown, it can be seen that four second sub-pixel units 201b are respectively connected to a second data sub-line Data2, a fifth data sub-line Data5, an eighth data sub-line Data8, and a twelfth data sub-line Data12. The second data sub-line Data2, the fifth data sub-line Data5, the eighth data sub-line Data8, and the twelfth data sub-line Data12 are respectively connected to the second electrodes of the fifth control transistor T21, the sixth control transistor T22, the seventh control transistor T23, and the eighth control transistor T24. The first electrodes of the fifth control transistor T21, the sixth control transistor T22, the seventh control transistor T23, and the eighth control transistor T24 are respectively connected to a second input sub-line S2, a fourth input sub-line S4, a sixth input sub-line S6, and an eighth input sub-line S8; the gates of the fifth control transistor T21, the sixth control transistor T22, the seventh control transistor T23, and the eighth control transistor T24 are all connected to the third control sub-line MUX3.

[0066] Specifically, as Figure 3As shown, another contrast display device is provided. It can be seen that two multiplexing transistors 12 connected to the first data trace D1 to which the red sub-pixel 111 is connected and the fourth data trace D4 are both connected to the first multiplexing line MUX01. Two multiplexing transistors 12 connected to the second data trace D2 to which the green sub-pixel 112 is connected and the fifth data trace D5 are both connected to the second multiplexing line MUX02. Two multiplexing transistors 12 connected to the third data trace D3 to which the blue sub-pixel 113 is connected and the sixth data trace D6 are both connected to the third multiplexing line MUX03. However, in this contrast display device, the timings of the first multiplexing line MUX01, the second multiplexing line MUX02, and the third multiplexing line MUX03 are different, and each multiplexing line is turned on in sequence, resulting in a shorter charging time for each sub-pixel unit.

[0067] In the embodiments of the present application, to address this technical problem, by making the phase of the signal of the third control sub-line MUX3 the same as that of the signal of one of the first control sub-line MUX1 and the second control sub-line MUX2, although three signal control lines are used, the charging time of each sub-pixel unit is similar to or even the same as the charging time when two signal control lines are used.

[0068] In some embodiments, as Figure 5 、 Figure 6 shown, the polarities of the signals output from two adjacent data lines Data to two adjacent sub-pixel units 201 are opposite. By making the polarities of the signals output from two adjacent data lines Data to two adjacent sub-pixel units 201 opposite, when the display panel is a liquid crystal display panel, the display effect of the display panel can be improved.

[0069] In some embodiments, as Figure 5 、 Figure 6 shown, among every four adjacent signal input lines SL arranged, the polarities of the signals output from the first signal input line SL and the fourth signal input line SL are the same, the polarities of the signals output from the second signal input line SL and the third signal input line SL are the same, and the polarities of the signals output from the first signal input line SL and the second signal input line SL are opposite, so that the polarities of the signals output from adjacent data lines can be made opposite.

[0070] For example, four adjacent signal input lines SL include a first input sub-line S1, a second input sub-line S2, a third input sub-line S3, and a fourth input sub-line S4. It can be seen that the polarities of the signals output from the first input sub-line S1 and the fourth input sub-line S4 are positive, and the polarities of the signals output from the second input sub-line S2 and the third input sub-line S3 are negative.

[0071] Specifically, as Figure 5 、 Figure 6As shown, the polarities of the signals output by the first input sub-line S1, the fourth input sub-line S4, the fifth input sub-line S5, and the eighth input sub-line S8 are positive; the polarities of the signals output by the second input sub-line S2, the third input sub-line S3, the sixth input sub-line S6, and the seventh input sub-line S7 are negative;

[0072] The polarities of the signals output by the first data sub-line Data1, the third data sub-line Data3, the fifth data sub-line Data5, the seventh data sub-line Data7, the ninth data sub-line Data9, and the eleventh data sub-line Data11 are positive; the polarities of the signals output by the second data sub-line Data2, the fourth data sub-line Data4, the sixth data sub-line Data6, the eighth data sub-line Data8, the tenth data sub-line Data10, and the twelfth data sub-line Data12 are negative.

[0073] In some embodiments, such as Figure 7 , Figure 8 As shown, the data lines Data connected to the first sub-pixel unit 201a and the data lines Data connected to the second sub-pixel unit 201b are electrically connected to the same signal input line SL; the signal control line MUX includes a first control sub-line MUX1 and a second control sub-line MUX2;

[0074] Among them, the gates of the multiple control transistors 22 connected to the data lines Data connected to the multiple first sub-pixel units 201a are connected to the first control sub-line MUX1, and the gates of the multiple control transistors 22 connected to the data lines Data connected to the multiple second sub-pixel units 201b are connected to the second control sub-line MUX2. By connecting the gates of the multiple control transistors 22 connected to the data lines Data connected to the multiple first sub-pixel units 201a to the first control sub-line MUX1, the multiple first sub-pixel units can be charged simultaneously, making the charging times of the first sub-pixel units similar or even the same, avoiding the appearance of vertical stripes; by connecting the gates of the multiple control transistors 22 connected to the data lines Data connected to the multiple second sub-pixel units 201b to the second control sub-line MUX2, the multiple second sub-pixel units 201b can be charged simultaneously, making the charging times of the second sub-pixel units 201b similar or even the same, avoiding the appearance of vertical stripes.

[0075] Specifically, when the display panel does not need to perform polarity inversion, for example, when the display panel is a liquid crystal display panel but does not require polarity inversion, or when the display panel is an OLED display panel or other types of display panels that do not require polarity inversion, the data lines connected to the adjacent first sub-pixel unit and the second sub-pixel unit can be connected to the same signal input line.

[0076] In some embodiments, such asFigure 7 As shown, the data line Data connected to the third sub-pixel unit 201c is directly connected to the signal input line SL. By directly connecting the data line Data connected to the third sub-pixel unit 201c to the signal input line SL, the third sub-pixel units 201c can be charged simultaneously, making the charging times of the third sub-pixel units 201c similar or even the same, thus avoiding the appearance of vertical stripes.

[0077] Specifically, as Figure 7 shown, the control transistor 22 includes a first sub-transistor T11, a second sub-transistor T12, a third sub-transistor T13, a fourth sub-transistor T14, a fifth control transistor T21, a sixth control transistor T22, a seventh control transistor T23, and an eighth control transistor T24; the signal control line MUX includes a first control sub-line MUX1 and a second control sub-line MUX2.

[0078] Specifically, as Figure 7 、 Figure 8 shown, it can be seen that four first sub-pixel units 201a are respectively connected to a first data sub-line Data1, a fourth data sub-line Data4, a seventh data sub-line Data7, and a tenth data sub-line Data10. The first data sub-line Data1, the fourth data sub-line Data4, the seventh data sub-line Data7, and the tenth data sub-line Data10 are respectively connected to the second electrodes of the first sub-transistor T11, the second sub-transistor T12, the third sub-transistor T13, and the fourth sub-transistor T14. The gates of the first sub-transistor T11, the second sub-transistor T12, the third sub-transistor T13, and the fourth sub-transistor T14 are all connected to the first control sub-line MUX1. The first electrodes of the first sub-transistor T11, the second sub-transistor T12, the third sub-transistor T13, and the fourth sub-transistor T14 are respectively connected to a first input sub-line S1, a third input sub-line S3, a fifth input sub-line S5, and a seventh input sub-line S7.

[0079] Specifically, as Figure 7 、 Figure 8As shown, it can be seen that four second sub-pixel units 201b are respectively connected to the second data sub-line Data2, the fifth data sub-line Data5, the eighth data sub-line Data8, and the twelfth data sub-line Data12. The second data sub-line Data2, the fifth data sub-line Data5, the eighth data sub-line Data8, and the twelfth data sub-line Data12 are respectively connected to the second electrodes of the fifth control transistor T21, the sixth control transistor T22, the seventh control transistor T23, and the eighth control transistor T24. The first electrodes of the fifth control transistor T21, the sixth control transistor T22, the seventh control transistor T23, and the eighth control transistor T24 are respectively connected to the first input sub-line S1, the third input sub-line S3, the fifth input sub-line S5, and the seventh input sub-line S7. The gates of the fifth control transistor T21, the sixth control transistor T22, the seventh control transistor T23, and the eighth control transistor T24 are all connected to the second control sub-line MUX2.

[0080] Specifically, as Figure 7 shown, it can be seen that four third sub-pixel units 201c are respectively connected to the third data sub-line Data3, the sixth data sub-line Data6, the ninth data sub-line Data9, and the twelfth data sub-line Data12. The third data sub-line Data3, the sixth data sub-line Data6, the ninth data sub-line Data9, and the twelfth data sub-line Data12 are respectively connected to the second input sub-line S2, the fourth input sub-line S4, the sixth input sub-line S6, and the eighth input sub-line S8.

[0081] Specifically, as Figure 7 shown, it can be seen that through two signal control lines, it is possible to connect the gates of multiple control transistors connected to multiple data lines of sub-pixel units of the same emission color to the same signal control line. Compared with the design using three signal control lines, space is saved, and the charging time is longer than that of the design using three signal control lines.

[0082] In some embodiments, as Figure 8 、 Figure 9 shown, a control transistor 22 is provided between the data line Data connected to the third sub-pixel unit 201c and the signal input line SL. The signal control line MUX further includes a third control sub-line MUX3. The gates of the multiple control transistors 22 connected to the data lines Data connected to the multiple third sub-pixel units 201c are connected to the third control sub-line MUX3;

[0083] wherein, the phase of the signal of the third control sub-line MUX3 is the same as that of one of the first control sub-line MUX1 and the second control sub-line MUX2.

[0084] Specifically, the timing of the third control sub-line MUX3 is the same as that of one of the first control sub-line MUX1 and the second control sub-line MUX2.

[0085] Specifically, considering that among the sub-pixel units of different emission colors, control transistors are provided between the data lines and the signal input lines connected to some sub-pixel units, while no control transistors are provided between the data lines and the signal input lines connected to some other sub-pixel units, there will be certain differences in the signals due to different voltage drops, resulting in poor display uniformity. Therefore, although the data lines Data connected to the third sub-pixel unit 201c are in one-to-one correspondence with the signal input lines SL, control transistors are still provided between the data lines Data connected to the third sub-pixel unit 201c and the signal input lines SL, so that the voltage drops of the signals received by the sub-pixel units of different emission colors are similar or even the same, improving the display uniformity.

[0086] At the same time, considering that increasing the signal control lines may lead to a shortened charging time, the phase of the signal of the third control sub-line can be made the same as that of one of the first control sub-line and the second control sub-line, so as not to shorten the charging time.

[0087] Specifically, as Figure 8 shown, the control transistor 22 further includes a ninth sub-transistor T31, a tenth sub-transistor T32, an eleventh sub-transistor T33, and a twelfth sub-transistor T34; the signal control line MUX further includes a third control sub-line MUX3.

[0088] Specifically, as Figure 8 shown, it can be seen that four third sub-pixel units 201c are respectively connected to a third data sub-line Data3, a sixth data sub-line Data6, a ninth data sub-line Data9, and a twelfth data sub-line Data12. The third data sub-line Data3, the sixth data sub-line Data6, the ninth data sub-line Data9, and the twelfth data sub-line Data12 are respectively connected to the second electrodes of the ninth sub-transistor T31, the tenth sub-transistor T32, the eleventh sub-transistor T33, and the twelfth sub-transistor T34. The gates of the ninth sub-transistor T31, the tenth sub-transistor T32, the eleventh sub-transistor T33, and the twelfth sub-transistor T34 are all connected to the third control sub-line MUX3. The first electrodes of the ninth sub-transistor T31, the tenth sub-transistor T32, the eleventh sub-transistor T33, and the twelfth sub-transistor T34 are respectively connected to a second input sub-line S2, a fourth input sub-line S4, a sixth input sub-line S6, and an eighth input sub-line S8.

[0089] Specifically, as Figure 9As shown, the timing of the third control sub-line MUX3 is the same as that of the first control sub-line MUX1, and the timing of the third control sub-line MUX3 is different from that of the second control sub-line MUX2; however, the embodiments of the present application are not limited thereto, and the timing of the third control sub-line MUX3 can be made the same as that of the second control sub-line MUX2, and the timing of the third control sub-line MUX3 can be different from that of the first control sub-line MUX1.

[0090] Specifically, the display panel can be a liquid crystal display panel.

[0091] Specifically, the display panel can be an OLED display panel.

[0092] Specifically, as Figure 4 shown, the display panel further includes a scan line Gate and a driving transistor T0. The scan line Gate includes a first scan sub-line Gate1, a second scan sub-line Gate2, a third scan sub-line Gate3, and a fourth scan sub-line Gate4. Each sub-pixel unit is connected to a data line and a scan line through a driving transistor.

[0093] Specifically, as Figure 4 shown, Figure 4 Taking the example that the light-emitting colors of the sub-pixel units in the same column are the same, the sub-pixel units in the same column are connected to the same data line, and the sub-pixel units in the same row are connected to the same row scan line for illustration, but the embodiments of the present application are not limited thereto. For example, the sub-pixel units in the same column can be connected to two adjacent data lines, and the polarities of the output signals of the two adjacent data lines can be opposite. When the display panel is a liquid crystal display panel, dot inversion can be achieved.

[0094] Specifically, the above embodiments have described the display panel in detail from aspects such as the pixel design of the display panel, the connection relationship of the signal control lines and control transistors of the display panel, and the connection relationship of the data lines and signal input lines. It can be understood that when there is no conflict among the embodiments, the embodiments can be combined. For example, the polarities of the signals output from two adjacent data lines to adjacent sub-pixel units are opposite, and the display panel is a liquid crystal display panel.

[0095] At the same time, the embodiments of the present application provide a display device, and the display device includes the display panel as described in any one of the above embodiments.

[0096] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0097] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0098] Among the embodiments, implementation manners and related technical features of the present application, they can be combined and replaced with each other without conflict.

[0099] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. However, any simple modifications, equivalent changes and decorations made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises a plurality of pixel units arranged in an array, each of the pixel units comprising a plurality of sub-pixel units of different luminous colors; the display panel comprises: Multiple data lines; A plurality of signal input lines, some of which are electrically connected to two of the data lines, and a control transistor is provided between the signal input line and the corresponding two data lines, and a gate of the control transistor is connected to the signal control line; Each of the sub-pixel units is connected to a data line, and gates of a plurality of control transistors connected to a plurality of data lines connected to the sub-pixel units of the same luminous color are connected to the same signal control line.

2. The display panel according to claim 1, characterized in that: The sub-pixel units include a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit of different luminous colors, and the second sub-pixel unit is arranged between the first sub-pixel unit and the third sub-pixel unit; Wherein, in one of the pixel units, two of the data line connected to the first sub-pixel unit, the data line connected to the second sub-pixel unit, and the data line connected to the third sub-pixel unit are electrically connected to the same signal input line.

3. The display panel according to claim 2, characterized in that: The data line connected to the first sub-pixel unit and the data line connected to the third sub-pixel unit are electrically connected to the same signal input line; The signal control line includes a first control sub-line and a second control sub-line; Among them, the gates of multiple control transistors connected to the data lines connected to the multiple first sub-pixel units are connected to the first control sub-line, and the gates of multiple control transistors connected to the data lines connected to the multiple third sub-pixel units are connected to the second control sub-line.

4. The display panel according to claim 3, characterized in that: The data line connected to the second sub-pixel unit is directly connected to the signal input line.

5. The display panel according to claim 3, characterized in that: A control transistor is provided between the data line connected to the second sub-pixel unit and the signal input line, the signal control line further comprises a third control sub-line, and gates of a plurality of control transistors connected to the data lines connected to a plurality of the second sub-pixel units are connected to the third control sub-line; The phase of the signal of the third control sub-line is the same as that of the signal of one of the first control sub-line and the second control sub-line.

6. The display panel according to any one of claims 3 to 5, characterized in that: The polarities of the signals output by the two adjacent data lines to the adjacent sub-pixel units are opposite.

7. The display panel according to any one of claims 3 to 5, characterized in that: Among every four adjacent signal input lines, the polarity of the signals output by the first signal input line and the fourth signal input line is the same, the polarity of the signals output by the second signal input line and the third signal input line is the same, and the polarity of the signals output by the first signal input line and the second signal input line is opposite.

8. The display panel according to claim 2, characterized in that: The data line connected to the first sub-pixel unit and the data line connected to the second sub-pixel unit are electrically connected to the same signal input line; The signal control line includes a first control sub-line and a second control sub-line; The gates of the control transistors connected to the data lines connected to the first sub-pixel units are connected to the first control sub-line, and the gates of the control transistors connected to the data lines connected to the second sub-pixel units are connected to the second control sub-line.

9. The display panel according to claim 8, characterized in that: The data line connected to the third sub-pixel unit is directly connected to the signal input line.

10. The display panel according to claim 8, characterized in that: A control transistor is provided between the data line connected to the third sub-pixel unit and the signal input line, the signal control line further comprises a third control sub-line, and the gates of the plurality of control transistors connected to the data lines connected to the plurality of third sub-pixel units are connected to the third control sub-line; The phase of the signal of the third control sub-line is the same as that of the signal of one of the first control sub-line and the second control sub-line.

11. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 10.

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