Impedance calibration circuit, semiconductor memory device and memory system

Abstract

The invention relates to an impedance calibration circuit, a semiconductor memory device and a memory system. The impedance calibration circuit includes a code generation circuit and a code update control circuit. The code generation circuit generates a first impedance code set by performing an impedance adjustment operation within an activation period of a data output enable signal generated in response to a read command. Before the data output enable signal is deactivated, the code update control circuit prevents an update of a second impedance code set to the first impedance code set, where the second impedance code set is used for impedance adjustment of the transmission circuit.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Application No. 10 - 2023 - 0176608, filed with the Korean Intellectual Property Office on December 7, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments generally relate to a semiconductor circuit including, but not limited to, an impedance calibration circuit, a semiconductor memory device having an impedance calibration function, and a memory system including the semiconductor memory device providing the impedance calibration function. Background Art

[0004] Recently, electronic systems have become faster and faster, and the data transfer speed between semiconductor circuits constituting the system has also become faster. For such high - speed data transfer, it has become increasingly important to match the impedance of the data transfer path and the output impedance of the output circuit. Therefore, the output impedance of the semiconductor circuit is adjusted to match the impedance of the transfer path, and an impedance calibration circuit is used for this purpose.

[0005] The impedance calibration circuit performs an impedance adjustment operation according to an externally input impedance adjustment command ZQC. The impedance adjustment command ZQC can be divided into a long - term impedance adjustment command ZQCL: ZQ Calibration Long and a short - term impedance adjustment command ZQCS: ZQ Calibration Short, and the two are distinguished by a fixed address sequence Ax. ZQCL is a command for performing an impedance adjustment operation that takes a longer time than the impedance adjustment operation performed in response to the command ZQCS.

[0006] Reference Figure 1 , a conventional semiconductor memory device includes a boot - up (BOOT - UP), ZQCL, and multiple training operations TRN in an initial training sequence. After the initial training sequence, the data output operation according to a read command RD and the short - term impedance adjustment operation according to a short - term impedance adjustment command ZQCS are sequentially repeated. Since the data output operation according to the read command RD and the short - term impedance adjustment operation according to the short - term impedance adjustment command ZQCS are sequentially executed, there is a problem of reduced timing margin during the operation of the semiconductor memory device. Summary of the Invention

[0007] In an embodiment, the impedance calibration circuit may include a code generation circuit and a code update control circuit. The code generation circuit may be configured to generate a first impedance code set by performing an impedance adjustment operation during an activation period of a data output enable signal generated in response to a read command. The code update control circuit may be configured to prevent updating a second impedance code set to the first impedance code set before the data output enable signal is deactivated, where the second impedance code set is used for impedance adjustment of a transmission circuit.

[0008] In an embodiment, a semiconductor memory device may include a memory area, a transmission circuit, an impedance calibration circuit, and a control circuit. The transmission circuit may be configured to adjust an impedance according to a second impedance code set, and may be configured to output data from the memory area during an activation period of a data output enable signal. The impedance calibration circuit may be configured to perform an impedance adjustment operation during the activation period of the data output enable signal to generate a first impedance code set, and may be configured to prevent updating the second impedance code set to the first impedance code set before the data output enable signal is deactivated. The control circuit may be configured to activate the data output enable signal in response to a read command.

[0009] In an embodiment, a memory system may include a semiconductor memory device and a controller. The semiconductor memory device may include a transmission circuit, which is configured to adjust an impedance according to a second impedance code set, may perform an impedance adjustment operation during a data output period of the transmission circuit in response to a read command to generate a first impedance code set, and may prevent a code update operation from updating the second impedance code set to the first impedance code set before the data output period is completed. The controller may be configured to provide an impedance control mode setting command to the semiconductor memory device to change the timing of the code update operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a timing diagram showing a known impedance adjustment sequence.

[0011] Figure 2 is a diagram showing an impedance calibration circuit according to an embodiment of the present disclosure.

[0012] Figure 3 is a diagram showing a code generation circuit according to an embodiment of the present disclosure.

[0013] Figure 4 is a diagram showing a code update control circuit according to an embodiment of the present disclosure.

[0014] Figure 5 is a diagram showing an update logic circuit according to an embodiment of the present disclosure.

[0015] Figure 6Is a diagram showing an update logic circuit according to an embodiment of the present disclosure.

[0016] Figure 7 Is a diagram showing an update timing detection circuit according to an embodiment of the present disclosure.

[0017] Figure 8 Is a diagram showing an update logic circuit according to an embodiment of the present disclosure.

[0018] Figure 9 Is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0019] Figure 10 Is a diagram showing a memory system according to an embodiment of the present disclosure.

[0020] Figures 11 to 15 Is a timing diagram showing an impedance adjustment sequence according to one or more embodiments of the present disclosure. Detailed Description

[0021] Various embodiments of the present disclosure can increase the timing margin of the operation of a semiconductor memory device and improve the control efficiency of a memory system. Since a controller operating in relation to a semiconductor memory device knows and participates in information related to impedance adjustment of the semiconductor memory device, the control efficiency of the memory system is improved compared to a system in which the controller does not know and participate in information related to impedance adjustment of the semiconductor memory device.

[0022] One or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0023] Figure 2 Is a diagram showing an impedance calibration circuit 1 according to an embodiment of the present disclosure.

[0024] Refer to Figure 2 , an impedance calibration circuit 1 according to an embodiment of the present disclosure includes a code generation circuit 10 and a code update control circuit 30.

[0025] The code generation circuit 10 is connected to a reference resistor RZQ external to a semiconductor memory device including the impedance calibration circuit 1. The code generation circuit 10 receives a plurality of control signals CTRL as inputs and outputs a first impedance code set ZQPUCD, ZQPDCD. The code generation circuit 10 generates the first impedance code set ZQPUCD, ZQPDCD by performing an impedance adjustment operation during a period in which data is output from a transmission circuit (e.g., Figure 4 TX shown) in response to at least one of the plurality of control signals CTRL. The plurality of control signals CTRL includes a data output enable signal (e.g., ENDOUT), which identifies a data output period in response to a read command.

[0026] The code update control circuit 30 receives a plurality of control signals CTRL and a first impedance code set ZQPUCD, ZQPDCD as inputs, and outputs a second impedance code set TXPUCD, TXPDCD. In response to at least one of the plurality of control signals CTRL, the code update control circuit 30 performs a code update operation after the transmission circuit completes data output to update a previous code value (e.g., the second impedance code set TXPUCD, TXPDCD) to a current code value (e.g., the first impedance code set ZQPUCD, ZQPDCD). In response to at least one of the plurality of control signals CTRL, the code update control circuit 30 prevents the code update operation until the transmission circuit completes data output. The second impedance code set TXPUCD, TXPDCD is applied to adjust the impedance of the transmission circuit (e.g., Figure 4 TX in).

[0027] ZQPUCD is referred to as the first impedance pull-up code, ZQPDCD is referred to as the first impedance pull-down code, TXPUCD is referred to as the second impedance pull-up code, and TXPDCD is referred to as the second impedance pull-down code. The first impedance pull-up code ZQPUCD, the first impedance pull-down code ZQPDCD, the second impedance pull-up code TXPUCD, and the second impedance pull-down code TXPDCD may each include a plurality of bits.

[0028] Figure 3 is a diagram showing an embodiment of the code generation circuit 10 as shown, for example, in Figure 2 as shown.

[0029] Referring to Figure 3 , the code generation circuit 10 receives a data output enable signal ENDOUT and a long-term impedance adjustment enable signal ENZQCL among the plurality of control signals CTRL. The data output enable signal ENDOUT identifies a data output period in response to a read command, for example. The long-term impedance adjustment enable signal ENZQCL is generated according to a long-term impedance adjustment command ZQCL and identifies an impedance adjustment period.

[0030] The code generation circuit 10 includes a first replication circuit RPC1 11, a first code adjustment circuit 12, a second replication circuit RPC2 13, a third replication circuit RPC3 14, a second code adjustment circuit 15, an oscillator OSC 16, a logic gate 17, and a reference voltage generation circuit VREF GEN 20.

[0031] The first replication circuit 11 is coupled between a power supply terminal and a first node ND1. A reference resistor RZQ is connected to the first node ND1 through a pad 21. The impedance of the first replication circuit 11 is adjusted according to the first impedance pull-up code ZQPUCD. The first replication circuit 11, for example, replicates as Figure 4configured by the pull-up driver of the transmission circuit TX shown.

[0032] The first code adjustment circuit 12 adjusts the value of the first impedance pull-up code ZQPUCD according to the comparison result between the voltage at the first node ND1 and the first reference voltage VREF1. The first code adjustment circuit 12 includes a comparator 12-1 and a counter CNTR12-2. During the activation period of the impedance adjustment enable signal ENZQ, the comparator 12-1 outputs a first comparison signal CMP1, which is the comparison result between the voltage at the first node ND1 and the first reference voltage VREF1. The comparator 12-1 determines that the bang-bang state of the first comparison signal CMP1 is lock-completed and stops the fluctuation of the first impedance pull-up code ZQPUCD. The bang-bang state includes, for example, a state including repeated "1" and "0". The counter 12-2 increases and decreases the value of the first impedance pull-up code ZQPUCD according to the counting clock signal CLKZQ to match the level of the first comparison signal CMP1.

[0033] The second replication circuit 13 is connected between the power supply terminal and the second node ND2. The second replication circuit 13 has an impedance adjusted according to the first impedance pull-up code ZQPUCD. The second replication circuit 13 can be configured substantially similarly to the first replication circuit 11.

[0034] The third replication circuit 14 is connected between the second node ND2 and the ground terminal. The third replication circuit 14 has an impedance adjusted according to the first impedance pull-down code ZQPDCD. The third replication circuit 14 is configured, for example, by replicating the pull-down driver of the transmission circuit TX as Figure 4 configured by the pull-up driver of the transmission circuit TX shown.

[0035] The second code adjustment circuit 15 adjusts the value of the first impedance pull-down code ZQPDCD according to the comparison result between the voltage at the second node ND2 and the second reference voltage VREF2. The second code adjustment circuit 15 includes a comparator 15-1 and a counter CNTR15-2. During the activation period of the impedance adjustment enable signal ENZQ, the comparator 15-1 outputs a second comparison signal CMP2, which is the comparison result between the voltage at the second node ND2 and the second reference voltage VREF2. The comparator 15-1 determines that the bang-bang state of the second comparison signal CMP2 is lock-completed and stops the fluctuation of the first impedance pull-down code ZQPDCD. The counter 15-2 increases and decreases the value of the first impedance pull-down code ZQPDCD according to the counting clock signal CLKZQ to match the level of the second comparison signal CMP2.

[0036] The oscillator (OSC) 16 generates a counting clock signal CLKZQ during the activation period of the impedance adjustment enable signal ENZQ.

[0037] The logic gate 17 outputs an impedance adjustment enable signal ENZQ, which is the result of a logical OR operation on the data output enable signal ENDOUT and the long-term impedance adjustment enable signal ENZQCL.

[0038] The reference voltage generation circuit 20 generates a first reference voltage VREF1 and a second reference voltage VREF2.

[0039] The operation of the code generation circuit 10 is described as follows.

[0040] The reference resistor RZQ is configured outside the semiconductor memory device so as to maintain a constant resistance value regardless of the internal operating environment of the semiconductor memory device. Operations can be performed to adjust the impedances of the first copy circuit 11 and the second copy circuit 13 using the resistance value of the reference resistor RZQ as a target value. The impedance adjustment enable signal ENZQ is activated during at least one of the activation period of the data output enable signal ENDOUT and the activation period of the long-term impedance adjustment enable signal ENZQCL. During the activation period of the impedance adjustment enable signal ENZQ, a counting clock signal CLKZQ is generated, and the first code adjustment circuit 12 and the second code adjustment circuit 15 are activated.

[0041] The first code adjustment circuit 12 compares the voltage of the first node ND1 with the first reference voltage VREF1. When the comparison result is within the tolerance range, the adjustment of the first impedance pull-up code ZQPUCD is completed.

[0042] The second code adjustment circuit 15 compares the voltage of the second node ND2 with the second reference voltage VREF2. When the comparison result is within the tolerance range, the adjustment of the first impedance pull-down code ZQPDCD is completed.

[0043] When the transmission circuit performs data output, that is, during the activation period of the data output enable signal ENDOUT, the code generation circuit 10 completes the adjustment of the first impedance code set ZQPUCD, ZQPDCD.

[0044] The activation / deactivation of signals (such as the data output enable signal ENDOUT and the impedance adjustment enable signal ENZQ) can be high level / low level, or low level / high level. For the sake of facilitating the description of the examples described herein, the activation of a signal is high level, while the deactivation of a signal is low level. Similarly, the activation period refers to the period during which the signal is activated at high level.

[0045] Figure 4 is a diagram showing an embodiment of the code update control circuit 30 as shown, for example, Figure 2 as shown.

[0046] Reference Figure 4 As shown in Figure 4 , the code update control circuit 30 includes a latch circuit 31 and an update logic circuit 40.

[0047] The latch circuit 31 responds to the activation of the update enable signal ENUDT and performs a code update operation by referring to the change of the values of the second impedance code set TXPUCD and TXPDCD to the values of the first impedance code set ZQPUCD and ZQPDCD. The latch circuit 31 includes a first latch LT1 32 and a second latch LT2 33. The first latch 32 performs a code update operation by providing the first impedance pull-up code ZQPUCD as the second impedance pull-up code TXPUCD to the pull-up driver 42 of the transmission circuit TX in response to the activation of the update enable signal ENUDT. The second latch 33 performs a code update operation by providing the first impedance pull-down code ZQPDCD as the second impedance pull-down code TXPDCD to the pull-down driver 44 of the transmission circuit TX in response to the activation of the update enable signal ENUDT.

[0048] The update logic circuit 40 receives a plurality of control signals CTRL as inputs and outputs an update enable signal ENUDT. The update logic circuit 40 can be configured in various ways, and Examples 40A, 40B, and 40C are described with reference to Figures 5 to 8 FIG. Figures 5 to 8 shows an example of the update logic circuit 40A according to an embodiment of the present disclosure.

[0049] Figure 5 FIG. Figure 5 is a diagram showing the update logic circuit 40A according to an embodiment of the present disclosure.

[0050] Reference Figure 5 As shown in Figure 5 , the update logic circuit 40A receives the data output enable signal ENDOUT and the long-term impedance adjustment enable signal ENZQCL among the plurality of control signals CTRL and outputs an update enable signal ENUDT. The update logic circuit 40A is configured to activate the update enable signal ENUDT when the data output enable signal ENDOUT is deactivated. The update logic circuit 40A is configured to activate the update enable signal ENUDT when the long-term impedance adjustment enable signal ENZQCL is deactivated.

[0051] The update logic circuit 40A includes a first signal generation circuit SG1 41, a second signal generation circuit SG2 42, and a logic gate 43.

[0052] The first signal generation circuit 41 generates a first preliminary signal PREA1 in the form of a pulse in response to the deactivation of the data output enable signal ENDOUT.

[0053] The second signal generation circuit 42 generates a second preliminary signal PREA2 in the form of a pulse in response to the deactivation of the long-term impedance adjustment enable signal ENZQCL.

[0054] The logic gate 43 outputs an update enable signal ENUDT, which is the result of a logical OR operation on the first preliminary signal PREA1 and the second preliminary signal PREA2.

[0055] Figure 6 FIG. is a diagram showing an update logic circuit 40B according to an embodiment of the present disclosure.

[0056] Referring to Figure 6 , the update logic circuit 40B receives a first impedance code set ZQPUCD, ZQPDCD and a second impedance code set TXPUCD, TXPDCD, receives a data output enable signal ENDOUT, a long-term impedance adjustment enable signal ENZQCL, a code update command ZQUDT, a control mode setting signal INF_ZQC among a plurality of control signals CTRL, and outputs an update enable signal ENUDT.

[0057] The update logic circuit 40B is configured to compare a previous code value (e.g., the value of the second impedance code set TXPUCD, TXPDCD) and a current code value (e.g., the value of the first impedance code set ZQPUCD, ZQPDCD) when the data output enable signal ENDOUT is disabled, and activate the update enable signal ENUDT when the value of the second impedance code set TXPUCD, TXPDCD does not match the value of the first impedance code set ZQPUCD, ZQPDCD. For example, when TXPUCD does not match ZQPUCD and when TXPDCD does not match ZQPDCD, the update enable signal ENUDT is activated. The update logic circuit 40B is configured to activate the update enable signal ENUDT when the long-term impedance adjustment enable signal ENZQCL is disabled.

[0058] The update logic circuit 40B includes a code operation circuit 50, an update timing detection circuit DET_UDTT 54, a signal generation circuit SG 56, a first logic gate 55, and a second logic gate 57.

[0059] The code operation circuit 50 compares the values of the first impedance code set ZQPUCD, ZQPDCD with the values of the second impedance code set TXPUCD, TXPDCD to determine whether the values match, and outputs the comparison result as an update determination signal CDV1. The code operation circuit 50 includes a plurality of logic gates 51, 52, 53. The plurality of first logic gates 51 output the result of a logical XOR (exclusive OR) operation on the first impedance pull-up code ZQPUCD and the second impedance pull-up code TXPUCD. The plurality of second logic gates 52 output the result of a logical XOR operation on the first impedance pull-down code ZQPDCD and the second impedance pull-down code TXPDCD. In Figure 6In the example, the values of the first impedance code set and the second impedance code set each include 3 bits. Therefore, the plurality of first logic gates 51 include three XOR gates 51, and the plurality of second logic gates 52 include three XOR gates 52, as Figure 6 indicated by the three dots above each XOR gate 51, 52 in

[0060] The update timing detection circuit 54 receives the data output enable signal ENDOUT, the code update command ZQUDT, and the control mode setting signal INF_ZQC as inputs, and outputs an update timing signal UDTT.

[0061] The first logic gate 55 outputs a first preliminary signal PREB1, which is the result of a logical AND operation on the update determination signal CDV1 and the update timing signal UDTT.

[0062] The signal generation circuit 56 generates a second preliminary signal PREB2 in the form of a pulse in response to the deactivation of the long-term impedance adjustment enable signal ENZQCL.

[0063] The second logic gate 57 outputs an update enable signal ENUDT, which is the result of a logical OR operation on the first preliminary signal PREB1 and the second preliminary signal PREB2.

[0064] Figure 7 is a diagram showing an embodiment of an update timing detection circuit such as Figure 6 shown.

[0065] Referring to Figure 7 , the update timing detection circuit 54 includes a first signal generation circuit SG1 54-1, a second signal generation circuit SG2 54-2, and a multiplexer 54-3.

[0066] The first signal generation circuit 54-1 generates a pulse signal in response to receiving the code update command ZQUDT.

[0067] The second signal generation circuit 54-2 generates a pulse signal in response to the deactivation of the data output enable signal ENDOUT.

[0068] The multiplexer 54-3 outputs an update timing signal UDTT according to the control mode setting signal INF_ZQC, and the update timing signal UDTT is the output of the first signal generation circuit 54-1 or the output of the second signal generation circuit 54-2.

[0069] The control mode setting signal INF_ZQC is a signal that identifies one of the first impedance control mode ZQMODE1 and the second impedance control mode ZQMODE2 as the operation mode of the semiconductor memory device. In the first impedance control mode ZQMODE1, the semiconductor memory device performs a code update operation. In the second impedance control mode ZQMODE2, a code update operation is performed according to a command received from outside the semiconductor memory device. The value of the control mode setting signal INF_ZQC is established according to an impedance control mode setting command provided from outside the semiconductor memory device. When the control mode setting signal INF_ZQC is "0" (low level), the operation mode of the semiconductor memory device is the first impedance control mode ZQMODE1. When the control mode setting signal INF_ZQC is "1" (high level), the operation mode of the semiconductor memory device is the second impedance control mode ZQMODE2.

[0070] The multiplexer 54-3 outputs the output of the second signal generation circuit 54-2 as the update timing signal UDTT when the control mode setting signal INF_ZQC is at a low level, and outputs the output of the first signal generation circuit 54-1 as the update timing signal UDTT when the control mode setting signal INF_ZQC is at a high level.

[0071] Figure 8 is a diagram showing an update logic circuit 40C according to an embodiment of the present disclosure.

[0072] Referring to Figure 8 , the update logic circuit 40C receives a selection signal SEL, a reference code REFCD, a first impedance code set ZQPUCD, ZQPDCD, and a second impedance code set TXPUCD, TXPDCD, receives a data output enable signal ENDOUT, a long-term impedance adjustment enable signal ENZQCL, a code update command ZQUDT, a control mode setting signal INF_ZQC among a plurality of control signals CTRL, and outputs an update enable signal ENUDT.

[0073] The update logic circuit 40C is configured to activate the update enable signal ENUDT when the data output enable signal ENDOUT is deactivated and the difference between the values of the first impedance code set ZQPUCD, ZQPDCD and the second impedance code set TXPUCD, TXPDCD is greater than a target value. The update logic circuit 40C is configured to enable the update enable signal ENUDT when the long-term impedance adjustment enable signal ENZQCL is deactivated.

[0074] The update logic circuit 40C includes a code operation circuit 60, an update timing detection circuit DET_UDTT 67, a signal generation circuit SG 69, a first logic gate 68, and a second logic gate 70.

[0075] The code operation circuit 60 calculates the difference between the first impedance code sets ZQPUCD and ZQPDCD and the second impedance code sets TXPUCD and TXPDCD, and outputs an update determination signal CDV2, which is the result of determining whether the difference is greater than a target value. The code operation circuit 60 includes a first subtractor SUBT1 61, a second subtractor SUBT2 62, a multiplexer 63, a first digital-to-analog converter DAC1 64, a second digital-to-analog converter DAC2 65, and a comparator 66. The first subtractor 61 detects the difference between the first impedance pull-up code ZQPUCD and the second impedance pull-up code TXPUCD. The second subtractor 62 detects the difference between the first impedance pull-down code ZQPDCD and the second impedance pull-down code TXPDCD. The multiplexer 63 selects and outputs one of the outputs of the first subtractor 61 and the second subtractor 62 according to a selection signal SEL. The first digital-to-analog converter 64 converts the output of the multiplexer 63 into an analog voltage and outputs the resulting analog voltage to the comparator 66. The second digital-to-analog converter 65 converts a reference code REFCD into an analog voltage to generate a target value VTGT. The comparator 66 outputs an update determination signal CDV2, which is the result of comparing the output of the first digital-to-analog converter 64 with the target value VTGT. When the voltage level of the output of the first digital-to-analog converter 64 is higher than the target value VTGT, the comparator 66 activates the update determination signal CDV2.

[0076] The update timing detection circuit 67 receives a data output enable signal ENDOUT, a code update command ZQUDT, and a control mode setting signal INF_ZQC as inputs, and outputs an update timing signal UDTT. The update timing detection circuit 67 can be configured similarly to the update timing detection circuit 54 Figure 7 described above.

[0077] The first logic gate 68 outputs a first preliminary signal PREC1, which is the result of performing a logical AND operation on the update determination signal CDV2 and the update timing signal UDTT.

[0078] The signal generation circuit 69 generates a second preliminary signal PREC2 in the form of a pulse in response to the deactivation of the long-term impedance adjustment enable signal ENZQCL.

[0079] The second logic gate 70 outputs an update enable signal ENUDT, which is the result of performing a logical OR operation on the first preliminary signal PREC1 and the second preliminary signal PREC2.

[0080] Figure 9 is a diagram showing a semiconductor memory device 100 according to an embodiment of the present disclosure.

[0081] Referring to Figure 9 , the semiconductor memory device 100 includes a memory region or memory bank having a plurality of planes Plane 1 to Plane k, a peripheral circuit 120, a control circuit 130, and an input / output pad circuit 140.

[0082] Each of the plurality of planes Plane 1 to Plane k includes a memory cell array, is coupled to an address decoder 121 through word lines WL, and is coupled to a read / write circuit 123 through bit lines BL1 to BLm, where k and m are positive integers. Each of the plurality of planes Plane 1 to Plane k includes a plurality of memory blocks BLK1 to BLKz, where z is a positive integer. The plurality of memory blocks BLK1 to BLKz are coupled to the address decoder 121 through word lines WL. The plurality of memory blocks BLK1 to BLKz are coupled to the read / write circuit 123 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. The plurality of memory cells may be non-volatile memory cells. The plurality of memory blocks BLK1 to BLKz may include a plurality of pages. Among the plurality of memory cells, the memory cells associated with the same word line may be configured as one page. The plurality of memory blocks BLK1 to BLKz may store normal data, such as data transmitted and received during normal read / write operations. Each memory cell may be a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0083] The peripheral circuit 120 includes an address decoder 121, a voltage generator 122, a read / write circuit 123, a data input / output circuit 124, and an impedance calibration circuit ZQCAL 125. The read / write circuit 123 includes a plurality of page buffers PB1 to PBm. The data input / output circuit 124 includes a transmission circuit TX as described in Figure 4 . The impedance calibration circuit 125 may be configured to perform an impedance adjustment operation similar to that of the impedance calibration circuit 1 described in Figures 2 to 8 .

[0084] The address decoder 121 is connected to Plane 1 PLANE1 through the word line WL. The address decoder 121 is configured to operate in response to the control of the control circuit 130. The address decoder 121 is provided with an address by the control circuit 130. The address decoder 121 selects at least one memory block among the memory blocks BLK1 to BLKz based on the decoded address. The address decoder 121 is configured to decode the row address in the received address. The address decoder 121 selects at least one word line by applying the voltage provided by the voltage generator 122 to at least one word line of the selected memory block according to the decoded row address. The address decoder 121 performs a programming operation by applying a programming voltage to the selected word line and applying a pass voltage at a lower level than the programming voltage to the unselected word lines. The address decoder 121 performs a read operation by applying a read voltage to the selected word line and applying a pass voltage higher than the read voltage to the unselected word lines.

[0085] The voltage generator 122 generates various voltages (e.g., read voltage, pass voltage, programming voltage, and erase voltage) under the control of the control circuit 130 and supplies these voltages to the address decoder 121, which are used during the operation of the semiconductor memory device 100.

[0086] The plurality of page buffers PB1 to PBm are connected to Plane 1 PLANE1 through the bit lines BL1 to BLm. The plurality of page buffers PB1 to PBm operate in response to control signals received from the control circuit 130. The plurality of page buffers PB1 to PBm perform data communication with the data input / output circuit 124. The plurality of page buffers PB1 to PBm perform a programming operation by receiving data to be stored via the data input / output circuit 124 and the data line DL and supplying the data to Plane 1 PLANE1. The read / write circuit 123 performs a read operation by reading data from the memory cells of the selected page via the bit lines BL1 to BLm and outputting the read data to the data input / output circuit 124. The read / write circuit 123 can perform an erase operation by floating the bit lines BL1 to BLm.

[0087] The data input / output circuit 124 is connected between a plurality of page buffers PB1 to PBm and the input / output pad circuit 140. The data input / output circuit 124 performs a data input operation and a data output operation in response to control signals received from the control circuit 130. During a read operation, the data input / output circuit 124 outputs data transmitted from a plurality of memory blocks BLK1 to BLKz through the plurality of page buffers PB1 to PBm via the input / output pad circuit 140. During a write operation, the data input / output circuit 124 transmits data input via the input / output pad circuit 140 to the plurality of page buffers PB1 to PBm. During a read operation of status information, the data input / output circuit 124 outputs status information transmitted from the control circuit 130 to an external device through the input / output pad circuit 140.

[0088] The control circuit 130 is connected to the address decoder 121, the voltage generator 122, the read / write circuit 123, the data input / output circuit 124, the impedance calibration circuit 125, and the input / output pad circuit 140. The control circuit 130 receives commands, addresses, and clock signals (collectively referred to as "CA") from the input / output pad circuit 140. The control circuit 130 generates various control signals in response to commands.

[0089] The control circuit 130 generates a data output enable signal ENDOUT in response to a read command, generates a long-term impedance adjustment enable signal ENZQCL in response to a long-term impedance adjustment command, and generates a control mode setting signal INF_ZQC in response to an impedance control mode setting command.

[0090] The control circuit 130 outputs a first impedance code set ZQPUCD, ZQPDCD and a second impedance code set TXPUCD, TXPDCD to the outside of the semiconductor memory device 100 through the input / output pad circuit 140 in response to a code read command provided from the outside of the semiconductor memory device 100.

[0091] The control circuit 130 outputs an update determination signal CDV1 or CDV2 as a flag signal to the outside of the semiconductor memory device 100 through the input / output pad circuit 140 according to a code status read command provided from the outside.

[0092] The input / output pad circuit 140 includes a plurality of pads 141 configured to receive commands, addresses, and clock signals, and input and output data DQ. Commands and addresses can be input separately according to the SCA (Separate Command Address) method or integratedly input according to the CA (Command and Address) method.

[0093] Figure 10 FIG. is a diagram showing a memory system 1000 according to an embodiment of the present disclosure.

[0094] Referring to Figure 10 , the memory system 1000 may include a semiconductor memory device 2000 and a controller 3000.

[0095] The semiconductor memory device 2000 includes a plurality of logic units LU0 to LUn, where n is a positive integer. Each of the plurality of logic units LU0 to LUn includes at least one memory die. Referring to Figure 9 The semiconductor memory device 100 according to an embodiment of the present disclosure described is any one of the plurality of logic units LU0 to LUn.

[0096] The controller 3000 generates a plurality of control signals CTRL and commands and provides them to the semiconductor memory device 2000. During a read operation and a write operation, the controller 3000 sends data to the semiconductor memory device 2000 and receives data from the semiconductor memory device 2000. The controller 3000 provides various commands CA related to an impedance adjustment operation to the semiconductor memory device 2000, such as a read command RD, an impedance adjustment command ZQCL, an impedance control mode setting command SETZQMODE, a code read command ZQRD, and a code status read command STTRD. The controller 3000 provides a code update command ZQUDT to the semiconductor memory device 2000 in response to determining whether to update based on information provided by the semiconductor memory device 2000 according to the code read command ZQRD and the code status read command STTRD.

[0097] Figures 11 to 15 FIG. is a diagram showing a method of an impedance adjustment sequence according to one or more embodiments of the present disclosure.

[0098] Figure 11 FIG. is a timing diagram showing an impedance adjustment sequence of an impedance adjustment operation of the semiconductor memory device 2000, where the impedance adjustment operation is independent of control external to the controller 3000.

[0099] Referring to Figure 11, an initial training sequence is executed. The initial training sequence includes a start sequence, a long-term impedance adjustment operation according to the long-term impedance adjustment command ZQCL, and a plurality of training operations TRN. The semiconductor memory device 2000 activates the long-term impedance adjustment enable signal ENZQCL according to the long-term impedance adjustment command ZQCL, and performs the long-term impedance adjustment operation during the period when the impedance adjustment enable signal ENZQCL is activated. The semiconductor memory device 2000 performs a code update operation in response to the deactivation of the long-term impedance adjustment enable signal ENZQCL (at this time, the update enable signal ENUDT is activated).

[0100] After the initial training sequence, the controller 3000 provides a read command RD to the semiconductor memory device 2000.

[0101] The semiconductor memory device 2000 activates the data output enable signal ENDOUT in response to receiving the read command RD, and performs a data output operation during the activation period of the data output enable signal ENDOUT.

[0102] In addition, the semiconductor memory device 2000 performs an impedance adjustment operation, such as a short-term impedance adjustment operation ZQCSi, simultaneously with the data output operation.

[0103] The semiconductor memory device 2000 performs the short-term impedance adjustment operation ZQCSi during the activation period of the data output enable signal ENDOUT. Different from the traditional method, the method of the present disclosure does not require the controller 3000 to provide a short-term impedance adjustment command ZQCS, and the semiconductor memory device 2000 performs the short-term impedance adjustment operation ZQCSi during the activation period of the data output enable signal ENDOUT without a short-term impedance adjustment command ZQCS.

[0104] The semiconductor memory device 2000 performs a code update operation in response to the deactivation of the data output enable signal ENDOUT (at this time, the update enable signal ENUDT is activated) to update the values of the second impedance code sets TXPUCD and TXPDCD to the values of the first impedance code sets ZQPUCD and ZQPDCD.

[0105] Thereafter, the short-term impedance adjustment operation ZQCSi and the code update operation can be performed each time the read command RD is input.

[0106] Figure 12 is a timing diagram showing an impedance adjustment sequence of the impedance adjustment operation of the semiconductor memory device 2000, where the impedance adjustment operation is independent of the control external to the controller 3000.

[0107] Refer to Figure 12 , execute including Figure 11An initial training sequence similar to the initial training sequence of the initial training sequence.

[0108] After the initial training sequence, the controller 3000 provides a read command RD to the semiconductor memory device 2000.

[0109] The semiconductor memory device 2000 activates the data output enable signal ENDOUT according to the read command RD and performs a data output operation during the activation period of the data output enable signal ENDOUT.

[0110] The semiconductor memory device 2000 performs a short-term impedance adjustment and comparison operation ZQCSi&CMPR simultaneously with the data output operation. The short-term impedance adjustment and comparison operation ZQCSi&CMPR includes generating an update determination signal CDV1 or CDV2 using a short-term impedance adjustment operation ZQCSi and code comparison, as referred to in Figure 6 and Figure 8 as described.

[0111] The semiconductor memory device 2000 performs a short-term impedance adjustment and comparison operation ZQCSi&CMPR during the activation period of the data output enable signal ENDOUT. Different from the conventional method, the method of the present disclosure does not require the controller 3000 to provide a short-term impedance adjustment command ZQCS, and the semiconductor memory device 2000 performs a short-term impedance adjustment and comparison operation ZQCSi&CMPR during the activation period of the data output enable signal ENDOUT without the short-term impedance adjustment command ZQCS.

[0112] The semiconductor memory device 2000 performs the above code update operation in response to the deactivation of the data output enable signal ENDOUT (at this time, the update enable signal ENUDT is activated and at the same time the update determination signal CDV1 or CDV2 is activated). When the update determination signal CDV1 or CDV2 is deactivated, the semiconductor memory device 2000 may not perform the code update operation.

[0113] Thereafter, the above short-term impedance adjustment and comparison operation ZQCSi&CMPR and code update operation can be performed each time a read command RD is input.

[0114] Figure 13 and Figure 14 are timing diagrams showing an impedance adjustment sequence of an impedance adjustment operation of the semiconductor memory device 2000 under external control. Figure 13 is an example of a timing diagram of an impedance adjustment sequence of an operation mode of the semiconductor memory device 2000 in the first impedance control mode ZQMODE1.

[0115] Refer to Figure 13, an operation of adding the included command to the initial training sequence is performed to set the operation mode of the semiconductor memory device 2000 to one of a first impedance control mode ZQMODE1 and a second impedance control mode ZQMODE2. In the first impedance control mode ZQMODE1, a code update operation is executed by the semiconductor memory device 2000. In the second impedance control mode ZQMODE2, the code update operation is executed in response to a command from the controller 3000.

[0116] The controller 3000 transmits an impedance control mode setting command SETZQMODE to the semiconductor memory device 2000 in the initial training sequence. The impedance control mode setting command SETZQMODE changes the timing of the code update operation. Although Figure 13 an example including the impedance control mode setting command SETZQMODE between the start sequence and the long-term impedance adjustment command ZQCL is shown, the impedance control mode setting command SETZQMODE can also be located at any position between subsequences, such as between the long-term impedance adjustment command ZQCL and the training data TRN.

[0117] In response to the impedance control mode setting command SETZQMODE, the semiconductor memory device 2000 generates a control mode setting signal INF_ZQC as referred to Figure 7 in the description. According to the control mode setting signal INF_ZQC, the operation mode of the semiconductor memory device 2000 is set to the first impedance control mode ZQMODE1 as shown Figure 13 .

[0118] After the initial training sequence, the semiconductor memory device 2000 performs a data output operation according to a read command RD while performing a short-term impedance adjustment operation ZQCSi as shown Figure 11 or a short-term impedance adjustment and comparison operation ZQCSi&CMPR as shown Figure 12 .

[0119] Since the operation mode of the semiconductor memory device 2000 is the first impedance control mode ZQMODE1, the above code update operation is executed in response to the deactivation of the data output enable signal ENDOUT and the activation of the update determination signal CDV1 or CDV2, as shown Figure 11 or Figure 12 .

[0120] Figure 14 is an example where the operation mode of the semiconductor memory device 2000 is the second impedance control mode ZQMODE2 according to the impedance control mode setting command SETZQMODE included in the initial training sequence.

[0121] Referring to Figure 14, after the initial training sequence, the semiconductor memory device 2000 performs the short-term impedance adjustment and comparison operation ZQCSi&CMPR as shown in Figure 12 while performing a data output operation according to the read command RD.

[0122] Since the operation mode of the semiconductor memory device 2000 is the second impedance control mode ZQMODE2, the controller 3000 transmits the code read command ZQRD to the semiconductor memory device 2000.

[0123] The semiconductor memory device 2000 outputs the first impedance code sets ZQPUCD, ZQPDCD and the second impedance code sets TXPUCD, TXPDCD to the controller 3000 in response to the code read command ZQRD.

[0124] The controller 3000 provides the code update command ZQUDT to the semiconductor memory device 2000, which indicates (facilitates) or prohibits the code update operation by determining the difference in code values (e.g., the difference between the first impedance code sets ZQPUCD, ZQPDCD and the second impedance code sets TXPUCD, TXPDCD).

[0125] When the code update command ZQUDT allows or facilitates the code update operation, the semiconductor memory device 2000 performs the code update operation, and when the code update instruction ZQUDT prohibits the code update operation, the semiconductor memory device 2000 does not perform the code update operation.

[0126] Figure 15 is a timing diagram during the code status read operation when the operation mode of the semiconductor memory device 2000 is the second impedance control mode ZQMODE2 according to the impedance control mode setting command SETZQMODE included in the initial training sequence.

[0127] Refer to Figure 15 , after the initial training sequence, the semiconductor memory device 2000 performs the short-term impedance adjustment and comparison operation ZQCSi&CMPR as shown in Figure 12 while performing a data output operation according to the read command RD.

[0128] Since the operation mode of the semiconductor memory device 2000 is the second impedance control mode ZQMODE2, the controller 3000 transmits the code status read command STTRD to the semiconductor memory device 2000.

[0129] The semiconductor memory device 2000 provides the update determination signal CDV1 or CDV2 as a flag signal to the controller 3000 in response to the code status read command STTRD.

[0130] The controller 3000 uses a flag signal to determine the impedance adjustment state of the semiconductor memory device 2000, or directly controls the code update operation by providing a code update command ZQUDT as shown to the semiconductor memory device 2000 based on the flag signal. Figure 14 shown to directly control the code update operation.

[0131] Those skilled in the art to which the present disclosure pertains can understand that the present disclosure can be implemented in other forms without changing the technical scope or essential features. The above embodiments are exemplary in all aspects and not restrictive. Therefore, the scope of the present disclosure should not be limited to the foregoing embodiments. All changes within the equivalent meaning and scope of the claims are included within its scope.

Claims

1. An impedance calibration circuit, comprising: a code generation circuit that generates a first impedance code set by performing an impedance adjustment operation during an activation period of a data output enable signal generated in response to a read command; as well as The code update control circuit prevents updating of a second impedance code set to the first impedance code set before the data output enable signal is disabled, wherein the second impedance code set is used for impedance adjustment of a transmitting circuit.

2. The impedance calibration circuit according to claim 1, wherein: The code generation circuit performs the impedance adjustment within an impedance adjustment time period identified by a long-term impedance adjustment enable signal generated according to a long-term impedance adjustment command.

3. The impedance calibration circuit according to claim 1, wherein: The code generation circuit comprises: a first replica circuit that adjusts impedance according to a first impedance pull-up code from the first impedance code set; a first code adjustment circuit, which adjusts the value of the first impedance pull-up code based on a result of comparing a first reference voltage with a voltage at a first node connected to the first replica circuit and a reference resistor during an activation period of an impedance adjustment enable signal; a second replica circuit, adjusting impedance according to the first impedance pull-up code; a third replica circuit that adjusts impedance according to a first impedance pull-down code from the first impedance code set; a second code adjustment circuit, which adjusts the value of the first impedance pull-down code based on a result of comparing a second reference voltage with a voltage at a second node to which the second replica circuit and the third replica circuit are connected, during an activation period of the impedance adjustment enable signal; and The logic circuit generates the impedance adjustment enable signal in response to the data output enable signal and the long-term impedance adjustment enable signal.

4. The impedance calibration circuit according to claim 3, wherein: The first replica circuit and the second replica circuit are configured by replicating a pull-up driver of the transmitting circuit, and the third replica circuit is configured by replicating a pull-down driver of the transmitting circuit.

5. The impedance calibration circuit according to claim 3, wherein: The first code adjustment circuit comprises: a first comparator, which generates a first comparison signal based on a comparison result between the first reference voltage and the voltage at the first node during an activation period of the impedance adjustment enable signal; and A first counter increases or decreases a value of the first impedance pull-up code based on the first comparison signal.

6. The impedance calibration circuit according to claim 1, wherein: The code update control circuit comprises: a latch circuit that updates the second impedance code set to the first impedance code set in response to activation of an update enable signal; and An update logic circuit activates the update enable signal in response to at least one of a plurality of control signals, the first impedance code set, and the second impedance code set.

7. The impedance calibration circuit according to claim 6, wherein: The update logic circuit activates the update enable signal when the data output enable signal is deactivated.

8. The impedance calibration circuit according to claim 6, wherein: The update logic circuit activates the update enable signal when the data output enable signal is deactivated and the first impedance code set and the second impedance code set do not match each other.

9. The impedance calibration circuit according to claim 6, wherein: The update logic circuit activates the update enable signal when the data output enable signal is deactivated and a difference between a value of the first impedance code set and a value of the second impedance code set is greater than a target value.

10. The impedance calibration circuit according to claim 6, wherein: When a code update command is input, the update logic circuit activates the update enable signal.

11. The impedance calibration circuit according to claim 6, wherein: The update logic circuit activates the update enable signal when the long-term impedance adjustment enable signal is disabled.

12. The impedance calibration circuit according to claim 6, wherein: The update logic circuit comprises: a code operation circuit that generates an update determination signal based on a result of determining whether the first impedance code set and the second impedance code set match; an update timing detection circuit that generates an update timing signal in response to the data output enable signal, the code update command, and the control mode setting signal; and A logic gate generates the update enable signal by performing a logic operation on the update determination signal and the update timing signal.

13. The impedance calibration circuit according to claim 6, wherein: The update logic circuit comprises: a code operation circuit that generates an update determination signal based on a result of determining whether a difference between the first impedance code set and the second impedance code set is greater than a target value; an update timing detection circuit that generates an update timing signal in response to the data output enable signal, the code update command, and the control mode setting signal; and A logic gate generates the update enable signal by performing a logic operation on the update determination signal and the update timing signal.

14. A semiconductor memory device comprising: Memory area; a transmitting circuit that adjusts impedance according to a second impedance code set and outputs data from the memory area during an activation period of a data output enable signal; an impedance calibration circuit that performs an impedance adjustment operation to generate a first impedance code set during an activation period of the data output enable signal, and prevents the second impedance code set from being updated to the first impedance code set until the data output enable signal is deactivated; as well as The control circuit activates the data output enable signal in response to a read command.

15. The semiconductor memory device according to claim 14, wherein: The memory region includes a plurality of logic cells, wherein each of the plurality of logic cells includes at least one memory die.

16. The semiconductor memory device according to claim 14, wherein: The impedance calibration circuit comprises: a latch circuit that updates the second impedance code set to the first impedance code set in response to activation of an update enable signal; and An update logic circuit activates the update enable signal in response to at least one of a plurality of control signals, the first impedance code set, and the second impedance code set.

17. The semiconductor memory device according to claim 16, wherein: The update logic circuit comprises: a code operation circuit that generates an update determination signal based on a result of determining whether the first impedance code set and the second impedance code set match; an update timing detection circuit that generates an update timing signal in response to the data output enable signal, the code update command, and the control mode setting signal; and A logic gate generates the update enable signal by performing a logic operation on the update determination signal and the update timing signal.

18. The semiconductor memory device according to claim 16, wherein: The update logic circuit comprises: a code operation circuit that generates an update determination signal based on a result of determining whether a difference between the first impedance code set and the second impedance code set is greater than a target value; an update timing detection circuit that generates an update timing signal in response to the data output enable signal, the code update command, and the control mode setting signal; and A logic gate generates the update enable signal by performing a logic operation on the update determination signal and the update timing signal.

19. The semiconductor memory device according to claim 16, wherein: The impedance calibration circuit further comprises: a first replica circuit that adjusts impedance according to a first impedance pull-up code from the first impedance code set; a first code adjustment circuit, which adjusts the value of the first impedance pull-up code based on a result of comparing a first reference voltage with a voltage of a first node to which the first replica circuit and a reference resistor are connected, during an activation period of an impedance adjustment enable signal; a second replica circuit, adjusting impedance according to the first impedance pull-up code; a third replica circuit that adjusts impedance according to a first impedance pull-down code from the first impedance code set; a second code adjustment circuit, which adjusts the value of the first impedance pull-down code based on a result of comparing a second reference voltage with a voltage of a second node to which the second replica circuit and the third replica circuit are connected, during an activation period of the impedance adjustment enable signal; and The logic circuit generates the impedance adjustment enable signal in response to the data output enable signal and the long-term impedance adjustment enable signal.

20. A memory system comprising: a semiconductor memory device comprising a transmitting circuit that adjusts impedance according to a second impedance code set, performs an impedance adjustment operation to generate a first impedance code set during a data output time period of the transmitting circuit in response to a read command, and prevents a code update operation from updating the second impedance code set to the first impedance code set before the data output time period is completed; as well as A controller provides an impedance control mode setting command to the semiconductor memory device to change the timing of the code update operation.

21. The memory system of claim 20, wherein: The controller sets the operation mode of the semiconductor memory device to a first impedance control mode using the impedance control mode setting command, and When the first impedance code set does not match the second impedance code set during the first impedance control mode, the semiconductor memory device performs the code update operation after the data output period is completed.

22. The memory system according to claim 20, wherein: The controller sets the operation mode of the semiconductor memory device to a first impedance control mode using the impedance control mode setting command, and When a difference between the first impedance code set and the second impedance code set during the first impedance control mode is greater than a target value, the semiconductor memory device performs the code update operation after the data output period is completed.

23. The memory system of claim 20, wherein: The controller provides a code update command to the semiconductor memory device after setting the operation mode of the semiconductor memory device to a second impedance control mode using the impedance control mode setting command, and The semiconductor memory device performs the code update operation in response to the code update command.

24. The memory system of claim 23, wherein: The controller provides a code read command to the semiconductor memory device before the code update command, and The semiconductor memory device provides at least one of the first impedance code set and the second impedance code set to the controller in response to the code read command, and performs the code update operation in response to the code update command.

25. The memory system of claim 20, wherein: The controller provides a code status read command to the semiconductor memory device, and The semiconductor memory device provides a flag signal to the controller in response to the code status read command to identify whether the first impedance code set matches the second impedance code set and whether a difference between the first impedance code set and the second impedance code set is greater than a target value.

26. The memory system of claim 20, wherein: The semiconductor memory device comprises: Memory area; the transmitting circuit adjusting impedance according to the second impedance code set and outputting data from the memory area during an activation period of a data output enable signal; an impedance calibration circuit that performs an impedance adjustment operation to generate the first impedance code set during an activation period of the data output enable signal, and prevents the second impedance code set from being updated to the first impedance code set until the data output enable signal is deactivated; and A control circuit sets the operation mode of the semiconductor memory device to one of a first impedance control mode and a second impedance control mode in response to the impedance control mode setting command, and activates the data output enable signal in response to the read command.

27. The memory system of claim 20, wherein: The semiconductor memory device comprises: a latch circuit that updates the second impedance code set to the first impedance code set in response to activation of an update enable signal; and An update logic circuit activates the update enable signal in response to at least one of a plurality of control signals, the first impedance code set, and the second impedance code set.

28. The memory system of claim 27, wherein: The update logic circuit comprises: a code operation circuit that generates an update determination signal based on a result of determining whether the first impedance code set and the second impedance code set match; an update timing detection circuit that generates an update timing signal in response to the data output enable signal, the code update command, and the control mode setting signal; and A logic gate generates the update enable signal by performing a logic operation on the update determination signal and the update timing signal.

29. The memory system of claim 27, wherein: The update logic circuit comprises: a code operation circuit that generates an update determination signal based on a result of determining whether a difference between the first impedance code set and the second impedance code set is greater than a target value; an update timing detection circuit that generates an update timing signal in response to the data output enable signal, the code update command, and the control mode setting signal; and A logic gate generates the update enable signal by performing a logic operation on the update determination signal and the update timing signal.

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