Voltage Monitoring Circuit of DLL Module and DRAM

Abstract

The voltage monitoring circuit and DRAM of the DLL module provided by the embodiments of the present disclosure include: a voltage dividing module, a voltage sampling module, and a comparison module; the voltage dividing module is configured to generate N different reference voltages after dividing the reference bandgap voltage; the voltage sampling module is configured to collect the operating voltage of the DLL module; the comparison module is configured to compare the relationship between the N different reference voltages and the operating voltage, generate a level signal, and determine the voltage range to which the operating voltage of the DLL module belongs according to the level signal. When a read / write error occurs in the DRAM, it is determined whether the DRAM read / write error is caused by too low an operating voltage of the DLL module according to the voltage range in which the operating voltage of the DLL module is located during the operating state.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of memory technologies and related technologies. Specifically, it relates to a voltage monitoring circuit and a DRAM applicable to a DLL module. Background Art

[0002] Dynamic Random Access Memory (DRAM) is an internal memory that directly exchanges data with the CPU. It has the characteristics of random read and write and high speed, and is usually used as a temporary data storage medium for the operating system or other running programs.

[0003] In the prior art, a power supply voltage port VDD is provided outside the DRAM. This port is the power supply port for the DRAM and also supplies power to all modules inside the DRAM. That is, the power supply voltage of the DLL (delay-locked loop) module in the DRAM is also this voltage. Among them, the role of the DLL module in the DRAM is delay locking, which can phase-lock the external clock information with the data clock signal. Since the power supply voltage port VDD is the unified power supply port for the DRAM, when the memory chip is working normally, other modules will also use the voltage provided by the power supply voltage port VDD as the power supply voltage. When other modules in the DRAM are working, they will generate power supply voltage ripple signals that will affect the DLL module. In addition, when other modules in the DRAM are working, they will generate local power supply voltage drops, and excessive power supply voltage drops will cause functional errors in the DLL module. Summary of the Invention

[0004] Embodiments described herein provide a voltage monitoring circuit and a DRAM for a DLL module, which can determine whether the DRAM read / write error is caused by too low a working voltage of the DLL module according to the voltage range in which the working voltage of the DLL module is located when the DLL module is in the working state.

[0005] In a first aspect, according to the content of the present disclosure, a voltage monitoring circuit for a DLL module is provided, including: a voltage dividing module, a voltage sampling module, and a comparison module;

[0006] The voltage dividing module is configured to divide the reference bandgap voltage to generate N different reference voltages;

[0007] The voltage sampling module is configured to collect the working voltage of the DLL module;

[0008] The comparison module is configured to compare the relationship between N different reference voltages and the working voltage to generate a level signal, so as to determine the voltage range to which the working voltage of the DLL module belongs according to the level signal.

[0009] In some embodiments of the present disclosure, the voltage division module includes an operational amplifier and N resistors connected in series. The first input terminal of the operational amplifier receives the bandgap reference voltage. The second input terminal of the operational amplifier is electrically connected to both the output terminal of the operational amplifier and the first terminal of the first resistor. The second terminal of the (i - 1)-th resistor is electrically connected to the first terminal of the i-th resistor. The second terminal of the N-th resistor is electrically connected to a ground node, where i is an integer greater than 1 and less than or equal to N.

[0010] In some embodiments of the present disclosure, the voltage sampling module includes a sampling unit and a working voltage determination unit;

[0011] The sampling unit is configured to collect the sampling working voltage of the DLL module at different sampling periods within a target sampling time period;

[0012] The working voltage determination unit is configured to obtain the sampling working voltage of the DLL module collected by the sampling unit at different sampling periods within a target sampling time period, and select the minimum value of the sampling working voltage of the DLL module within the target sampling time period as the working voltage of the DLL module and send it to the comparison module.

[0013] In some embodiments of the present disclosure, the comparison module includes at least a first comparison unit;

[0014] The first comparison unit is configured to compare the relationship between N different reference voltages and the working voltage, and generate N level signals.

[0015] In some embodiments of the present disclosure, the first comparison unit includes N comparators. The first input terminals of the N comparators respectively receive the working voltage. The second input terminal of the i-th comparator receives the i-th reference voltage. The output terminal of the i-th comparator outputs the i-th level signal, where i is an integer greater than 1 and less than or equal to N.

[0016] In some embodiments of the present disclosure, the comparison module further includes a latching unit;

[0017] The latching unit is configured to latch the N level signals generated by the comparison unit when receiving a test enable signal.

[0018] In some embodiments of the present disclosure, the latching unit includes N latches. The data input terminal of the i-th latch receives the i-th level signal. The enable terminals of the latches receive the test enable signal, where i is an integer greater than 1 and less than or equal to N.

[0019] In some embodiments of the present disclosure, a DLL module voltage determination module is further included;

[0020] The DLL module voltage determination module is configured to determine the minimum voltage range to which the operating voltage of the DLL module belongs according to the latch signals of the latch units in different sampling periods within a target sampling time period.

[0021] In some embodiments of the present disclosure, the DLL module voltage determination module includes a DLL module voltage range determination unit and a second comparison unit;

[0022] The DLL module voltage range determination unit is configured to determine the voltage range to which the operating voltage of the DLL module in different sampling periods within a target sampling time period belongs according to the latch signals of the latch units in different sampling periods within the target sampling time period;

[0023] The second comparison unit is configured to determine the minimum voltage range to which the operating voltage of the DLL module belongs from the voltage ranges to which the operating voltages of the DLL module in different sampling periods within a target sampling time period belong.

[0024] In a second aspect, according to the content of the present disclosure, a DRAM is provided, including the circuit according to any one of the first aspect.

[0025] The voltage monitoring circuit and DRAM of the DLL module provided in the embodiments of the present disclosure, by setting the voltage monitoring circuit to include a voltage division module, a voltage sampling module, and a comparison module, the voltage sampling module collects the operating voltage of the DLL module in the operating state and sends the collected operating voltage to the comparison module, the voltage division module divides the bandgap reference voltage to generate N different reference voltages and sends the N different reference voltages to the comparison module, the comparison module respectively compares the N different reference voltages with the operating voltage of the DLL module to generate N level signals, and further realizes determining the voltage range in which the operating voltage of the DLL module is located in the operating state according to the N level signals generated by the comparison module, and realizes determining whether the DRAM read / write error is caused by too low operating voltage of the DLL module according to the voltage range in which the operating voltage of the DLL module is located in the operating state when the DRAM read / write error occurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0027] Figure 1 is a schematic structural diagram of a voltage monitoring circuit of a DLL module provided by an embodiment of the present disclosure;

[0028] Figure 2 is a schematic structural diagram of another voltage monitoring circuit of a DLL module provided by an embodiment of the present disclosure;

[0029] Figure 3 It is a schematic structural diagram of another voltage monitoring circuit of the DLL module provided by an embodiment of the present disclosure;

[0030] Figure 4 It is a schematic structural diagram of another voltage monitoring circuit of the DLL module provided by an embodiment of the present disclosure. Detailed implementation manners

[0031] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts shall also fall within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the subject matter of the present disclosure belongs. Further, it will be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless expressly defined otherwise herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0033] In all embodiments of the present disclosure, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0034] Unless the context clearly indicates otherwise, the singular forms of the words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" will be interpreted as including rather than exclusively. Likewise, the term "including" and "or" should be interpreted as inclusive, unless expressly prohibited in this document. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and explanatory and should not be considered exclusive or extensive.

[0035] Based on the problems existing in the prior art, an embodiment of the present disclosure provides a voltage monitoring circuit for a DLL module, Figure 1 It is a schematic structural diagram of a voltage monitoring circuit of a DLL module provided by an embodiment of the present disclosure, asFigure 1 As shown, the voltage monitoring circuit of the DLL module includes: a voltage division module 10, a voltage sampling module 20, and a comparison module 30; the voltage division module 10 is configured to divide the reference bandgap voltage to generate N different reference voltages; the voltage sampling module 20 is configured to collect the operating voltage of the DLL module; the comparison module 30 is configured to compare the relationship between the N different reference voltages and the operating voltage, generate a level signal, and determine the voltage range to which the operating voltage of the DLL module belongs according to the level signal.

[0036] In the prior art, since the DLL module in the DRAM and other modules (such as the receiving module and the regulating module) are all powered by the power supply voltage, on the one hand, the power supply voltage ripple signal generated by the receiving module and the regulating module during the working state will affect the operating voltage of the DLL module. On the other hand, the local power supply voltage dropout generated by other modules in the DRAM during operation will also cause the voltage of the DLL module to be too low. For example, the power supply voltage ripple signal generated by the receiving module and the regulating module during the working state makes the operating voltage of the DLL module too low. Another example is that the local power supply voltage dropout that occurs in the receiving module and the regulating module during the working state will cause the DLL module to malfunction, and the malfunction of the DLL module will lead to DRAM read and write errors. Therefore, when a DRAM read and write error is detected, one implementation solution is to monitor the operating voltage of the DLL module in the DRAM, and determine whether the DRAM read and write error is caused by the DLL module being at an abnormal operating voltage according to the voltage range to which the monitored operating voltage of the DLL module belongs.

[0037] In a specific embodiment, the voltage monitoring circuit of the DLL module includes a voltage sampling module 20. The voltage sampling module 20 collects the operating voltage of the DLL module in the working state and sends the collected operating voltage to the comparison module 30. The voltage division module 10 divides the bandgap reference voltage to generate N different reference voltages and sends the N different reference voltages to the comparison module 30. The comparison module 30 respectively compares the N different reference voltages with the operating voltage of the DLL module to generate N level signals, and further realizes determining the voltage range in which the operating voltage of the DLL module is located in the working state according to the N level signals generated by the comparison module. When a DRAM read and write error occurs, it is determined whether the DRAM read and write error is caused by the operating voltage of the DLL module being too low according to the voltage range in which the operating voltage of the DLL module is located in the working state.

[0038] It should be noted that the bandgap reference voltage is generated based on a bandgap reference module. The bandgap reference voltage generated by the bandgap reference module is independent of the chip temperature, process, and power supply voltage. Therefore, the N different reference voltages generated based on the bandgap reference voltage are also independent of the chip temperature, process, and power supply voltage, thereby ensuring the accuracy of the voltage range in which the operating voltage of the DLL module determined according to the level signal generated by the comparison module is located.

[0039] For the voltage monitoring circuit of the DLL module provided in the embodiments of the present disclosure, by setting the voltage monitoring circuit to include a voltage dividing module, a voltage sampling module, and a comparison module, the voltage sampling module samples the operating voltage of the DLL module in the operating state and sends the sampled operating voltage to the comparison module. The voltage dividing module divides the bandgap reference voltage to generate N different reference voltages and sends the N different reference voltages to the comparison module. The comparison module compares the N different reference voltages with the operating voltage of the DLL module respectively to generate N level signals. Furthermore, according to the N level signals generated by the comparison module, the voltage range in which the operating voltage of the DLL module is located in the operating state is determined, so as to determine whether the DRAM read / write error is caused by the too low operating voltage of the DLL module according to the voltage range in which the operating voltage of the DLL module is located in the operating state.

[0040] In a specific implementation manner, as Figure 2 shown, the voltage dividing module 10 includes an operational amplifier U and N resistors R (R1, R2,..., RN) connected in series. The first input terminal of the operational amplifier U receives the bandgap reference voltage. The second input terminal of the operational amplifier U is electrically connected to the output terminal of the operational amplifier U and the first terminal of the first resistor R1. The second terminal of the (i - 1)th resistor Ri - 1 is electrically connected to the first terminal of the ith resistor Ri. The second terminal of the Nth resistor RN is electrically connected to the ground node, where i is an integer greater than 1 and less than or equal to N.

[0041] As Figure 2As shown, the voltage division module includes an operational amplifier U electrically connected to N series-connected resistors R (R1, R2, ..., RN). The first input terminal of the operational amplifier U receives the bandgap reference voltage VBandgap. The second input terminal of the operational amplifier U is electrically connected to the output terminal, such that the voltage at the output terminal of the operational amplifier U is the same as the voltage at the first input terminal, that is, the voltage at the output terminal of the operational amplifier U is the bandgap reference voltage VBandgap. The bandgap reference voltage VBandgap is divided by multiple resistors to generate N reference voltages (Vref1, Vref2, ..., VrefN). Among them, the first reference voltage Vref1 is the bandgap reference voltage output by the operational amplifier U, the second reference voltage Vref2 is the bandgap reference voltage VBandgap minus the voltage drop across the first resistor R1, the third reference voltage Vref3 is the bandgap reference voltage VBandgap minus the voltage drops across the first resistor R1 and the second resistor R2, and the Nth reference voltage VrefN is the bandgap reference voltage VBandgap minus the voltage drops across the first resistor R1, the second resistor R2, ..., and the (N - 1)th resistor RN-1.

[0042] After the voltage division module 10 obtains N different reference voltages through the voltage division of the operational amplifier U and N series-connected resistors R (R1, R2, ..., RN), it sends the N different reference voltages to the comparison module 30. The comparison module 30 respectively receives the N different reference voltages generated by the voltage division module 10 and the operating voltage of the DLL module collected by the voltage sampling module 20, and respectively compares the relationship between the first reference voltage Vref1 and the operating voltage Vx of the DLL module, the relationship between the second reference voltage Vref2 and the operating voltage Vx of the DLL module, ...., and the relationship between the Nth reference voltage VrefN and the operating voltage Vx of the DLL module, and then generates a level signal.

[0043] In a specific embodiment, continuing in conjunction with Figure 2 , the comparison module 30 includes at least a first comparison unit 31; the first comparison unit 31 is configured to compare the relationship between N different reference voltages and the operating voltage and generate N level signals.

[0044] As a specific embodiment, the comparison module 30 includes a first comparison unit 31. By comparing the relationship between N different reference voltages and the operating voltage of the DLL module through the first comparison unit 31, a level signal is generated.

[0045] A specific exemplary first comparison unit 31 includes N comparators (Comp1, Comp2,..., CompN). The first input terminals of the N comparators respectively receive the working voltage Vx. The second input terminal of the first comparator Comp1 receives the first reference voltage Vref1 generated by the voltage division module 10. The second input terminal of the second comparator Comp2 receives the second reference voltage Vref2 generated by the voltage division module 10,..., and the second input terminal of the Nth comparator CompN receives the Nth reference voltage VrefN generated by the voltage division module 10. The first comparator Comp1 compares the relationship between the working voltage Vx of the DLL module and the first reference voltage Comp1 to generate a first level signal. The second comparator Comp2 compares the relationship between the working voltage Vx of the DLL module and the second reference voltage Vref2 to generate a second level signal. The Nth comparator CompN compares the relationship between the working voltage Vx of the DLL module and the Nth reference voltage VrefN to generate an Nth level signal. Exemplarily, if the positive input terminal of the first comparator is the working voltage of the DLL module and the negative input terminal of the first comparator is the first reference voltage, when the working voltage of the DLL module is greater than the first reference voltage, the first comparator outputs a high level, and when the working voltage of the DLL module is less than the first reference voltage, the first comparator outputs a low level.

[0046] Based on the above embodiments, as a preferred implementation manner, continue to refer to Figure 2 , the comparison module 30 further includes a latch unit 32; the latch unit 32 is configured to latch the N level signals generated by the comparison unit when receiving a test enable signal.

[0047] Since the working voltage of the DLL module is constantly changing, by arranging the latch unit 32 behind the comparison unit 31, the latch unit 32 latches the level signals output by the comparison unit 31 in the current sampling period, preventing data from being corrupted due to interference or noise during transmission and improving the reliability of the circuit.

[0048] In a specific implementation manner, the latch unit 32 includes N latches L (L1, L2,..., LN). The output terminal of the ith comparator Compi outputs the ith level signal to the data input terminal of the ith latch Li. The enable terminals of the latches receive the test enable signal, where the ith latch latches the level signal output by the ith comparator.

[0049] It should be noted that in the above embodiments, when the latch unit receives the test enable signal, it latches the N level signals generated by the comparison unit.

[0050] As a preferred implementable manner, such asFigure 3 As shown in the figure, the voltage sampling module 20 includes a sampling unit 21 and a working voltage determination unit 22. Among them, the sampling unit 21 is configured to collect the sampling working voltage of the DLL module at different sampling periods within the target sampling time period; the working voltage determination unit 22 is configured to obtain the sampling working voltage of the DLL module collected by the sampling unit at different sampling periods within the target sampling time period, and select the minimum value of the sampling working voltage of the DLL module within the target sampling time period as the working voltage of the DLL module and send it to the comparison module.

[0051] In the working state of the DRAM, the working timings of different modules are different. Therefore, the voltage ripple signals generated by different modules in the DRAM have different effects on the working voltage of the DLL module. Therefore, to determine that the DRAM read / write error is caused by the too low working voltage of the DLL module, when the DRAM read / write error occurs, by setting the voltage sampling module to include a sampling unit and a working voltage determination unit, the sampling unit collects the sampling working voltage of the DLL module at different sampling periods within the target sampling time period, and then the working voltage determination unit selects the minimum value of the sampling working voltage of the DLL module within the target sampling time period as the working voltage of the DLL module and sends it to the comparison module. That is, after sending the minimum value of the sampling working voltage of the DLL module within the target sampling time period as the working voltage of the DLL module to the comparison module, at this time, based on the relationship between the minimum sampling working voltage and N reference voltages, it is determined that the voltage range interval where the working voltage of the DLL module is located is the voltage range interval where the minimum working voltage of the DLL module is located within the target sampling time period. Furthermore, by comparing the voltage range interval where the minimum working voltage of the DLL module is located with the threshold voltage for the normal operation of the DLL module, when the voltage range interval where the minimum working voltage of the DLL module is located is less than the threshold voltage for the normal operation of the DLL module, it can be determined that the reason for the DRAM read / write error within the target sampling time period is that the voltage ripple signal generated by other modules in the DRAM affects the working voltage of the DLL module, or because of the local power supply voltage drop generated by other modules in the DRAM during operation, which affects the working voltage of the DLL module, resulting in too low voltage of the DLL module and causing the DLL module to fail to work properly.

[0052] As another preferred implementable manner, as Figure 4 shown in the figure, the voltage monitoring circuit of the DLL module further includes a DLL module voltage determination module 40; the DLL module voltage determination module 40 is configured to determine the minimum voltage interval to which the working voltage of the DLL module belongs according to the latch signals of the latch unit at different sampling periods within the target sampling time period.

[0053] Specifically, the DLL module voltage determination module 40 includes a DLL module voltage range determination unit 41 and a second comparison unit 42. The DLL module voltage range determination unit 41 is configured to determine the voltage range to which the operating voltage of the DLL module belongs within different sampling periods during the target sampling period according to the latch signals of the latch units within different sampling periods. The second comparison unit 42 is configured to determine the minimum voltage range to which the operating voltage of the DLL module belongs based on the voltage ranges to which the operating voltage of the DLL module belongs within different sampling periods during the target sampling period.

[0054] Similarly, in the operating state of the DRAM, the operating timings of different modules are different. Therefore, the voltage ripple signals generated by different modules in the DRAM have different effects on the operating voltage of the DLL module. Thus, to determine whether the read / write error of the DRAM is caused by the too low operating voltage of the DLL module, as another implementable manner, the voltage monitoring circuit of the DLL module is provided with a DLL module voltage determination module. Among them, the DLL module voltage range determination unit of the DLL module voltage determination module is used to determine the voltage range to which the operating voltage of the DLL module belongs within different sampling periods during the target sampling period according to the latch signals of the latch units within different sampling periods. The second comparison unit is used to determine the minimum voltage range to which the operating voltage of the DLL module belongs based on the voltage ranges to which the operating voltage of the DLL module belongs within different sampling periods during the target sampling period. Furthermore, by comparing the minimum voltage range to which the operating voltage of the DLL module belongs with the threshold voltage for the normal operation of the DLL module, when the minimum voltage range to which the operating voltage of the DLL module belongs is less than the threshold voltage for the normal operation of the DLL module, it can be determined that the reason for the read / write error of the DRAM during the target sampling period is due to the influence of the voltage ripple signals generated by other modules in the DRAM on the operating voltage of the DLL module, or due to the influence of the local power supply voltage drop during the operation of other modules in the DRAM on the operating voltage of the DLL module, resulting in too low voltage of the DLL module and causing the DLL module to be unable to operate normally.

[0055] It should be noted that in the above embodiments, the number of comparison modules is not specifically limited in the embodiments of the present disclosure. The more the number of comparison modules, the finer the divided range of the reference voltage obtained from the bandgap reference voltage, and the more accurate the determined range where the operating voltage is located based on the reference voltage.

[0056] The embodiments of the present disclosure also provide a DRAM, which includes the voltage monitoring circuit of the DLL module provided in the embodiments of the present disclosure and has the beneficial effects described in any of the above embodiments.

[0057] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should also be understood that when the terms "comprising" and / or "including" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0058] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present application, the order numbers of the above steps / processes do not mean the sequence of execution. The execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. Moreover, the serial numbers of the embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0059] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above drawings are used to distinguish similar objects and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0060] The above are only the preferred embodiments of the present disclosure and are not used to limit the present disclosure. For those skilled in the art, the present disclosure may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A voltage monitoring circuit for a DLL module, characterized in that, Comprising: A voltage dividing module, a voltage sampling module, and a comparison module; The voltage dividing module is configured to divide the bandgap reference voltage to generate N different reference voltages; The voltage sampling module is configured to collect the operating voltage of the DLL module; The comparison module is configured to compare the relationship between N different reference voltages and the operating voltage, generate a level signal, and determine the voltage range to which the operating voltage of the DLL module belongs according to the level signal It further includes a DLL module voltage determination module; The DLL module voltage determination module is configured to determine the minimum voltage range to which the operating voltage of the DLL module belongs according to the level signals of different sampling periods within the target sampling period; The DLL module voltage determination module includes a DLL module voltage range determination unit and a second comparison unit; the DLL module voltage range determination unit is configured to determine the voltage range to which the operating voltage of the DLL module belongs during different sampling periods within the target sampling period according to the level signals of different sampling periods within the target sampling period; the second comparison unit is configured to determine the minimum voltage range to which the operating voltage of the DLL module belongs according to the voltage ranges to which the operating voltages of the DLL module belong during different sampling periods within the target sampling period; Wherein, DLL is a delay locked loop in a dynamic random access memory.

2. The circuit according to claim 1, wherein The voltage dividing module includes an operational amplifier and N resistors connected in series. The first input terminal of the operational amplifier receives the bandgap reference voltage. The second input terminal of the operational amplifier is electrically connected to the output terminal of the operational amplifier and the first terminal of the first resistor. The second terminal of the (i - 1)th resistor is electrically connected to the first terminal of the ith resistor. The second terminal of the Nth resistor is electrically connected to a ground node, where i is an integer greater than 1 and less than or equal to N.

3. The circuit according to claim 1, characterized in that, The voltage sampling module includes a sampling unit and an operating voltage determination unit; The sampling unit is configured to collect the sampled operating voltage of the DLL module during different sampling periods within the target sampling period; The operating voltage determination unit is configured to obtain the sampled operating voltage of the DLL module collected by the sampling unit during different sampling periods within the target sampling period, and select the minimum value of the sampled operating voltage of the DLL module within the target sampling period as the operating voltage of the DLL module and send it to the comparison module.

4. The circuit according to claim 1, characterized in that, The comparison module includes at least a first comparison unit; The first comparison unit is configured to compare the relationship between N different reference voltages and the operating voltage, and generate N level signals.

5. The circuit according to claim 4, wherein The first comparison unit includes N comparators. The first input terminals of the N comparators respectively receive the operating voltage. The second input terminal of the ith comparator receives the ith reference voltage. The output terminal of the ith comparator outputs the ith level signal, where i is an integer greater than 1 and less than or equal to N.

6. The circuit according to claim 4 or 5, characterized in that, The comparison module further includes a latch unit; The latch unit is configured to latch the N level signals generated by the comparison unit when receiving a test enable signal.

7. The circuit according to claim 6, wherein The latch unit includes N latches. The data input terminal of the i-th latch receives the i-th level signal, and the enable terminals of the latches receive a test enable signal, where i is an integer greater than 1 and less than or equal to N.

8. A DRAM, characterized in that, Comprising the circuit according to any one of claims 1-7.

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