Method for optimizing polycrystalline silicon residues on SGT structure
By etching the shielded gate polysilicon layer in two steps and thinning the field oxide layer, the G/S shorting problem caused by polysilicon residue in the SGT structure is solved, and the reliability and performance of the device are improved.
Patent Information
- Application Number
- CN202510169534.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2025-06-10
AI Technical Summary
In the SGT structure, polysilicon remains due to the step difference between the junction position of the AA region and the GR region, forming a G/S short connection, resulting in device failure.
By etching the shielded gate polysilicon layer in two steps and adding a thinning-field oxide layer between the two steps, the side ceramic phenomenon of the field oxide layer on both sides of the shielded gate polysilicon layer is avoided, and the thickness of the field oxide layer is thinned to improve polysilicon residue.
It effectively avoids G/S shorting, improves polysilicon residue, and improves device reliability and performance.
Smart Images
Figure CN120127006A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a method for optimizing polysilicon residue on an SGT structure. Background Art
[0002] The SGT (Shield Gate Trench) MOS device structure has been widely applied to the field of medium and low voltage devices due to its advantages of low on-resistance and small Miller capacitance.
[0003] Due to the increasing demand for breakdown voltage of SGT products, the thickness of the required field oxide is getting thicker. Under the current process conditions, there will be a step difference after HDP deposition at the junction between the AA region (active region) and the GR (Dummy) region, and the existence of the step difference will cause a relatively thick oxide layer to remain in the GR (Dummy) region after AA HDP wet etching, resulting in obvious Poly residue in the oxide layer thickness transition region and the position with relatively thick oxide layer after subsequent GatePoly (gate polysilicon) etching (as Figure 1 and Figure 2 shown); and the Poly residue in the transition region between the AA region and the GR (Dummy) region will connect the Gate (gate) lead-out region and the Source (source) lead-out region, resulting in G / S short-circuit of the device; at the same time, the polysilicon residue in the region with relatively thick oxide layer causes the CT (contact hole) to be unable to be opened normally, resulting in a decrease in the Schottky breakdown voltage (BV Drop).
[0004] Currently, in view of the problem of excessive Poly residue in the oxide layer thickness transition region and the region with relatively thick oxide layer of SGT, over-etching is used for improvement, but simply increasing the over-etching amount (OE amount) of Poly etching can no longer meet the requirements of the Poly morphology in both the Cell and GR regions at the same time. Summary of the Invention
[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for optimizing polysilicon residue on an SGT structure, which is used to solve the problem that the existing G / S short-circuit causes device failure.
[0006] To achieve the above purpose and other related purposes, the present invention provides a method for optimizing polysilicon residue on an SGT structure, and the method includes:
[0007] A semiconductor structure is provided, which includes a substrate, deep trenches, a field oxide layer, and a shield gate polysilicon layer. The substrate includes an AA region and a Dummy region. The deep trenches are formed in the substrate at intervals. The field oxide layer is formed at the bottom and sidewalls of the deep trenches and extends to the surface of the substrate. The shield gate polysilicon layer fills the deep trenches and extends to the surface of the field oxide layer above the substrate. Wherein, the thickness of the field oxide layer is greater than
[0008] Use a first etching process to etch the shield gate polysilicon layer until its height is flush with the height of the field oxide layer on the surface of the substrate;
[0009] Thin the field oxide layer so that the thickness of the field oxide layer formed on the surface of the substrate is less than or equal to
[0010] Use a second etching process to etch the shield gate polysilicon layer until its height is flush with the height of the substrate surface;
[0011] Use an etching process to remove the shield gate polysilicon layer with a preset depth in the deep trenches to form shallow trenches, wherein the deep trenches are deep trenches formed in the AA region;
[0012] Fill a control gate polysilicon layer in the shallow trenches.
[0013] Optionally, the field oxide layer is formed by a thermal oxidation process and / or a CVD process.
[0014] Optionally, the first etching process and the second etching process are dry etching.
[0015] Optionally, use a wet etching process to thin the field oxide layer.
[0016] Optionally, after the field oxide layer is thinned, its thickness is
[0017] Optionally, the method of using an etching process to remove the shield gate polysilicon layer with a preset depth in the deep trenches to form the shallow trenches includes:
[0018] Use a third etching process to etch the shield gate polysilicon layer to form an HDP filling trench in the deep trench;
[0019] Use a wet etching process to thin the field oxide layer on the sidewalls of the HDP filling trench and the surface of the substrate to widen the width of the HDP filling trench;
[0020] Use an HDP filling process to form a filler in the widened HDP filling trench;
[0021] The filler is removed by wet etching to obtain the shallow trench. At this time, the shallow trench is the HDP filling trench without the field oxide layer on its sidewalls.
[0022] Optionally, when etching the shield gate polysilicon layer by the third etching process to form the HDP filling trench in the deep trench, a protective layer is formed on the Dummy region.
[0023] Optionally, the protective layer includes photoresist.
[0024] Optionally, the third etching process is dry etching.
[0025] Optionally, when forming the filler in the HDP filling trench by the HDP filling process, the filler extends to the Dummy region.
[0026] Optionally, before filling the control gate polysilicon layer in the shallow trench, the method further includes a step of forming a gate oxide layer, and the gate oxide layer is formed on the bottom and sidewalls of the shallow trench.
[0027] Optionally, the control gate polysilicon layer and the gate oxide layer are formed by a furnace tube process.
[0028] Optionally, the substrate is a silicon substrate.
[0029] As described above, the method for reducing polysilicon residue on the optimized SGT structure of the present invention etches the shield gate polysilicon layer in two steps, and adds a step of thinning the field oxide layer between the two steps. By the above method, side etching of the field oxide layer on both sides of the shield gate polysilicon layer can be avoided, and at the same time, the thickness of the field oxide layer in the AA region and the Dummy region can be effectively thinned, effectively improving the polysilicon residue formed in the subsequent Dummy region, and thus solving the problem of device failure caused by G / S short circuit. Description of the Drawings
[0030] Figure 1 A transmission electron microscopy image showing polysilicon residue in the existing oxide layer thickness transition region.
[0031] Figure 2 A transmission electron microscopy image showing polysilicon residue in the existing region with a relatively thick oxide layer.
[0032] Figures 3 to 14 A cross-sectional structure schematic diagram showing the process of forming the control gate of the present invention.
[0033] Figure 15 A flowchart showing the method for reducing polysilicon residue on the optimized SGT structure of the present invention.
[0034] Description of the Attached Reference Numerals
[0035] 10: Semiconductor structure; 11: Substrate; 12: Deep trench; 13: Field oxide layer; 14: Shield gate polysilicon layer; 20: Shallow trench; 30: HDP filled trench; 40: Filler; 50: Protective layer; 60: Control gate polysilicon layer Detailed Embodiment
[0036] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0037] Please refer to Figures 1 to 15 . It should be noted that the drawings provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation, the form, number, and ratio of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.
[0038] As Figure 15 shown, this embodiment provides a method for optimizing polysilicon residue on an SGT structure. The method includes: step 1), step 2), step 3), step 4), step 5), and step 6).
[0039] As Figures 3 to 5 shown, in step 1), a semiconductor structure 10 is provided, which includes a substrate 11, a deep trench 12, a field oxide layer 13, and a shield gate polysilicon layer 14. The substrate 11 includes an AA region and a Dummy region. The deep trenches 12 are formed at intervals in the substrate 11. The field oxide layer 13 is formed at the bottom, sidewalls of the deep trenches 12 and extends to the surface of the substrate 11. The shield gate polysilicon layer 14 fills the deep trenches 12 and extends to the surface of the field oxide layer 13 above the substrate 11. Among them, the thickness of the field oxide layer 13 is greater than
[0040] As Figure 3 shown, in this embodiment, the deep trenches 12 are formed by etching the substrate 11. The number of them is multiple and they are distributed in the AA region and the Dummy region.
[0041] Specifically, the substrate 11 is a silicon substrate.
[0042] Specifically, the field oxide layer 13 is formed by a thermal oxidation process and / or a CVD process. AsFigure 4 As shown, in this embodiment, the material of the field oxide layer 13 includes silicon oxide.
[0043] As Figure 6 shown, in step 2), the first etching process is used to etch the shield gate polysilicon layer 14 until its height is flush with the height of the field oxide layer 13 on the surface of the substrate 11.
[0044] Specifically, the first etching process and the second etching process are dry etching.
[0045] As Figure 7 shown, in step 3), the field oxide layer 13 is thinned so that the thickness of the field oxide layer 13 formed on the surface of the substrate 11 is less than or equal to
[0046] Specifically, the wet etching process is used to thin the field oxide layer 13.
[0047] Specifically, after the field oxide layer 13 is thinned, its thickness is
[0048] In this embodiment, by thinning the field oxide layer 13, the side etching phenomenon of the field oxide layer 13 on both sides of the shield gate polysilicon 14 is avoided, and at the same time, the thickness of the field oxide layer 13 on the surface of the substrate 11 in the AA region and the Dummy region is effectively thinned in advance, effectively improving the polysilicon (Poly) residue formed in the Dummy region (the oxide layer thickness transition region and the position with a relatively thick oxide layer thickness), and solving the problem of device failure caused by G / S short circuit.
[0049] As Figure 8 shown, in step 4), the second etching process is used to etch the shield gate polysilicon layer 14 until its height is flush with the height of the surface of the substrate 11.
[0050] As Figures 9 to 13 shown, in step 5), the etching process is used to remove the shield gate polysilicon layer 14 with a preset depth in the deep trench 12 to form a shallow trench, where the deep trench 12 is the deep trench 12 formed in the AA region;
[0051] Specifically, the method for forming the shallow trench 20 by removing the shield gate polysilicon layer 14 with a preset depth in the deep trench 12 includes: Step 51) etching the shield gate polysilicon layer 14 by a third etching process to form an HDP filling trench 30 in the deep trench 12; Step 52) thinning the field oxide layer 13 located on the sidewall of the HDP filling trench 30 and the surface of the substrate 11 by a wet etching process to widen the width of the HDP filling trench 30; Step 53) forming a filler 40 in the widened HDP filling trench 30 by an HDP filling process; Step 54) removing the filler 40 by a wet etching process to obtain the shallow trench 20. At this time, the shallow trench 20 is the HDP filling trench 30 without the field oxide layer 13 on its sidewall.
[0052] More specifically, when etching the shield gate polysilicon layer 14 by the third etching process to form the HDP filling trench 30 in the deep trench 12, a protective layer 50 is formed on the Dummy area.
[0053] As an example, the protective layer 50 includes photoresist.
[0054] More specifically, the third etching process is a dry etching process.
[0055] Specifically, when forming the filler 40 in the HDP filling trench 30 by the HDP filling process, the filler 40 extends to the Dummy area.
[0056] In this embodiment, before performing Step 54), the method includes a step of removing the protective layer 50. Therefore, the filler 40 is also formed on the Dummy area. Moreover, when removing the filler 40 by a wet etching process to obtain the shallow trench 20, the filler 40 formed in the Dummy area is also removed, but the filler 40 formed in the Dummy area cannot be completely removed during the actual operation. Therefore, in Figure 13 and Figure 14 the uneven pattern is used to represent the incompletely removed filler 40. It should be noted that the incompletely removed filler 20 is a relatively flat film layer, which has no influence on the subsequent processes and the electrical properties of the device.
[0057] As Figure 14 shown, Step 6) fills the control gate polysilicon layer 60 in the shallow trench 20.
[0058] In this embodiment, when forming the control gate polysilicon layer 60, the control gate polysilicon layer 60 is also formed in the Dummy region and then removed. Since the thickness of the field oxide layer 13 is thinned, the step difference of the filler 40 in the AA region and the Dummy region is small. When removing the filler 40 formed in the Dummy region, less of the filler 40 remains, so that when removing the control gate polysilicon layer 60 formed in the Dummy region, less polysilicon remains in the Dummy region, thereby avoiding G / S short circuit of the device.
[0059] Specifically, before filling the control gate polysilicon layer 60 in the shallow trench 20, the method further includes a step of forming a gate oxide layer, and the gate oxide layer is formed on the bottom and side walls of the shallow trench 20.
[0060] In this embodiment, the gate oxide layer is also formed on the surface of the substrate 11 in the AA region. Moreover, the material of the gate oxide layer is the same as that of the field oxide layer 13, both being silicon oxide.
[0061] More specifically, the control gate polysilicon layer 60 and the gate oxide layer are formed by a furnace tube process.
[0062] In summary, the method for reducing polysilicon residue on the optimized SGT structure of the present invention etches the shielding gate polysilicon layer in two steps and adds a step of thinning the field oxide layer between the two steps. By the above method, side etching of the field oxide layer on both sides of the shielding gate polysilicon layer can be avoided, and the thickness of the field oxide layer in the AA region and the Dummy region can be effectively thinned, effectively improving the polysilicon residue formed in the Dummy region subsequently, and further solving the problem of device failure caused by G / S short circuit. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0063] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for optimizing polysilicon residue on an SGT structure, characterized in that: The method comprises: A semiconductor structure is provided, which includes a substrate, a deep trench, a field oxide layer and a shielding gate polysilicon layer, wherein the substrate includes an AA region and a Dummy region, the deep trench is spaced apart and formed in the substrate, the field oxide layer is formed at the bottom and sidewall of the deep trench and extends to the surface of the substrate, the shielding gate polysilicon layer fills the deep trench and extends to the surface of the field oxide layer above the substrate, wherein the thickness of the field oxide layer is greater than Etching the shield gate polysilicon layer by a first etching process until its height is flush with the height of the field oxide layer located on the surface of the substrate; The field oxide layer is thinned so that the thickness of the field oxide layer formed on the surface of the substrate is less than or equal to Etching the shield gate polysilicon layer by a second etching process until its height is flush with the height of the substrate surface; Using an etching process to remove the shield gate polysilicon layer at a preset depth in the deep trench to form a shallow trench, wherein the deep trench is a deep trench formed in the AA region; A control gate polysilicon layer is filled in the shallow trench.
2. The method for optimizing polysilicon residue on SGT structure according to claim 1, characterized in that: The field oxide layer is formed by a thermal oxidation process and / or a CVD process.
3. The method for optimizing polysilicon residue on SGT structure according to claim 1, characterized in that: The first etching process and the second etching process are dry etching.
4. The method for optimizing polysilicon residue on SGT structure according to claim 1, characterized in that: The field oxide layer is thinned by using a wet etching process.
5. The method for optimizing polysilicon residue on SGT structure according to claim 4, characterized in that: After the field oxide layer is thinned, its thickness is 6. The method for optimizing polysilicon residue on SGT structure according to claim 1, characterized in that: The method of removing the shield gate polysilicon layer to a preset depth in the deep trench by an etching process to form the shallow trench comprises: Etching the shield gate polysilicon layer using a third etching process to form a HDP filling trench in the deep trench; Thinning the field oxide layer located on the sidewall of the HDP filling trench and the surface of the substrate by a wet etching process to widen the width of the HDP filling trench; forming a filling material in the widened HDP filling trench by using a HDP filling process; The filler is removed by wet etching to obtain the shallow trench. At this time, the shallow trench is the HDP filled trench without the field oxide layer on the sidewall.
7. The method for optimizing polysilicon residue on SGT structure according to claim 6, characterized in that: When the shield gate polysilicon layer is etched by the third etching process to form the HDP filling trench in the deep trench, a protection layer is formed on the Dummy region.
8. The method for optimizing polysilicon residue on SGT structure according to claim 7, characterized in that: The protection layer includes photoresist.
9. The method for optimizing polysilicon residue on SGT structure according to claim 6, characterized in that: The third etching process is dry etching.
10. The method for optimizing polysilicon residue on SGT structure according to claim 1, characterized in that: When the filling material is formed in the HDP filling trench by utilizing the HDP filling process, the filling material extends to the Dummy region.
11. The method for optimizing polysilicon residue on SGT structure according to claim 1, characterized in that Before the control gate polysilicon layer is filled in the shallow trench, the method further includes the step of forming a gate oxide layer, and the gate oxide layer is formed on the bottom and sidewalls of the shallow trench.
12. The method for optimizing polysilicon residue on SGT structure according to claim 11, characterized in that: The control gate polysilicon layer and the gate oxide layer are formed by a furnace tube process.
13. The method for optimizing polysilicon residue on SGT structure according to claim 1, characterized in that: The substrate is a silicon substrate.