Power package with multiple molding compounds

Abstract

A semiconductor device package includes a lead frame, a first power semiconductor device mounted on a first portion of the lead frame, and a second power semiconductor device mounted on a second portion of the lead frame. The first power semiconductor device is encapsulated by a first molding compound. The second power semiconductor device is encapsulated by a second molding compound. The first molding compound and the second molding compound are substantially separated from each other. The lead frame includes an intermediate portion disposed between a first portion and a second portion. The intermediate portion is not covered by the first molding compound or by the second molding compound.

Description

Technical Field

[0001] The present disclosure generally relates to the technology of semiconductor device packaging, and particularly relates to aspects of packaging power semiconductor devices that provide product-to-system improvements and high power dissipation capabilities. Background Art

[0002] Semiconductor device manufacturers continuously strive to increase the performance of their products while reducing the costs of their manufacturing and system integration. The performance of a semiconductor device depends on the heat dissipation capability provided by the package. Additionally, a package that can be easily implemented in a system with high thermal robustness at low overhead is desired. Summary of the Invention

[0003] One aspect of the present disclosure relates to a semiconductor device package. The semiconductor device package includes a lead frame, a first power semiconductor device mounted on a first portion of the lead frame, and a second power semiconductor device mounted on a second portion of the lead frame. The first power semiconductor device is encapsulated by a first mold compound. The second power semiconductor device is encapsulated by a second mold compound. The first mold compound and the second mold compound are substantially separated from each other. The lead frame includes an intermediate portion disposed between the first portion and the second portion, and the intermediate portion is not covered by the first mold compound or the second mold compound.

[0004] One aspect of the present disclosure relates to a power semiconductor system. The power semiconductor system includes a semiconductor device package that includes a lead frame, a first power semiconductor device mounted on a first portion of the lead frame, and a second power semiconductor device mounted on a second portion of the lead frame. The first power semiconductor device is encapsulated by a first mold compound. The second power semiconductor device is encapsulated by a second mold compound. The first mold compound and the second mold compound are substantially separated from each other. The lead frame includes an intermediate portion disposed between the first portion and the second portion, and the intermediate portion is not covered by the first mold compound or the second mold compound. The power semiconductor system further includes at least one heat sink thermally and mechanically coupled to the first mold compound and the second mold compound.

[0005] One aspect of the present disclosure relates to a method of manufacturing a semiconductor device package. The method includes mounting a first power semiconductor device on a first portion of a lead frame and mounting a second power semiconductor device on a second portion of the lead frame. Encapsulating the first power semiconductor device with a first mold compound. Encapsulating the second power semiconductor device with a second mold compound. The first mold compound and the second mold compound are substantially separated from each other. The lead frame includes an intermediate portion disposed between the first portion and the second portion, and the intermediate portion is not covered by the first mold compound or the second mold compound. Brief Description of the Drawings

[0006] The accompanying drawings are included to provide a further understanding of the various aspects and are incorporated into and form a part of this specification. The drawings illustrate the various aspects and, together with the description, are used to explain the principles of the various aspects. Many other aspects and many of the expected advantages thereof will be readily apparent, as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals may designate corresponding like parts. It is to be understood that the features of the various examples of the embodiments described below may be combined with each other, unless specifically noted otherwise.

[0007] Figure 1A is a cross-sectional view of an example of a semiconductor device package 100 according to various embodiments.

[0008] Figure 1B is a top view of the semiconductor device package 100 before encapsulation according to various embodiments.

[0009] Figure 2 is a cross-sectional view of an example of a semiconductor device package 200 according to various embodiments.

[0010] Figure 3A is a cross-sectional view of an example of a semiconductor device package 300 according to various embodiments.

[0011] Figure 3B is a top view of the semiconductor device package 300 before encapsulation according to various embodiments.

[0012] Figure 4 is a cross-sectional view of an example of a semiconductor device package 400 according to various embodiments.

[0013] Figure 5 is a perspective top view of an array of semiconductor device packages 500, each including first and second package bodies, in a manufacturing process stage before lead separation.

[0014] Figure 6 is Figure 5 a perspective top view of an array of semiconductor device packages 500 in a manufacturing process stage before encapsulating first and second power semiconductor devices in first and second molding compounds, respectively.

[0015] Figure 7 is a cross-sectional view of an example of a semiconductor device package 700 along line A-A Figure 6 after encapsulation.

[0016] Figure 8A is a perspective view of a lead frame in a manufacturing process stage before mounting first and second power semiconductor devices thereon.

[0017] Figure 8BIs a perspective view of an example of a semiconductor device package 800 including first and second encapsulation bodies.

[0018] Figure 8C Is another perspective view of the semiconductor device package 800.

[0019] Figure 8D Is another perspective view of the semiconductor device package 800 showing the interior of the encapsulation body by a cut-away molded plastic.

[0020] Figure 9A Is a partial (one encapsulation body) perspective view of an example of a semiconductor device package 900 including a lead frame exposed at the bottom of the semiconductor device package.

[0021] Figure 9B Is a perspective view of a semiconductor device package 900', which corresponds to the semiconductor device package 900 having a thermal interface material (TIM) applied to the exposed surface of the lead frame.

[0022] Figure 9C Is Figure 9B A cross-sectional view of an example of the semiconductor device package 900'.

[0023] Figure 10A Is a perspective top view of a lead frame 1020 having a cutout serving as a hybrid lead frame in a manufacturing process stage before mounting first and second power semiconductor devices on the lead frame.

[0024] Figure 10B Is a top view of an example of a power semiconductor device pad and a power semiconductor device mounted thereon, which is configured to be inserted into Figure 10A The cutout of the lead frame.

[0025] Figure 10C Is Figure 10B A perspective bottom view of the power semiconductor device pad.

[0026] Figure 10D Is a partial perspective top view of an array of semiconductor device packages 1000 in a manufacturing process stage before encapsulating first and second power semiconductor devices in first and second molded plastics, respectively.

[0027] Figure 10E Is a perspective top view of the semiconductor device package 1000 showing the interior of one encapsulation body by a cut-away molded plastic.

[0028] Figure 10F Is a perspective bottom view of the semiconductor device package 1000 showing the lead frame exposed from the first and / or second molded plastics.

[0029] Figure 11AIt is a perspective view of a semiconductor device package 1100 having a first package body and a second package body that are bent relative to each other.

[0030] Figure 11B It is a perspective view of a semiconductor device package 1100 showing the inside of the package body by cutting the molded compound.

[0031] Figure 12A It is a perspective view of a semiconductor device package 1200 implementing a three-phase bridge circuit, where the number of package bodies is 6.

[0032] Figure 12B It is Figure 12A Another perspective view of the semiconductor device package 1200, where one package body is cut.

[0033] Figure 13 It is a cross-sectional view of an example of a power system 1300 having a common heat sink with a first package body and a second package body that are thermally and mechanically coupled to the semiconductor device package.

[0034] Figure 14A It is a perspective view of a semiconductor device package 1400 having two package bodies.

[0035] Figure 14B It is Figure 14A A perspective view of the semiconductor device package 1400 having a first package body and a second package body that are bent relative to each other.

[0036] Figure 15A It is a perspective view of a semiconductor device package 1500 having 6 package bodies.

[0037] Figure 15B It is Figure 15A A perspective view of the semiconductor device package 1500 having a first and a second package body that are bent relative to each other.

[0038] Figure 16 It is having a thermal and mechanical coupling to Figure 15B A perspective view of an example of a power system 1600 having a common heat sink of the semiconductor device package.

[0039] Figure 17 It is, for example, in Figures 12A - 12B And a circuit diagram of a three-phase bridge 1700 implemented in semiconductor device packages 15A - 15B.

[0040] Figure 18 It is a flowchart illustrating stages of an exemplary method of manufacturing a semiconductor device package according to the present disclosure. Detailed Description

[0041] In the following detailed description, reference is made to the accompanying drawings which form a part hereof and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. As used in this specification, the terms "bonded", "attached", "connected", "mounted", "coupled", and / or "electrically connected / electrically coupled" do not necessarily mean that elements or layers must be in direct contact with each other; elements that are "interposed", "attached", "connected", "mounted", "coupled", and / or "electrically connected / electrically coupled" respectively. However, according to the present disclosure, the above-mentioned terms may also optionally have the specific meaning that elements or layers are in direct contact with each other, that is, no intervening elements or layers are provided between the elements that are "bonded", "attached", "connected", "mounted", "coupled", and / or "electrically connected / electrically coupled" respectively.

[0042] In addition, the term "on" used with respect to a portion, element, or layer of material formed or located "on" a surface may be used herein to mean that the portion, element, or layer of material is "directly" located (e.g., placed, formed, deposited, etc.) on the implied surface, e.g., in direct contact with the implied surface. The term "on" used with respect to a portion, element, or layer of material formed or located "on" a surface may be used herein to mean that the portion, element, or layer of material is "indirectly" located (e.g., placed, formed, deposited, etc.) on the implied surface, with one or more additional portions, elements, or layers disposed between the implied surface and the portion, element, or layer of material.

[0043] The semiconductor device packages described herein include at least two molding compounds. Each molding compound may form a package body of the semiconductor device package. Each molding compound may include a power semiconductor device. Each power semiconductor device may include one or more power semiconductor chips. The semiconductor power chips (e.g., one or more transistors, e.g., one or more transistors of any of the types recited below) may be monolithically integrated.

[0044] More specifically, the power semiconductor chips may be configured, for example, as power MISFETs (metal-insulator-semiconductor field effect transistors), power MOSFETs (metal-oxide-semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), JFETs (junction gate field effect transistors), HEMTs (high electron mobility transistors), power bipolar transistors, or power diodes (such as, for example, PIN diodes or Schottky diodes).

[0045] (Multiple) power semiconductor chips can, for example, have a vertical structure, i.e., (multiple) semiconductor chips can be manufactured in such a way that current can flow in a direction perpendicular to the main surface of the (multiple) semiconductor chips. A semiconductor chip with a vertical structure has electrodes on its two main surfaces (i.e., on its top side and bottom side). As an example, in a vertical device, the source contact electrode and the gate contact electrode of a power MISFET or a power MOSFET or a power JFET or a HEMT can be located on one main surface, while the drain contact electrode of the power MISFET or the power MOSFET or the power JFET or the power HEMT can be arranged on the other main surface. Similarly, in a bipolar transistor vertical device, the emitter contact electrode and the gate contact electrode of a power IGBT can be located on one main surface, while the collector contact electrode of the power IGBT can be arranged on the other main surface. In the case of a power diode, the anode contact electrode can be located on one main surface, while the cathode contact electrode of the power diode can be arranged on the other main surface. Additionally, it is also possible that the drain (collector) contact electrode and the gate contact electrode are located on one main surface, while the source (emitter) contact electrode is located on the other main surface.

[0046] Furthermore, a semiconductor device package may be involved that includes (multiple) semiconductor chips having a horizontal structure. A semiconductor chip with a horizontal structure has chip electrodes only on one of its two main surfaces (e.g., on its active surface). Logic integrated circuit chips as well as power semiconductor chips (such as a power MISFET or a power MOSFET or a power JFET or a power HEMT) can have a horizontal structure.

[0047] The semiconductor chip can be made of a specific semiconductor material (such as, for example, Si, SiC, SiGe, GaAs, GaN, AlGaN, InGaAs, InAlAs, etc.), and further may include inorganic and / or organic materials that are not semiconductors. In particular, the semiconductor chip is made of multiple layers of the above materials. For example, a gallium nitride on silicon chip or a gallium nitride on silicon carbide chip may be involved. The semiconductor chip can have different types and can be manufactured by different technologies.

[0048] The semiconductor chip may have electrodes (chip pads) that allow electrical contact with the integrated circuit included in the semiconductor chip. The electrodes may include one or more metal layers applied to the semiconductor material of the semiconductor chip. The metal layer may be fabricated with any desired geometry and any desired material composition. The metal layer may, for example, take the form of a layer or land covering an area. As an example, any desired metal (e.g., Cu, Ni, NiSn, Au, Ag, Pt, Pd, In, Sn) capable of forming a soldering bond or a diffusion bonding and alloys of one or more of these metals may be used as the material. The metal layer need not be uniform or made of only one material, that is, various compositions and concentrations of the materials included in the metal layer are possible.

[0049] The semiconductor device package described herein includes a conductive lead frame. The lead frame may be encapsulated in a first molding compound forming a first package body and a second molding compound forming a second package body. The lead frame may include a single (i.e., not formed by a plurality of pieces joined together) intermediate portion that is not covered by the first molding compound or the second molding compound.

[0050] The lead frame may form part of a structured metal sheet. The structured metal sheet may be made of any metal or metal alloy (e.g., copper or a copper alloy).

[0051] Each package body may include a power semiconductor device encapsulated in the molding compound. Each of the molding compounds may form part of the periphery of the corresponding package body, that is, may at least partially define the shape of the semiconductor package body.

[0052] The molding compound is made of at least one encapsulating material. The encapsulating material may be an electrically insulating material. The encapsulating material may include or be a thermosetting material or a thermoplastic material. The thermosetting material may be made, for example, on the basis of an epoxy resin, a silicone resin, or an acrylic resin. The thermoplastic material may include, for example, one or more materials selected from the group consisting of polyetherimide (PEI), polyethersulfone (PES), polyphenylene sulfide (PPS), polyamide-imide (PAI), and polyethylene terephthalate (PET). The thermoplastic material melts during molding or lamination by applying pressure and heat and hardens (reversibly) upon cooling and release of pressure.

[0053] The encapsulation material can include, or be, a polymeric material such as a rigid plastic polymeric material. The encapsulation material can include filled or unfilled mold material, filled or unfilled thermoplastic material, filled or unfilled thermosetting material, filled or unfilled laminate material, fiber-reinforced laminate material, fiber-reinforced polymeric laminate material, and fiber-reinforced polymeric laminate material having filler particles, or at least one of the materials.

[0054] The encapsulation material is a mold material. The encapsulation material can be applied to a power semiconductor device (such as a semiconductor chip) and a lead frame by molding. Various techniques (such as, for example, compression molding, injection molding, powder molding, liquid molding, transfer molding, or film-assisted molding (FAM)) can be used to form the molding compound.

[0055] A variety of different types of electronic power devices and / or power systems can be configured to use the semiconductor device package as described herein. As an example, an electronic power device and / or power system according to the present disclosure can constitute, for example, an engine control unit (ECU), a power supply, a DC-DC voltage converter, an AC-DC voltage converter, a power amplifier, and many other devices.

[0056] Generally, any power device and / or power system including at least two package bodies (including at least one semiconductor power device or chip having a high thermal power loss for dissipating heat power and / or a relatively small footprint) can benefit from the disclosure herein. As an example, having a thermal power loss equal to or greater than, for example, 1 W, 10 W, 20 W, 50 W, 100 W, 200 W, 300 W, 400 W, 500 W, or 1000 W in operation and, for example, and equal to or less than, for example, 200 mm 2 、150 mm 2 、100 mm 2 、50 mm 2 、25 mm 2 、10 mm 2 、5 mm 2 、3 mm 2 、or 1 mm 2 of footprint for thermal power dissipation of a semiconductor power chip can use the multi-body power package as described herein for improved handling during product-to-system assembly and thermal performance and power dissipation during operation.

[0057] Figure 1A A cross-sectional view showing an example of the semiconductor device package 100 and Figure 1BShows a top view of a semiconductor device package 100 before encapsulation. The semiconductor device package 100 includes a first molding compound 114 and a second molding compound 124 (shown in dashed lines in Figure 1B ). The first power semiconductor device 112 is encapsulated by the first molding compound 114 that can form a first package body 110. The second power semiconductor device 122 is encapsulated by the second molding compound 124 that can form a second package body 120. The first molding compound 114 and the second molding compound 124 are substantially separated from each other. Throughout this disclosure, the term "substantially separated" may mean, for example, that there may be no connection of encapsulation material between the first molding compound 114 and the second molding compound 124 or there may be only an insignificant connection of encapsulation material between the first molding compound 114 and the second molding compound 124, which is not rigid and / or non - bendable and / or bulky enough to transfer mechanical properties (such as mechanical stress from one molding compound 114, 124 to the other molding compounds 124, 114). In other words, the first and second molding compounds 114, 124 are mechanically decoupled from each other with respect to any stress - transfer coupling via the encapsulation material.

[0058] The first power semiconductor device 112 is mounted on a first portion of the lead frame 130 and the second power semiconductor device 122 is mounted on a second portion of the lead frame 130. The lead frame 130 mechanically and electrically connects the first molding compound 114 and the second molding compound 124. More specifically, the first portion of the lead frame 130 can be cast in the first molding compound 114 and the second portion of the lead frame 130 can be cast in the second molding compound 124.

[0059] The lead frame 130 can have a first main surface 130A and a second main surface 130B opposite to the first main surface 130A. The first power semiconductor device 112 and the second power semiconductor device 122 can be mounted on the same main surface of the lead frame 130, for example, on the first main surface 130A.

[0060] The lead frame 130 is encapsulated by the first molding compound 114 and by the second molding compound 124. An intermediate portion 132 of the lead frame 130 disposed between the first portion and the second portion can be exposed from the first molding compound 114 and from the second molding compound 124. More specifically, the first surface 130A of the intermediate portion 132 of the lead frame 130 and / or the second surface 130B of the intermediate portion 132 of the lead frame 130 may be exposed by both the first and second molding compounds 114, 124 (i.e., exposed from both the first and second molding compounds 114, 124).

[0061] It should be noted that the middle part 132 is an integral part of the lead frame 130 (which is a single component). That is to say, the middle part 132 does not provide a bonding joint (such as a welding joint, a soldering joint, an adhesive joint, etc.) through which the lead frame 130 will be made of more than one part. More precisely, although the first molding compound 114 that defines the first package body 110 and the second molding compound 124 that defines the second package body 120 are separated from each other, the single lead frame 130 can be an integral part that inherently becomes a part of the two package bodies 110, 120.

[0062] In addition, the middle part 132 of the lead frame 130 can have inherent structural stability sufficient to hold the first package body 110 and the second package body 120 in place, even without being supported by other holding devices. That is to say, rather than being a flexible package carrier (such as a flexible PCB, for example), the lead frame 130 and particularly its middle part 132 can provide sufficient hardness and / or stiffness to control the positional relationship between the first molding compound 114 and the second molding compound 124 without any further holding or supporting devices. In this regard, the semiconductor device package 100 can be regarded as a single semiconductor package having a spacing 140 (such as a continuous spacing) between the first molding compound 114 and the second package 124, and the second package 124 exposes at least one main surface 130A, 130B of the lead frame 130 and separates the first molding compound 114 from the second molding compound 124 (or in other words separates the first package body 110 from the second package body 120). The middle part 132 of the lead frame can form a power lead connecting a plurality (here two, for example) of molding compounds 114, 124 (or package bodies 110, 120).

[0063] The middle part 132 of the lead frame 130 can be plastically deformable by bending to allow the first molding compound 114 and the second molding compound 124 to be brought into a defined spatial relationship with respect to each other (not shown in FIG. 1).

[0064] In various embodiments, the lead frame 130 can also be a hybrid carrier composed of, for example, a lead frame and any other substrate, as will be described in further detail below.

[0065] In some embodiments, the lead frame 130 can have a constant thickness along its extension. For example, particularly the thickness of the middle part 132 can be the same as the thickness in the part of the lead frame 130 that is encapsulated by the first molding compound 114 and / or the second molding compound 124. In other embodiments, the lead frame 130 can have different thicknesses along its extension, as will be described in further detail below.

[0066] The breakdown of a large package body into a multi-body package design as disclosed herein may be beneficial in several aspects: First, the larger the area (or diagonal length) of the molding compound (package body), the more mechanical stress is generated in the package due to the CTE (coefficient of thermal expansion) mismatch of the various materials of the package (such as the carrier, encapsulation material, chip material). Therefore, it may be beneficial to break down a large molding compound (package body) into multiple smaller molding compounds (package bodies) in order to avoid the detrimental effects based on CTE mismatch (such as package warpage, degradation of thermal contact to the heat sink, reliability in the case of large temperature cycles). In addition, the separation of the first and second molding compounds from each other allows for separation taking into account the thermal load experienced by the molding compounds. As an example, temperature-sensitive components (such as, for example, logic integrated circuits (ICs) or sensors and / or actuators) can be placed in a molding compound that has a lower thermal load or peak temperature than another molding compound that houses more temperature-resistant components (such as, for example, power switches).

[0067] Figure 2 A cross-sectional view showing an example of a semiconductor device package 200. The semiconductor device package 200 is similar to the semiconductor device package 100, except that the second surface 130B of the lead frame 130 may remain completely exposed by the first molding compound 114 of the first package body 110 and the second molding compound 124 of the second package body 120 or at least partially within the outline of the molding compounds 114, 124. Other features are disclosed in connection with the semiconductor device package 100, and reference is made to its description to avoid repetition.

[0068] Figure 3A A cross-sectional view showing an example of a semiconductor device package 300, and Figure 3B a top view showing the semiconductor device package 300 before encapsulation. The semiconductor device package 300 may be similar or identical to the semiconductor device package 100, except that the lead frame 130 is a hybrid carrier, also referred to hereinafter as the hybrid lead frame 330. The hybrid lead frame 330 may include a common frame structure 330_1, 330_2, 330_3 and two power semiconductor device pads 332_1, 332_2. The common frame structure 330_1, 330_2, 330_3 is a lead frame. The middle portion 132 of the lead frame 130 (here the hybrid lead frame 330) is formed by the common frame structure 330_2. Generally, at least one opening 330_1 may be provided in the common frame structure 330_1, 330_2, 330_3 and at least one power semiconductor device pad 332_1 may be inserted into this opening. In other words, although one of the package bodies 110, 120 may have a design as shown in Figure 1A , 1B shown, the other package bodies 120, 110 may be according to Figure 3A ,3B Designed.

[0069] Each of the first power semiconductor device pad 332_1 and the second power semiconductor device pad 332_2 can be selected from the group consisting of, for example, an insulated metal substrate (IMS), a metal substrate (such as a metal plate (e.g., a copper plate), a metal composite plate (e.g., a copper composite plate)), a ceramic-based substrate (in particular a direct bonded copper (DBC) substrate, a ceramic thick film coated substrate), an active metal brazing (AMB) substrate, or a printed circuit board (PCB). The first and second power semiconductor device pads 332_1, 332_2 can be formed as inlays to fit into the first and second cutouts or openings 335_1, 335_2 in the common frame structures 330_1, 330_2, 330_3. The first and second power semiconductor device pads 332_1, 332_2 can have higher thermal and / or electrical conduction characteristics (i.e., lower thermal resistance and / or lower resistance) than the common frame structures 330_1, 330_2, 330_3 (e.g., lead frames) to provide advanced heat dissipation and / or conductivity.

[0070] As shown in Figure 3A and 3B The first and second power semiconductor device pads 332_1, 332_2 can be completely encapsulated by the first molding compound 114 and the second molding compound 124, respectively. That is, except for the regions where the first and second power semiconductor devices 112, 122 are bonded thereto, the entire periphery including the sides of the first and second power semiconductor device pads 332_1, 332_2 can be covered by the encapsulating material. The first molding compound 114 and the second molding compound 124 are shown in dashed lines in Figure 3B A cross-sectional view illustrating an example of the semiconductor device package 400. The semiconductor device package 400 can be similar or identical to the semiconductor device package 300, except that the bottom surfaces of the common frame structures 330_1, 330_2, 330_3 and / or the bottom surfaces of the first and second power semiconductor device pads 332_1, 332_2 are completely exposed by the first molding compound 114 and the second molding compound 124, or at least partially within the profiles of the molding compounds 114, 124. Thus, similar to

[0071] Figure 4 the exposed second surface 130B of the lead frame 130 in Figure 2 direct thermal and electrical contact to the bottom surfaces of the first and second power semiconductor device pads 332_1, 332_2 can be achieved, and if desired, direct thermal and electrical contact to the bottom surfaces of the common frame structures 330_1, 330_2, 330_3 can also be achieved. In addition, although one of the package bodies 110, 120 can have as in Figure 2the design shown in, but other package bodies 120, 110 can be designed according to Figure 4 to design.

[0072] The common frame structures 330_1, 330_2, 330_3 can be made of the same material as the first and second power semiconductor device pads 332_1, 332_2 or can be made of a material different from the first and second power semiconductor device pads 332_1, 332_2. The first power semiconductor device pad 332_1 can be made of the same material as the second power semiconductor device pad 332_2 or can be made of a material different from the second power semiconductor device pad 332_2. In addition, the thickness of the common frame structures 330_1, 330_2, 330_3 can be the same as the thickness of the first and second power semiconductor device pads 332_1, 332_2 or greater than or less than the thickness of the first and second power semiconductor device pads 332_1, 332_2. It should be noted that the thickness of all parts is measured in the direction from the upper surface (e.g., the first surface 130A of the lead frame 130) to the lower surface (e.g., the second surface 130B of the lead frame 130) of the corresponding part.

[0073] The thickness of the lead frame 130 and / or the hybrid lead frame 330 (in particular the common frame structures 330_1, 330_2, 330_3 and / or the first and second power semiconductor device pads 332_1, 332_2) can be, for example, equal to or greater than or less than 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1.0 mm, 1.2 mm, 1.4 mm, 1.6 mm, 1.8 mm, 2.0 mm, 2.2 mm, 2.4 mm, 2.6 mm, 2.8 mm, or 3.0 mm. For example, in the hybrid lead frame 330 or in a lead frame 130 with different thicknesses (e.g., a so-called dual-gauge lead frame), the thickness of the first and second power semiconductor device pads 332_1, 332_2 can be greater than the thickness of one or more of the parts of the common frame structures 330_1, 330_2, 330_3, 330_1, where the ratio of the thicknesses can be, for example, equal to or greater than a factor of 1.2, 1.4, 1.6, 1.8, 2.0, 2.5, 3.0 or more. The area sizes of the first and second power semiconductor device pads 332_1, 332_2 can be, for example, equal to or greater than or less than the values stated above for the occupied area of the power semiconductor chip.

[0074] Figure 5 is a perspective top view of an array of semiconductor device packages 500 each including first and second package bodies 110 and 120 respectively. As shown in Figure 5As shown, the package bodies 110, 120 of each semiconductor device package 500 are separated by a spacing 140. The middle portion 132 of the lead frame 130 is exposed from the first and second molding compounds 114, 124 within the spacing 140.

[0075] The lead frame 130 may further include a first end portion 134 protruding from the first molding compound 114 and a second end portion 136 protruding from the second molding compound 124. In addition, leads 135 and / or 137 may protrude from the first molding compound 114 and the second molding compound 124, respectively.

[0076] Adjacent semiconductor device packages 500 may be connected to each other via tie bars 510. The tie bar 510 may also connect the first end portion 134 to the longitudinal frame bar 522 of the continuous lead frame 520 and the tie bar 510 may be used to connect the second end portion 136 to another longitudinal frame bar 524 of the continuous lead frame 520. During the manufacturing process, the individual semiconductor device packages 500 are separated from the continuous lead frame 520 by cutting the tie bar 520 between the first end portion 134 and the longitudinal frame bar 522, the tie bar 510 between the second end portion 136 and the longitudinal frame bar 524, and the tie bar 510 between adjacent semiconductor device packages 500. In addition, the semiconductor device package 500 may have any of the features explained in connection with the semiconductor device packages 100-400 illustrated in FIGS. 1-4, and vice versa.

[0077] Figure 6 is Figure 5 A top view of an array of semiconductor device packages 500 at a manufacturing process stage before the first and second power semiconductor devices 112, 122 are respectively encapsulated in the first and second molding compounds 114, 124. In this example, the lead frame 130 corresponds to, for example, the lead frame 130 as shown in Figure 1A , 1B and FIG. 2.

[0078] In Figure 6In the example shown, the first power semiconductor device 112 includes a plurality of semiconductor power chips 610, 612 and the second power semiconductor device 122 may include a plurality of power semiconductor chips 620, 622. The power semiconductor chips 610, 612 and the power semiconductor chips 620, 622 may be directly mounted on the lead frame 130, for example. In addition, the first power semiconductor device 112 and / or the second power semiconductor device 122 may include driver and / or control functions as well as one or more power semiconductor chips. For example, the semiconductor chips 610, 620 may include control electrode (e.g., gate) driver circuits, while the semiconductor chips 612, 622 may be power semiconductor chips as described above. In addition, stacked chip arrangements (not shown) are also possible, such as power chip on power chip or driver chip on power chip and so on.

[0079] Figure 7 The figure shows an example of a cross-sectional view of a semiconductor device package 500 along line A-A after encapsulation. As is apparent from Figure 6 The middle portion 132 of the lead frame 130 can be connected to the power semiconductor device 612 through electrical connection elements 710 (such as bonding wires), for example. Similar connections can be provided between the power semiconductor chips 612 and 610 and between the semiconductor chip 610 and the lead 137. Figure 7 As is apparent, the middle portion 132 of the lead frame 130 can be connected to the power semiconductor device 612 through electrical connection elements 710 (such as bonding wires), for example. Similar connections can be provided between the power semiconductor chips 612 and 610 and between the semiconductor chip 610 and the lead 137.

[0080] Figure 8A is a perspective view of the continuous lead frame 520 for the lead frame 130 in a manufacturing process stage before the first and second power semiconductor devices 112, 122 are mounted on the lead frame 130.

[0081] Figure 8B is a perspective view of an example of a semiconductor device package 800 including a first package body 110 and a second package body 120. The semiconductor device package 800 has been separated from the continuous lead frame 520. In addition, as shown in Figure 8BAs shown, leads 135, 137 and first and second end portions 134, 136 of lead frame 130 can be bent at an angle, such as approximately 90°. Additionally, the middle portion 132 of lead frame 130 can include a cut line that defines a tab (e.g., bent-out flap 132_1). The bent-out flap 132_1 is bent from the plane of lead frame 130 to extend, for example, in a plane perpendicular to the plane of lead frame 130. The bent-out flap 132_1 of the middle portion 132 of lead frame 130 can be provided with a through hole. It should be noted that leads 135 and / or 137 can also protrude from first molding compound 114 and second molding compound 124 at opposite package body sides (i.e., adjacent to the middle portion 132 of lead frame 130). In this and other cases, it is possible that leads 135 and 137 are single (i.e., integral parts necessary to form the middle portion 132 of lead frame 130). Such a design allows for the combination of connectivity and / or functionality (e.g., control and / or sensing functions) associated with leads 135 and 137 in respective package bodies 110, 120.

[0082] Figure 8C FIG. 4 is a perspective view of semiconductor device package 800 that is the bottom of the illustrated package. Apparently, semiconductor device package 800 can be constructed according to semiconductor device package 100, i.e., lead frame 130 can be covered with first molding compound 114 and second molding compound 124 at both first and second surfaces 130A, 130B.

[0083] Figure 8D FIG. 8 is a perspective view of semiconductor device package 800 that shows the interior of the package body by cutting through first and second molding compounds 114, 124.

[0084] Figure 9A FIG. 12 is a partial perspective bottom view of an example of semiconductor device package 900. Only one package body 120 with molding compound 124 is depicted. As is apparent from Figure 9A FIG. 14, in this case, lead frame 130 is exposed at the bottom of semiconductor device package 900. Thus, semiconductor device package 900 can be designed according to Figure 2 semiconductor device package 200. Additionally, semiconductor device package 900 provides features similar or identical to those in semiconductor device packages 700 and 800, and reference is made to the corresponding disclosures to avoid repetition.

[0085] Figure 9BFIG. illustrates a semiconductor device package 900’ that is the same as semiconductor device package 900, except that a thermal interface material (TIM) 910 can be applied to the exposed second major surface 130B of lead frame 130. The TIM 910 can, for example, partially or completely cover the bottom of each package body 112, 122. The TIM 910 can provide electrical insulation for the second surface 130B of lead frame 130 that is exposed from the first and second molding compounds 114, 124. Further, if the second surface 130B of lead frame 130 is to be covered by a potting material (as illustrated in Figure 8C ), then the TIM 910 can provide a lower thermal resistance than the first and second molding compounds 114, 124.

[0086] Figure 9C is Figure 9B a partial cross-sectional view of semiconductor device package 900’. Figure 9C FIG. illustrates electrical connection elements (e.g., bonding wires) 710 that interconnect, for example, a first power semiconductor chip 610 and a second power semiconductor chip 620.

[0087] Figure 10A is a top view of a continuous lead frame 1020 that serves as a hybrid lead frame. The continuous lead frame 1020 can be the same as or similar to the continuous lead frame 520 of Figure 8A , except that the lead frame has cutouts 1030 that correspond to the openings (notches) 335_1, 335_2 of the hybrid lead frame 330 of Figure 3A , 3B and 4.

[0088] Figure 10B is a top view of a power semiconductor device pad 1332 and an example of a power semiconductor device 1100 mounted thereon. As an example, the power semiconductor device 1100 can be a first power semiconductor device 112 that includes, for example, power semiconductor chips 610, 612, or can be a second power semiconductor device 122 that includes, for example, power semiconductor chips 620, 622.

[0089] Figure 10C is a perspective bottom view of a power semiconductor device pad 1332. The power semiconductor device pad 1332 can be implemented, for example, by one of the examples of the first and / or second power semiconductor device pads 332_1, 332_2 as referred to in Figure 3A , 3B and 4. In the example illustrated in Figure 10C , the power semiconductor device pad 1332 can be a direct bonded copper (DBC) substrate, which can include, for example, a bottom copper layer 1332_1, a top copper layer 1332_3, and a ceramic material layer 1332_2 sandwiched between the two copper layers 1332_1 and 1332_3.

[0090] Figure 10D is a partial perspective top view of an array of semiconductor device packages 1000 during a manufacturing process stage prior to encapsulation. As shown in Figure 10D , the power semiconductor device pad 1332 has been inserted into the cutout 1030 of the continuous lead frame 1020. Additional features of the hybrid continuous lead frame 1020 are similar to those of the continuous lead frame 520, and reference is made to the above disclosure to avoid repetition.

[0091] Figure 10E and 10F respectively illustrate a top side and a bottom side perspective view of the semiconductor device package 1000. Figure 10E illustrates the interior of the first package body, which is similar to the first package body 110 shown in Figure 8D .

[0092] Figure 10F illustrates that in the semiconductor device package 1000, the bottom side (e.g., the bottom copper layer 1332_1) of the power semiconductor device pad 1332 can be exposed, while the portions of the lead frame 130 that define the cutout 1030 ( Figure 3A , 3B and 4: openings 335_1, 335_2) can be covered, for example, with a encapsulation material. This concept of the exposed power semiconductor device pad 1332 (e.g., the exposed DBC) (which can also be applied to the hybrid lead frame 330 shown in Figure 3A , 3B and 4) allows for high heat dissipation capacity while ensuring high mechanical robustness of the first and second package bodies 110, 120.

[0093] Figure 11A and 11B illustrate a perspective view of a semiconductor device package 1100 having a first package body 110 and a second package body 120 that are bent towards each other at a predetermined angle (e.g., towards each other). In various embodiments, the first and second package bodies are "reverse-bent", i.e., the bottom sides of the package bodies 110, 120 are bent towards each other. All package bodies 110, 120 of the semiconductor device packages described herein can be brought into this positional relationship.

[0094] In all semiconductor device packages, the first power semiconductor device 112 can include NS1 power switches and the second power semiconductor device 122 can include NS2 power switches. NS1 and NS2 are integers equal to or greater than 1. That is, each package body 110, 120 can include, for example, a number of power switches such as 1, 2, 3,....

[0095] In addition, as an example in Figure 12A and 12BAs shown in the figure, the semiconductor device package disclosed herein may have a first molding compound (e.g., the first package body 110) in the number of 1, 2, 3, … and may have a molding compound (e.g., the second package body 120) in the number of 1, 2, 3, …. Figure 12A and 12B Figure 1200 illustrates a semiconductor device package that includes three first molding compounds (the first package body 110) and three second molding compounds (the second package body 120). Generally, the semiconductor device package disclosed herein may include a molding compound (or package body) in the number of NB, where NB is an integer equal to or greater than 2.

[0096] The three first molding compounds 114 (package body 110) and the three second molding compounds 124 (package body 120) are interconnected to each other through the interconnecting portion 1135 of the lead frame 130. The interconnecting portion 1135 may have the same material as the middle portion 132 of the lead frame 130 and have the same mechanical properties as it. However, the interconnecting portion 1135 is connected between the first molding compounds 114 (the first package body 110) that are coplanar with each other, or between the second molding compounds 124 (the second package body 120) that are also coplanar with each other, but not between the first and second molding compounds (the first and second package bodies 110, 120) that can be bent to planes such as inclined or parallel but away from each other.

[0097] Generally, the multi-package body semiconductor device package disclosed herein can implement a variety of different power devices. In various embodiments, a semiconductor device package having two molding compounds 114, 124 (package bodies, e.g., the first package body 110 and the second package body 120) may include a half-bridge circuit, where the first molding compound 114 (the first package body 110) houses the low-side (LS) switch of the half-bridge circuit and the second molding compound 124 (the second package body 120) houses the high-side (HS) switch of the half-bridge circuit, or vice versa.

[0098] If the semiconductor device package includes four molding compounds 114, 124 (or package bodies), i.e., NB = 4, then the semiconductor device package may include, for example, a two-phase bridge circuit, where each of the two first molding compounds 114 (the first package body 110) houses the low-side switch of the two-phase bridge circuit and each of the two second molding compounds 124 (the second package body 120) houses the high-side switch of the two-phase bridge circuit, or vice versa. Similarly, if the semiconductor device package includes six molding compounds 114, 124 (package bodies 110, 120), i.e., NB = 6 (as, for example, in Figure 12A 、 12BIf (as shown in the figure), the semiconductor device package may include a three-phase bridge circuit, where each of the three first molding compounds 114 (first package body 110) houses a low-side switch of the three-phase bridge circuit and each of the three second molding compounds 124 (second package body 120) houses a high-side switch of the three-phase bridge circuit, or vice versa.

[0099] In addition, in all semiconductor device packages disclosed herein, first and second end portions 134, 136 protruding from the first and second molding compounds 114, 124, respectively, may form load external terminals of the semiconductor device package (i.e., terminals connected to load electrodes of power transistors included in the first or second power semiconductor devices 112, 122), and the leads 135, 137 may form control and / or sensing terminals of the semiconductor device package, i.e., external terminals connected to gate electrodes or voltage and / or temperature sensing electrodes of power transistors included in the first or second power semiconductor devices 112, 124.

[0100] The first power semiconductor device 112 and the second power semiconductor device 122 of the semiconductor device package disclosed herein may have the same function or may have different functions.

[0101] In addition, depending on the application of the semiconductor device package described herein, the semiconductor device package may be operated (e.g., switched) from a voltage such as 2V or equal to or greater than or less than, for example, 12V, 48V, 100V, 500V, 1.0 kV, 1.2 kV, 1.5 kV, 2.0 kV, 2.5 kV, or even up to 6.5 kV.

[0102] Figure 13 is a cross-sectional view of an example of a power system 1300. The power system 1300 includes a semiconductor device package, for example, according to one or more of the multi-body semiconductor device packages described above. That is, the semiconductor device package includes a first package body 110 having a first power semiconductor device encapsulated in a first molding compound 114 and a second package body 120 including a second power semiconductor device encapsulated in a second molding compound 124. The semiconductor device package further includes a lead frame 130 configured to mechanically and electrically connect the first package body 110 and the second package body 120, where the first power semiconductor device and the second power semiconductor device are mounted on the lead frame 130. As explained above, the lead frame 130 may have an intermediate portion 132 bent at an angle of, for example, approximately 180°. The power system 1300 further includes at least one heat sink, such as a common heat sink 1310 that is thermally and mechanically coupled to the first molding compound 114 (first package body 110) and the second molding compound 124 (second package body 120).

[0103] More specifically, the (e.g., common) heat sink 1310 may include a plate having a first surface 1310A and a second surface 1310B opposite the first surface 1310A. The first molding compound 114 (first package body 110) may be thermally and mechanically coupled to the first surface 1310A of the plate and the second molding compound 124 (second package body 120) may be thermally and mechanically coupled to the second surface 1310B of the plate. As described above, the thermal coupling may be provided by the direct adjacency of the bottom side materials (e.g., lead frame, encapsulation material, or TIM) of the semiconductor device package to the first and second surfaces 1310A, 1310B of the common heat sink 1310. In particular, it may be possible that no additional materials (e.g., thermal grease or any other thermal bonding material) are used between the semiconductor device package and the common heat sink 1310 during the assembly of the power system 1300.

[0104] The semiconductor device package of the power system 1300 may be, for example, a two-body package, a three-body package, a four-body package, a five-body package, a six-body package, and so on. As an example, the semiconductor device package may include a half-bridge circuit, a two-phase bridge circuit, or a three-phase bridge circuit. As shown in Figure 13 , screw clips 1320 may be used to press the first and second package bodies 110, 120 onto the heat sink 1310. The screw clips 1320 may include, for example, a clamping bracket 1322 that surrounds the first and second molding compounds 114, 124 (package bodies 110, 120) and a plurality of fixing screws 1324 for pressing the clamping bracket 1322 together.

[0105] As shown in Figure 13 , the first and second end portions 134, 136 of the lead frame 130 may be used as external terminals of the semiconductor device package. In addition, a gate driver PCB 1330 is shown to provide gate control signals and / or voltage or temperature sensing signals.

[0106] Figure 14A and 14B are perspective views of a semiconductor device package 1400 having a first molding compound 114 (first package body 110) and a second molding compound 124 (second package body 120). The semiconductor device package 1400 has features similar to those described above, and reference is made to the above disclosure to avoid repetition. In particular, it is apparent from Figure 14A and 14B that the first and second package bodies 110, 120 may be standard package bodies, such as, for example, a TO247 package, which is conventional art except for the lead frame 130 and its single intermediate portion 132.

[0107] The middle portion 132 (e.g., power leads) of the lead frame 130 may have an annular central region 132_5. The annular central region 132_5 may define a through-hole in the middle portion 132 of the lead frame. The annular central region 132_5 of the middle portion 132 of the lead frame 130 may serve as an (common) external terminal of the semiconductor device package 1400. The semiconductor device package 1400 may implement, for example, a half-bridge circuit.

[0108] Figure 15A and 15B Perspective view of a semiconductor device package 1500 having, for example, six molding compounds (package bodies), where three of the six molding compounds (package bodies) are first molding compounds 114 (first package bodies 110) and the remaining three are second molding compounds 124 (second package bodies 120). Again, each package body 110, 120 may be, for example, a standard package body, such as, for example, a TO247 package.

[0109] The middle portion 132 of the lead frame 130 may include at least three separate connections 132a, 132b, and 132c. Each of these connections is single (necessary to form a whole) and connects the molding compound 114 (first package body 110) to the second molding compound 124 (second package body 120).

[0110] Figure 16 Perspective view of an example of a power system 1600. The power system 1600 may be similar to the power system 1300, except for using the semiconductor device package 1500. Therefore, reference is made to the above description to avoid repetition. Similarly to in the power system 1300, a (common) heat sink 1310 with a plate is used for heat dissipation and the package bodies 110, 120 are bent backward and adjacent to the plate. It should be noted that in the power system 1600, each individual molding compound 114, 124 (package body 110, 120) is provided with through-holes that allow the molding compounds 114, 124 (package bodies 110, 120) to be fixed (e.g., screwed) to the plate. Additionally, throughout this disclosure, instead of the common heat sink 1310, multiple heat sinks may be provided (e.g., one for each molding compound 114, 124 (package body 110, 120) or one for each pair of molding compounds 114, 124 (package bodies 110, 120)).

[0111] Figure 17 is a circuit diagram of a three-phase bridge circuit 1700. Such a three-phase bridge circuit 1700 may be implemented, for example, in the semiconductor device packages shown in Figures 12A - 12B and 15A - 15B.

[0112] The three-phase bridge circuit includes three half-bridges. The first half-bridge includes a low-side switch LS1 and a high-side switch HS1 connected in series between a negative supply voltage (e.g., ground: GND) 1701 and a positive supply voltage (e.g., battery: BAT) 1702. The second half-bridge includes a low-side switch LS2 and a high-side switch HS2 connected in series between the negative supply voltage 1701 and the positive supply voltage 1702. The third half-bridge includes a low-side switch LS3 and a high-side switch HS3 connected in series between the negative supply voltage 1701 and the positive supply voltage 1702. The control electrodes (e.g., gate electrodes) of the low-side switches LS1, LS2, and LS3 are respectively connected to nodes 1703, 1704, and 1705. The control electrodes (e.g., gate electrodes) of the high-side switches HS1, HS2, and HS3 are respectively connected to nodes 1707, 1708, and 1709.

[0113] The connections between the low-side switches LS1 and the high-side switches HS1 of the first, second, and third half-bridges are respectively connected to node 1412, node 1413, and node 1414.

[0114] In Figure 17 the example illustrated, for example, the low-side switches LS1, LS2, LS3 and the high-side switches HS1, HS2, HS3 are implemented by MOSFETs. In Figure 17 , D represents the drain and S represents the source. However, other types of switches and other polarities are also possible. As an example, it is also possible that the low-side switches LS1, LS2, LS3 and the high-side switches HS1, HS2, HS3 are implemented by IGBTs. In this case, the circuit diagram will be similar to Figure 17 's circuit diagram, except that the IGBTs replace the MOSFETs. Then, the emitter will replace the source S and the collector will replace the drain D. In addition, the two-phase bridge circuit only includes the first and second half-bridges LS1, HS1, LS2, HS2, and the half-bridge circuit only includes the first half-bridge LS1, HS1.

[0115] As can be understood by comparing the Figure 17 circuit diagram with the semiconductor device package disclosed herein, it seems that the (multiple) first molding compounds 114 ((multiple) first package bodies 110) correspond to, for example, the (multiple) LS switches, and the (multiple) second molding compounds 124 ((multiple) second package bodies 120) correspond to, for example, the (multiple) HS switches.

[0116] Figure 18 is a flowchart illustrating the stages of an exemplary method of manufacturing a semiconductor device package according to the present disclosure.

[0117] At S1, a first power semiconductor device is mounted on a first part of a lead frame.

[0118] At S2, a second power semiconductor device is mounted on the second part of the lead frame. In S1 and S2, any mounting technique can be used, such as, for example, soldering, adhesive gluing, sintering, and so on.

[0119] At S3, the first power semiconductor device is encapsulated with a first molding compound.

[0120] At S4, the second power semiconductor device is encapsulated with a second molding compound, the first molding compound and the second molding compound being substantially separated from each other, wherein the lead frame includes an intermediate part disposed between the first part and the second part, the intermediate part not being covered by the first molding compound or the second molding compound.

[0121] The method may further include separating the leads of the lead frame to monomerize the semiconductor device package outside the lead frame.

[0122] Throughout the present disclosure, the first molding compound may be the same encapsulation material as the second molding compound or may be a different encapsulation material from the second molding compound. Further, throughout the present disclosure, the first molding compound and the second molding compound may be formed (e.g., molded, laminated, etc.) in one manufacturing process or in separate manufacturing processes (e.g., in one or more molding and / or lamination processes).

[0123] The method may further include bending the intermediate part of the lead frame to fold the first molding compound (the first encapsulation body) back onto the second molding compound (the second encapsulation body).

[0124] The following examples relate to further aspects of the present disclosure: Example 1 is a semiconductor device package that includes a lead frame; a first power semiconductor device mounted on a first part of the lead frame; a second power semiconductor device mounted on a second part of the lead frame; the first power semiconductor device being encapsulated with a first molding compound; the second power semiconductor device being encapsulated with a second molding compound; wherein the first molding compound and the second molding compound are substantially separated from each other, and the lead frame includes an intermediate part disposed between the first part and the second part, the intermediate part not being covered by the first molding compound or the second molding compound.

[0125] In Example 2, the subject matter of Example 1 may optionally include wherein the first part of the lead frame is cast in the first molding compound and the second part of the lead frame is cast in the second molding compound.

[0126] In Example 3, the subject matter of Example 1 or 2 may optionally include wherein the lead frame is a single piece.

[0127] In Example 4, the subject matter of any one of Examples 1 to 3 may optionally include where the middle portion of the lead frame has an inherent structural stability sufficient to keep the first molding compound in place relative to the second molding compound.

[0128] In Example 5, the subject matter of any one of Examples 1 to 4 may optionally include where the middle portion of the lead frame is plastically deformable by bending to allow bringing the first molding compound and the second molding compound into positions relative to each other.

[0129] In Example 6, the subject matter of any one of Examples 1 to 5 may optionally include where the middle portion of the lead frame includes a cut line defining a tongue joint.

[0130] In Example 7, the subject matter of any one of Examples 1 to 6 may optionally include where the middle portion of the lead frame is provided with through holes.

[0131] In Example 8, the subject matter of any one of Examples 1 to 7 may optionally include where the first portion of the lead frame includes a notch and a device pad inserted into the notch, and where the first power semiconductor device is mounted on the device pad.

[0132] In Example 9, the subject matter of any one of Examples 1 to 8 may optionally include where the first power semiconductor device is mounted on the first surface of the first portion of the lead frame, and the second surface of the first portion of the lead frame opposite the first surface is exposed from the first molding compound.

[0133] In Example 10, the subject matter of any one of Examples 1 to 9 may optionally include where the lead frame further includes at least one of a first end portion protruding from the first molding compound and a second end portion protruding from the second molding compound.

[0134] In Example 11, the subject matter of any one of Examples 1 to 10 may optionally include a half-bridge circuit, where the first molding compound houses the low-side switch of the half-bridge circuit and the second molding compound houses the high-side switch of the half-bridge circuit.

[0135] In Example 12, the subject matter of any one of Examples 1 to 11 may optionally include a number NB of first and second molding compounds, where NB is an integer equal to or greater than 3.

[0136] In Example 13, the subject matter of Example 12 may optionally include at least one of a two-phase bridge circuit where NB is equal to or greater than 4 and a three-phase bridge circuit where NB is equal to or greater than 6.

[0137] Example 14 is a power system that includes a semiconductor device package. The semiconductor device package includes a lead frame; a first power semiconductor device mounted on a first portion of the lead frame; a second power semiconductor device mounted on a second portion of the lead frame; the first power semiconductor device is encapsulated by a first molding compound; the second power semiconductor device is encapsulated by a second molding compound; wherein the first molding compound and the second molding compound are substantially separated from each other, and the lead frame includes an intermediate portion disposed between the first portion and the second portion, and the intermediate portion is not covered by the first molding compound or the second molding compound; and a heat sink thermally and mechanically coupled to the first molding compound and the second molding compound.

[0138] In Example 15, the subject matter of Example 14 may optionally include wherein the heat sink includes a plate having a first surface and a second surface opposite the first surface, the first molding compound is thermally and mechanically coupled to the first surface, and the second molding compound is thermally and mechanically coupled to the second surface.

[0139] In Example 16, the subject matter of Example 14 or 15 may optionally include at least one of a half-bridge circuit, a two-phase bridge circuit, and a three-phase bridge circuit.

[0140] Example 17 is a method of manufacturing a semiconductor device package, including mounting a first power semiconductor device on a first portion of a lead frame; mounting a second power semiconductor device on a second portion of the lead frame; encapsulating the first power semiconductor device with a first molding compound; encapsulating the second power semiconductor device with a second molding compound, the first molding compound and the second molding compound are substantially separated from each other, and wherein the lead frame includes an intermediate portion disposed between the first portion and the second portion, and the intermediate portion is not covered by the first molding compound or the second molding compound.

[0141] In Example 18, the subject matter of Example 17 may optionally include wherein encapsulating the first power semiconductor device includes casting the first portion of the lead frame in the first molding compound; and encapsulating the second power semiconductor device includes casting the second portion of the lead frame in the second molding compound.

[0142] In Example 19, the subject matter of Example 17 or 18 may optionally include cutting the leads of the lead frame to monomerize the semiconductor device package outside the lead frame after encapsulation.

[0143] In Example 20, the subject matter of any one of Examples 17 to 19 may optionally include bending the intermediate portion of the lead frame to fold the first molding compound back onto the second molding compound.

[0144] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will recognize that various alternatives and / or equivalent implementations may substitute the specific embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any modifications or variations of the specific embodiments discussed herein.

Claims

1. A method of manufacturing a semiconductor device package, the method comprising: mounting a first power semiconductor device on a first portion of a lead frame; mounting a second power semiconductor device on a second portion of the lead frame; encapsulating the first power semiconductor device with a first molding compound; and encapsulating the second power semiconductor device with a second molding compound, the first molding compound and the second molding compound being substantially separated from each other, wherein the lead frame includes an intermediate portion disposed between the first portion and the second portion, wherein the intermediate portion is not covered by the first molding compound or the second molding compound.

2. The method according to claim 1, wherein: encapsulating the first power semiconductor device includes casting the first portion of the lead frame in the first molding compound; and encapsulating the second power semiconductor device includes casting the second portion of the lead frame in the second molding compound.

3. The method according to claim 1, further comprising: cutting the leads of the lead frame to monomerize the semiconductor device package outside the lead frame after encapsulation.

4. The method according to claim 1, further comprising: bending the intermediate portion of the lead frame to fold the first molding compound back onto the second molding compound.

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