Packaging structure and packaging method
By using technical means such as solder pads and rewiring layers in the package structure, the existing packaging structure is complex and difficult to operate, and a higher packaging integration and a simple packaging method are achieved.
Patent Information
- Application Number
- CN202311678204.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-07
- Publication Date
- 2025-06-10
AI Technical Summary
The existing packaging structure is complex, and the packaging method is difficult to be simple and easy to operate.
The packaging structure including a substrate, a chip bridge, a re-wiring layer, a solder pad, a first chip and a chip structure is adopted. The electrical connection between the chip bridge and the substrate is realized through the solder pad, and the electrical connection between the chip structure and the first chip is achieved through the re-wiring layer.
The height difference between the chip bridge and the substrate is reduced, the overall height of the packaging structure is reduced, the packaging integration of the packaging structure is improved, and the operation steps of the packaging method are simplified.
Smart Images
Figure CN120127076A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and particularly to a packaging structure and a packaging method. Background Art
[0002] For the size of a single chip, conventional chip manufacturing technologies are being pushed to their limits. However, applications are eager to use the latest technologies to achieve the ability of large-size integrated circuits, and there are great challenges in achieving high-speed and small-size interconnections between chips.
[0003] One current solution is to use smaller integrated circuits of silicon bridge (Si Bridge) chips embedded in a silicon substrate to achieve interconnection between chips through the silicon bridge chips, thereby providing heterogeneous chip packaging.
[0004] However, the structure of the current packaging structure is relatively complex. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method, which are beneficial to making the packaging method simple and easy to operate.
[0006] To solve the above problems, the present invention provides a packaging structure, including: a substrate; a chip bridge, including a chip front and a chip back facing away from each other, the chip back of the chip bridge faces the substrate and is bonded to the substrate; a redistribution layer, bonded to the chip front of the chip bridge, the redistribution layer includes one or more stacked interconnect layers, the interconnect layer includes an interconnect via hole and an interconnect metal layer located on the interconnect via hole, and the chip bridge is in contact with the interconnect metal layer; a solder pad, located between the chip front and the substrate, the solder pad is electrically connected to the chip bridge and the redistribution layer; a first chip, bonded to the redistribution layer, the first chip is electrically connected to the redistribution layer and the chip bridge; a chip structure, bonded to the redistribution layer on the side of the first chip, the chip structure is electrically connected to the redistribution layer, and the chip structure is electrically connected to the first chip through the chip bridge.
[0007] Optionally, the packaging structure further includes: interconnect posts, separated on the substrate on both sides of the chip bridge, and the interconnect posts are electrically connected to the redistribution layer.
[0008] Optionally, the packaging structure further includes: a first sealing layer, filling the gaps between adjacent interconnect posts between the substrate and the redistribution layer, and between adjacent solder pads.
[0009] Optionally, the packaging structure further includes: conductive bumps located between the redistribution layer and the first chip, and between the redistribution layer and the chip structure, the conductive bumps electrically connect the first chip and the redistribution layer, and the conductive bumps also electrically connect the chip structure and the redistribution layer.
[0010] Optionally, the encapsulation structure further includes: a second sealing layer, which is filled between adjacent conductive bumps and in the gaps between adjacent conductive bumps, and covers the conductive bumps.
[0011] Optionally, the first chip includes a logic chip, the chip structure includes one or a plurality of second chips stacked longitudinally, and the second chip includes a memory chip.
[0012] Optionally, the thickness of the chip bridge is 2 μm to 100 μm.
[0013] Correspondingly, an embodiment of the present invention further provides an encapsulation method, including: providing a first substrate on which a redistribution layer is formed; bonding a chip bridge to the redistribution layer, the chip bridge including a chip front and a chip back facing away from each other, and the chip front of the chip bridge facing the redistribution layer; bonding a second substrate to the chip back of the chip bridge; removing the first substrate to expose the redistribution layer; bonding a chip structure and a first chip to the redistribution layer, the chip structure being located on the side of the first chip, the chip structure being electrically connected to the redistribution layer, the first chip being electrically connected to the redistribution layer, and the first chip and the chip structure being electrically connected through the chip bridge.
[0014] Optionally, in the step of bonding the chip bridge to the redistribution layer, a solder pad is formed between the chip front and the redistribution layer.
[0015] Optionally, before bonding the chip bridge to the redistribution layer, the encapsulation method further includes: forming discrete interconnect posts on the redistribution layer on both sides of the chip bridge; in the step of bonding the second substrate to the chip back of the chip bridge, the second substrate is also bonded to the interconnect posts.
[0016] Optionally, after forming discrete interconnect posts on the redistribution layer on both sides of the chip bridge and before bonding the second substrate to the chip back of the chip bridge, the encapsulation method further includes: forming a first sealing layer on the redistribution layer, the first sealing layer filling the gaps between adjacent interconnect posts and between adjacent solder pads, and the first sealing layer exposing the tops of the interconnect posts; in the step of bonding the second substrate to the chip back of the chip bridge, the second substrate is also bonded to the first sealing layer.
[0017] Optionally, the step of forming the first sealing layer on the redistribution layer includes: forming a first sealing material layer on the redistribution layer that fills the gaps between adjacent interconnect posts and between adjacent solder pads, the first sealing material layer covering the conductive posts and the chip bridge; performing a planarization process on the first sealing material layer until the tops of the conductive posts are exposed.
[0018] Optionally, in the step of providing the first substrate, the redistribution layer includes one or more stacked interconnect layers, the interconnect layer includes interconnect vias and an interconnect metal layer located on the interconnect vias, and the chip bridge is in contact with the interconnect metal layer.
[0019] Optionally, the step of bonding the chip structure and the first chip on the redistribution layer includes: forming conductive bumps on the redistribution layer; alternatively, forming conductive bumps on the first chip and the chip structure; and bonding the chip structure and the first chip to the redistribution layer by using the conductive bumps.
[0020] Optionally, the packaging method further includes: forming a second sealing layer filled between adjacent conductive bumps and in the gaps between adjacent conductive bumps, and the second sealing layer covers the conductive bumps.
[0021] Optionally, the first chip includes a logic chip, the chip structure includes one or a plurality of second chips stacked longitudinally, and the second chips include memory chips.
[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0023] The embodiment of the present invention provides a packaging structure. The chip bridge includes a chip front and a chip back facing away from each other. The chip back of the chip bridge faces the substrate and is bonded to the substrate. The solder pads are located between the chip front and the substrate, and the solder pads are electrically connected to the chip bridge and the redistribution layer. In the embodiment of the present invention, the solder pads are used to realize the electrical connection between the chip bridge and the substrate. Usually, the solder pads are thinner, that is, the thickness is smaller. Compared with using bumps to realize the electrical connection between the chip bridge and the substrate, it is beneficial to reduce the height difference between the chip bridge and the substrate, thereby being beneficial to reducing the overall height of the packaging structure, and further being beneficial to improving the packaging integration of the packaging structure.
[0024] The embodiment of the present invention provides a packaging method. Bond the chip bridge to the redistribution layer. The chip bridge includes a chip front and a chip back facing away from each other. The chip front of the chip bridge faces the redistribution layer. Bond the second substrate to the chip back of the chip bridge, remove the first substrate to expose the redistribution layer, and bond the chip structure and the first chip on the redistribution layer. In the embodiment of the present invention, conductive bumps are usually formed on the chip front of the chip bridge to realize the electrical connection between the chip bridge and the redistribution layer. Compared with the solution of bonding the chip back of the chip bridge to the second substrate after forming conductive bumps on the chip front of the chip bridge, since the conductive bumps cause unevenness on the chip front, it is difficult to bond the chip bridge with the chip back facing down on the second substrate. In the embodiment of the present invention, first bond the chip front of the chip bridge to the redistribution layer, and then bond the second substrate to the chip back of the chip bridge, avoiding the step of sucking up the chip bridge with an uneven chip front, making it easy to bond the chip back of the chip bridge to the second substrate, and thus making the packaging method simple and easy to operate. Description of the Drawings
[0025] Figures 1 to 3 is a schematic structural diagram corresponding to each step in a packaging method;
[0026] Figure 4 It is a schematic structural diagram of an embodiment of the encapsulation structure of the present invention;
[0027] Figures 5 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of the encapsulation method of the present invention. Detailed implementation manners
[0028] As can be seen from the background art, the current encapsulation method is relatively difficult and complex. Now, in combination with an encapsulation method, the reasons for the difficulty and complexity of the encapsulation method are analyzed.
[0029] Figures 1 to 3 It is a schematic structural diagram corresponding to each step in an encapsulation method.
[0030] Refer to Figure 1 , a substrate 11 is provided, and the substrate 11 includes a bonding area for bonding chips; an interconnect post 10 is formed on the substrate 11 at the side of the bonding area.
[0031] Refer to Figure 2 , a chip bridge 20 is provided, which includes a chip front surface 2a and a chip back surface 2b facing away from each other, and discrete conductive bumps 51 are formed on the chip front surface 2a.
[0032] Refer to Figure 3 , bond the chip back surface 2b of the chip bridge 20 to the substrate 11.
[0033] Due to the unevenness of the chip front surface 2a caused by the conductive bumps 51, when bonding the chip back surface 2b of the chip bridge 20 to the substrate 11, it is difficult to directly pick up the chip bridge 20 due to the conductive bumps 51 on the chip front surface 2a, resulting in difficulty and complex operation in bonding the chip bridge 20 with the chip back surface 2b facing down to the substrate 11.
[0034] To solve the technical problems, an embodiment of the present invention provides an encapsulation method, including: providing a first substrate on which a redistribution layer is formed; bonding a chip bridge to the redistribution layer, the chip bridge includes a chip front surface and a chip back surface facing away from each other, and the chip front surface of the chip bridge faces the redistribution layer; bonding a second substrate to the chip back surface of the chip bridge; removing the first substrate to expose the redistribution layer; bonding a chip structure and a first chip on the redistribution layer, the chip structure is located at the side of the first chip, the chip structure is electrically connected to the redistribution layer, the first chip is electrically connected to the redistribution layer, and the first chip is electrically connected to the chip structure through the chip bridge.
[0035] In the embodiments of the present invention, conductive bumps are usually formed on the front side of the chip of the chip bridge to achieve electrical connection between the chip bridge and the redistribution layer. Compared with the solution of bonding the back side of the chip of the chip bridge to the second substrate after forming the conductive bumps on the front side of the chip of the chip bridge, since the conductive bumps cause unevenness on the front side of the chip, it is difficult to bond the chip bridge with the back side of the chip facing down to the second substrate. In the embodiments of the present invention, the front side of the chip of the chip bridge is first bonded to the redistribution layer, and then the second substrate is bonded to the back side of the chip of the chip bridge, avoiding the step of picking up the chip bridge with an uneven front side of the chip, making it easy to bond the back side of the chip of the chip bridge to the second substrate, and thus making the packaging method simple and easy to operate.
[0036] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.
[0037] Figure 4 It is a schematic structural diagram of an embodiment of the packaging structure of the present invention.
[0038] The packaging structure includes: a substrate 120; a chip bridge 200, including a front side 20a and a back side 20b of the chip that face away from each other. The back side 20b of the chip bridge 200 faces the substrate 120 and is bonded to the substrate 120; a redistribution layer 700, bonded to the front side 20a of the chip bridge 200. The redistribution layer 700 includes one or more stacked interconnect layers. The interconnect layer includes an interconnect via 710 and an interconnect metal layer 720 located on the interconnect via 710. The chip bridge 200 is in contact with the interconnect metal layer 720; a solder pad 510, located between the front side 20a of the chip and the substrate 120. The solder pad 510 electrically connects the chip bridge 200 and the redistribution layer 700; a first chip 440, bonded to the redistribution layer 700. The first chip 440 is electrically connected to the redistribution layer 700 and the chip bridge 200; a chip structure 400, bonded to the redistribution layer 700 on the side of the first chip 440. The chip structure 400 is electrically connected to the redistribution layer 700, and the chip structure 400 is electrically connected to the first chip 440 through the chip bridge 200.
[0039] The substrate 120 is used to provide a process operation basis for realizing the bonding between the chip bridge 200 and the redistribution layer 700.
[0040] In this embodiment, the material of the substrate 120 is silicon.
[0041] Specifically, in this embodiment, the substrate 120 is a carrier substrate.
[0042] In this embodiment, the substrate 120 is a wafer. In other embodiments, the substrate can also be a glass substrate.
[0043] The bridge die 200 is used to implement the electrical connection between the chip structure 400 and the first chip 440.
[0044] The bridge die 200 includes a front chip surface 20a and a back chip surface 20b which face away from each other. The front chip surface 20a is used to implement the electrical connection between the bridge die 200 and the outside, and the back chip surface 20b is used to be bonded to the substrate 120 by fitting.
[0045] In this embodiment, a circuit structure is formed in the bridge die 200, and the first chip 440 and the chip structure 400 are electrically connected through the circuit structure.
[0046] In this embodiment, the bridge die 200 includes a silicon bridge or an interposer.
[0047] It should be noted that in this embodiment, the thickness of the bridge die 200 should not be too large or too small. If the thickness of the bridge die 200 is too large, it is easy to cause the thickness of the interconnect structure to be too large, which is not conducive to improving the integration degree of the package structure; if the thickness of the bridge die 200 is too small, it is easy to affect the formation of the circuit structure in the bridge die 200 and affect the electrical connection performance of the bridge die 200. For this reason, in this embodiment, the thickness of the bridge die 200 is 2 μm to 100 μm.
[0048] The Redistribution Layer 700 is used to bond with the bridge die 200, so as to realize the electrical connection between the Redistribution Layer 700 and the bridge die 200. The Redistribution Layer 700 is also used to bond with the chip structure 400 and the first chip 440, so as to realize the electrical connection between the Redistribution Layer 700 and the chip structure 400 and the first chip 440.
[0049] In this embodiment, the Redistribution Layer 700 includes one or more interconnect layers. The interconnect layer includes interconnect vias 710 and an interconnect metal layer 720 located on the interconnect vias 710. The bridge die 200 is in contact with the interconnect metal layer 720. That is to say, in this embodiment, after the bridge die 200 is bonded to the Redistribution Layer 700, the substrate 120 is bonded to the bridge die 200.
[0050] The first chip 440 is used to be electrically connected to the Redistribution Layer 700 to realize the electrical connection between the first chip 440 and the outside in the longitudinal direction. Correspondingly, the first chip 440 is electrically connected to the bridge die 200 through the Redistribution Layer 700, and the electrical connection between the first chip 440 and the chip structure 400 is realized through the bridge die 200.
[0051] Specifically, in this embodiment, the package structure includes a plurality of chip structures 400. The first chip 440 is electrically connected to the Redistribution Layer 700 and then electrically connected to each chip structure 400 through the bridge die 200.
[0052] In this embodiment, the first chip 440 is a logic chip. As the first logic chip in this embodiment, it is used to control the memory chips of the chip structure 400. Specifically, the first logic chip can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or a system on chip (SoC).
[0053] The chip structure 400 is used to be electrically connected to the redistribution layer 700 to achieve the electrical connection of the chip structure 400 with the outside in the longitudinal direction. Correspondingly, the chip structure 400 is electrically connected to the chip bridge 200 through the redistribution layer 700, and the electrical connection between the chip structure 400 and the first chip 440 is realized through the chip bridge 200.
[0054] In this embodiment, the chip structure 400 includes one or a plurality of second chips 410 stacked along the longitudinal direction (as shown in the Z direction in Figure 4 ), so as to realize the electrical connection between each second chip 410 and the first chip 440, and the electrical connection between each second chip 410 and the outside in the longitudinal direction.
[0055] Specifically, in this embodiment, the chip structure 400 is electrically connected to the redistribution layer 700 and electrically connected to the first chip 440 through the chip bridge 200.
[0056] In this embodiment, in the chip structure 400, a high bandwidth memory (HBM) structure composed of a plurality of second chips 410 stacked along the longitudinal direction is adopted. By adopting the HBM structure, it is beneficial to meet the requirements for higher information transmission speed.
[0057] Among them, the second chip 410 includes a bottom chip located at the bottom and a top chip stacked on the bottom chip. The number of top chips can be one or more. In this embodiment, the number of top chips is taken as four as an example for illustration. In other embodiments, the number of top chips can also be other numbers.
[0058] Therefore, in this embodiment, the top chip is a memory chip. In a specific implementation, the top chip is a high bandwidth memory (HBM) chip.
[0059] In this embodiment, the bottom chip is a second logic chip. Specifically, the bottom chip is used as the logic control chip in the chip structure 400.
[0060] In this embodiment, the bottom chip and the substrate 120 , as well as the adjacent second chips 410 in the vertical direction are electrically connected, thereby achieving electrical integration between the second chips 410 and electrical integration between the second chips 410 and the substrate 120 .
[0061] In this embodiment, there are multiple chip structures 400 , and multiple chip structures 400 are electrically connected to the first chip 440 , which is beneficial to increasing the memory of the package structure, improving the chip speed and reducing the chip power consumption.
[0062] The pad 510 is used to realize electrical connection between the chip bridge 200 and the redistribution layer 700 .
[0063] This embodiment uses a solder pad 510 to achieve electrical connection between the chip bridge 200 and the substrate 700. Usually, the solder pad 510 is thinner, that is, the thickness is smaller. Compared with using a bump to achieve electrical connection between the chip bridge and the substrate, it is beneficial to reduce the height difference between the chip bridge 200 and the substrate 700, thereby helping to reduce the overall height of the packaging structure, and further helping to improve the packaging integration of the packaging structure.
[0064] In this embodiment, the material of the pad 510 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the pad 510 is tin.
[0065] In this embodiment, the packaging structure further includes: interconnection pillars 100 , which are separated on the substrate 120 at both sides of the chip bridge 200 , and the interconnection pillars 100 are electrically connected to the redistribution layer 700 .
[0066] The interconnect pillar 100 is used to electrically connect to the redistribution layer 700 , and correspondingly to the first chip 440 and the chip structure 400 , so that the first chip 440 is electrically connected to the outside in the vertical direction, and the chip structure 400 is electrically connected to the outside in the vertical direction through the interconnect pillar 100 .
[0067] In this embodiment, the interconnection pillar 100 is a copper pillar, that is, the material of the interconnection pillar 100 is copper.
[0068] In this embodiment, the packaging structure further includes: a first sealing layer 310 filling the gaps between adjacent interconnect pillars 100 between the substrate 120 and the redistribution layer 700 , and between adjacent pads 510 .
[0069] The first sealing layer 310 is used to achieve sealing between the chip bridge 200 and the redistribution layer 700 , to achieve sealing between adjacent interconnect pillars 100 , and to achieve sealing of adjacent pads 510 .
[0070] In this embodiment, the encapsulation structure further includes: conductive bumps 520 located between the redistribution layer 700 and the first chip 440, and between the redistribution layer 700 and the chip structure 400. The conductive bumps 520 electrically connect the first chip 440 to the redistribution layer 700, and the conductive bumps 520 also electrically connect the chip structure 400 to the redistribution layer 700.
[0071] The conductive bumps 520 are used to achieve the electrical connection between the first chip 440 and the redistribution layer 700, and the electrical connection between the chip structure 400 and the redistribution layer 700.
[0072] In this embodiment, the material of the conductive bumps 520 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the conductive bumps 520 is tin.
[0073] In this embodiment, the conductive bumps 520 can be micro-bumps (uBumps). The micro-bump density is relatively high, which is beneficial to improving the communication speed between the first chip 440 and the redistribution layer 700, and between the chip structure 400 and the redistribution layer 700.
[0074] In this embodiment, the encapsulation structure further includes: a second sealing layer 320, which is filled in the gaps between adjacent conductive bumps 520 and between adjacent conductive bumps 520, and covers the conductive bumps 520.
[0075] The second sealing layer 320 is used to seal between the first chip 440 and the redistribution layer 700, seal between the chip structure 400 and the redistribution layer 700, and seal adjacent conductive bumps 520.
[0076] Figures 5 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of the encapsulation method of the present invention.
[0077] Reference Figure 5 , provide the first substrate 110.
[0078] The first substrate 110 is used to provide a process operation basis for the subsequent formation of the redistribution layer.
[0079] In this embodiment, the material of the first substrate 110 is silicon.
[0080] Specifically, in this embodiment, the first substrate 110 is a carrier substrate.
[0081] In this embodiment, the first substrate 110 is a wafer. In other embodiments, the first substrate can also be a glass substrate.
[0082] Reference Figure 6 , a redistribution layer 700 is formed on the first substrate 110.
[0083] The redistribution layer 700 is used for subsequent bonding with the chip bridge to achieve electrical connection between the redistribution layer 700 and the chip bridge. The redistribution layer 700 is also used for subsequent bonding with the chip structure and the first chip to achieve electrical connection between the redistribution layer 700 and the chip structure and the first chip.
[0084] In this embodiment, in the step of providing the first substrate, the redistribution layer 700 includes one or more stacked interconnect layers. The interconnect layer includes interconnect vias 710 and an interconnect metal layer 720 located on the interconnect vias 710.
[0085] Reference Figure 7 , before subsequently bonding the chip bridge to the redistribution layer 700, the packaging method further includes: forming discrete interconnect posts 100 on the redistribution layer 700 on both sides of the area for bonding the chip bridge.
[0086] The interconnect posts 100 are used for electrical connection with the redistribution layer 700 and are subsequently electrically connected to the first chip and the chip structure, so as to achieve longitudinal electrical connection between the first chip and the outside and longitudinal electrical connection between the chip structure and the outside through the interconnect posts 100.
[0087] In this embodiment, the interconnect posts 100 are copper posts, that is, the material of the interconnect posts 100 is copper.
[0088] Reference Figure 8 , bonding the chip bridge 200 to the redistribution layer 700. The chip bridge 200 includes a chip front 20a and a chip back 20b facing away from each other. The chip front 20a of the chip bridge 200 faces the redistribution layer 700.
[0089] The chip bridge 200 is used for subsequent electrical connection between the chip structure and the first chip.
[0090] The chip bridge 200 includes a chip front 20a and a chip back 20b facing away from each other. The chip front 20a is used for electrical connection between the chip bridge 200 and the outside, and the chip back 20b is used for subsequent bonding with the second substrate by fitting.
[0091] In this embodiment, a circuit structure is formed in the chip bridge 200, so that the first chip and the chip structure are electrically connected through the circuit structure subsequently.
[0092] In this embodiment, the chip bridge 200 includes a silicon bridge or an interposer.
[0093] It should be noted that in this embodiment, the thickness of the chip bridge 200 should not be too large or too small. If the thickness of the chip bridge 200 is too large, it is likely to cause the thickness of the interconnect structure to be too large, which is not conducive to improving the integration degree of the packaging structure; if the thickness of the chip bridge 200 is too small, it is likely to affect the formation of the circuit structure in the chip bridge 200 and affect the electrical connection performance of the chip bridge 200. Therefore, in this embodiment, the thickness of the chip bridge 200 is 2 μm to 100 μm.
[0094] Bond the chip bridge 200 to the redistribution layer 700, and expose the chip back surface 20b of the chip bridge 200 to prepare for bonding the second substrate to the chip back surface 20b subsequently.
[0095] In this embodiment, in the step of bonding the chip bridge 200 to the redistribution layer 700, a solder pad 510 is formed between the chip front surface 20a and the redistribution layer 700.
[0096] The solder pad 510 is used to realize the electrical connection between the chip bridge 200 and the redistribution layer subsequently.
[0097] In this embodiment, the material of the solder pad 510 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the solder pad 510 is tin.
[0098] In this embodiment, after bonding the redistribution layer 700 to the first substrate 110, bond the chip bridge 200 to the redistribution layer 700. Correspondingly, in this embodiment, in the step of bonding the chip bridge 200 to the redistribution layer 700, the chip bridge 200 is in contact with the interconnect metal layer 720.
[0099] In this embodiment, in the step of bonding the chip bridge 200 to the redistribution layer 700, the redistribution layer 700 is electrically connected to the solder pad 510, and accordingly, the electrical connection between the redistribution layer 700 and the chip bridge 200 is realized through the solder pad 510.
[0100] In this embodiment, in the step of bonding the chip bridge 200 to the redistribution layer 700, the redistribution layer 700 is also electrically connected to the interconnect post 100, and accordingly, the electrical connection between the redistribution layer 700 and the outside in the longitudinal direction is realized through the interconnect post 100.
[0101] Combined with reference Figure 9 and Figure 10, after forming discrete interconnect posts 100 on the redistribution layers 700 on both sides of the region for bonding the chip bridge 200, and before subsequently bonding the second substrate to the chip back surface 20b of the chip bridge 200, the packaging method further includes: forming a first sealing layer 310 on the redistribution layer 700, the first sealing layer 310 filling the gaps between adjacent interconnect posts 100 and between adjacent pads 510, and the first sealing layer 310 exposing the tops of the interconnect posts 100.
[0102] The first sealing layer 310 is used to achieve sealing between the chip bridge 200 and the redistribution layer 700, achieve sealing between adjacent interconnect posts 100, and achieve sealing of adjacent pads 510.
[0103] Specifically, in this embodiment, the step of forming the first sealing layer 310 on the redistribution layer 700 includes: referring to Figure 9 , forming a first sealing material layer 300 on the redistribution layer 700 that fills the gaps between adjacent interconnect posts 100 and between adjacent pads 510, and the first sealing material layer 300 covering the conductive posts 100 and the chip bridge 200.
[0104] The first sealing material layer 300 is used to directly form the first sealing layer 310.
[0105] Referring to Figure 10 , performing a planarization process on the first sealing material layer 300 until the tops of the conductive posts 100 are exposed.
[0106] Performing a planarization process on the first sealing material layer 300 to obtain a top surface with better flatness, providing a better process platform for subsequent bonding of the second substrate. The first sealing layer 310 exposes the tops of the conductive posts 100, preparing for subsequent electrical connection between the conductive posts 100 and the redistribution layer.
[0107] It should be noted that in the step of performing a planarization process on the first sealing material layer 300, a back thinning process is also performed on the chip bridge 200, removing a part of the thickness of the chip bridge 200 along the chip back surface 20b to obtain a chip bridge 200 with a smaller thickness, which is beneficial to reducing the height difference introduced by the chip bridge 200 and reducing the occupied volume of the chip bridge 200.
[0108] Referring to Figure 11 , bonding the second substrate 120 to the chip back surface 20b of the chip bridge 200.
[0109] The second substrate 120 is used to provide a process operation basis for subsequent bonding of the redistribution layer 700 with the first chip and the chip structure.
[0110] In this embodiment, the material of the second substrate 120 is silicon.
[0111] Specifically, in this embodiment, the second substrate 120 is a carrier substrate.
[0112] In this embodiment, the second substrate 120 is a wafer. In other embodiments, the second substrate may also be a glass substrate.
[0113] Bond the second substrate 120 to the back side 20b of the chip of the chip bridge 200 to prepare for subsequent removal of the first substrate 110.
[0114] In this embodiment, conductive bumps are usually formed on the front side 20a of the chip of the chip bridge 200 to achieve electrical connection between the chip bridge 200 and the redistribution layer 700. Compared with the solution of bonding the back side of the chip of the chip bridge to the second substrate after forming conductive bumps on the front side of the chip of the chip bridge, due to the unevenness of the front side of the chip caused by the conductive bumps, it is more difficult to bond the chip bridge with the back side of the chip facing down to the second substrate. Therefore, in this embodiment, first bond the front side 20a of the chip of the chip bridge 200 to the redistribution layer 700, and then bond the second substrate 120 to the back side 20b of the chip of the chip bridge 200, avoiding the step of picking up the chip bridge with the uneven front side 20a of the chip, making it easy to bond the back side 20b of the chip of the chip bridge 200 to the second substrate 120, and thus making the packaging method simple and easy to operate.
[0115] Correspondingly, in this embodiment, in the step of bonding the second substrate 120 to the back side 20b of the chip of the chip bridge 200, the second substrate 120 is also bonded to the interconnect posts 100.
[0116] Correspondingly, in this embodiment, in the step of bonding the second substrate 120 to the back side 20b of the chip of the chip bridge 200, the second substrate 120 is also bonded to the first sealing layer 310.
[0117] Continue to refer to Figure 11 , remove the first substrate 110 to expose the redistribution layer 700.
[0118] Exposing the redistribution layer 700 prepares for subsequent bonding of the first chip and the chip structure on the redistribution layer 700.
[0119] Refer to Figure 12 , bond the chip structure 400 and the first chip 440 on the redistribution layer 700. The chip structure 400 is located on the side of the first chip 440. The chip structure 440 is electrically connected to the redistribution layer 700. The first chip 440 is electrically connected to the redistribution layer 700. The first chip 440 is electrically connected to the chip structure 400 through the chip bridge 200.
[0120] The first chip 440 is used to be electrically connected to the redistribution layer 700, so as to realize the electrical connection of the first chip 440 with the outside in the longitudinal direction. Correspondingly, the first chip 440 is electrically connected to the chip bridge 200 through the redistribution layer 700, and the electrical connection between the first chip 440 and the chip structure 400 is realized through the chip bridge 200. The first chip 440 and the chip structure 400 are used to form an integrated package structure.
[0121] Specifically, in this embodiment, the package structure includes a plurality of chip structures 400. The first chip 440 is electrically connected to the redistribution layer 700, and then is electrically connected to each chip structure 400 through the chip bridge 200.
[0122] In this embodiment, the first chip 440 is a logic chip. As the first logic chip in this embodiment, it is used to control the memory chips of the chip structure 400. Specifically, the first logic chip can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or a system on chip (SoC).
[0123] The chip structure 400 is used to be electrically connected to the redistribution layer 700, so as to realize the electrical connection of the chip structure 400 with the outside in the longitudinal direction. Correspondingly, the chip structure 400 is electrically connected to the chip bridge 200 through the redistribution layer 700, and the electrical connection between the chip structure 400 and the first chip 440 is realized through the chip bridge 200.
[0124] In this embodiment, the chip structure 400 includes one or a plurality of second chips 410 stacked along the longitudinal direction (as shown in the Z direction in Figure 12 ), so as to realize the electrical connection between each second chip 410 and the first chip 440, and the electrical connection of each second chip 410 with the outside in the longitudinal direction.
[0125] Specifically, in this embodiment, the chip structure 400 is electrically connected to the redistribution layer 700 and is electrically connected to the first chip 440 through the chip bridge 200.
[0126] In this embodiment, in the chip structure 400, a high bandwidth memory (HBM) structure formed by a plurality of second chips 410 stacked along the longitudinal direction is adopted. By adopting the HBM structure, it is beneficial to meet the requirements for higher information transmission speed.
[0127] Among them, the second chip 410 includes a bottom chip located at the bottommost part and a top chip stacked on the bottom chip, and the number of top chips can be one or more. In this embodiment, an example is given where the number of top chips is four. In other embodiments, the number of top chips can also be other values.
[0128] Therefore, in this embodiment, the top chip is a memory chip. In a specific implementation, the top chip is a High Bandwidth Memory chip.
[0129] In this embodiment, the bottom chip is a second logic chip. Specifically, the bottom chip is used as the logic control chip in the chip structure 400.
[0130] In this embodiment, the bottom chip is electrically connected to the substrate 120 and between adjacent second chips 410 in the longitudinal direction, thereby realizing electrical integration between the second chips 410 and electrical integration between the second chips 410 and the substrate 120.
[0131] In this embodiment, the number of chip structures 400 is multiple. Using multiple chip structures 400 to be electrically connected to the first chip 440 is beneficial to increasing the memory of the package structure, improving the chip speed, and reducing the chip power consumption.
[0132] In this embodiment, the steps of bonding the chip structure 400 and the first chip 440 on the redistribution layer 700 include: forming conductive bumps 520 on the redistribution layer 700; or, forming conductive bumps 520 on the first chip 440 and the chip structure 400.
[0133] The conductive bumps 520 are used to realize electrical connection between the first chip 440 and the redistribution layer 700 and electrical connection between the chip structure 400 and the redistribution layer 700.
[0134] In this embodiment, the material of the conductive bumps 520 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the conductive bumps 520 is tin.
[0135] In this embodiment, the conductive bumps 520 can be micro-bumps (uBump). The micro-bump density is relatively high, which is beneficial to improving the communication speed between the first chip 440 and the redistribution layer 700 and between the chip structure 400 and the redistribution layer 700.
[0136] Correspondingly, in this embodiment, the chip structure 400 and the first chip 440 are bonded to the redistribution layer 700 by using the conductive bumps 520.
[0137] In this embodiment, the encapsulation method further includes: forming a second sealing layer 320 filled between adjacent conductive bumps 520 and in the gaps between adjacent conductive bumps 520, and the second sealing layer 320 covers the conductive bumps 520.
[0138] The second sealing layer 320 is used to seal between the first chip 440 and the redistribution layer 700, to seal between the chip structure 400 and the redistribution layer 700, and to seal adjacent conductive bumps 520.
[0139] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. An encapsulation structure, characterized in that, it includes: a substrate; a chip bridge, including a chip front and a chip back facing away from each other, the chip back of the chip bridge faces the substrate and is bonded to the substrate; a redistribution layer, bonded to the chip front of the chip bridge, the redistribution layer includes one or more stacked interconnect layers, the interconnect layer includes an interconnect via hole and an interconnect metal layer located on the interconnect via hole, and the chip bridge is in contact with the interconnect metal layer; bonding pads, located between the chip front and the substrate, the bonding pads electrically connect the chip bridge and the redistribution layer; a first chip, bonded to the redistribution layer, the first chip is electrically connected to the redistribution layer and the chip bridge; a chip structure, bonded to the redistribution layer on the side of the first chip, the chip structure is electrically connected to the redistribution layer, and the chip structure is electrically connected to the first chip through the chip bridge.
2. The encapsulation structure according to claim 1, characterized in that, the encapsulation structure further includes: interconnect posts, separated on the substrate on both sides of the chip bridge, and the interconnect posts are electrically connected to the redistribution layer.
3. The encapsulation structure according to claim 2, characterized in that, the encapsulation structure further includes: a first sealing layer, filling the gaps between adjacent interconnect posts between the substrate and the redistribution layer, and between adjacent bonding pads.
4. The encapsulation structure according to claim 1, characterized in that, the encapsulation structure further includes: conductive bumps located between the redistribution layer and the first chip, and between the redistribution layer and the chip structure, the conductive bumps electrically connect the first chip and the redistribution layer, and the conductive bumps also electrically connect the chip structure and the redistribution layer.
5. The encapsulation structure according to claim 4, characterized in that, the encapsulation structure further includes: a second sealing layer, filling the gaps between adjacent conductive bumps and within the gaps between adjacent conductive bumps, and covering the conductive bumps.
6. The encapsulation structure according to claim 1, characterized in that, the first chip includes a logic chip, the chip structure includes one or a plurality of second chips stacked longitudinally, and the second chips include memory chips.
7. The encapsulation structure according to claim 1, characterized in that, the thickness of the chip bridge is 2μm to 100μm.
8. An encapsulation method, characterized in that, it includes: providing a first substrate, on which a redistribution layer is formed; bonding a chip bridge to the redistribution layer, the chip bridge includes a chip front and a chip back facing away from each other, and the chip front of the chip bridge faces the redistribution layer; bonding a second substrate to the chip back of the chip bridge; removing the first substrate to expose the redistribution layer; bonding a chip structure and a first chip on the redistribution layer, the chip structure is located on the side of the first chip, the chip structure is electrically connected to the redistribution layer, the first chip is electrically connected to the redistribution layer, and the first chip is electrically connected to the chip structure through the chip bridge.
9. The encapsulation method according to claim 8, characterized in that, In the step of chip bridge bonding to the redistribution layer, bonding pads are formed between the front side of the chip and the redistribution layer.
10. The packaging method according to claim 9, wherein, before chip bridge bonding to the redistribution layer, the packaging method further includes: forming discrete interconnect posts on the redistribution layer on both sides of the area for bonding the chip bridge; in the step of bonding the second substrate to the back side of the chip of the chip bridge, the second substrate is also bonded to the interconnect posts.
11. The packaging method according to claim 10, wherein, after forming discrete interconnect posts on the redistribution layer on both sides of the area for bonding the chip bridge and before bonding the second substrate to the back side of the chip of the chip bridge, the packaging method further includes: forming a first sealing layer on the redistribution layer, the first sealing layer filling the gaps between adjacent interconnect posts and between adjacent bonding pads, and the first sealing layer exposing the tops of the interconnect posts; in the step of bonding the second substrate to the back side of the chip of the chip bridge, the second substrate is also bonded to the first sealing layer.
12. The packaging method according to claim 11, wherein, the step of forming the first sealing layer on the redistribution layer includes: forming a first sealing material layer on the redistribution layer that fills the gaps between adjacent interconnect posts and between adjacent bonding pads, the first sealing material layer covering the conductive posts and the chip bridge; performing a planarization process on the first sealing material layer until the tops of the conductive posts are exposed.
13. The packaging method according to claim 8, wherein, in the step of providing the first substrate, the redistribution layer includes one or more stacked interconnect layers, and the interconnect layer includes interconnect vias and an interconnect metal layer located on the interconnect vias; in the step of bonding the chip bridge to the redistribution layer, the chip bridge is in contact with the interconnect metal layer.
14. The packaging method according to claim 8, wherein, the step of bonding the chip structure and the first chip to the redistribution layer includes: forming conductive bumps on the redistribution layer; or forming conductive bumps on the first chip and the chip structure; bonding the chip structure and the first chip to the redistribution layer using the conductive bumps.
15. The packaging method according to claim 14, wherein, the packaging method further includes: forming a second sealing layer that fills the gaps between adjacent conductive bumps and within the gaps between adjacent conductive bumps, the second sealing layer covering the conductive bumps.
16. The packaging method according to claim 8, wherein, the first chip includes a logic chip, the chip structure includes one or a plurality of second chips stacked longitudinally, and the second chips include memory chips.