A high-voltage LDO power supply circuit

Abstract

The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a high-voltage LDO power supply circuit, which includes an output Vout, an overshoot optimization module, an MOS transistor MP2, and a transient optimization module; the transient optimization module includes a transconductance amplifier A2, a capacitor C3, a comparator A3, a transient suppression sub-module, and a transient recovery sub-module; one end of the capacitor C3 is connected to the output Vout; the other end of the capacitor C3 is connected to the positive input terminal of the transconductance amplifier A2; the output terminal of the transconductance amplifier A2 is connected to the positive input terminal of the comparator A3; the negative input terminal of the transconductance amplifier A2 is grounded; the negative input terminal of the comparator A3 is connected to a reference current Iref; the input terminals of the transient suppression sub-module and the transient recovery sub-module are respectively connected to the output terminal of the comparator A3; the output terminals of the transient suppression sub-module and the transient recovery sub-module are respectively connected to the gate of the MOS transistor MP2; improving the transient response performance and reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and particularly to a high-voltage LDO power supply circuit. Background Art

[0002] In a high-voltage LDO power supply circuit, the input voltage is usually 12V, 24V, 36V or 48V, etc. When the load changes, the output voltage may have a large overshoot or undershoot phenomenon, resulting in a decline in system performance or even damage to sensitive devices. To address this problem, the prior art usually sets an overshoot suppression module to respond to load changes to reduce the amplitude and duration of the overshoot voltage.

[0003] However, when the output voltage fluctuates caused by a load transient jump, the existing overshoot suppression module often cannot respond to the transient jump in time to suppress the transient overshoot caused by the transient jump. Therefore, the existing high-voltage LDO power supply circuit still has the problem of low transient response performance. Summary of the Invention

[0004] The object of the present invention is to overcome the above-mentioned drawbacks and provide a high-voltage LDO power supply circuit to improve the transient response performance and reliability.

[0005] To achieve the above object, the specific solution of the present invention is as follows:

[0006] A high-voltage LDO power supply circuit includes an output Vout, an overshoot optimization module, a MOS transistor MP2, and a transient optimization module; the overshoot optimization module is connected to the gate of the MOS transistor MP2; the drain of the MOS transistor MP2 is connected to the output Vout; the source of the MOS transistor MP2 is grounded;

[0007] The transient optimization module includes a transconductance amplifier A2, a capacitor C3, a comparator A3, a transient suppression sub-module, and a transient recovery sub-module; one end of the capacitor C3 is connected to the output Vout; the other end of the capacitor C3 is connected to the positive input terminal of the transconductance amplifier A2; the output terminal of the transconductance amplifier A2 is connected to the positive input terminal of the comparator A3; the negative input terminal of the transconductance amplifier A2 is grounded; the negative input terminal of the comparator A3 is connected to a reference current Iref; the input terminals of the transient suppression sub-module and the transient recovery sub-module are respectively connected to the output terminal of the comparator A3; the output terminals of the transient suppression sub-module and the transient recovery sub-module are respectively connected to the gate of the MOS transistor MP2.

[0008] Optionally, the transient suppressor module includes MOS transistor Q1, MOS transistor Q2, MOS transistor Q3, MOS transistor Q4, and MOS transistor MP3. The gates of MOS transistor Q1 and MOS transistor Q3 are connected and then connected to the output terminal of comparator A3. The drains of MOS transistor Q1 and MOS transistor Q3 are connected. The sources of MOS transistor Q1 and MOS transistor Q2 are connected and then connected to power supply VDD3. The gates of MOS transistor Q2 and MOS transistor Q4 are connected and then connected to the drain of MOS transistor Q1. The sources of MOS transistor Q3 and MOS transistor Q4 are connected and then grounded. The drains of MOS transistor Q2 and MOS transistor Q4 are connected and then connected to the gate of MOS transistor MP3. The drain of MOS transistor MP3 is connected to the gate of MOS transistor MP2. The source of MOS transistor MP3 is grounded.

[0009] Optionally, a diode D2 is connected in series between the gate and the source of MOS transistor MP3. The cathode of diode D2 is connected to the gate of MOS transistor MP3. The anode of diode D2 is connected to the source of MOS transistor MP3. The gate of MOS transistor MP3 is also grounded through a series-connected resistor R1.

[0010] Optionally, the transient recovery sub-module includes inverter A6, transconductance amplifier A4, capacitor C1, resistor R2, MOS transistor Q13, MOS transistor Q14, MOS transistor Q15, MOS transistor Q16, MOS transistor Q17, MOS transistor Q5, and MOS transistor Q6. The input terminal of inverter A6 is connected to the output terminal of comparator A3. One end of resistor R2 is connected to the output terminal of inverter A6. The other end of resistor R2 is respectively connected to one end of capacitor C1, the gate of MOS transistor Q13, and the gate of MOS transistor Q15. The sources of MOS transistor Q13, MOS transistor Q14, and the drain of MOS transistor Q17 are connected to power supply VDD3. The drains of MOS transistor Q13, the gate of MOS transistor Q14, the drains of MOS transistor Q15, and the gate of MOS transistor Q16 are connected. The drains of MOS transistor Q14, the drains of MOS transistor Q16, and the gate of MOS transistor Q17 are connected. The other end of capacitor C1, the sources of MOS transistor Q15, and the sources of MOS transistor Q16 are grounded.

[0011] The positive input terminal of transconductance amplifier A4 is connected to the source of MOS transistor Q17. The negative input terminal of transconductance amplifier A4 is grounded. The gates, drains of MOS transistor Q5, and the gate of MOS transistor Q6 are connected and then connected to the output terminal of transconductance amplifier A4. The sources of MOS transistor Q5 and MOS transistor Q6 are connected and then grounded. The drain of MOS transistor Q6 is connected to the gate of MOS transistor MP2.

[0012] Optionally, the transient optimization module further includes a diode D1; the anode of the diode D1 is grounded; the cathode of the diode D1 is connected to the output terminal of the comparator A3.

[0013] Optionally, the high-voltage LDO power supply circuit further includes an error amplifier A1, a MOS transistor MP1, and a resistor feedback network;

[0014] The positive input terminal of the error amplifier A1 is connected to the resistor feedback network; the negative input terminal of the error amplifier A1 is connected to a reference voltage Vref; the output terminal of the error amplifier A1 is connected to the gate of the MOS transistor MP1; the drain of the MOS transistor MP1 is connected to a power supply VDD1; the source of the MOS transistor MP1 is connected to the output Vout; the resistor feedback network is connected to the source of the MOS transistor MP1.

[0015] Optionally, the overshoot optimization module includes a MOS transistor Q9, a MOS transistor Q10, a MOS transistor Q11, a resistor R4, a resistor R5, a current source I1, and a current source I2; the gate of the MOS transistor Q9 is connected to the gate of the MOS transistor Q10; the drain of the MOS transistor Q9 is connected to the gate of the MOS transistor Q9; the drain of the MOS transistor Q9 is connected in series with the resistor R4 and then connected to the power supply VDD1; the source of the MOS transistor Q9 is connected in series with the current source I1 and then grounded; the source of the MOS transistor Q10 is connected to the gate of the MOS transistor MP2; the drain of the MOS transistor Q10 is connected to the output terminal of the error amplifier A1; one end of the current source I2 is connected to the source of the MOS transistor Q10; one end of the resistor R5 is connected to the source of the MOS transistor Q10; the drain of the MOS transistor Q11 is connected to the other end of the resistor R5; the gate of the MOS transistor Q11 is connected to the drain of the MOS transistor Q11; the source of the MOS transistor Q11 is connected to the other end of the current source I2 and grounded.

[0016] Optionally, the resistor feedback network includes a resistor RF1 and a resistor RF2; one end of the series connection of the resistor RF1 and the resistor RF2 is connected to the source of the MOS transistor MP1; the other end of the series connection of the resistor RF1 and the resistor RF2 is grounded; the positive input terminal of the error amplifier A1 is connected to the common terminal of the resistor RF1 and the resistor RF2.

[0017] Optionally, the high-voltage LDO power supply circuit further includes a capacitor CL and a resistor RL; one end of the capacitor CL and one end of the resistor RL are respectively connected to the output Vout; the other end of the capacitor CL and the other end of the resistor RL are respectively grounded.

[0018] Optionally, the high-voltage LDO power supply circuit further includes a transient feedback reset module; the transient feedback reset module includes a capacitor C5, a resistor R6, an inverter A5, and a MOS transistor Q12; two ends of the resistor R6 are respectively connected to an output end of an error amplifier A1 and a gate of the MOS transistor MP1; the capacitor C5 is connected in parallel with the resistor R6; an input end of the inverter A5 is connected to the output end of the error amplifier A1; a gate of the MOS transistor Q12 is connected to an output end of the inverter A5; a source of the MOS transistor Q12 is grounded; a drain of the MOS transistor Q12 is connected to the gate of the MOS transistor MP1.

[0019] The beneficial effects of the present invention are as follows: By the cooperative cooperation of the capacitor C3, the transconductance amplifier A2, and the comparator A3, the present invention performs real-time detection on the transient jump of the output Vout to quickly respond to the transient jump of the output Vout. At the same time, by the cooperative cooperation of the transient suppression sub-module and the transient recovery sub-module, the transient jump is suppressed and the smooth exit after suppression is achieved, thereby improving the transient response performance and reliability. Description of the Drawings

[0020] Figure 1 is the circuit schematic diagram of the high-voltage LDO power supply circuit of the present invention;

[0021] Figure 2 is the circuit schematic diagram of the transient optimization module of the present invention;

[0022] Figure 3 is the circuit schematic diagram of the bias configuration module of the present invention;

[0023] Description of the reference numerals: 100, overshoot optimization module; 200, resistor feedback network; 300, transient optimization module; 301, transient suppression sub-module; 302, transient recovery sub-module; 303, bias configuration module; 400, transient feedback reset module. Detailed Embodiments

[0024] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments, and the scope of implementation of the present invention is not limited thereto.

[0025] Such as Figures 1 to 3As shown in the figure, a high-voltage LDO power supply circuit described in this embodiment includes an error amplifier A1, a MOS transistor MP1, an output Vout, an overshoot optimization module 100, a resistor feedback network 200, a MOS transistor MP2, and a transient optimization module 300; the positive input terminal of the error amplifier A1 is connected to the resistor feedback network 200; the negative input terminal of the error amplifier A1 is connected to a reference voltage Vref; the output terminal of the error amplifier A1 is connected to the gate of the MOS transistor MP1; the drain of the MOS transistor MP1 is connected to a power supply VDD1; the source of the MOS transistor MP1 is connected to the output Vout; the resistor feedback network 200 is connected to the source of the MOS transistor MP1. The number of stages of the error amplifier A1 uses a single-stage operational amplifier or a multi-stage operational amplifier, and the structure of the error amplifier A1 uses a two-stage operational amplifier or a cascode structure. The power supply VDD1 is a high-voltage input power supply, such as a 12V, 24V, 36V, or 48V voltage source.

[0026] The high-voltage LDO power supply circuit further includes a capacitor CL and a resistor RL; one end of the capacitor CL and one end of the resistor RL are respectively connected to the output Vout; the other end of the capacitor CL and the other end of the resistor RL are respectively grounded. The capacitor CL uses a Miller frequency compensation capacitor.

[0027] The resistor feedback network 200 includes a resistor RF1 and a resistor RF2; one end of the series connection of the resistor RF1 and the resistor RF2 is connected to the source of the MOS transistor MP1; the other end of the series connection of the resistor RF1 and the resistor RF2 is grounded; the positive input terminal of the error amplifier A1 is connected to the common terminal of the resistor RF1 and the resistor RF2. The common terminal of the resistor RF1 and the resistor RF2 serves as a voltage feedback node, and the positive input terminal of the error amplifier A1 collects the feedback voltage Vfb of the feedback node, and compares the feedback voltage Vfb with the reference voltage Vref to maintain the stability of the output Vout.

[0028] The overshoot optimization module 100 is connected to the gate of the MOS transistor MP2; the drain of the MOS transistor MP2 is connected to the output Vout; the source of the MOS transistor MP2 is grounded; the overshoot optimization module 100 is used for steady-state overshoot suppression. Both the MOS transistor MP1 and the MOS transistor MP2 are PMOS transistors.

[0029] Such as Figure 1 And Figure 2As shown, the transient optimization module 300 is used for fast response and recovery during dynamic load transient jumps to make up for the situation where the overshoot optimization module 100 cannot respond to transient jumps in a timely manner. Specifically, the transient optimization module 300 includes a transconductance amplifier A2, a capacitor C3, a comparator A3, a transient suppression sub-module 301, and a transient recovery sub-module 302; one end of the capacitor C3 is connected to node A of the output Vout; the other end of the capacitor C3 is connected to the positive input terminal of the transconductance amplifier A2; the output terminal of the transconductance amplifier A2 is connected to the positive input terminal of the comparator A3; the negative input terminal of the transconductance amplifier A2 is grounded; the negative input terminal of the comparator A3 is connected to the reference current Iref; the output terminal of the comparator A3 outputs a TRIG trigger signal; the input terminals of the transient suppression sub-module 301 and the transient recovery sub-module 302 are respectively connected to the output terminal of the comparator A3; the output terminals of the transient suppression sub-module 301 and the transient recovery sub-module 302 are respectively connected to the gate of the MOS transistor MP2.

[0030] Specifically, the capacitor C3 is used for high-frequency dV / dt signal extraction and blocks DC offset. The capacitance value of the capacitor C3 is set according to the parasitic capacitance of the output Vout and the transient response requirements. For example, it is 100 fF. The capacitance value of the capacitor C3 is set small enough, and the capacitance value of the capacitor C3 is much smaller than the total parasitic capacitance of the output Vout node. For example, it is less than 1 / 10 of the parasitic capacitance, to avoid signal attenuation and only transmit high-frequency transient signals to avoid interfering with the steady-state feedback. The transconductance amplifier A2 has a high bandwidth. The bandwidth of the transconductance amplifier A2 can be set to be more than 10 times the load transient frequency to ensure nanosecond-level response. For example, the bandwidth of the transconductance amplifier A2 is greater than 100 MHz to quickly capture high-frequency dV / dt signals and be able to capture nanosecond-level transients. The reference current Iref is calibrated according to the maximum allowable overshoot slope of the LDO power supply circuit (such as 10 mV / ns) to ensure triggering only at the initial stage of overshoot. The calibration formula of the reference current Iref is as follows: , where Iref is the reference current, is the capacitance value of the capacitor C3, is the maximum allowable overshoot slope.

[0031] When the load is in a steady state, the transient optimization module 300 is in an inoperative state, and a voltage feedback loop composed of the error amplifier A1 and the resistor feedback network 200 stably regulates the output Vout;

[0032] When there is a transient jump in the load, a high-frequency dV / dt signal will be generated at the output Vout. The high-frequency dV / dt signal is input to the transconductance amplifier A2 through the capacitor C3. The transconductance amplifier A2 outputs a current signal Igm. The current signal Igm flows into the input terminal of the comparator A3 and is compared with the reference current Iref. The comparator A3 outputs a trigger signal TRIG. When Igm is greater than Iref, the comparator A3 outputs a high-level trigger signal TRIG, that is, TRIG = 1, driving the transient suppression sub-module 301 to pull down the gate voltage of the MOS transistor MP2 to a low level, accelerating the conduction of the MOS transistor MP2, and triggering the pull-down current in advance to quickly respond to the transient jump of the output Vout.

[0033] When the trigger signal TRIG jumps from a high level to a low level, that is, TRIG changes from 1 to 0, a short pulse signal is generated. During the pulse, the transient recovery sub-module 302 is activated to generate a linearly decreasing ramp current, controlling the gate voltage of the MOS transistor MP2 to rise slowly to avoid premature turn-off resulting in secondary fluctuations.

[0034] When the transient suppression sub-module 301 fails to completely eliminate the overshoot and the output terminal of the comparator A3 still maintains the output of the low-level trigger signal TRIG, or the transient optimization module 300 is not triggered; at this time, since the trigger signal TRIG output by the comparator A3 does not jump, the transient recovery sub-module 302 is turned off, and the error amplifier A1 outputs a high level, so that the MOS transistor MP1 remains off. At this time, the overshoot optimization module 100 will be triggered to output a low level to the gate of the MOS transistor MP2, and the MOS transistor MP2 conducts, continuing to provide a pull-down current for the output Vout until the feedback voltage Vfb is equal to the reference voltage Vref. When the error amplifier A1 outputs a low level, the MOS transistor MP1 conducts again, and the overshoot optimization module 100 is turned off, and the MOS transistor MP2 is turned off, returning to the voltage feedback loop regulation under normal conditions.

[0035] In this embodiment, through the coordinated cooperation of the capacitor C3, the transconductance amplifier A2 and the comparator A3, the transient jump of the output Vout is detected in real time to quickly respond to the transient jump of the output Vout. At the same time, the transient suppression sub-module 301 and the transient recovery sub-module 302 are used in coordination to suppress the transient jump and smoothly exit after suppression, improving the transient response performance and reliability.

[0036] Such as Figure 1 and Figure 2As shown, in the high-voltage LDO power supply circuit of this embodiment, in some embodiments, the transient suppression sub-module 301 includes MOS transistor Q1, MOS transistor Q2, MOS transistor Q3, MOS transistor Q4, and MOS transistor MP3; the gates of MOS transistor Q1 and MOS transistor Q3 are connected and then connected to the output terminal of comparator A3; the drains of MOS transistor Q1 and MOS transistor Q3 are connected; the sources of MOS transistor Q1 and MOS transistor Q2 are connected and then connected to power supply VDD3; the gates of MOS transistor Q2 and MOS transistor Q4 are connected and then connected to the drain of MOS transistor Q1; the sources of MOS transistor Q3 and MOS transistor Q4 are connected and then grounded; the drains of MOS transistor Q2 and MOS transistor Q4 are connected and then connected to the gate of MOS transistor MP3; the drain of MOS transistor MP3 and the gate of MOS transistor MP2 are connected to node B; the source of MOS transistor MP3 is grounded. MOS transistor Q1, MOS transistor Q2, and MOS transistor MP3 are all PMOS transistors; MOS transistor Q3 and MOS transistor Q4 are all NMOS transistors. The power supply VDD3 can be provided by the output Vout.

[0037] In this embodiment, a low-delay buffer is formed by MOS transistor Q1, MOS transistor Q2, MOS transistor Q3, and MOS transistor Q4 to enhance the signal driving ability, reduce the signal rise / fall time, and avoid the delay caused by the gate capacitance of MOS transistor MP3, making the transient response of the transient suppression sub-module 301 faster. When the comparator A3 outputs a high-level trigger signal TRIG, the trigger signal TRIG drives the gate of MOS transistor MP3 through the low-delay buffer, causing MOS transistor MP3 to conduct, pulling down the voltage of MOS transistor MP2, causing MOS transistor MP2 to conduct, providing a pull-down current for the output Vout, and enhancing the pull-down current to suppress overshoot. When the comparator A3 outputs a low-level trigger signal TRIG, MOS transistor MP3 is turned off, causing the transient suppression sub-module 301 to exit the overshoot suppression operation.

[0038] As Figure 1 and Figure 2As shown in the figure, in the high-voltage LDO power supply circuit of this embodiment, in some embodiments, a diode D2 is connected in series between the gate and the source of MOS transistor MP3; the cathode of diode D2 is connected to the gate of MOS transistor MP3; the anode of diode D2 is connected to the source of MOS transistor MP3; the gate of MOS transistor MP3 is also grounded after being connected in series with resistor R1. In this embodiment, by setting diode D2 between the gate and the source of MOS transistor MP3, the gate of MOS transistor MP3 is effectively prevented from being broken down by overvoltage; by setting the gate of MOS transistor MP3 to be grounded after being connected in series with resistor R1, it is used to pull down the gate potential of MOS transistor MP3 to ground when MOS transistor MP3 is turned off, so as to ensure that when comparator A3 outputs a low-level trigger signal TRIG, MOS transistor MP3 can be completely turned off, and the structural reliability is higher. The resistance value of resistor R1 can be set to 10 kΩ.

[0039] As Figure 1 and Figure 2 As shown in the figure, in the high-voltage LDO power supply circuit of this embodiment, in some embodiments, the transient recovery sub-module 302 includes inverter A6, transconductance amplifier A4, capacitor C1, resistor R2, MOS transistors Q13, Q14, Q15, Q16, Q17, Q5 and Q6; the input end of inverter A6 is connected to the output end of comparator A3, and one end of resistor R2 is connected to the output end of inverter A6; the other end of resistor R2 is connected to one end of capacitor C1, the gate of MOS transistor Q13 and the gate of MOS transistor Q15; the source of MOS transistor Q13, the source of MOS transistor Q14, and the drain of MOS transistor Q17 are connected to power supply VDD3; the drain of MOS transistor Q13, the gate of MOS transistor Q14, the drain of MOS transistor Q15, and the gate of MOS transistor Q16 are connected together; the drain of MOS transistor Q14, the drain of MOS transistor Q16, and the gate of MOS transistor Q17 are connected together; the other end of capacitor C1, the source of MOS transistor Q15, and the source of MOS transistor Q16 are grounded;

[0040] The positive input end of transconductance amplifier A4 is connected to the source of MOS transistor Q17; the negative input end of transconductance amplifier A4 is grounded; the gate, drain of MOS transistor Q5, and the gate of MOS transistor Q6 are connected together and then connected to the output end of transconductance amplifier A4; the source of MOS transistor Q5 and the source of MOS transistor Q6 are connected together and then grounded; the drain of MOS transistor Q6 is connected to the gate of MOS transistor MP2 and connected to node B. MOS transistors Q13 and Q14 are PMOS transistors; MOS transistors Q15, Q16, Q17, Q5 and Q6 are all NMOS transistors.

[0041] Specifically, the capacitor C1 and the resistor R2 form an RC delay circuit for generating a linearly decreasing voltage ramp. The time constant of the RC delay circuit is greater than the turn-off time of the transient suppression sub-module 301. The time constant is obtained by the following formula: , where is the resistance value of the resistor R2, is the capacitance value of the capacitor C1. When, for example, and , . The MOS transistors Q13, Q14, Q15, and Q16 form a low-delay buffer to enhance the signal driving ability; the transconductance amplifier A4, the MOS transistors Q5, and Q6 form a ramp current source; the transconductance amplifier A4 is preferably a high-linearity transconductance amplifier with a THD < 1% to ensure the ramp accuracy.

[0042] When the trigger signal TRIG jumps from a high level to a low level, after being processed by the inverter A6, the inverter A6 outputs a high-level signal. The high-level signal triggers the delay circuit to generate a linearly decreasing voltage ramp. After being enhanced by the low-delay buffer, it drives the MOS transistor Q17 to conduct. At this time, the ramp current source is activated, and the transconductance amplifier A4 converts the linearly decreasing voltage ramp into a linearly decreasing ramp current. The source of the MOS transistor Q5 and the MOS transistor Q6 cooperate to mirror the ramp current to the gate of the MOS transistor MP2, causing the gate voltage of the MOS transistor MP2 to rise slowly, realizing smooth control of the pull-down current and avoiding secondary fluctuations; thus improving the reliability and stability of transient overshoot suppression.

[0043] As Figure 1 and Figure 2 shown, in the high-voltage LDO power supply circuit of this embodiment, in some embodiments, the transient optimization module 300 further includes a diode D1; the anode of the diode D1 is grounded; the cathode of the diode D1 is connected to the output terminal of the comparator A3. In this embodiment, the diode D1 is provided to perform negative voltage clamping on the output terminal of the comparator A3 to prevent the overshoot signal from damaging the circuit.

[0044] As Figure 3As shown, in the high-voltage LDO power supply circuit of this embodiment, in some embodiments, the transconductance amplifier A2 has a bias pin BIAS; the bias pin BIAS is connected to a bias configuration module 303; the bias configuration module 303 includes an MOS transistor Q7, an MOS transistor Q8, a resistor R3, a capacitor C2, and a capacitor C4; the gates of the MOS transistor Q7 and the MOS transistor Q8 are connected; the sources of the MOS transistor Q7 and the MOS transistor Q8 are connected and then grounded; the drain of the MOS transistor Q8 is connected to the bias pin BIAS; one end of the resistor R3 is connected to the drain of the MOS transistor Q7; the other end of the resistor R3 is connected to the power supply VDD2; one end of the capacitor C2 is connected to the other end of the resistor R3; the other end of the capacitor C2 is grounded; one end of the capacitor C4 is connected to the drain of the MOS transistor Q8; the other end of the capacitor C4 is grounded. Both the MOS transistor Q7 and the MOS transistor Q8 are NMOS transistors. The power supply VDD2 can be provided by the output Vout.

[0045] Specifically, by setting the capacitor C2, the power supply ripple of the power supply VDD2 is reduced, and its capacitance value can be set to 100 nF; by setting the capacitor C4, high-frequency noise is suppressed, and its capacitance value can be set to 10 pF; the MOS transistor Q7 and the MOS transistor Q8 form a current mirror, and the power supply VDD2 and the resistor R3 cooperate to generate a reference current Ib. The current mirror mirrors the reference current Ib to the bias pin BIAS of the transconductance amplifier A2 according to a certain ratio. The transconductance amplifier A2 generates a bias voltage Vbias through its internal circuit, thereby controlling the transconductance gain Gm of the transconductance amplifier A2 to adapt to different load slew rates and meet different application scenarios.

[0046] As Figure 1 As shown, in the high-voltage LDO power supply circuit of this embodiment, in some embodiments, the overshoot optimization module 100 includes an MOS transistor Q9, an MOS transistor Q10, an MOS transistor Q11, a resistor R4, a resistor R5, and current sources I1 and I2; the gates of the MOS transistor Q9 and the MOS transistor Q10 are connected; the drain of the MOS transistor Q9 is connected to its gate; the drain of the MOS transistor Q9 is connected in series with the resistor R4 and then connected to the power supply VDD1; the source of the MOS transistor Q9 is connected in series with the current source I1 and then grounded; the source of the MOS transistor Q10 is connected to the gate of the MOS transistor MP2 and connected to the node B; the drain of the MOS transistor Q10 is connected to the output terminal of the error amplifier A1; one end of the current source I2 is connected to the source of the MOS transistor Q10; one end of the resistor R5 is connected to the source of the MOS transistor Q10; the drain of the MOS transistor Q11 is connected to the other end of the resistor R5; the gate of the MOS transistor Q11 is connected to its drain; the source of the MOS transistor Q11 is grounded. The current sources I1 and I2 are both current loads described by simulation. For example, the current value of the current source I1 is 10 μA, and the current value of the current source I2 is 20 μA. The MOS transistor Q9, the MOS transistor Q10, and the MOS transistor Q11 are all PMOS transistors.

[0047] Specifically, when the transient suppressor module 301 fails to completely eliminate the overshoot and the trigger signal TRIG with a low level output remains at the output terminal of comparator A3, or when the transient optimization module 300 is not triggered, the error amplifier A1 outputs a high level, turning off the MOS transistor MP1. At this time, the MOS transistor Q10 is turned on, and the current flows through the resistor R5 and the MOS transistor Q11, causing the MOS transistor MP2 to conduct, providing a pull-down current for the output Vout to suppress the transient overshoot. Until the feedback voltage Vfb is equal to the reference voltage Vref, the MOS transistor MP1 is turned on again and the MOS transistor Q10 is turned off, thereby achieving the suppression of the secondary overshoot.

[0048] As Figure 1 shown, in some embodiments of the high-voltage LDO power supply circuit of this embodiment, the high-voltage LDO power supply circuit further includes a transient feedback reset module 400. The transient feedback reset module 400 is used to quickly reset the gate voltage of the MOS transistor MP1 after the transient suppression is completed. Specifically, the transient feedback reset module 400 includes a capacitor C5, a resistor R6, an inverter A5, and a MOS transistor Q12. The two ends of the resistor R6 are respectively connected to the output terminal of the error amplifier A1 and the gate of the MOS transistor MP1. The capacitor C5 is connected in parallel with the resistor R6. The input terminal of the inverter A5 is connected to the output terminal of the error amplifier A1. The gate of the MOS transistor Q12 is connected to the output terminal of the inverter A5. The source of the MOS transistor Q12 is grounded. The drain of the MOS transistor Q12 is connected to the gate of the MOS transistor MP1. The resistor R6 can be set to 1Ω to 100Ω, and the capacitance value of the capacitor C5 can be set to 1pF to 100pF. The MOS transistor Q12 is an NMOS transistor.

[0049] Specifically, in the steady state, the resistor R6 serves as a DC path, and the capacitor C5 is regarded as an open circuit, which does not affect the DC level. The output voltage of the error amplifier A1 controls the conduction of the MOS transistor MP1 through the resistor R6 to ensure the stability of the output Vout. During a load transient jump, the capacitor C5 provides a low-impedance path, and the transient current is directly coupled to the gate of the MOS transistor MP1 through the capacitor C5, accelerating the adjustment of the gate voltage of the MOS transistor MP1. At this time, the error amplifier A1 outputs a high level, and the MOS transistor Q12 is in the off state.

[0050] After the overshoot suppression is completed, the error amplifier A1 outputs a low level, the inverter A5 outputs a high level, driving the MOS transistor Q12 to conduct, thereby quickly pulling down the gate level of MP1 to the ground, accelerating the turn-off speed of MP1, optimizing the transient response, and enhancing the circuit reliability.

[0051] The above description is only a preferred embodiment of the present invention. Therefore, any equivalent changes or modifications made according to the structures, features, and principles described in the scope of the present invention patent application are included in the protection scope of the present invention patent application.

Claims

1. A high-voltage LDO power supply circuit, characterized in that, It includes an output Vout, an overshoot optimization module (100), an MOS transistor MP2, and a transient optimization module (300); the overshoot optimization module (100) is connected to the gate of the MOS transistor MP2; the drain of the MOS transistor MP2 is connected to the output Vout; the source of the MOS transistor MP2 is grounded; The transient optimization module (300) includes a transconductance amplifier A2, a capacitor C3, a comparator A3, a transient suppression sub-module (301), and a transient recovery sub-module (302); one end of the capacitor C3 is connected to the output Vout; the other end of the capacitor C3 is connected to the positive input terminal of the transconductance amplifier A2; the output terminal of the transconductance amplifier A2 is connected to the positive input terminal of the comparator A3; the negative input terminal of the transconductance amplifier A2 is grounded; the negative input terminal of the comparator A3 is connected to a reference current Iref; the input terminals of the transient suppression sub-module (301) and the transient recovery sub-module (302) are respectively connected to the output terminal of the comparator A3; the output terminals of the transient suppression sub-module (301) and the transient recovery sub-module (302) are respectively connected to the gate of the MOS transistor MP2.

2. The high-voltage LDO power supply circuit according to claim 1, wherein The transient suppression sub-module (301) includes MOS transistors Q1, Q2, Q3, Q4, and an MOS transistor MP3; the gates of the MOS transistor Q1 and the MOS transistor Q3 are connected together and then connected to the output terminal of the comparator A3; the drains of the MOS transistor Q1 and the MOS transistor Q3 are connected; the sources of the MOS transistor Q1 and the MOS transistor Q2 are connected together and then connected to a power supply VDD3; the gates of the MOS transistor Q2 and the MOS transistor Q4 are connected together and then connected to the drain of the MOS transistor Q1; the sources of the MOS transistor Q3 and the MOS transistor Q4 are connected together and then grounded; the drains of the MOS transistor Q2 and the MOS transistor Q4 are connected together and then connected to the gate of the MOS transistor MP3; the drain of the MOS transistor MP3 is connected to the gate of the MOS transistor MP2; the source of the MOS transistor MP3 is grounded.

3. The high-voltage LDO power supply circuit according to claim 2, wherein, A diode D2 is connected in series between the gate and the source of the MOS transistor MP3; the cathode of the diode D2 is connected to the gate of the MOS transistor MP3; the anode of the diode D2 is connected to the source of the MOS transistor MP3; the gate of the MOS transistor MP3 is also grounded through a series-connected resistor R1.

4. The high-voltage LDO power supply circuit according to claim 2, wherein The transient recovery sub-module (302) includes an inverter A6, a transconductance amplifier A4, a capacitor C1, a resistor R2, MOS transistors Q13, Q14, Q15, Q16, Q17, Q5, and Q6; the input end of the inverter A6 is connected to the output end of the comparator A3, and one end of the resistor R2 is connected to the output end of the inverter A6; the other end of the resistor R2 is respectively connected to one end of the capacitor C1, the gate of the MOS transistor Q13, and the gate of the MOS transistor Q15; the source of the MOS transistor Q13, the source of the MOS transistor Q14, and the drain of the MOS transistor Q17 are connected to the power supply VDD3; the drain of the MOS transistor Q13, the gate of the MOS transistor Q14, the drain of the MOS transistor Q15, and the gate of the MOS transistor Q16 are connected; the drain of the MOS transistor Q14, the drain of the MOS transistor Q16, and the gate of the MOS transistor Q17 are connected; the other end of the capacitor C1, the source of the MOS transistor Q15, and the source of the MOS transistor Q16 are grounded; the positive input end of the transconductance amplifier A4 is connected to the source of the MOS transistor Q17; the negative input end of the transconductance amplifier A4 is grounded; the gates of the MOS transistors Q5, Q5's drain, and the gate of the MOS transistor Q6 are connected and then connected to the output end of the transconductance amplifier A4; the sources of the MOS transistors Q5 and Q6 are connected and then grounded; the drain of the MOS transistor Q6 is connected to the gate of the MOS transistor MP2.

5. The high-voltage LDO power supply circuit according to claim 1, wherein The transient optimization module (300) further includes a diode D1; the anode of the diode D1 is grounded; the cathode of the diode D1 is connected to the output end of the comparator A3.

6. The high-voltage LDO power supply circuit according to claim 1, wherein The high-voltage LDO power supply circuit further includes an error amplifier A1, a MOS transistor MP1, and a resistor feedback network (200); the positive input end of the error amplifier A1 is connected to the resistor feedback network (200); the negative input end of the error amplifier A1 is connected to the reference voltage Vref; the output end of the error amplifier A1 is connected to the gate of the MOS transistor MP1; the drain of the MOS transistor MP1 is connected to the power supply VDD1; the source of the MOS transistor MP1 is connected to the output Vout; the resistor feedback network (200) is connected to the source of the MOS transistor MP1.

7. The high-voltage LDO power supply circuit according to claim 6, wherein The overshoot optimization module (100) includes MOS transistor Q9, MOS transistor Q10, MOS transistor Q11, resistor R4, resistor R5, current source I1 and current source I2; the gate of MOS transistor Q9 is connected to the gate of MOS transistor Q10; the drain of MOS transistor Q9 is connected to the gate of MOS transistor Q9; the drain of MOS transistor Q9 is connected in series with resistor R4 and then connected to power supply VDD1; the source of MOS transistor Q9 is connected in series with current source I1 and then grounded; the source of MOS transistor Q10 is connected to the gate of MOS transistor MP2; the drain of MOS transistor Q10 is connected to the output terminal of error amplifier A1; one end of current source I2 is connected to the source of MOS transistor Q10; one end of resistor R5 is connected to the source of MOS transistor Q10; the drain of MOS transistor Q11 is connected to the other end of resistor R5; the gate of MOS transistor Q11 is connected to the drain of MOS transistor Q11; the source of MOS transistor Q11 is connected to the other end of current source I2 and then grounded.

8. The high-voltage LDO power supply circuit according to claim 6, characterized in that The resistor feedback network (200) includes resistor RF1 and resistor RF2; one end of the series connection of resistor RF1 and resistor RF2 is connected to the source of MOS transistor MP1; the other end of the series connection of resistor RF1 and resistor RF2 is grounded; the positive input terminal of error amplifier A1 is connected to the common terminal of resistor RF1 and resistor RF2.

9. The high-voltage LDO power supply circuit according to claim 6, wherein The high-voltage LDO power supply circuit further includes capacitor CL and resistor RL; one end of capacitor CL and one end of resistor RL are respectively connected to output Vout; the other end of capacitor CL and the other end of resistor RL are respectively grounded.

10. The high-voltage LDO power supply circuit according to claim 6, characterized in that, The high-voltage LDO power supply circuit further includes a transient feedback reset module (400); the transient feedback reset module (400) includes capacitor C5, resistor R6, inverter A5 and MOS transistor Q12; both ends of resistor R6 are respectively connected to the output terminal of error amplifier A1 and the gate of MOS transistor MP1; capacitor C5 is connected in parallel with resistor R6; the input terminal of inverter A5 is connected to the output terminal of error amplifier A1; the gate of MOS transistor Q12 is connected to the output terminal of inverter A5; the source of MOS transistor Q12 is grounded; the drain of MOS transistor Q12 is connected to the gate of MOS transistor MP1.

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