Voltage balance control method of modular direct current transformer and related device

Abstract

The invention discloses a voltage balance control method of a modular direct current transformer and a related device. The method comprises the following steps: acquiring a capacitor voltage value and a bridge arm current value of each bridge arm sub-module of an MMDC; according to the current value of the bridge arm, calculating the charge quantity Qk absorbed by a sub-module capacitor corresponding to each pulse delay phase shift Sk of the MMDC in one period; storing the pulse delay phase shift Sk corresponding to the charge quantity Qk into a set Pos or a pulse phase shift set Neg according to the positive and negative conditions of the charge quantity Qk; sorting the capacitor voltage values to form a sub-module voltage set; and distributing the pulse delay phase shift Sk in the set Pos and the pulse phase shift set Neg to the sub-modules corresponding to the sub-module voltage set, so that the capacitor voltage of each sub-module is balanced. Therefore, the problem that the capacitor voltage of the MMDC sub-module cannot be balanced by an existing sorting algorithm is solved.

Description

Technical Field

[0001] The present invention relates to the technical fields of DC distribution networks, DC transformers, and power electronics, and particularly to a voltage equalization control method and related device for a modular DC transformer. Background Art

[0002] In order to solve the problem of the IGBT (Insulate-Gate Bipolar Transistor - IGBT) switching voltage stress of the Dual Active Bridge DC-DC converter DAB (Dual Active Bridge), the Modular Multilevel DC Converter (MMDC) replaces a single switch in the DAB with cascaded submodules (Submodule, SM) to increase the voltage and rated power of the system. However, it introduces a large number of submodule capacitors as voltage support and energy buffer units, increasing the difficulty of balancing the capacitor voltages of the arm submodules. The imbalance of the internal submodule capacitor voltages of the MMDC will cause overcharging of the submodule capacitors, affecting the normal operation of the converter and even causing equipment damage.

[0003] Due to the intermittency and volatility of renewable energy sources such as photovoltaic and wind power on the medium-voltage side, the primary-side power supply voltage of the MMDC will fluctuate to a certain extent, resulting in a change in the power of the DC transformer, and further causing a mismatch between the primary and secondary voltages of the MMDC. Under this working condition, using the traditional sorting algorithm, the capacitor voltages of the submodules of the MMDC cannot be balanced. Therefore, it is necessary to study the problem of submodule voltage balance under the condition of mismatch between the primary and secondary voltages of the MMDC. Summary of the Invention

[0004] The present invention provides a voltage equalization control method and related device for a modular DC transformer, which are used to solve the problem that the existing sorting algorithm cannot balance the capacitor voltages of the submodules of the MMDC.

[0005] In view of this, in the first aspect of the present invention, a voltage equalization control method for a modular DC transformer is provided, and the method includes:

[0006] Obtain the capacitor voltage values and arm current values of each arm submodule of the MMDC;

[0007] Calculate the charge Qk absorbed by the submodule capacitor within one cycle corresponding to each pulse delay phase shift Sk of the MMDC according to the arm current value;

[0008] Deposit the pulse delay phase shift Sk corresponding to the charge Qk into the set Pos or the pulse phase shift set Neg according to the positive or negative situation of the charge Qk;

[0009] Sort each of the capacitor voltage values to form a sub-module voltage set;

[0010] After allocating the pulse delay phase shift Sk in one of the sets Pos and the pulse phase shift set Neg to the sub-modules corresponding to the sub-module voltage set, then allocate the pulse delay phase shift Sk in the other set to the sub-modules corresponding to the sub-module voltage set, so as to balance the capacitor voltages of each sub-module.

[0011] Optionally, the storing the pulse delay phase shift Sk corresponding to the charge quantity Qk into the set Pos or the pulse phase shift set Neg according to the positive or negative condition of the charge quantity Qk includes:

[0012] Judge the positive or negative of the charge quantity Qk. If the charge quantity Qk is greater than 0, then store the pulse delay phase shift Sk corresponding to the charge quantity Qk into the set Pos; otherwise, store the pulse delay phase shift Sk corresponding to the charge quantity Qk into the pulse phase shift set Neg.

[0013] Optionally, the allocating the pulse delay phase shift Sk in one of the sets Pos and the pulse phase shift set Neg to the sub-modules corresponding to the sub-module voltage set, and then allocating the pulse delay phase shift Sk in the other set to the sub-modules corresponding to the sub-module voltage set, so as to balance the capacitor voltages of each sub-module, includes:

[0014] Allocate the pulse delay phase shift Sk in the set Pos to the sub-modules corresponding to the sub-module voltage set. After the pulse delay phase shift Sk in the set Pos is allocated, then allocate the pulse delay phase shift Sk in the pulse phase shift set Neg to the sub-modules corresponding to the sub-module voltage set.

[0015] Optionally, the sorting each of the capacitor voltage values to form a sub-module voltage set includes:

[0016] Sort each of the capacitor voltage values in descending order to form a sub-module voltage set.

[0017] In a second aspect of the present invention, there is provided a voltage balancing control system for a modular DC transformer, the system includes:

[0018] An acquisition module, configured to acquire the capacitor voltage values and arm currents of each bridge arm sub-module of the MMDC;

[0019] A calculation module, configured to calculate the charge quantity Qk absorbed by the capacitor of each sub-module corresponding to each pulse delay phase shift Sk of the MMDC within one period according to the arm current value;

[0020] A partitioning module, configured to store the pulse delay phase shift Sk corresponding to the charge quantity Qk into the set Pos or the pulse phase shift set Neg according to the positive or negative condition of the charge quantity Qk;

[0021] A sorting module, configured to sort each of the capacitor voltage values to form a sub-module voltage set;

[0022] A control module, configured to, after allocating the pulse delay phase shift Sk in one of the set Pos and the pulse phase shift set Neg to the sub-modules corresponding to the sub-module voltage set, then allocate the pulse delay phase shift Sk in the other set to the sub-modules corresponding to the sub-module voltage set, so as to balance the capacitor voltages of each sub-module.

[0023] Optionally, the partitioning module is specifically configured to:

[0024] Judge the positive or negative of the charge quantity Qk. If the charge quantity Qk is greater than 0, store the pulse delay phase shift Sk corresponding to the charge quantity Qk into the set Pos; otherwise, store the pulse delay phase shift Sk corresponding to the charge quantity Qk into the pulse phase shift set Neg.

[0025] Optionally, the control module is specifically configured to:

[0026] Allocate the pulse delay phase shift Sk in the set Pos to the sub-modules corresponding to the sub-module voltage set. After the pulse delay phase shift Sk in the set Pos is allocated, then allocate the pulse delay phase shift Sk in the pulse phase shift set Neg to the sub-modules corresponding to the sub-module voltage set.

[0027] Optionally, the sorting module is specifically configured to:

[0028] Sort each of the capacitor voltage values in descending order to form a sub-module voltage set.

[0029] In a third aspect of the present invention, there is provided a voltage equalization control device for a modular DC transformer, and the device includes a processor and a memory:

[0030] The memory is configured to store program codes and transmit the program codes to the processor;

[0031] The processor is configured to execute the steps of the voltage equalization control method for the modular DC transformer as described in the first aspect above according to the instructions in the program codes.

[0032] In the fourth aspect of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium is used to store program codes, and the program codes are used to execute the voltage equalization control method of the modular DC transformer described in the first aspect above.

[0033] As can be seen from the above technical solutions, the present invention has the following advantages:

[0034] The voltage equalization control method of the modular DC transformer provided by the present invention realizes the capacitance voltage balance of sub-modules by calculating and constructing a pulse phase shift sequence set in each cycle and distributing it to the obtained sub-module capacitance voltage set; by reconstructing and distributing the pulse phase shift set, the capacitance energy of the MMDC sub-modules in the modular DC transformer is balanced, and the full-range normal operation is achieved; thus solving the problem that the existing sorting algorithms cannot balance the capacitance voltage of the sub-modules of the MMDC. Since only the positive and negative of the absorbed energy need to be judged, in the method of the present invention, only one sorting of the sub-module capacitance voltage is required in each cycle, which greatly reduces the memory consumption of the computer. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 It is a schematic flow chart of a voltage equalization control method of a modular DC transformer provided by an embodiment of the present invention;

[0037] Figure 2 It is a topological structure diagram of MMDC of the voltage equalization control method of the modular DC transformer provided by an embodiment of the present invention;

[0038] Figure 3 It is a half-bridge structure diagram of the sub-module of MMDC of the voltage equalization control method of the modular DC transformer provided by an embodiment of the present invention;

[0039] Figure 4 It is a single sub-module structure diagram of the voltage equalization control method of the modular DC transformer provided by an embodiment of the present invention;

[0040] Figure 5 It is a series sub-module structure diagram of MMDC of the voltage equalization control method of the modular DC transformer provided by an embodiment of the present invention;

[0041] Figure 6The equivalent voltage waveform diagram at both ends of the modular DC transformer provided by the embodiment of the present invention;

[0042] Figure 7 The simulation diagram of Case 1 of the voltage balance control method of the modular DC transformer provided by the embodiment of the present invention;

[0043] Figure 8 The structural schematic diagram of a voltage balance control system of a modular DC transformer provided by the embodiment of the present invention. Detailed implementation manners

[0044] To make the objectives, features, and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the embodiments described below are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0045] The following is the description of the voltage balance control principle of the modular DC transformer provided by the present invention:

[0046] Based on the analysis of the working principle of MMDC and the mathematical modeling of the capacitor voltage of the sub-module, the present invention proposes a voltage balance control method for a modular multi-level transformer.

[0047] The working principle of MMDC is as follows:

[0048] Figure 2 is the topological structure of MMDC, which consists of an intermediate frequency transformer, a full-bridge structure, and MMC. MMC includes two phase units, each phase unit consists of an upper bridge arm and a lower bridge arm. In each bridge arm, n sub-modules (Submodule, denoted as SM1~SMn respectively) with the same circuit parameters are connected in series, and a bridge arm inductor Lp is connected in series in the bridge arm. The sub-module of MMDC is a half-bridge structure composed of IGBT and capacitor. Taking the half-bridge structure shown in Figure 3 as an example to illustrate the working principle of the half-bridge sub-module. The working principle of the half-bridge sub-module includes controlling the switching devices T Figure 4 shown in 1 and the switching device T 2 in different on or off states, so that the sub-module capacitor can be put into or cut off.

[0049] When the switching device T 1 or the freewheeling diode D1 is turned on, the sub-module is put into operation, and the arm current i arm flows through the sub-module capacitor C sm , and the output voltage v sm =vc ; When the switching device T 2 or the freewheeling diode D2 conducts, the sub-module is cut out, and the output voltage v sm = 0.

[0050] S sm is the sub-module switching function, and S sm = 1 corresponds to the sub-module being put into the working state; S sm = 0 corresponds to the cut-out working state of the sub-module. T s is the switching period, and Ds is the duty cycle of S sm . The arm switching function S sm is the sum of the sub-module switching functions. The input voltage v arm of the sub-module chain is the sum of the input voltages of each sub-module. It can be seen from Figure 6 and Figure 5 that the arm of the MMDC full-bridge sub-module structure can be regarded as a single large sub-module with a capacitor voltage of NVc.

[0051] In the embodiment of the present application, the expression of the sub-module switching function S sm is:

[0052]

[0053] In the formula, t 0 is the time starting point of the switching period, t is the independent variable time, and D s is the switch conduction time within a switching period. The output voltage v sm of the sub-module can be written as the product of the switching function S sm and the sub-module capacitor voltage v c , that is . In the quasi-two-level modulation mode, ignoring the capacitor voltage ripple and the transient conversion process of the arm voltage, the entire sub-module chain can be equivalent to a single sub-module with the capacitor voltage enlarged by N times. At this time, the sum of the arm capacitor voltages V arm is:

[0054]

[0055] Mathematical model of the charge absorbed by the MMDC sub-module capacitor in each cycle:

[0056] Taking the lower arm of phase A as an example, the charge absorbed by the sub-module capacitor in each cycle is the integral of the lower arm current ial within the sub-module input interval, which is equal to the area enclosed by ial and the time axis within the corresponding time period.

[0057] Among them, the formula for the absorbed charge is:

[0058]

[0059] Wherein, Q k is the absorbed charge quantity of the k-th sub-module, t end is the end time of the time period t, t start is the initial time of the time period t, d k is the pulse phase shift of the k-th sub-module, T h is the duration of half a switching period, i al (t) is the arm current during the time period t.

[0060] Within each switching period, when the trigger delay signal Sk with Qk>0 is assigned to the sub-module capacitor, the voltage of the sub-module capacitor rises within one period. When the trigger delay signal Sk with Qk<0 is assigned to the sub-module capacitor, the voltage of the sub-module capacitor drops within one period. Therefore, the pulse phase shift Sk corresponding to Qk>0 can be assigned to the sub-module with a higher voltage to reduce its voltage, and the pulse phase shift Sk corresponding to Qk<0 can be assigned to the sub-module with a lower voltage to increase its voltage, so as to achieve the balance of the sub-module capacitor voltage. Based on this principle, the present invention proposes to achieve the balance of the arm sub-module capacitor voltage by judging the positive or negative of the absorbed charge quantity Qk of the MMDC arm sub-modules (each arm has N) in one period. In addition, in order to improve the convergence speed of the sub-module capacitor voltage, the present invention proposes to assign the trigger signals Sk corresponding to all Qk<0 after all the triggers Sk corresponding to Qk>0 are assigned. Thereby improving the convergence speed of the sub-module capacitor voltage balance. Specifically, please refer to the following voltage equalization control method of the modular DC transformer.

[0061] Please refer to Figure 1 , a voltage equalization control method of a modular DC transformer provided in an embodiment of the present invention includes:

[0062] Step 101, obtain the capacitor voltage value and the arm current value of each arm sub-module of the MMDC.

[0063] It should be noted that in this embodiment, the capacitor voltage values of each arm sub-module (the number is N) of the MMDC are obtained through AD sampling and voltage sensors. The arm current value of the MMDC is obtained through AD sampling and current sensors.

[0064] Step 102, calculate the charge quantity Qk absorbed by the sub-module capacitor in one period corresponding to each pulse delay phase shift Sk of the MMDC according to the arm current value.

[0065] It should be noted that according to the arm current value, the charge quantity Qk (k = 1,..., N) absorbed by the sub-module capacitor in one period corresponding to each pulse delay phase shift Sk (k = 1,..., N) of the MMDC is calculated.

[0066] Specifically, substitute the arm current value into the absorbed charge formula to calculate the charge Qk absorbed by the sub-module capacitor in one period corresponding to each pulse delay phase shift Sk of the MMDC.

[0067] Among them, the absorbed charge formula is:

[0068]

[0069] In the formula, Q k is the charge absorbed by the k-th sub-module, t end is the end time of the time period t, t start is the start time of the time period t, d k is the pulse phase shift of the k-th sub-module, T h is the duration of half a switching period, i al (t) is the arm current in the time period t.

[0070] Step 103: Store the pulse delay phase shift Sk corresponding to the charge Qk into the set Pos or the pulse phase shift set Neg according to the positive or negative situation of the charge Qk.

[0071] In one embodiment, step 103 includes:

[0072] Judge the positive or negative of the charge Qk. If the charge Qk is greater than 0, store the pulse delay phase shift Sk corresponding to the charge Qk into the set Pos; otherwise, store the pulse delay phase shift Sk corresponding to the charge Qk into the pulse phase shift set Neg.

[0073] Step 104: Sort the capacitor voltage values to form a sub-module voltage set.

[0074] It should be noted that in this embodiment, the capacitor voltages of the MMDC arm sub-modules obtained by sampling are arranged in descending order to form a sub-module voltage set.

[0075] Step 105: After allocating the pulse delay phase shift Sk in one of the sets Pos and the pulse phase shift set Neg to the sub-modules corresponding to the sub-module voltage set, then allocate the pulse delay phase shift Sk in the other set to the sub-modules corresponding to the sub-module voltage set, so as to balance the capacitor voltages of each sub-module.

[0076] In one embodiment, step 105 includes:

[0077] Allocate the pulse delay phase shift Sk in the set Pos to the sub-modules corresponding to the sub-module voltage set. After the pulse delay phase shift Sk in the set Pos is allocated, then allocate the pulse delay phase shift Sk in the pulse phase shift set Neg to the sub-modules corresponding to the sub-module voltage set.

[0078] A voltage equalization control method for a modular DC transformer provided by an embodiment of the present invention realizes the capacitance voltage balance of sub-modules by calculating and constructing a pulse phase shift sequence set in each cycle and distributing it to the obtained sub-module capacitance voltage set; by reconstructing and distributing the pulse phase shift set, the capacitance energy of the MMDC sub-module in the modular DC transformer is balanced and it operates normally in the full range; thus solving the problem that the existing sorting algorithm cannot balance the capacitance voltage of the sub-modules of the MMDC. Since only the positive and negative of the absorbed energy need to be judged, under the method of the present invention, only one sorting of the sub-module capacitance voltage is required in each cycle, greatly reducing the memory consumption of the computer.

[0079] The following are simulation examples:

[0080] Figure 7 This is the simulation of Case 1 of the voltage equalization control method for the modular DC transformer of the embodiment of the present application.

[0081] In the embodiment of the present application, the voltage equalization control method of the modular DC transformer is simulated through Case 1, Case 2, Case 3 and Case 4. According to Figure 2 the shown modular DC transformer, use MATLAB / Simulink software to build the modular DC transformer structure as shown in Figure 2 and conduct simulation verification for this topology. The simulation parameters are shown in Table 1 below. As shown in Figure 7 based on the following three working states, the proposed voltage equalization control strategy of the modular DC transformer is verified in the voltage mismatch scenario. The specific working state descriptions are as follows:

[0082] State 1: During 0 - 0.5 s, the primary side voltage V dc1 of the MMDC is 20 kV, and the transmission power is 0.4 p.u. The secondary side voltage V dc2 is 750 V. At this time, the primary side and secondary side voltages are matched.

[0083] State 2: During 0.5 - 1.5 s, the primary side voltage V dc1 changes from 20 kV to 18 kV, resulting in a voltage mismatch between the primary side and secondary side of the MMDC.

[0084] State 3: During 1.5 - 3.5 s, activate the proposed sub-module energy balance control strategy.

[0085] As shown in Figure 7 in State 2, the sub-module capacitance voltages become unbalanced, indicating that the conventional sorting algorithm is not applicable at a voltage conversion ratio of 0.9. By adopting the proposed scheme, the sub-module capacitance voltage balance can be restored in State 3.

[0086]

[0087] The above is a voltage equalization control method for a modular DC transformer provided in an embodiment of the present invention. The following is a voltage equalization control system for a modular DC transformer provided in an embodiment of the present invention.

[0088] Please refer to Figure 8 , a voltage equalization control system for a modular DC transformer provided in an embodiment of the present invention, includes:

[0089] An acquisition module 201, configured to acquire the capacitance voltage value and the arm current value of each arm sub-module of the MMDC;

[0090] A calculation module 202, configured to calculate the charge Qk absorbed by the capacitance of each sub-module corresponding to each pulse delay phase shift Sk of the MMDC within one period according to the arm current value.

[0091] A partitioning module 203, configured to store the pulse delay phase shift Sk corresponding to the charge Qk into the set Pos or the pulse phase shift set Neg according to the positive or negative situation of the charge Qk.

[0092] A sorting module 204, configured to sort the capacitance voltage values to form a sub-module voltage set.

[0093] A control module 205, configured to, after allocating the pulse delay phase shift Sk in one of the set Pos and the pulse phase shift set Neg to the sub-module corresponding to the sub-module voltage set, then allocate the pulse delay phase shift Sk in the other set to the sub-module corresponding to the sub-module voltage set, so as to balance the capacitance voltages of each sub-module.

[0094] Further, an embodiment of the present invention also provides a voltage equalization control device for a modular DC transformer. The device includes a processor and a memory:

[0095] The memory is used to store program code and transmit the program code to the processor;

[0096] The processor is configured to execute the steps of the voltage equalization control method for a modular DC transformer as described in the above method embodiment according to the instructions in the program code.

[0097] Further, an embodiment of the present invention also provides a computer-readable storage medium. The computer-readable storage medium is used to store program code, and the program code is used to execute the voltage equalization control method for a modular DC transformer as described in the above method embodiment.

[0098] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0099] In several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections between each other can be through some interfaces, and the indirect couplings or communication connections of devices or units can be in electrical, mechanical, or other forms.

[0100] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0101] In addition, in each embodiment of the present invention, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0102] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in each embodiment of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0103] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A voltage balancing control method for a modular DC transformer, characterized in that: include: Obtain the capacitor voltage value and bridge arm current value of each bridge arm submodule of the MMDC; The charge amount Qk absorbed by the submodule capacitor corresponding to each pulse delay phase shift Sk of the MMDC in one cycle is calculated according to the bridge arm current value; According to the positive or negative condition of the charge quantity Qk, the pulse delay phase Sk corresponding to the charge quantity Qk is stored in the set Pos or the pulse phase shift set Neg; Sorting the capacitor voltage values ​​to form a submodule voltage set; After allocating the pulse delay phase shift Sk in one of the sets Pos and the pulse phase shift set Neg to the submodules corresponding to the submodule voltage set, the pulse delay phase shift Sk in the other set is allocated to the submodules corresponding to the submodule voltage set, so that the capacitor voltages of the submodules are balanced.

2. The voltage balancing control method of a modular DC transformer according to claim 1, characterized in that: The step of storing the pulse delay phase Sk corresponding to the charge quantity Qk into the set Pos or the pulse phase shift set Neg according to the positive or negative condition of the charge quantity Qk comprises: The positive or negative value of the charge amount Qk is determined. If the charge amount Qk is greater than 0, the pulse delay phase shift Sk corresponding to the charge amount Qk is stored in the set Pos; otherwise, the pulse delay phase shift Sk corresponding to the charge amount Qk is stored in the pulse phase shift set Neg.

3. The voltage balancing control method of a modular DC transformer according to claim 1, characterized in that: After allocating the pulse delay phase Sk in one of the set Pos and the pulse phase shift set Neg to the submodule corresponding to the submodule voltage set, the pulse delay phase Sk in the other set is allocated to the submodule corresponding to the submodule voltage set, so that the capacitor voltage of each submodule is balanced, including: The pulse delay phase shift Sk in the set Pos is allocated to the submodule corresponding to the submodule voltage set. After the pulse delay phase shift Sk in the set Pos is allocated, the pulse delay phase shift Sk in the pulse phase shift set Neg is allocated to the submodule corresponding to the submodule voltage set.

4. The voltage balancing control method of a modular DC transformer according to claim 1, characterized in that: The step of sorting the capacitor voltage values ​​to form a submodule voltage set includes: The capacitor voltage values ​​are arranged in descending order to form a submodule voltage set.

5. A voltage balancing control system for a modular DC transformer, characterized in that: include: An acquisition module is used to obtain the capacitor voltage value and bridge arm current value of each bridge arm submodule of the MMDC; A calculation module, used for calculating the charge amount Qk absorbed by the submodule capacitor corresponding to each pulse delay phase shift Sk of the MMDC within one cycle according to the bridge arm current value; A division module, used for storing the pulse delay phase Sk corresponding to the charge quantity Qk into a set Pos or a pulse phase shift set Neg according to the positive or negative condition of the charge quantity Qk; A sorting module, used for sorting the capacitor voltage values ​​to form a submodule voltage set; A control module is used to allocate the pulse delay phase shift Sk in one of the sets Pos and the pulse phase shift set Neg to the submodules corresponding to the submodule voltage set, and then allocate the pulse delay phase shift Sk in the other set to the submodules corresponding to the submodule voltage set, so that the capacitor voltages of the submodules are balanced.

6. The voltage balancing control method of a modular DC transformer according to claim 5, characterized in that: The division module is specifically used for: The positive or negative value of the charge amount Qk is determined. If the charge amount Qk is greater than 0, the pulse delay phase shift Sk corresponding to the charge amount Qk is stored in the set Pos; otherwise, the pulse delay phase shift Sk corresponding to the charge amount Qk is stored in the pulse phase shift set Neg.

7. The voltage balancing control method of a modular DC transformer according to claim 5, characterized in that: The control module is specifically used for: The pulse delay phase shift Sk in the set Pos is allocated to the submodule corresponding to the submodule voltage set. After the pulse delay phase shift Sk in the set Pos is allocated, the pulse delay phase shift Sk in the pulse phase shift set Neg is allocated to the submodule corresponding to the submodule voltage set.

8. The voltage balancing control method of a modular DC transformer according to claim 5, characterized in that: The sorting module is specifically used for: The capacitor voltage values ​​are arranged in descending order to form a submodule voltage set.

9. A voltage balancing control device for a modular DC transformer, characterized in that: The device comprises a processor and a memory: The memory is used to store program codes and transmit the program codes to the processor; The processor is used to execute the voltage balancing control method of the modular DC transformer according to any one of claims 1 to 4 according to the instructions in the program code.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store program codes, and the program codes are used to execute the voltage balancing control method of the modular DC transformer according to any one of claims 1 to 4.

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