Signal processing device and operation method thereof

Abstract

The invention relates to a signal processing device and an operation method thereof. A signal processing device comprises a circuit system, and the circuit system comprises an amplifier, a temperature compensation circuit and an operational circuit. The amplifier is used for amplifying an input signal according to the temperature compensation current to generate an output signal. The DC offset of the output signal is associated with the temperature compensation current. The temperature compensation circuit comprises a detection resistor and a comparator. The detection resistor is used for generating detection voltage according to the temperature compensation current. The comparator is used for comparing a reference voltage with a detection voltage to generate a comparison signal. The operational circuit is used for adjusting the temperature compensation current according to the comparison signal, so that the detection voltage is close to the reference voltage.

Description

Technical Field

[0001] This disclosure relates to signal processing technologies, and particularly to a signal processing device and its operation method that can save operation time. Background Art

[0002] Amplifiers are widely used in the receiving (Rx) path or transmitting (Tx) path of signals. The leakage current at the input end of an amplifier can affect the DC offset of the output signal of the amplifier, causing signal distortion. Therefore, commercially available chips usually perform DC offset correction on the gain of each stage of the amplifier and store voltage parameters or current parameters suitable for subsequent operation according to the correction results. However, since the electronic characteristics of the amplifier change with the real-time change of the operating temperature, the previously stored parameters cannot effectively compensate for the DC offset variation of the amplifier. Summary of the Invention

[0003] This disclosure provides a signal processing device, which includes a circuit system, and the circuit system includes an amplifier, a temperature compensation circuit, and an arithmetic circuit. The amplifier is used to amplify an input signal according to a temperature compensation current to generate an output signal. The DC offset of the output signal is related to the temperature compensation current. The temperature compensation circuit includes a detection resistor and a comparator. The detection resistor is used to generate a detection voltage according to the temperature compensation current. The comparator is used to compare a reference voltage with the detection voltage to generate a comparison signal. The arithmetic circuit is used to adjust the temperature compensation current according to the comparison signal so that the detection voltage is close to the reference voltage.

[0004] This disclosure provides an operation method, which is applicable to a signal processing device. The signal processing device includes a circuit system, and the circuit system includes an amplifier, a temperature compensation circuit, and an arithmetic circuit. The operation method includes: using the amplifier to amplify the input signal of the amplifier according to a temperature compensation current, where the DC offset of the output signal of the amplifier is related to the temperature compensation current; using the detection resistor of the temperature compensation circuit to generate a detection voltage according to the temperature compensation current; using the comparator of the temperature compensation circuit to compare a reference voltage with the detection voltage to generate a comparison signal; and using the arithmetic circuit to adjust the temperature compensation current according to the comparison signal so that the detection voltage is close to the reference voltage.

[0005] The advantages of the above signal processing device and operation method are saving operation time and high temperature adaptability. Brief Description of the Drawings

[0006] Figure 1 It is a simplified functional block diagram of a circuit system according to an embodiment of this disclosure.

[0007] Figure 2 It is a simplified functional block diagram of a circuit system according to an embodiment of this disclosure.

[0008] Figure 3 A simplified functional block diagram of a signal processing device according to an embodiment of the present disclosure document.

[0009] Figure 4 A flowchart of an operation method according to an embodiment of the present disclosure document. Detailed implementation manners

[0010] Embodiments of the present disclosure document will be described below in conjunction with relevant drawings. In the drawings, the same reference numerals denote the same or similar elements or method flows.

[0011] FIG. 1 is a simplified functional block diagram of a circuit system 100 according to an embodiment of the present disclosure document. The circuit system 100 includes an amplifier 110, a temperature compensation circuit 120, and an arithmetic circuit 130. The amplifier 110 is configured to amplify an input signal VI according to a temperature compensation current I_sen to generate an output signal VO. The DC offset of the output signal VO is related to the temperature compensation current I_sen. In some embodiments, the input signal VI is a differential signal and includes an inverting input signal Vin and a non-inverting input signal Vip, and the output signal VO is a differential signal and includes an inverting output signal Von and a non-inverting output signal Vop, but the present disclosure document is not limited thereto. The aforementioned DC offset of the output signal VO refers to the difference obtained by subtracting the inverting output signal Von from the non-inverting output signal Vop.

[0012] The temperature compensation circuit 120 includes a detection resistor Rsen, a comparator Cmp, and a first current source CS1, where the first current source CS1 is configured to generate a temperature compensation current I_sen. The detection resistor Rsen is serially coupled to the first current source CS1, and there is a first node N1 between the detection resistor Rsen and the first current source CS1. The detection resistor Rsen is configured to generate a detection voltage Vsen at the first node N1 according to the temperature compensation current I_sen. For example, when the temperature compensation current I_sen flows through the detection resistor Rsen, the detection voltage Vsen can be generated at the first node N1. The first input terminal (e.g., the inverting input terminal) of the comparator Cmp is coupled to the first node N1 to receive the detection voltage Vsen. The second input terminal (e.g., the non-inverting input terminal) of the comparator Cmp is configured to receive a reference voltage Vref, where the reference voltage Vref is a bandgap reference voltage that does not change with temperature in some embodiments. The comparator Cmp is configured to compare the reference voltage Vref with the detection voltage Vsen to generate a comparison signal DCK_sen.

[0013] The arithmetic circuit 130 is used to adjust the temperature compensation current I_sen according to the comparison signal DCK_sen, so that the detection voltage Vsen is close to the reference voltage Vref. Specifically, when the arithmetic circuit 130 determines that the detection voltage Vsen is not equal to the reference voltage Vref according to the comparison signal DCK_sen, the arithmetic circuit 130 can sequentially increase or sequentially decrease the temperature compensation current I_sen until the detection voltage Vsen is approximately equal to the reference voltage Vref.

[0014] The circuit system 100 further includes a second current source CS2 and a third current source CS3, where the second current source CS2 and the third current source CS3 are respectively used to generate a first gain compensation current I_dck- and a second gain compensation current I_dck+. The first input terminal (e.g., the inverting input terminal) and the second input terminal (e.g., the non-inverting input terminal) of the amplifier 110 are respectively used to receive an inverting input signal Vin and a non-inverting input signal Vip, and are respectively used to receive the first gain compensation current I_dck- and the second gain compensation current I_dck+. The DC offset of the output signal VO of the amplifier 110 is related to the first gain compensation current I_dck- and the second gain compensation current I_dck+. The amplifier 110 is also used to adjust the gain of the amplifier 110 according to the gain control signal Sgc. The gain control signal Sgc is also transmitted to the arithmetic circuit 130, so that the arithmetic circuit 130 correspondingly adjusts the first gain compensation current I_dck- and the second gain compensation current I_dck+ according to the gain control signal Sgc.

[0015] For example, the amplifier 110 can be implemented with a transimpedance amplifier (TIA) and is disposed in the receive chain of the data receiving end (i.e., the Rx end). For one or more stages of gain (e.g., each stage of gain) in the amplifier 110, the arithmetic circuit 130 can determine and record the appropriate magnitudes of the first gain compensation current I_dck- and the second gain compensation current I_dck+ according to the signal strength (e.g., the received signal strength indicator, RSSI for short) to achieve the DC offset correction of the output signal VO. After the correction is completed, whenever the amplifier 110 changes the gain according to the gain control signal Sgc, the arithmetic circuit 130 can correspondingly adjust the first gain compensation current I_dck- and the second gain compensation current I_dck+ to appropriate magnitudes according to the gain control signal Sgc.

[0016] In some embodiments, the temperature of the circuit system 100 may affect the device characteristics of the second current source CS2 and the third current source CS3, thereby reducing the effect of DC offset correction. As described above, by operating in cooperation with the temperature compensation circuit 120, the arithmetic circuit 130 can continuously detect the influence of temperature on the first current source CS1 to adjust the magnitude of the temperature compensation current I_sen in real time. In some embodiments, the amplifier 110 includes a differential output pair (not shown) for generating the output signal VO, and the temperature compensation current I_sen is used as a part of the bias current of the differential output pair. Therefore, by adjusting the temperature compensation current I_sen in real time, the DC offset of the output signal VO changed due to temperature variation can be compensated in real time.

[0017] In other words, the first gain compensation current I_dck- and the second gain compensation current I_dck+ can be used to perform coarse compensation on the DC offset of the output signal VO, and the temperature compensation current I_sen can be used to perform fine compensation on the DC offset of the output signal VO.

[0018] FIG. 2 is a simplified functional block diagram of a circuit system 200 according to an embodiment of the present disclosure. The circuit system 200 includes an amplifier 210, a temperature compensation circuit 220, and an arithmetic circuit 230. The circuit system 200 is similar to the circuit system 100 in FIG. 1, so only the differences between the two will be described below. The difference between the temperature compensation circuit 220 and the temperature compensation circuit 120 in FIG. 1 is that the temperature compensation circuit 220 uses a first switching circuit SW1, a fourth current source CS4, and a fifth current source CS5 to replace the first current source CS1, where the fourth current source CS4 is used to generate a first candidate current I_ca1, the fifth current source CS5 is used to generate a second candidate current I_ca2, and the first candidate current I_ca1 is different from the second candidate current I_ca2. In some embodiments, the first candidate current I_ca1 and the second candidate current I_ca2 have different temperature coefficients.

[0019] The first switching circuit SW1 is coupled to the fourth current source CS4, the fifth current source CS5, and the sense resistor Rsen, and is configured to transfer one of the first candidate current I_ca1 and the second candidate current I_ca2 as the temperature compensation current I_sen to the sense resistor Rsen, so that the sense resistor Rsen generates a sense voltage Vsen at the first node N1. The amplifier 210 uses the one of the first candidate current I_ca1 and the second candidate current I_ca2 (i.e., the temperature compensation current I_sen) to adjust the DC offset of the output signal VO. In other words, the sense resistor Rsen and the amplifier 210 receive the same first candidate current I_ca1 or receive the same second candidate current I_ca2.

[0020] The operation circuit 230 switches the first switching circuit SW1 to output the first candidate current I_ca1 or the second candidate current I_ca2 according to the operating state of the circuit system 200. The operating state may be, for example, using the operation circuit 230 in a receive chain or using the operation circuit 230 in a transmit chain as described hereinafter in conjunction with FIG. 3, but the present disclosure is not limited thereto. The operation circuit 230 adjusts the magnitude of the first candidate current I_ca1 or the second candidate current I_ca2 to make the detection voltage Vsen close to the reference voltage Vref. The adjustment method is similar to the method of adjusting the magnitude of the temperature compensation current I_sen described above in conjunction with FIG. 1, and will not be repeated here. In summary, the circuit system 200 can adjust the compensation direction and / or degree of the DC offset according to its current operating state to adapt to different temperature change scenarios for different purposes.

[0021] In some embodiments, the amplifier 210 includes a differential output pair (not shown) for generating the output signal VO, and the first candidate current I_ca1 or the second candidate current I_ca2 received by the amplifier 210 (i.e., the temperature compensation current I_sen) is used as a part of the bias current of the differential output pair.

[0022] FIG. 3 is a simplified functional block diagram of a signal processing device 300 according to an embodiment of the present disclosure. The signal processing device 300 includes a second switching circuit SW2, a third switching circuit SW3, a circuit system 310, a mixer 320, a receive-end baseband circuit 330, a digital-to-analog conversion circuit (DAC) 340, and a transmit-end baseband circuit 350. The circuit system 310 includes an amplifier 312, a temperature compensation circuit 314, an operation circuit 316, and a first switching circuit SW1. The circuit system 310 can be implemented by the circuit system 200 in FIG. 2. That is, the amplifier 312, the temperature compensation circuit 314, the operation circuit 316, and the first switching circuit SW1 are respectively similar to the amplifier 210, the temperature compensation circuit 220, the operation circuit 230, and the first switching circuit SW1 in FIG. 2. For the sake of simplicity, it will not be repeated here.

[0023] In some embodiments, the signal processing device 300 operates in a time-domain duplexing (TDD) mode. Therefore, the receive chain and the transmit chain of the signal processing device 300 can share the amplifier 312 to save circuit area. The receive chain refers to the path from the mixer 320 to the receive-end baseband circuit 330, and the transmit chain refers to the path from the DAC 340 to the transmit-end baseband circuit 350.

[0024] FIG. 4 is a flowchart of an operation method 400 according to an embodiment of the present disclosure. The operation method 400 is applicable to the signal processing apparatus 300. Any combination of the features of the operation method 400 can be implemented by a plurality of instructions stored in a non-transitory computer-readable medium. When these instructions are executed by one or more processors, these instructions cause some or all of the steps of the operation method 400 to be executed. It should be understood that the operation method 400 may include more or fewer steps than those shown in the flowchart, and the steps in the operation method 400 can be executed in any suitable order.

[0025] In step S410, in response to the amplifier 312 being used to receive a string, the first switch circuit SW1 transfers the first candidate current I_ca1 as the temperature compensation current I_sen to the detection resistor Rsen to cause the detection resistor Rsen to generate a detection voltage Vsen, and the amplifier 312 uses the temperature compensation current I_sen to adjust the DC offset of the output signal VO. In this case, the first mixer 320 receives the first radio frequency signal Srf1 and converts the first radio frequency signal Srf1 into a first baseband signal Sbb1.

[0026] The first mixer 320 is further used to transmit the first baseband signal Sbb1 to the second switch circuit SW2. Then, the second switch circuit SW2 outputs the first baseband signal Sbb1 as the input signal VI to the amplifier 312. The amplifier 312 amplifies the input signal VI to generate an output signal VO, and the amplifier 312 uses the temperature compensation current I_sen to adjust the DC offset of the output signal VO. Then, the third switch circuit SW3 receives the output signal VO from the amplifier 312 and transfers the output signal VO to the receiving end baseband circuit 330 to enable the receiving end baseband circuit 330 to perform a filtering process on the output signal VO. In some embodiments, the receiving end baseband circuit 330 includes a filter.

[0027] In step S420, in response to the amplifier 312 being used for transmitting a burst, the first switch circuit SW1 transfers the second candidate current I_ca2 as the temperature compensation current I_sen to the sense resistor Rsen to cause the sense resistor Rsen to generate a sense voltage Vsen, and the amplifier 312 uses the temperature compensation current I_sen to adjust the DC offset of the output signal VO of the amplifier 312. The DAC 340 transmits the second fundamental frequency signal Sbb2 to the second switch circuit SW2. Then, the second switch circuit SW2 outputs the second fundamental frequency signal Sbb2 as the input signal VI to the amplifier 312. The amplifier 312 amplifies the input signal VI to generate an output signal VO, and the amplifier 312 uses the temperature compensation current I_sen to adjust the DC offset of the output signal VO. Then, the third switch circuit SW3 receives the output signal VO from the amplifier 312 and transfers the output signal VO to the transmit-end fundamental frequency circuit 350 to cause the transmit-end fundamental frequency circuit 350 to perform filtering processing on the output signal VO. In some embodiments, the transmit-end fundamental frequency circuit 350 includes a filter.

[0028] In step S430, the amplifier 312 amplifies the input signal VI to generate an output signal VO according to the received first candidate current I_ca1 or second candidate current I_ca2 (i.e., the temperature compensation current I_sen), wherein the DC offset of the output signal VO of the amplifier 312 is related to the first candidate current I_ca1 or second candidate current I_ca2 (i.e., the temperature compensation current I_sen) received by the amplifier 312. The DC offset of the output signal VO is also related to the first gain compensation current I_dck- and the second gain compensation current I_dck+. Similar to the content described in connection with FIGS. 1-2, the first input terminal and the second input terminal of the amplifier 312 receive the input signal VI, the first gain compensation current I_dck-, and the second gain compensation current I_dck+. The amplifier 312 adjusts the gain of the amplifier 312 according to the gain control signal Sgc. The arithmetic circuit 316 adjusts the first gain compensation current I_dck- and the second gain compensation current I_dck+ according to the gain control signal Sgc to adaptively compensate for the change in the DC offset of the output signal VO for the current gain of the amplifier 312.

[0029] In step S440, similar to the content described in connection with FIGS. 1-2, the sense resistor Rsen of the temperature compensation circuit 314 generates a sense voltage Vsen according to the received first candidate current I_ca1 or second candidate current I_ca2 (i.e., the temperature compensation current I_sen).

[0030] In step S450, similar to the content described in connection with FIGS. 1-2, the comparator Cmp of the temperature compensation circuit 314 compares the reference voltage Vref with the sense voltage Vsen to generate a comparison signal DCK_sen.

[0031] In step S460, similar to the content described in conjunction with FIGS. 1-2, the arithmetic circuit 316 adjusts the first candidate current I_ca1 or the second candidate current I_ca2 (i.e., the temperature compensation current I_sen) received by the detection resistor Rsen according to the comparison signal DCK_sen, so that the detection voltage Vsen approaches the reference voltage Vref.

[0032] In some embodiments, the transmit string in the signal processing device 300 can be omitted, that is, the DAC 340, the second switch circuit SW2, the third switch circuit SW3, and the transmit-end baseband circuit 350 can be omitted. In this case, the mixer 320 and the receive-end baseband circuit 330 are coupled to the amplifier 312, and step S420 can be omitted from the operation method 400.

[0033] In some embodiments, the receive string in the signal processing device 300 can be omitted, that is, the mixer 320, the receive-end baseband circuit 330, the second switch circuit SW2, and the third switch circuit SW3 can be omitted. In this case, the DAC 340 and the transmit-end baseband circuit 350 are coupled to the amplifier 312, and step S410 can be omitted from the operation method 400.

[0034] In some embodiments, steps S430-S460 can be executed simultaneously with step S410, or simultaneously with step S420.

[0035] In summary, when the operating temperature changes, the circuit systems 100-200, the signal processing device 300, and the operation method 400 can adjust the DC offset in real time by means of the temperature compensation current I_sen, without having to re-calibrate the first gain compensation current I_dck- and the second gain compensation current I_dck+ for each gain level when the temperature changes. Therefore, the circuit systems 100-200, the signal processing device 300, and the operation method 400 have the advantages of saving operation time and high temperature adaptability.

[0036] Regarding the use of "about", "approximately", or "substantially about" in this article, generally, the error or range of the numerical value is within twenty percent, preferably within ten percent, and more preferably within five percent. If there is no clear indication in the text, the numerical values mentioned are regarded as approximate values, that is, the error or range indicated by "about", "approximately", or "substantially about".

[0037] In the specification and the claims for the patent application, certain terms are used to refer to specific elements. However, those of ordinary skill in the art should understand that the same element may be referred to by different terms. The specification and the claims for the patent application do not use the difference in names as a way to distinguish elements, but rather use the difference in the functions of the elements as the basis for distinction. The term "comprising" mentioned in the specification and the claims for the patent application is an open-ended term and should be interpreted as "including but not limited to". In addition, "coupled" herein includes any direct and indirect connection means. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission or other signal connection means, or can be indirectly electrically or signal-connected to the second element through other elements or connection means.

[0038] The description method of "and / or" used herein includes any combination of one or more of the items listed. In addition, unless specifically specified in the specification, any singular term also includes the plural meaning.

[0039] The above are only the preferred embodiments of this disclosure document. Without departing from the scope or spirit of this disclosure document, various modifications and equivalent changes can be made to this disclosure document. In summary, all modifications and equivalent changes made to this disclosure document within the scope of the following claims are covered by this disclosure document.

[0040]

Symbol Explanation

[0041] 100, 200: Circuit system

[0042] 110, 210, 312: Amplifier

[0043] 120, 220, 314: Temperature compensation circuit

[0044] 130, 230, 316: Operational circuit

[0045] 300: Signal processing device

[0046] 310: Circuit system

[0047] 320: Mixer

[0048] 330: Receiver baseband circuit

[0049] 340: Digital-to-analog conversion circuit

[0050] 350: Transmitter baseband circuit

[0051] 400: Operating method

[0052] S410~S460: Steps

[0053] SW1: First switching circuit

[0054] SW2: Second switching circuit

[0055] SW3: Third switching circuit

[0056] Srf1: First radio frequency signal

[0057] Sbb1: First baseband signal

[0058] Sbb2: Second baseband signal

[0059] I_sen: Temperature compensation current

[0060] I_ca1: First candidate current

[0061] I_ca2: Second candidate current

[0062] I_dck-: First gain compensation current

[0063] I_dck+: Second gain compensation current

[0064] Cmp: Comparator

[0065] CS1: First current source

[0066] CS2: Second current source

[0067] CS3: Third current source

[0068] CS4: Fourth current source

[0069] CS5: Fifth current source

[0070] DCK_sen: Comparison signal

[0071] Rsen: Detection resistor

[0072] Vref: Reference voltage

[0073] Vsen: Detection voltage

[0074] VI: Input signal

[0075] Vin: Inverting input signal

[0076] Vip: Non-inverting input signal

[0077] VO: Output signal

[0078] Von: Inverting output signal

[0079] Vop: Non-inverting output signal

[0080] N1: First node

[0081] Sgc: Gain control signal.

Claims

1. A signal processing device, comprising a circuit system, wherein, the circuit system includes: an amplifier for amplifying an input signal according to a temperature compensation current to generate an output signal, wherein a DC offset of the output signal is related to the temperature compensation current; a temperature compensation circuit, including: a detection resistor for generating a detection voltage according to the temperature compensation current; and a comparator for comparing a reference voltage with the detection voltage to generate a comparison signal; and an arithmetic circuit for adjusting the temperature compensation current according to the comparison signal so that the detection voltage approaches the reference voltage.

2. The signal processing device according to claim 1, wherein, a first input terminal and a second input terminal of the amplifier are used to receive the input signal, a first gain compensation current and a second gain compensation current, wherein the DC offset of the output signal of the amplifier is related to the first gain compensation current and the second gain compensation current, wherein the amplifier is used to adjust a gain of the amplifier according to a gain control signal, and the arithmetic circuit is used to adjust the first gain compensation current and the second gain compensation current according to the gain control signal.

3. The signal processing device according to claim 1, wherein, the reference voltage is a bandgap reference voltage.

4. The signal processing device according to claim 1, further comprising: a mixer coupled to the amplifier for converting a first radio frequency signal into a first baseband signal and outputting the first baseband signal as the input signal to the amplifier; and a receiving end baseband circuit coupled to the amplifier for filtering the output signal.

5. The signal processing device according to claim 1, further comprising: a digital-to-analog converter coupled to the amplifier for outputting a second baseband signal and outputting the second baseband signal as the input signal to the amplifier; and a transmitting end baseband circuit coupled to the amplifier for filtering the output signal.

6. The signal processing device according to claim 1, wherein, the temperature compensation circuit further includes: a first switch circuit coupled to the detection resistor and used to transfer one of a first candidate current and a second candidate current as the temperature compensation current to the detection resistor so that the detection resistor generates the detection voltage, wherein the amplifier uses one of the first candidate current and the second candidate current to adjust the DC offset of the output signal of the amplifier, wherein the first candidate current is different from the second candidate current.

7. The signal processing device according to claim 6, wherein, the first candidate current and the second candidate current have different temperature coefficients.

8. The signal processing device according to claim 6, further comprising: a mixer; a transmitting end baseband circuit; a receiving end baseband circuit; a digital-to-analog converter; a second switch circuit coupled to the amplifier for transferring the input signal to the amplifier; and a third switch circuit coupled to the amplifier for receiving the output signal, wherein, When the first switching circuit transfers the first candidate current as the temperature compensation current to the detection resistor, the second switching circuit outputs a first fundamental frequency signal generated by the mixer as the input signal, and the third switching circuit transfers the output signal to the receiving end fundamental frequency circuit. Wherein, when the first switching circuit transfers the second candidate current as the temperature compensation current to the detection resistor, the second switching circuit outputs a second fundamental frequency signal generated by the digital-to-analog converter as the input signal, and the third switching circuit transfers the output signal to the transmitting end fundamental frequency circuit.

9. The signal processing device according to claim 1, wherein, the amplifier is a transresistance amplifier.

10. An operation method, applicable to a signal processing device, wherein, the signal processing device includes a circuit system, and the circuit system includes an amplifier, a temperature compensation circuit, and an arithmetic circuit. The operation method includes: amplifying an input signal of the amplifier according to a temperature compensation current by using the amplifier, wherein a DC offset of an output signal of the amplifier is related to the temperature compensation current; generating a detection voltage according to the temperature compensation current by using a detection resistor of the temperature compensation circuit; comparing a reference voltage with the detection voltage by using a comparator of the temperature compensation circuit to generate a comparison signal; and adjusting the temperature compensation current according to the comparison signal by using the arithmetic circuit so that the detection voltage approaches the reference voltage.

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