Output stage circuit with low power consumption and high driving capability and operational amplifier

Abstract

The invention discloses an output stage circuit with low power consumption and high driving capability, comprising an AB type output stage circuit which comprises PNP tubes P1 and P2 and NPN tubes N1 and N2; the input end of the turn-off circuit is connected with the OUT output end of the AB type output stage circuit, and the turn-off circuit is used for turning off P2 or N2 according to the output signal of the AB type output stage circuit; the upper end delay starting current source is used for providing static working current for the P1 and starting the P1 in a delay manner; the lower end delay starting current source is used for providing static working current for the N1 and starting the N1 in a delay manner; and the input end of the heavy load feedback circuit is connected with the OUT output end of the AB type output stage circuit so as to adjust the output current of the OUT output end. The invention also discloses an operational amplifier comprising the output stage circuit, which not only can protect an output stage transistor when the circuit is turned off, but also can avoid the risk of large current of a bias device so as to avoid the damage of turn-off / enable operation to a chip, and can also enable the driving capability to be improved under heavy load and maintain low quiescent current at the same time.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit technology, and particularly relates to an output stage circuit and an operational amplifier with enabling, low power consumption and high driving ability. Background Art

[0002] The output resistance of an integrated operational amplifier is one of its core indicators.

[0003] When driving a small-resistance load, the greater the output resistance of the operational amplifier, the more serious the attenuation of the open-loop gain; when driving a large-capacitance load, the greater the output resistance of the operational amplifier, the worse the stability. Reducing the output resistance of the operational amplifier is the key to avoiding these two problems.

[0004] To reduce the output resistance, an emitter output method is often adopted; at the same time, to control the static current, an AB-class output stage structure is often adopted.

[0005] Such as Figure 1 shown is a typical AB-class output stage structure, where P2 and N2 are output transistors, both connected to the output terminal OUT with their emitters. I1 and I2 are active loads of the gain stage, equivalent to two current sources here; I3 and I4 are current sources that provide bias current to P1 and N1. P1, P2, N1, and N2 together form an AB-class output stage structure, and when designing this structure, it is ensured that K N1N2 = K P1P2 , so I P2C = I N2C = K N2N1 I P1C , to ensure that the static current of the output transistors is controllable. Among them, K N1N2 represents the ratio of the emitter area of transistor N1 to that of transistor N2, K P1P2 represents the ratio of the emitter area of transistor P1 to that of transistor P2, I P2C represents the collector current of transistor P2, I N2C represents the collector current of transistor N2, K N2N1 represents the ratio of the emitter area of transistor N2 to that of transistor N1, I P1C represents the collector current of transistor P1.

[0006] Since transistors P2 and N2 need to drive the load, their emitter areas are usually large and can withstand large currents; transistors P1 and N1 do not need to drive the load, so their emitter areas are usually small and can withstand small currents.

[0007] When the operational amplifier is turned off, the currents I1, I2, I3, and I4 are usually set to zero, and at this time, the base of transistor P1 is floating. When there are no protective diodes D1 and D2, if after turning off, V P1B (the base voltage of transistor P1) relative to VOUT is low, then V N2B ≈V P1B + 0.7V. Wherein, V N2B is the base voltage of transistor N2, and V P1B is the base voltage of transistor P1.

[0008] Assume that the reverse breakdown voltage of the BE junction of the NPN transistor is V MN , and the reverse breakdown voltage of the BE junction of the PNP is V MP , then when V OUT - V N1B > V MN + 0.7V, there is a risk of damage to transistor N2; similarly, when V N1B - V OUT > V MP + 0.7V, there is a risk of damage to transistor P2.

[0009] Adding diodes D1 and D2 can prevent the risk of damage caused by the reverse voltage of the BE junctions of transistors N2 and P2 exceeding the maximum breakdown voltage, but there are still other problems.

[0010] D1 and D2 are only used to limit the reverse voltage of the BE junction, so generally the PN junction area is small and the current-carrying capacity is weak.

[0011] If, when the chip is turned on, I3 and I4 turn on before I1 and I2, then at this time I 3 = I N2B (base current of transistor N2), I 4 = I P2B (base current of transistor P2), resulting in a large current flowing directly from the emitter of transistor N2 to the emitter of transistor P2. Since this current directly flows from VCC through the chip interior to VEE, it brings extremely high power consumption instantly and there is a risk of burning out the chip.

[0012] If control measures are taken such that when the chip is turned on, I1 and I2 turn on before I3 and I4, since there is also an order in the turn-on of I1 and I2, let's assume I1 turns on first, then at this time I 1 = I N1B (base current of transistor N1), then it is possible that a large current flows out from the OUT port through diode D2 from the emitter of N1. Since the current-carrying capacities of transistors N1 and D2 are weak, there is a risk of damage. Similarly, if I2 turns on first, there is a risk of damage to P1 and D1.

[0013] When transistor N2 needs to output a large current, its maximum output current value is I 3 β N (β NThat is, the current gain of the NPN transistor. Since transistors N1 and N2 are integrated on a chip using the same process, their amplification factors are approximately equal, both represented by β N When P2 needs to output a large current, its maximum output current value is I 4 β P (β P That is, the current gain of the PNP transistor. Since transistors P1 and P2 are integrated on a chip using the same process, their amplification factors are approximately equal, both represented by β P It can be seen that the maximum output current is limited by the magnitudes of I3 and I4 currents, and thus is limited by the quiescent current. SUMMARY OF THE INVENTION

[0014] To solve the above problems, the present invention provides an output stage circuit and an operational amplifier with low power consumption and high driving ability, which can protect the output stage transistors when the operational amplifier is turned off, avoid the risk of large currents in the bias devices of the driving devices to prevent damage to the chip caused by turn-off / enable operations, improve the driving ability under heavy loads, and maintain a low quiescent current at the same time.

[0015] The technical solution adopted by the present invention is as follows:

[0016] In a first aspect, the present invention discloses an output stage circuit with low power consumption and high driving ability, including: a class-AB output stage circuit, whose OUT output terminal is used to connect to a load, and the class-AB output stage circuit includes PNP transistors P1, P2 and NPN transistors N1, N2; a turn-off circuit, whose input terminal is connected to the OUT output terminal of the class-AB output stage circuit, and is used to turn off transistor P2 or N2 according to the output signal of the class-AB output stage circuit; an upper-end delay-on current source, used to provide a quiescent operating current for transistor P1 and delay the turn-on of transistor P1; a lower-end delay-on current source, used to provide a quiescent operating current for transistor N1 and delay the turn-on of transistor N1; a heavy-load feedback circuit, whose first output terminal is connected to the upper-end delay-on current source, whose second output terminal is connected to the lower-end delay-on current source, and whose input terminal is connected to the OUT output terminal of the class-AB output stage circuit to adjust the output current I OUT .

[0017] As an optional technical solution, for the class-AB output stage circuit, the emitter of transistor P1 is connected to the base of transistor N2, the base of transistor P1 is connected to the base of transistor N1, the emitter of transistor N1 is connected to the base of transistor P2, and the emitter of transistor P2 is connected to the emitter of transistor N2 and connected to the output terminal OUT.

[0018] As an alternative technical solution, the turn-off circuit includes PNP transistors P3, P4 and NPN transistors N3, N4; wherein, the bases of transistors P3 and N3 are both connected to the OUT output terminal, the emitter of transistor P3 is connected to the base of transistor N4 and the base of transistor P2, the collector of transistor P3 is connected to the collector of transistor N3 and the emitter of transistor N4, the emitter of transistor N4 is further connected to the emitter of transistor P4, the base of transistor P4 is connected to the emitter of transistor N3, and the emitter of transistor N3 is further connected to the base of transistor N2.

[0019] As an alternative technical solution, the turn-off circuit further includes PNP transistors P12, P13 and NPN transistors N15, N16; wherein, the bases of transistors P12 and P13 are connected, the collectors of transistors P12 and N15 are connected, the collector and the base of transistor P12 are short-circuited, the collector of transistor P13 is connected to the emitter of transistor P3, the bases of transistors N15 and N16 are connected, and the collector of transistor N16 is connected to the emitter of transistor N3.

[0020] As an alternative technical solution, the output stage circuit with low power consumption and high driving ability further includes NPN transistors N12, N13 and N14; wherein, the collectors of transistors N12 and N13 are connected, the bases of transistors N13 and N14 are connected, the base of transistor N14 is further connected to the base of transistor N15, the collector and the base of transistor N12 are short-circuited, and the collector and the base of transistor N14 are short-circuited.

[0021] As an alternative technical solution, the upper-end delay turn-on current source includes PNP transistors P5, P6, P7 and resistors R1, R2, R3, R4 and capacitor C1; wherein, the bases of transistors P5, P6, P7 are connected, the emitter of transistor P5 is connected to VCC through resistor R1, the emitter of transistor P6 is connected to VCC through resistor R2, the emitter of transistor P7 is connected to VCC through resistor R3, resistor R4 and capacitor C1 form a low-pass filter and are connected to the base of transistor P7, and the collector of transistor P7 is connected to the emitter of transistor P1.

[0022] As an alternative technical solution, the lower-end delay turn-on current source includes NPN transistors N5, N6, N7 and resistors R5, R6, R7, R8 and capacitor C2; wherein, the emitter of transistor N5 is connected to VEE through resistor R5, the emitter of transistor N6 is connected to VEE through resistor R6, the emitter of transistor N7 is connected to VEE through resistor R7, and resistor R8 and capacitor C2 form a low-pass filter and are connected to the base of transistor N7.

[0023] As an alternative technical solution, the overload feedback circuit includes PNP transistors P8 and P9 and NPN transistors N8 and N9. The emitter of transistor N9 is connected to the emitter of transistor P9. The base of transistor N9 is connected to the emitter of transistor P8. The collectors of transistors P8 and N8 are connected and then connected to the OUT output terminal of the class-AB output stage circuit. The emitter of transistor N8 is connected to the base of transistor P9. The bases of transistors P8 and N8 are connected. The base of transistor P8 is further connected to the upper delay turn-on current source. The base of transistor N8 is further connected to the lower delay turn-on current source.

[0024] As an alternative technical solution, the overload feedback circuit further includes PNP transistors P10 and P11 and NPN transistors N10 and N11. Among them, the bases of transistors P10 and P11 are connected. The collector of transistor P10 is connected to the emitter of transistor P8. The collectors of transistors P11 and N11 are connected. The base and the collector of transistor P11 are short-circuited. The base of transistor N11 is connected to the base of transistor N10. The collector of transistor N10 is connected to the emitter of transistor N8.

[0025] In a second aspect, the present application also discloses an operational amplifier, including the output stage circuit with low power consumption and high driving ability as described in the first aspect above.

[0026] The beneficial effects of the present invention are as follows: In the present application, the output stage structure of the operational amplifier adopts a class-AB output stage structure with emitter output, which has advantages such as strong driving ability and small quiescent current. It adopts a turn-off circuit with output voltage synchronized to the reference potential to fully protect the output stage transistors while turning off. It adopts a delay turn-on current source structure to avoid the risk of large current in the bias device of the driving device. It adopts an overload feedback circuit, which can increase the maximum output current to more than twice without almost increasing the quiescent current. Description of the Drawings

[0027] Figure 1 is a schematic diagram of a typical class-AB output stage structure in the prior art.

[0028] Figure 2 is a circuit block diagram of the output stage circuit with low power consumption and high driving ability in an exemplary embodiment.

[0029] Figure 3 is a circuit schematic diagram of the output stage circuit with low power consumption and high driving ability in an exemplary embodiment.

[0030] Figure 4 is a circuit schematic diagram of the output stage circuit with low power consumption and high driving ability in another exemplary embodiment.

[0031] Figure 5 is a circuit schematic diagram of the output stage circuit with low power consumption and high driving ability in yet another exemplary embodiment. Detailed implementation manners

[0032] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. The components of the embodiments of the present invention described and illustrated herein generally may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but is merely representative of selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0033] To illustrate this embodiment more clearly and concisely, first, the relevant naming rules in this application will be described.

[0034] In this application, Px represents the x-th PNP transistor, Ny represents the y-th NPN transistor, and I Pxz / V Pxz respectively represent the z-port current / voltage of the x-th PNP transistor, and I Nxz / V Nxz respectively represent the z-port current / voltage of the x-th NPN transistor. z can be C (collector), B (base), or E (emitter). For example, I P1E represents the emitter current of the 1st PNP transistor (i.e., transistor P1), and I N2C represents the collector current of the 2nd NPN transistor (i.e., transistor N2).

[0035] K NxNy represents the ratio of the emitter areas of transistor Nx and transistor Ny. For example, K N1N2 represents the ratio of the emitter areas of transistor N1 and transistor N2; K PxPy represents the ratio of the emitter areas of transistor Px and transistor Py. For example, K P1P2 represents the ratio of the emitter areas of transistor P1 and transistor P2; K PxNy represents the ratio of the emitter areas of transistor Px and transistor Ny. For example, K P1N2 represents the ratio of the emitter areas of transistor P1 and transistor N2; K NyPx represents the ratio of the emitter areas of transistor Ny and transistor Px. For example, K N2P1 represents the ratio of the emitter areas of transistor N2 and transistor P1; K RxRy represents the ratio of the resistances of resistor Rx and resistor Ry. For example, K R1R2 = R1 / R2.

[0036] β NThat is, the current gain of the NPN transistor. Since all the NPN transistors in this embodiment are integrated on a single chip using the same process, their amplification factors are approximately equal, all denoted by β N ; β P That is, the current gain of the PNP transistor. Since all the PNP transistors in this embodiment are integrated on a single chip using the same process, their amplification factors are approximately equal, all denoted by β P .

[0037] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0038] Embodiment 1

[0039] As shown in Figure 2 , the present invention discloses an output stage circuit with low power consumption and high driving ability, including: a class-AB output stage circuit 100, whose OUT output terminal is used to connect to a load, and the class-AB output stage circuit 100 includes PNP transistors P1, P2 and NPN transistors N1, N2; a turn-off circuit 200, whose input terminal is connected to the OUT output terminal of the class-AB output stage circuit 100, and is used to turn off transistor P2 or N2 according to the output signal of the class-AB output stage circuit 100; an upper-end delay-on current source 400, which is used to provide a static operating current for transistor P1 and delay the turn-on of transistor P1; a lower-end delay-on current source 500, which is used to provide a static operating current for transistor N1 and delay the turn-on of transistor N1; a heavy-load feedback circuit 300, whose first output terminal is connected to the upper-end delay-on current source 400, whose second output terminal is connected to the lower-end delay-on current source 500, and whose input terminal is connected to the OUT output terminal of the class-AB output stage circuit 100 to adjust the output current I of the OUT output terminal OUT .

[0040] As an optional implementation manner, as shown in Figure 3 , for the class-AB output stage circuit 100, the emitter of transistor P1 is connected to the base of transistor N2, the base of transistor P1 is connected to the base of transistor N1, the emitter of transistor N1 is connected to the base of transistor P2, and the emitter of transistor P2 is connected to the emitter of transistor N2 and connected to the output terminal OUT.

[0041] As an optional implementation manner, as shown in Figure 3 , the turn-off circuit 200 includes PNP transistors P3, P4 and NPN transistors N3, N4; wherein, the bases of transistors P3 and N3 are both connected to the OUT output terminal, the emitter of transistor P3 is connected to the base of transistor N4 and the base of transistor P2, the collector of transistor P3 is connected to the collector of transistor N3 and the emitter of transistor N4, the emitter of transistor N4 is also connected to the emitter of transistor P4, the base of transistor P4 is connected to the emitter of transistor N3, and the emitter of transistor N3 is also connected to the base of transistor N2.

[0042] As an alternative embodiment, as Figure 3 shown, the upper-end delayed turn-on current source 400 includes PNP transistors P5, P6, P7 and resistors R1, R2, R3, R4 and capacitor C1; wherein, the bases of transistors P5, P6, P7 are connected together, the emitter of transistor P5 is connected to VCC through resistor R1, the emitter of transistor P6 is connected to VCC through resistor R2, the emitter of transistor P7 is connected to VCC through resistor R3, resistor R4 and capacitor C1 form a low-pass filter and are connected to the base of transistor P7, and the collector of transistor P7 is connected to the emitter of transistor P1.

[0043] As an alternative embodiment, as Figure 3 shown, the lower-end delayed turn-on current source 500 includes NPN transistors N5, N6, N7 and resistors R5, R6, R7, R8 and capacitor C2; wherein, the emitter of transistor N5 is connected to VEE through resistor R5, the emitter of transistor N6 is connected to VEE through resistor R6, the emitter of transistor N7 is connected to VEE through resistor R7, resistor R8 and capacitor C2 form a low-pass filter and are connected to the base of transistor N7.

[0044] As an alternative embodiment, as Figure 3 shown, the overload feedback circuit 300 includes PNP transistors P8, P9 and NPN transistors N8, N9. The emitter of transistor N9 is connected to the emitter of transistor P9, the base of transistor N9 is connected to the emitter of transistor P8, the collectors of transistors P8 and N8 are connected together and then connected to the OUT output terminal of the class AB output stage circuit. The emitter of transistor N8 is connected to the base of transistor P9, the bases of transistors P8 and N8 are connected together, the base of transistor P8 is further connected to the upper-end delayed turn-on current source 400, and the base of transistor N8 is further connected to the lower-end delayed turn-on current source 500.

[0045] In this embodiment, for matching considerations, design K PdP6 = K R1R2 , K P6P7 = K R2R3 , K N5N6 = K R5R6 , K N6N7 = K R6R7 .

[0046] Through the control of the enable circuit, when the circuit is operating normally, I 1 = I 2 = 0, I 3 = I 4 .

[0047] When the circuit is operating normally, if the output current of the operational amplifier is 0, then I N9C = I P9C , V P1B = V OUT。

[0048] When the circuit is operating normally, if the output current of the operational amplifier is I OUT >0, at this time V P1B >V OUT , then N8 enters the saturation region, and I N8C and I P8C decrease simultaneously, which in turn causes the base currents of N9 and P9 to increase, and I N9C and I P9C increase simultaneously. Similarly, if the output current of the operational amplifier is I OUT <0, I N9C and I P9C will also increase simultaneously.

[0049] Due to the addition of the heavy-load feedback circuit 300, if β P <β N , the maximum value of the output pull-up current increases by I 4 β P β N K R3R1 ; if β P >β N , the maximum value of the output pull-up current increases

[0050] Due to the addition of the heavy-load feedback circuit 300, if β P <β N , the maximum value of the output pull-down current increases If β P >β N , the maximum value of the output pull-down current increases by I 3 β P β N K R7R5 。

[0051] Due to the addition of the heavy-load feedback circuit 300, the maximum output current value has been greatly improved. Taking the output pull-up current in the case of β P <β N as an example, without the heavy-load feedback circuit 300, the maximum value of the output pull-up current is I P7C β N . If we want to double the maximum value of the output pull-up current, we only need to make If β P =100, K R3R1 =1, then we only need In the typical case, the static current consumed by I P7C is within one-tenth of the total static current. Therefore, the static current increased by the heavy-load feedback circuit 300 is negligible.

[0052] Through enabling circuit control, when the circuit is turned off, I 3 = I 4 = 0, I 1 = I 2 .

[0053] When the circuit is turned off, I1 pulls up the base voltage of P2 to V P2B ≈ V OUT + 0.7V; I2 pulls down the base voltage of N2 to V N2B ≈ V OUT - 0.7V; V P1B ≈ V OUT . The turn-off circuit 200 fully turns off P2 and N2, and avoids the risk of breakdown of their BE junctions.

[0054] When the chip starts up, due to the delay effects of the low-pass filters formed by R4 and C1, and R8 and C2, P7 and N7 output collector current later than P5, P6, N5, and N6. Therefore, no large current will flow through P1 and N1 during the startup process, avoiding the risk of damage.

[0055] Embodiment 2

[0056] As Figure 4 shown, the circuit structure of this embodiment is substantially the same as that of Embodiment 1, except that:

[0057] The input circuit uses NPN differential pair transistors N17 and N18.

[0058] The turn-off circuit 200 further includes PNP transistors P12 and P13 and NPN transistors N15 and N16; wherein, the base of transistor P12 is connected to the base of transistor P13, the collector of transistor P12 is connected to the collector of transistor N15, the collector and the base of transistor P12 are short-circuited, the collector of transistor P13 is connected to the emitter of transistor P3, the base of transistor N15 is connected to the base of transistor N16, and the collector of transistor N16 is connected to the emitter of transistor N3.

[0059] The low-power high-drive-capability output stage circuit further includes NPN transistors N12, N13, and N14; wherein, the collector of transistor N12 is connected to the collector of transistor N13, the base of transistor N13 is connected to the base of transistor N14, the base of transistor N14 is also connected to the base of transistor N15, the collector and the base of transistor N12 are short-circuited, and the collector and the base of transistor N14 are short-circuited.

[0060] The overload feedback circuit 300 further includes PNP transistors P10, P11 and NPN transistors N10, N11; wherein, the base of transistor P10 is connected to the base of transistor P11, the collector of transistor P10 is connected to the emitter of transistor P8, the collector of transistor P11 is connected to the collector of transistor N11, the base and the collector of transistor P11 are short-circuited, the base of transistor N11 is connected to the base of transistor N10, and the collector of transistor N10 is connected to the emitter of transistor N8.

[0061] Wherein, I1 and I3 are fixed current sources, I2 is a controlled current source. When the circuit is working normally, I 2 = 0; when the circuit is turned off, I2 outputs a non-zero current.

[0062] When the circuit is working normally, since I 2 = 0, then I N15C = I N16C = I P12C = I P13C = 0. Therefore, I N3C = I N4C = I P3C = I P4C = 0, and the turn-off circuit 200 does not work.

[0063] When the circuit is working normally, since I 2 = 0, then I N12C = I 1 , for matching considerations, design K N10N12 = K N11N12 K P10P11 . Therefore, I N10C = I P10C = K N10N12 I 1 , and the overload feedback circuit 300 can improve the output current capacity when driving a heavy load.

[0064] Design K N13N14 I 2 > I 1 , then when the circuit is turned off, I N12C = 0, and the overload feedback circuit 300 does not work.

[0065] When the circuit is turned off, I1 pulls up the base voltage of P2 to V P2B ≈ V OUT + 0.7V; I2 pulls down the base voltage of N2 to V N2B ≈ V OUT - 0.7V; V P1B ≈ V OUT . The turn-off circuit 200 fully turns off P2 and N2, and avoids the risk of breakdown of their BE junctions.

[0066] When the chip starts up, due to the delay effect of the low-pass filters composed of R4 and C1, and R8 and C2, the collector currents of P7 and N7 are output later than those of P5, P6, N5, and N6. Therefore, no large current will flow through P1 and N1 during the startup process, avoiding the risk of damage.

[0067] Embodiment 3

[0068] As Figure 5 shown, the circuit structure of this embodiment is roughly the same as that of Embodiment 2, except that: the input circuit uses NPN (N17, N18), PNP (P14, P15) complementary differential pairs and the current source has been correspondingly changed.

[0069] Among them, I1, I3, I4, I5, and I6 are fixed current sources, and I2 is a controlled current source. When the circuit is working normally, I 2 = 0; when the circuit is turned off, I2 outputs a non-zero current.

[0070] When the circuit is working normally, since I 2 = 0, then I N15C = I N16C = I P12C = I P13C = 0, so I N3C = I N4C = I P3C = I P4C = 0, and the turn-off circuit 200 does not work.

[0071] When the circuit is working normally, since I 2 = 0, then I N12C = I 1 , for matching considerations, design K N10N12 = K N11N12 K P10P11 , so I N10C = I P10C = K N10N12 I 1 , and the heavy-load feedback circuit 300 can improve the output current capacity when driving a heavy load.

[0072] Design K N13N14 I 2 > I 1 , then when the circuit is turned off, I N12C = 0, and the heavy-load feedback circuit 300 does not work.

[0073] When the circuit is turned off, I1 pulls up the base voltage of P2 to V P2B ≈ V OUT + 0.7V; I2 pulls down the base voltage of N2 to V N2B ≈ V OUT-0.7V; V P1B ≈V OUT The turn-off circuit 200 fully turns off P2 and N2, and avoids the risk of breakdown of their BE junctions.

[0074] When the chip starts up, due to the delay effects of the low-pass filters formed by R4 and C1, and R8 and C2, the collector currents of P7 and N7 are output later than those of P5, P6, N5, and N6. Therefore, no large current will flow through P1 and N1 during the startup process, avoiding the risk of damage.

[0075] Embodiment 4

[0076] This embodiment discloses an operational amplifier, including the output stage circuit with low power consumption and high driving ability as described in any one of Embodiment 1, Embodiment 2, or Embodiment 3.

[0077] As mentioned above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, and all of them should be covered by the protection scope of the present application. Any technical solution falling within the scope defined by the claims of the present invention falls within the protection scope of the present invention.

Claims

1. An output stage circuit with low power consumption and high driving capability, characterized in that: include: The AB class output stage circuit has an OUT output terminal for connecting a load. The AB class output stage circuit includes PNP tubes P1 and P2 and NPN tubes N1 and N2. A shut-down circuit, whose input end is connected to the OUT output end of the class AB output stage circuit, and is used to shut down the tube P2 or N2 according to the output signal of the class AB output stage circuit; The upper delayed-on current source is used to provide a static operating current for the tube P1 and delay the turning on of the tube P1; The lower end delayed start current source is used to provide a static working current for the tube N1 and delay the start of the tube N1; A heavy load feedback circuit, whose first output end is connected to the upper end delayed start current source, whose second output end is connected to the lower end delayed start current source, and whose input end is connected to the OUT output end of the AB class output stage circuit to adjust the output current I of the OUT output end OUT .

2. The output stage circuit with low power consumption and high driving capability according to claim 1, characterized in that: For the AB class output stage circuit, the emitter of tube P1 is connected to the base of tube N2, the base of tube P1 is connected to the base of tube N1, the emitter of tube N1 is connected to the base of tube P2, the emitter of tube P2 is connected to the emitter of tube N2 and connected to the output terminal OUT.

3. The output stage circuit with low power consumption and high driving capability according to claim 1, characterized in that: The shutdown circuit includes PNP tubes P3 and P4 and NPN tubes N3 and N4; wherein the bases of tubes P3 and N3 are both connected to the OUT output terminal, the emitter of tube P3 is connected to the base of tube N4 and the base of tube P2, the collector of tube P3 is connected to the collector of tube N3 and the emitter of tube N4, the emitter of tube N4 is also connected to the emitter of tube P4, the base of tube P4 is connected to the emitter of tube N3, and the emitter of tube N3 is also connected to the base of tube N2.

4. The output stage circuit with low power consumption and high driving capability according to claim 3, characterized in that: The shutdown circuit also includes PNP tubes P12 and P13 and NPN tubes N15 and N16; wherein the base of tube P12 is connected to the base of tube P13, the collector of tube P12 is connected to the collector of tube N15, the collector and base of tube P12 are short-circuited, the collector of tube P13 is connected to the emitter of tube P3, the base of tube N15 is connected to the base of tube N16, and the collector of tube N16 is connected to the emitter of tube N3.

5. The output stage circuit with low power consumption and high driving capability according to claim 4, characterized in that: The output stage circuit with low power consumption and high driving capability also includes NPN tubes N12, N13 and N14; wherein the collector of tube N12 is connected to the collector of tube N13, the base of tube N13 is connected to the base of tube N14, the base of tube N14 is also connected to the base of tube N15, the collector and base of tube N12 are short-circuited, and the collector and base of tube N14 are short-circuited.

6. The output stage circuit with low power consumption and high driving capability according to claim 1, characterized in that: The upper delayed-on current source includes PNP tubes P5, P6, P7 and resistors R1, R2, R3, R4 and capacitor C1; wherein the bases of tubes P5, P6 and P7 are connected, the emitter of tube P5 is connected to VCC through resistor R1, the emitter of tube P6 is connected to VCC through resistor R2, and the emitter of tube P7 is connected to VCC through resistor R3; the resistor R4 and the capacitor C1 form a low-pass filter connected to the base of tube P7, and the collector of tube P7 is connected to the emitter of tube P1.

7. The output stage circuit with low power consumption and high driving capability according to claim 1, characterized in that: The lower end delayed start current source includes NPN tubes N5, N6, N7 and resistors R5, R6, R7, R8 and capacitor C2; wherein the emitter of tube N5 is connected to VEE through resistor R5, the emitter of tube N6 is connected to VEE through resistor R6, and the emitter of tube N7 is connected to VEE through resistor R7, and resistor R8 and capacitor C2 form a low-pass filter connected to the base of tube N7.

8. The output stage circuit with low power consumption and high driving capability according to claim 1, characterized in that: The heavy-load feedback circuit includes PNP tubes P8 and P9 and NPN tubes N8 and N9. The emitter of tube N9 is connected to the emitter of tube P9, the base of tube N9 is connected to the emitter of tube P8, the collector of tube P8 is connected to the collector of tube N8 and then connected to the OUT output end of the AB class output stage circuit, the emitter of tube N8 is connected to the base of tube P9, the base of tube P8 is connected to the base of tube N8, the base of tube P8 is also connected to the upper end delayed start current source, and the base of tube N8 is also connected to the lower end delayed start current source.

9. The output stage circuit with low power consumption and high driving capability according to claim 8, characterized in that: The heavy-load feedback circuit further includes PNP tubes P10 and P11 and NPN tubes N10 and N11; wherein the base of tube P10 is connected to the base of tube P11, the collector of tube P10 is connected to the emitter of tube P8, the collector of tube P11 is connected to the collector of tube N11, the base and collector of tube P11 are short-circuited, the base of tube N11 is connected to the base of tube N10, and the collector of tube N10 is connected to the emitter of tube N8.

10. An operational amplifier, characterized in that: An output stage circuit with low power consumption and high driving capability comprising the output stage circuit as claimed in any one of claims 1 to 9.

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