Duty Cycle Calibration Circuit and Duty Cycle Calibration Method

Abstract

The present application relates to the field of integrated circuit technology and provides a duty cycle calibration circuit and a duty cycle calibration method. For the duty cycle calibration problem of clock signals in a wide frequency range, the duty cycle calibration circuit and method utilize a two-layer calibration code design of a range calibration code and a duty cycle calibration code and their cooperation, and combine dedicated circuit designs such as a first inverter and a second inverter with adjustable pull-up and pull-down capabilities, realizing automatic calibration of the driving ability of the forward clock transmission circuit, decoupling the two dimensions of frequency and duty cycle. When transmitting high-speed clock signals, there is no need to add excessive loads on the clock path. When transmitting low-speed clock signals, it is also possible to achieve a finer granularity at the output end and realize high-precision adjustment, and there is no need to occupy a large amount of space to store calibration codes, which is beneficial to controlling the circuit scale, contributing to miniaturization, integration, and improving system stability.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a duty cycle calibration circuit and a duty cycle calibration method. Background Art

[0002] In relevant applications of high-speed digital integrated circuits, such as artificial intelligence, industrial control, data centers, intelligent vehicles, etc., various clock chips, interface chips, etc. are widely used. For this reason, it is often necessary to perform duty cycle calibration (Duty Cycle Corrector, DCC) on input clock signals, output clock signals, etc., in order to calibrate the duty cycle of the clock signal to a design value, such as 50%, so as to cooperate with the subsequent modules and maintain system stability. For the duty cycle calibration circuits and methods of the prior art, one is to use an AC coupling method to decouple the common-mode value of the input clock signal, and then control the voltage at a specific point by adjusting the injected charge, thereby adjusting the duty cycle of the output clock signal. However, the AC coupling part and the injected charge part require additional circuits and hardware, and in differential applications, there may be an offset after calibrating the duty cycle, which is not conducive to system stability; another is also to use an AC coupling method to decouple the common-mode value of the input clock signal, and then utilize the pull-up ability and pull-down ability of the inverter to adjust the duty cycle of the output clock signal. However, a large number of loads cannot be mounted at the output end, so the granularity at the output end is relatively coarse and high-precision adjustment cannot be achieved; there is also one that uses a DC coupling method to transmit the clock signal, and adjusts the pull-up and pull-down abilities by configuring the number of static transistors for pull-up and pull-down, thereby adjusting the rising edge speed and falling edge speed of the clock signal, and further adjusting the duty cycle of the output clock signal. However, the control path needs to be deployed on the main clock path, so the granularity at the output end is relatively coarse and high-precision adjustment cannot be achieved. In addition, for the duty cycle calibration circuits and methods based on AC coupling in the prior art, in order to improve the adjustment accuracy to obtain fine time adjustment ability, the maximum data length of the calibration code is increased to cover a wider calibration range. However, this increases the hardware implementation difficulty and algorithm complexity, especially in the application of low-frequency clocks, a large amount of resources are occupied to store and maintain the calibration code.

[0003] Therefore, this application provides a duty cycle calibration circuit and a duty cycle calibration method, which can not only achieve a relatively fine granularity at the output end and high-precision adjustment, but also be suitable for duty cycle calibration of clock signals in a wide frequency range, providing an efficient and reliable calibration algorithm for clock signals from low frequency to high frequency, without introducing too much load on the clock path and without occupying a large amount of space to store the calibration code, which is beneficial to controlling the circuit scale, contributing to miniaturization, integration, and improving system stability. Summary of the Invention

[0004] In a first aspect, the present application provides a duty cycle calibration circuit. The duty cycle calibration circuit includes: a first branch, wherein the first branch includes a first inverter with adjustable pull-up and pull-down capabilities, the positive pole of the input differential clock signal is the input signal of the first inverter, the output signal of the first inverter is inverted and used as the positive pole of the output differential clock signal, the duty cycle calibration of the output signal of the first inverter relative to the duty cycle of the input signal of the first inverter is performed by a duty cycle calibration module, the pull-up and pull-down capabilities of the first inverter are adjusted by a range calibration code, and the duty cycle calibration module is configured by a duty cycle calibration code; a second branch, wherein the second branch includes a second inverter with adjustable pull-up and pull-down capabilities, the negative pole of the input differential clock signal is the input signal of the second inverter, the output signal of the second inverter is inverted and used as the negative pole of the output differential clock signal, the duty cycle calibration of the output signal of the second inverter relative to the duty cycle of the output signal of the second inverter is performed by the duty cycle calibration module, and the pull-up and pull-down capabilities of the second inverter are adjusted by the range calibration code.

[0005] Through the first aspect of the present application, in the face of the duty cycle calibration problem of clock signals in a wide frequency range, by using the two-layer calibration code design of the range calibration code and the duty cycle calibration code and their cooperation, and combining specialized circuit designs such as the first inverter and the second inverter with adjustable pull-up and pull-down capabilities, the driving ability of the forward clock transmission circuit is automatically calibrated, the two dimensions of frequency and duty cycle are decoupled, no excessive load needs to be added to the clock path when transmitting high-speed clock signals, and finer granularity at the output end and high-precision adjustment can also be achieved when transmitting low-speed clock signals. Moreover, there is no need to occupy a large amount of space to store the calibration code, which is beneficial to controlling the circuit scale and helps with miniaturization, integration, and improving system stability.

[0006] In a possible implementation manner of the first aspect of the present application, the driving ability of the forward clock transmission circuit of the first branch is determined based on the pull-up and pull-down capabilities of the first inverter, the range calibration code is used to configure the driving ability of the forward clock transmission circuit of the first branch, the driving ability of the forward clock transmission circuit of the second branch is determined based on the pull-up and pull-down capabilities of the second inverter, and the range calibration code is used to configure the driving ability of the forward clock transmission circuit of the second branch.

[0007] In a possible implementation of the first aspect of the present application, the duty cycle calibration code has a fixed maximum data length. The duty cycle calibration code increases or decreases at least one unit code value within the adjustment range of the duty cycle calibration code according to the unit code value. The adjustment range of the duty cycle calibration code is determined based on the fixed maximum data length, and the time value of the high and low level adjustment corresponding to the unit code value is determined based on the range calibration code.

[0008] In a possible implementation of the first aspect of the present application, when the range calibration code increases, the time value of the high and low level adjustment corresponding to the unit code value decreases; when the range calibration code decreases, the time value of the high and low level adjustment corresponding to the unit code value increases. Moreover, the range calibration code is automatically calibrated based on the frequency of the input differential clock signal. When the frequency of the input differential clock signal decreases, the range calibration code decreases; when the frequency of the input differential clock signal increases, the range calibration code increases.

[0009] In a possible implementation of the first aspect of the present application, the adjustment range of the duty cycle calibration code is from -15 to +15, and the unit code value is 1.

[0010] In a possible implementation of the first aspect of the present application, the duty cycle calibration code has a fixed adjustment range, and the range calibration code is automatically calibrated based on the frequency of the input differential clock signal, so that the duty cycle calibration module, when configured with the duty cycle calibration code of the first code value, performs duty cycle calibration to make the duty cycle of the output differential clock signal 50%, where the first code value is within the adjustment range.

[0011] In a possible implementation of the first aspect of the present application, the duty cycle calibration code varies between a fixed minimum value and a fixed maximum value. The automatic calibration of the range calibration code includes: configuring the range calibration code as the initial value, and then, when the duty cycle of the output differential clock signal is less than 50% when the duty cycle calibration code is the preset minimum value and greater than 50% when the duty cycle calibration code is the preset maximum value, gradually increasing the range calibration code until, after the range calibration code is increased from the first value to the second value, the duty cycle of the output differential clock signal is less than 50% or greater than 50% when the duty cycle calibration code is the preset minimum value and the preset maximum value, and selecting the first value as the value of the range calibration code after automatic calibration.

[0012] In a possible implementation manner of the first aspect of the present application, the fixed minimum value is less than the preset minimum value, the fixed maximum value is greater than the preset maximum value, and the difference between the fixed minimum value and the preset minimum value and the difference between the fixed maximum value and the preset maximum value are based on the design margin and the circuit state deviation margin for accommodating process voltage temperature condition changes.

[0013] In a possible implementation manner of the first aspect of the present application, the duty cycle of the output differential clock signal is 50% after the duty cycle calibration by the duty cycle calibration module.

[0014] In a possible implementation manner of the first aspect of the present application, the range calibration code is determined based on the frequency of the input differential clock signal.

[0015] In a possible implementation manner of the first aspect of the present application, the output differential clock signal output by the duty cycle calibration circuit is for the subsequent module of the duty cycle calibration circuit.

[0016] In a second aspect, an embodiment of the present application further provides a duty cycle calibration method. The duty cycle calibration method includes: providing a first branch of the duty cycle calibration circuit, where the first branch includes a first inverter with adjustable pull-up and pull-down capabilities, the positive pole of the input differential clock signal is the input signal of the first inverter, the output signal of the first inverter is inverted and used as the positive pole of the output differential clock signal, and the duty cycle calibration of the output signal of the first inverter relative to the duty cycle of the input signal of the first inverter is performed by the duty cycle calibration module of the duty cycle calibration circuit; providing a second branch of the duty cycle calibration circuit, where the second branch includes a second inverter with adjustable pull-up and pull-down capabilities, the negative pole of the input differential clock signal is the input signal of the second inverter, the output signal of the second inverter is inverted and used as the negative pole of the output differential clock signal, and the duty cycle calibration of the output signal of the second inverter relative to the duty cycle of the output signal of the second inverter is performed by the duty cycle calibration module; adjusting the pull-up and pull-down capabilities of the first inverter and the second inverter through the range calibration code, and configuring the duty cycle calibration module through the duty cycle calibration code.

[0017] In the second aspect of the present application, in the face of the duty cycle calibration problem of clock signals in a wide frequency range, by using a two-layer calibration code design of a range calibration code and a duty cycle calibration code and their cooperation, and combining dedicated circuit designs such as a first inverter and a second inverter with adjustable pull-up and pull-down capabilities, the driving ability of the positive clock transmission circuit is automatically calibrated, decoupling the two dimensions of frequency and duty cycle. When transmitting high-speed clock signals, it is not necessary to add excessive loads to the clock path. When transmitting low-speed clock signals, it is also possible to achieve a finer granularity at the output end and realize high-precision adjustment, and it is not necessary to occupy a large amount of space to store calibration codes, which is beneficial to controlling the circuit scale and contributes to miniaturization, integration, and improvement of system stability.

[0018] In a possible implementation manner of the second aspect of the present application, the driving ability of the positive clock transmission circuit of the first branch is determined based on the pull-up and pull-down capabilities of the first inverter, and the range calibration code is used to configure the driving ability of the positive clock transmission circuit of the first branch. The driving ability of the positive clock transmission circuit of the second branch is determined based on the pull-up and pull-down capabilities of the second inverter, and the range calibration code is used to configure the driving ability of the positive clock transmission circuit of the second branch.

[0019] In a possible implementation manner of the second aspect of the present application, the duty cycle calibration code has a fixed maximum data length. The duty cycle calibration code increases or decreases at least one unit code value within the adjustment range of the duty cycle calibration code according to the unit code value. The adjustment range of the duty cycle calibration code is determined based on the fixed maximum data length, and the time value of the high and low level adjustment corresponding to the unit code value is determined based on the range calibration code. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1 It is a schematic diagram of an application scenario of a clock chip;

[0022] Figure 2 It is a schematic diagram of a duty cycle calibration circuit provided by an embodiment of the present application;

[0023] Figure 3 It is a schematic flowchart of a duty cycle calibration method provided by an embodiment of the present application. Detailed Embodiments

[0024] The embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0025] It should be understood that in the description of the present application, "at least one" means one or more, and "a plurality" means two or more. In addition, words such as "first" and "second" are only used for the purpose of distinguishing descriptions unless otherwise specified, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0026] Figure 1 It is a schematic diagram of an application scenario of a clock chip. As Figure 1As shown, in the clock chip, the clock signal of the front-stage module 101 is transmitted to the duty cycle calibration circuit 103, and the clock signal is output to the back-stage module 105 after the duty cycle calibration of the duty cycle calibration circuit 103. In the relevant applications of high-speed digital integrated circuits, such as artificial intelligence, industrial control, data centers, smart cars, etc., clock chips need to be widely used to build high-speed digital integrated circuit interfaces or as part of more complex systems. Here, the duty cycle (Duty Cycle, DC) generally refers to the ratio of the high level duration in the pulse signal to the entire cycle time. The clock signal switches back and forth between the high level and the low level at a certain frequency. The calculation formula of the duty cycle is generally the ratio of the high level duration of the pulse to the entire pulse cycle. For example, assuming that the high level duration of the pulse signal is 6 milliseconds and the pulse cycle is 10 milliseconds, the duty cycle is 60%. In general, the duty cycle of the clock signal in the expected design is 50%, that is, the high level duration and the low level duration each occupy half of the entire cycle, which is helpful for operations such as sampling and comparison. Because the duty cycle of the clock signal may be affected by factors such as skew and jitter, it may deviate from the ideal 50%. This may cause the width of the data output corresponding to the high level and the low level on the timing diagram of the output end to be inconsistent, for example, the data width of the odd and even numbers is inconsistent, which may cause data reading errors, sampling errors, data loss, etc. For this reason, it is often necessary to perform duty cycle correction (DCC) on the input clock signal, output clock signal, etc., so as to calibrate the duty cycle of the clock signal to the design value, such as 50%, so as to maintain system stability. Applications such as artificial intelligence, industrial control, data centers, and smart cars have increasingly higher requirements for data transmission rate and data transmission performance, and in order to cover the needs of complex and changing application environments, it is necessary to provide multiple operating frequencies, that is, multiple frequency points. For this reason, it is necessary to provide a clock signal that can be adjusted within a wide frequency range, that is, the clock chip or the digital system using the clock signal needs to provide clock signals at multiple different frequency points from low frequency to high frequency. The lower the frequency, the longer the single clock cycle is. This means that for the same 1% adjustment of the clock cycle, the low-frequency clock signal requires a higher absolute time value than the high-frequency clock signal. Therefore, in order to provide high-precision time adjustment capabilities and fine granularity at the output, it is necessary to consider the flexibility and adaptability of the absolute time value adjustment capabilities corresponding to the clock signal with a wide frequency range from low frequency to high frequency. Figure 2As described in detail in the specific embodiments of the present application, a duty cycle calibration circuit and a duty cycle calibration method provided by the present application can not only achieve a finer granularity at the output end and realize high-precision adjustment, but also be suitable for duty cycle calibration of clocks in a wide frequency range, providing an efficient and reliable calibration algorithm for clock signals from low frequency to high frequency. It does not require introducing excessive load in the clock path or occupying a large amount of space to store calibration codes, which is beneficial to controlling the circuit scale and helps with miniaturization, integration, and improving system stability.

[0027] Figure 2 It is a schematic diagram of a duty cycle calibration circuit provided by an embodiment of the present application. As Figure 2 shown, the duty cycle calibration circuit includes a first branch and a second branch. The first branch includes a first inverter 201 with adjustable pull-up and pull-down capabilities. The positive pole 210 of the input differential clock signal is the input signal of the first inverter 201, and the output signal of the first inverter 201 is inverted and used as the positive pole 220 of the output differential clock signal. The duty cycle calibration of the output signal of the first inverter 201 relative to the duty cycle of the input signal of the first inverter 201 is performed by a duty cycle calibration module 205. The pull-up and pull-down capabilities of the first inverter 201 are adjusted by a range calibration code, and the duty cycle calibration module 205 is configured by a duty cycle calibration code. The second branch includes a second inverter 203 with adjustable pull-up and pull-down capabilities. The negative pole 212 of the input differential clock signal is the input signal of the second inverter 203. The output signal of the second inverter 203 is inverted and used as the negative pole 222 of the output differential clock signal. The duty cycle calibration of the output signal of the second inverter 203 relative to the duty cycle of the output signal of the second inverter 203 is performed by the duty cycle calibration module 205. The pull-up and pull-down capabilities of the second inverter 203 are adjusted by the range calibration code.

[0028] Figure 2The shown duty cycle calibration circuit can be applied to application fields such as artificial intelligence, industrial control, data centers, and intelligent vehicles. These application fields need to face the requirements of complex and changeable application environments and need to provide multiple operating frequencies, that is, multiple frequency points. For this reason, a clock signal adjustable within a wide frequency range needs to be provided. That is, a clock chip or a digital system using a clock signal needs to provide clock signals at multiple different frequency points from low frequency to high frequency. The lower the frequency, the longer the single clock cycle. This also means that, for the same 1% adjustment of the clock cycle, the low-frequency clock signal requires a higher absolute time value adjustment compared to the high-frequency clock signal. Especially at the output end using a differential clock output signal, the output clock calibration ability is determined by the minimum granularity of the time value that the duty cycle calibration circuit can adjust the high and low level times. The higher the frequency of the output clock signal, the shorter the single clock cycle, and the smaller the minimum granularity of the time value for adjusting the high and low level times. Taking the duty cycle adjustment with a granularity of plus or minus 5% at the output end as an example, this means the time adjustment ability to adjust the absolute time value corresponding to 5% of the entire clock cycle. For example, when the frequency of the output clock signal is ten billion hertz, that is, 10 gigahertz (GHz), here, 1 gigahertz, that is, 1 GHz, is 10 to the 9th power of hertz. Therefore, ten billion hertz corresponds to 100 picoseconds. That is to say, the single clock cycle is 100 picoseconds (picosecond, PS), and 1 second is equal to 10 to the 12th power of picoseconds. One thousandth, that is, 0.1% of the duty cycle corresponds to one thousandth of the single clock cycle, which is one thousandth of 100 picoseconds, that is, 0.1 picosecond. This means that for a 5% duty cycle adjustment, an absolute time value of 5 picoseconds needs to be adjusted. In contrast, when the frequency of the output clock signal is one billion hertz, that is, 1 GHz, the single clock cycle is 1000 picoseconds, and one thousandth of the duty cycle corresponds to 1 picosecond. This means that for a 5% duty cycle adjustment, an absolute time value of 50 picoseconds needs to be adjusted. It can be seen that for the duty cycle calibration of clock signals in a wide frequency range, from 1 GHz to 10 GHz, the single clock cycle ranges from 1000 picoseconds to 100 picoseconds, and the absolute time value corresponding to the plus or minus 5% duty cycle adjustment ranges from 50 picoseconds to 5 picoseconds. Therefore, in order to provide high-precision time adjustment ability and fine granularity at the output end, it is necessary to consider the flexibility and adaptability of the adjustment ability of the absolute time value corresponding to the clock signals in a wide frequency range from low frequency to high frequency. If adjusted from the absolute driving ability of the calibration circuit, the adjustable high and low level time values obtained in this way are absolute time values. This means that the fine degree requirements for the duty cycle adjustment of the output clock signal are met through a certain length of duty cycle calibration code, and the time value that each duty cycle calibration code can provide for high and low level adjustment is absolute. Therefore, the longer the absolute time value corresponding to the minimum granularity of the duty cycle adjustment means more duty cycle calibration codes.Taking the frequencies of the output clock signal as 10 billion Hz and 1 billion Hz as examples, when the frequency of the output clock signal is 10 billion Hz, adjusting the duty cycle by 5% requires adjusting the absolute time value of 5 picoseconds, which requires 100 duty cycle calibration codes and occupies 7 bits (2 to the power of 7 is 128). In contrast, when the frequency of the output clock signal is 1 billion Hz, adjusting the duty cycle by 5% requires adjusting the absolute time value of 50 picoseconds, which requires 1000 duty cycle calibration codes and occupies 10 bits (2 to the power of 10 is 1024). Therefore, if relying on the absolute driving ability of the calibration circuit and the duty cycle calibration codes to directly adjust the high and low level time values, which are absolute time values, this is reflected in the duty cycle calibration codes, meaning that longer code values of duty cycle calibration codes are required to support the fine granularity of lower frequency clock signals at the output, such as adjusting the duty cycle by plus or minus 5%. For this reason,... Figure 2 The duty cycle calibration circuit shown decouples the two dimensions of the frequency of the clock signal and the duty cycle of the clock signal by introducing a two-layer calibration code design, thus avoiding the drawbacks brought by the prior art duty cycle calibration scheme that relies on the absolute driving ability of the calibration circuit and the duty cycle calibration codes to directly adjust the high and low level time values, which are absolute time values. The following will be further described in detail.

[0029] Refer to Figure 2 , the input differential clock signal of the duty cycle calibration circuit is a differential clock signal, so it is divided into the positive electrode 210 of the input differential clock signal and the negative electrode 212 of the input differential clock signal. In contrast, the duty cycle calibration circuit includes a first branch and a second branch, which are respectively used to adjust the positive electrode 210 of the input differential clock signal and the negative electrode 212 of the input differential clock signal, so that the duty cycle of the finally output output differential clock signal reaches the design purpose. Specifically, Figure 2 The duty cycle calibration circuit shown introduces a two-layer calibration code design, namely the range calibration code (RangeCalibration Code) and the duty cycle calibration code (DCC, Duty Calibration Code). Using the range calibration code and the duty cycle calibration code, first automatically calibrate the driving ability of the forward clock transmission circuit, and then adjust the duty cycle of the transmitted clock to the designed value, such as 50%. In this way, the driving ability of the forward clock transmission circuit can be configured according to the frequency of the currently transmitted clock signal, and then the duty cycle of the output clock signal can be calibrated. Specifically, using the two-layer calibration code design, the first layer is the range calibration code, and the function of the range calibration code is to amplify or reduce the time value of the high and low level adjustment that can be provided by the unit code value of the duty cycle calibration code. In other words, by introducing the range calibration code and taking Figure 2For a dedicated circuit design such as this, the two dimensions of the frequency of the clock signal and the duty cycle of the clock signal are decoupled. Instead of relying on the absolute driving ability of the calibration circuit and directly adjusting the high and low level time values (which are absolute time values) according to the duty cycle calibration code, through the design of two layers of calibration codes, namely the range calibration code and the duty cycle calibration code, the time value of the high and low levels that can be adjusted by the unit code value of the duty cycle calibration code in the duty cycle calibration circuit is determined by the range calibration code. Specifically, the larger the range calibration code, the smaller the time value of the high and low level adjustment that can be provided by the unit code value of the duty cycle calibration code. Conversely, the smaller the range calibration code, the larger the time value of the high and low level adjustment that can be provided by the unit code value of the duty cycle calibration code. Therefore, the maximum data length of the duty cycle calibration code can be set to a fixed value, such as 8 bits or 10 bits. That is to say, the duty cycle calibration code can be set to vary within a fixed adjustment range, for example, between a fixed minimum value and a fixed maximum value, such as -15 to +15, or -12 to +12. Under the constraint that the duty cycle calibration code has a fixed maximum data length, the time adjustment ability that the duty cycle calibration code can provide is determined by the time value of the high and low level adjustment that can be provided by the unit code value of the duty cycle calibration code and the maximum (minimum) value of the duty cycle calibration code. Therefore, by adjusting the range calibration code, the time value of the high and low level adjustment that can be provided by the unit code value of the duty cycle calibration code can be changed, and thus, on the basis that the duty cycle calibration code has a fixed maximum data length, a flexibly adjustable time adjustment ability can be provided. For example, the larger the range calibration code, the smaller the time value of the high and low level adjustment that can be provided by the unit code value of the duty cycle calibration code, and thus the time value of the high and low level adjustment corresponding to the maximum (minimum) value of the duty cycle calibration code is also smaller, which means a smaller adjustment range. In addition, by setting the maximum data length of the duty cycle calibration code to a fixed value, or setting the duty cycle calibration code to vary within a fixed adjustment range, it avoids occupying a large amount of space to store and manage the duty cycle calibration code, and the duty cycle calibration code with a unified maximum data length is also conducive to the optimized utilization of storage resources.

[0030] Continue to refer to Figure 2, through the cooperation between the range calibration code and the duty cycle calibration code, under the restriction that the duty cycle calibration code has a fixed maximum data length, the duty cycle calibration code varies between a fixed minimum value and a fixed maximum value. For example, it is set that the duty cycle calibration code varies between -15 and +15. Optionally, considering the design margin, the duty cycle calibration code can be restricted to vary within a smaller range, such as between -12 and +12, that is, from -12 to +12. Here, the larger the negative value, that is, the smaller the code value of the duty cycle calibration code, it means the higher the degree of adjustment in the direction of decreasing the duty cycle, that is, reducing the duty cycle of the output clock signal. On the contrary, the higher the positive value, that is, the larger the code value of the duty cycle calibration code, it means the higher the degree of adjustment in the direction of increasing the duty cycle, that is, increasing the duty cycle of the output clock signal. In this way, in the face of clock signals with a wide frequency range, the appropriate range calibration code can be found in combination with the frequency of the clock signal, and finally the corresponding code value of the duty cycle calibration code can be found within the allowed variation range of the designed duty cycle calibration code, so as to achieve the design purpose of calibrating the duty cycle of the output clock signal to the designed value, such as 50%. The code value of the duty cycle calibration code found in this way can not only meet the duty cycle calibration requirements, but also will surely not exceed the established data length. And, by reserving a certain space as the design margin, various situations can be better dealt with. For example, the circuit state deviation margin due to the change of process voltage temperature (PVT) conditions, that is, considering that the actual state of the circuit deviates due to the change of PVT conditions, such as the deviation of logic gate delay, electrical characteristics of electronic devices, etc. This may cause the actual operation of the circuit to change with temperature and supply voltage. Reserving the design margin, such as 3 unit code values (restricted from -15 to -12 and +12), can be used for interval time calibration.

[0031] Continue to refer to Figure 2, the input node of the first inverter 201 is the first node 240, and the output node of the first inverter 201 is the second node 242. The duty cycle calibration module 205 is connected to the first node 240 and the second node 242. Thus, the duty cycle calibration of the output signal of the first inverter 201 relative to the duty cycle of the input signal of the first inverter 201 is performed by the duty cycle calibration module 205. The input node of the second inverter 203 is the third node 250, and the output node of the second inverter 203 is the fourth node 252. The duty cycle calibration module 205 is connected to the third node 250 and the fourth node 252. Thus, the duty cycle calibration of the output signal of the second inverter 203 relative to the duty cycle of the output signal of the second inverter 203 is performed by the duty cycle calibration module 205. The duty cycle calibration module 205 can adopt any suitable specific calibration algorithm, circuit design, hardware, etc. For example, the duty cycle calibration module 205 can adopt an AC coupling method to decouple the common-mode value of the input clock signal, and then use the charge injection technique or any other suitable technique to adjust the rising edge speed and falling edge speed of the clock signal to achieve the purpose of adjusting the duty cycle of the output clock signal. Therefore, for the specific implementation form of the duty cycle calibration module 205, as long as it can support the design of the above two-layer calibration codes, that is, support the cooperation between the range calibration code and the duty cycle calibration code, so that the time value of the high and low levels that can be provided by the unit code value of the duty cycle calibration code in the duty cycle calibration circuit is determined by the range calibration code. In this way, the duty cycle calibration module 205 can cooperate with the first inverter 201 and the second inverter 203 to first automatically calibrate the driving ability of the forward clock transmission circuit, and then adjust the duty cycle of the transmitted clock to the designed value, such as 50%. Thus, the driving ability of the forward clock transmission circuit can be configured according to the frequency of the currently transmitted clock signal, and then the duty cycle of the output clock signal is calibrated. Here, the pull-up and pull-down capabilities of the first inverter 201 are adjusted by the range calibration code, the duty cycle calibration module 205 is configured by the duty cycle calibration code, and the pull-up and pull-down capabilities of the second inverter 203 are adjusted by the range calibration code. Thus, the range calibration code is used to adjust the pull-up and pull-down capabilities of the first inverter 201, so that the driving ability of the forward clock transmission circuit can be automatically calibrated for the first branch, and the range calibration code is used to adjust the pull-up and pull-down capabilities of the second inverter 203, so that the driving ability of the forward clock transmission circuit can be automatically calibrated for the second branch.The duty cycle calibration module 205 is configured by a duty cycle calibration code, and the duty cycle calibration of the output signal of the first inverter 201 relative to the duty cycle of the input signal of the first inverter 201 is performed through the duty cycle calibration module 205, and the duty cycle calibration of the output signal of the second inverter 203 relative to the duty cycle of the output signal of the second inverter 203 is also performed. In this way, the duty cycle calibration of the clock signal in a wide frequency range is achieved, decoupling the two dimensions of frequency and duty cycle, which is beneficial to reducing the circuit scale and simplifying the calibration algorithm. Moreover, when transmitting a high-speed clock signal, too much load will not be added to the clock path, and when transmitting a low-speed clock signal, a large calibration range can still be achieved.

[0032] Reference Figure 2 , the output signal of the first inverter 201 is inverted and used as the positive pole 220 of the output differential clock signal. Here, the output signal of the first inverter 201 is inverted by the first output terminal inverter 230 and used as the positive pole 220 of the output differential clock signal. The output signal of the second inverter 203 is inverted and used as the negative pole 222 of the output differential clock signal. Here, the output signal of the second inverter 203 is inverted by the second output terminal inverter 232 and used as the negative pole 222 of the output differential clock signal. It should be understood that in some embodiments, the first output terminal inverter 230 and the second output terminal inverter 232 can be regarded as part of the subsequent module, that is Figure 2 The duty cycle calibration circuit shown can be limited to the first inverter 201, the second inverter 203 and the duty cycle calibration module 205 shown in the dotted box. In other embodiments, the first output terminal inverter 230 and the second output terminal inverter 232 can be regarded as Figure 2 Part of the duty cycle calibration circuit shown.

[0033] In short, Figure 2 For the duty cycle calibration problem of clock signals in a wide frequency range, the duty cycle calibration circuit shown utilizes the two-layer calibration code design of the range calibration code and the duty cycle calibration code and their cooperation, and combines special circuit designs such as the first inverter 201 and the second inverter 203 with adjustable pull-up and pull-down capabilities to achieve automatic calibration of the driving ability of the forward clock transmission circuit, decouple the two dimensions of frequency and duty cycle, do not require too much load to be added to the clock path when transmitting high-speed clock signals, can also achieve a finer granularity at the output end and high-precision adjustment when transmitting low-speed clock signals, and do not require a large amount of space to store the calibration code, which is beneficial to controlling the circuit scale and helps to miniaturize, integrate and improve system stability.

[0034] Reference Figure 2, in a possible implementation, the driving capability of the positive clock transmission circuit of the first branch is determined based on the pull-up and pull-down capabilities of the first inverter 201, and the range calibration code is used to configure the driving capability of the positive clock transmission circuit of the first branch. The driving capability of the positive clock transmission circuit of the second branch is determined based on the pull-up and pull-down capabilities of the second inverter 203, and the range calibration code is used to configure the driving capability of the positive clock transmission circuit of the second branch. In this way, the range calibration code is used to adjust the pull-up and pull-down capabilities of the first inverter 201, so that the driving capability of the positive clock transmission circuit can be automatically calibrated for the first branch. Moreover, the range calibration code is used to adjust the pull-up and pull-down capabilities of the second inverter 203, so that the driving capability of the positive clock transmission circuit can be automatically calibrated for the second branch. The driving capability of the positive clock transmission circuit can be configured according to the frequency of the currently transmitted clock signal, and then the duty cycle of the output clock signal is calibrated. The duty cycle calibration of the clock signal in a wide frequency range is realized, decoupling the two dimensions of frequency and duty cycle, which is beneficial to reducing the circuit scale and simplifying the calibration algorithm. Also, when transmitting high-speed clock signals, too much load will not be added to the clock path, and when transmitting low-speed clock signals, a large calibration range can still be achieved.

[0035] In a possible implementation, the duty cycle calibration code has a fixed maximum data length. The duty cycle calibration code increases or decreases at least one unit code value within the adjustment range of the duty cycle calibration code according to the unit code value. The adjustment range of the duty cycle calibration code is determined based on the fixed maximum data length, and the time value of the high and low level adjustment corresponding to the unit code value is determined based on the range calibration code. The unit code value refers to the minimum change amount by which the duty cycle calibration code increases or decreases within the adjustment range of the duty cycle calibration code. For example, if it is set that the duty cycle calibration code varies between -15 and +15, the unit code value can be set to 1. That is, the duty cycle calibration code can increase from +8 to +9, or can decrease from -10 to -11. If the duty cycle calibration code is recorded in binary data format, 100 duty cycle calibration codes occupy 7 bits (2 to the power of 7 is 128), and 1000 duty cycle calibration codes occupy 10 bits (2 to the power of 10 is 1024). Here, the unit code value can be set to the least significant bit of the duty cycle calibration code, that is, the minimum change amount by which the duty cycle calibration code increases or decreases is the change amount caused by the least significant bit of the duty cycle calibration code changing from 0 to 1 or from 1 to 0. As described above, if adjusted from the absolute driving ability of the calibration circuit, the adjustable high and low level time values obtained in this way are absolute time values. This means that the duty cycle adjustment fineness requirements of the output clock signal are met by a certain length of duty cycle calibration code, and the time value of the high and low level adjustment that each duty cycle calibration code can provide is absolute. Therefore, the absolute time value corresponding to the longer minimum granularity duty cycle adjustment means more duty cycle calibration codes. For this reason, Figure 2 The shown duty cycle calibration circuit introduces a two-layer calibration code design, decoupling the two dimensions of the frequency of the clock signal and the duty cycle of the clock signal, thereby avoiding the drawbacks brought about by the fact that the duty cycle calibration scheme of the prior art depends on the absolute driving ability of the calibration circuit and the duty cycle calibration code to directly adjust the high and low level time values being absolute time values. By introducing the range calibration code and Figure 2For a dedicated circuit design such as this, it decouples the two dimensions of the frequency of the clock signal and the duty cycle of the clock signal, so that instead of relying on the absolute driving ability of the calibration circuit and directly adjusting the high and low level time values according to the duty cycle calibration code (which are absolute time values), through the design of two layers of calibration codes, namely the range calibration code and the duty cycle calibration code, the time value of the high and low levels that can be adjusted by the unit code value of the duty cycle calibration code in the duty cycle calibration circuit is determined by the range calibration code. The duty cycle calibration code can be set to vary within a fixed adjustment range, for example, between a fixed minimum value and a fixed maximum value, such as from -15 to +15, or from -12 to +12. Under the constraint of the fixed maximum data length of the duty cycle calibration code, the time adjustment ability that the duty cycle calibration code can provide is determined by the time value of the high and low level adjustments that the unit code value of the duty cycle calibration code can provide together with the maximum (minimum) value of the duty cycle calibration code. Therefore, by adjusting the range calibration code, the time value of the high and low level adjustments that the unit code value of the duty cycle calibration code can provide can be changed, and thus, based on the fixed maximum data length of the duty cycle calibration code, a flexibly adjustable time adjustment ability can be provided. In this way, the driving ability of the forward clock transmission circuit is automatically calibrated, the two dimensions of frequency and duty cycle are decoupled, there is no need to add excessive load on the clock path when transmitting high-speed clock signals, and when transmitting low-speed clock signals, a finer granularity at the output end can be achieved and high-precision adjustment can be realized. Also, there is no need to occupy a large amount of space to store the calibration code, which is beneficial to controlling the circuit scale and contributes to miniaturization, integration, and improving system stability.

[0036] In some embodiments, when the range calibration code increases, the time value for adjusting the high and low levels corresponding to the unit code value decreases; when the range calibration code decreases, the time value for adjusting the high and low levels corresponding to the unit code value increases. Moreover, the range calibration code is automatically calibrated based on the frequency of the input differential clock signal. When the frequency of the input differential clock signal decreases, the range calibration code decreases; when the frequency of the input differential clock signal increases, the range calibration code increases. Thus, the larger the range calibration code, the smaller the time value for adjusting the high and low levels that can be provided by the unit code value of the duty cycle calibration code. Conversely, the smaller the range calibration code, the larger the time value for adjusting the high and low levels that can be provided by the unit code value of the duty cycle calibration code. Under the constraint that the duty cycle calibration code has a fixed maximum data length, the time adjustment ability that the duty cycle calibration code can provide is determined by the time value for adjusting the high and low levels that can be provided by the unit code value of the duty cycle calibration code and the maximum (minimum) value of the duty cycle calibration code. Therefore, by adjusting the range calibration code, the time value for adjusting the high and low levels that can be provided by the unit code value of the duty cycle calibration code can be changed, and thus, based on the fact that the duty cycle calibration code has a fixed maximum data length, a flexibly adjustable time adjustment ability can be provided. For example, the larger the range calibration code, the smaller the time value for adjusting the high and low levels that can be provided by the unit code value of the duty cycle calibration code, and thus, the time value for adjusting the high and low levels corresponding to the maximum (minimum) value of the duty cycle calibration code is also smaller, which means a smaller adjustment range. Additionally, by setting the maximum data length of the duty cycle calibration code as a fixed value, or setting the duty cycle calibration code to vary within a fixed adjustment range, it is possible to avoid occupying a large amount of space for storing and managing the duty cycle calibration code, and the duty cycle calibration code with a unified maximum data length is also beneficial for optimizing the utilization of storage resources.

[0037] In some embodiments, the adjustment range of the duty cycle calibration code is from -15 to +15, and the unit code value is 1. Thus, in the face of the duty cycle calibration problem of clock signals with a wide frequency range, by using the two-layer calibration code design of the range calibration code and the duty cycle calibration code and their cooperation, and combining with specialized circuit designs such as the first inverter 201 and the second inverter 203 with adjustable pull-up and pull-down capabilities, the driving ability of the forward clock transmission circuit is automatically calibrated, decoupling the two dimensions of frequency and duty cycle. When transmitting high-speed clock signals, there is no need to add excessive loads on the clock path. When transmitting low-speed clock signals, a finer granularity at the output end can be achieved and high-precision adjustment can be realized, and there is also no need to occupy a large amount of space to store the calibration code, which is beneficial to controlling the circuit scale, contributing to miniaturization, integration, and improving system stability.

[0038] In a possible implementation, the duty cycle calibration code has a fixed adjustment range, and the range calibration code is automatically calibrated based on the frequency of the input differential clock signal, so that the duty cycle calibration module, when configured with the duty cycle calibration code of the first code value, performs duty cycle calibration to make the duty cycle of the output differential clock signal 50%, where the first code value is within the adjustment range. In this way, for the duty cycle calibration problem of clock signals with a wide frequency range, by using the two-layer calibration code design of the range calibration code and the duty cycle calibration code and their cooperation, and combining the dedicated circuit design such as the first inverter 201 and the second inverter 203 with adjustable pull-up and pull-down capabilities, the driving ability of the forward clock transmission circuit is automatically calibrated, decoupling the two dimensions of frequency and duty cycle. When transmitting high-speed clock signals, there is no need to add too much load on the clock path. When transmitting low-speed clock signals, a finer granularity at the output end can be achieved and high-precision adjustment can be realized, and there is no need to occupy a large amount of space to store calibration codes, which is beneficial to controlling the circuit scale and helps with miniaturization, integration, and improving system stability.

[0039] In a possible implementation, the duty cycle calibration code varies between a fixed minimum value and a fixed maximum value. The automatic calibration of the range calibration code includes: configuring the range calibration code to an initial value, and then, when the duty cycle of the output differential clock signal is less than 50% when the duty cycle calibration code is the preset minimum value and greater than 50% when the duty cycle calibration code is the preset maximum value, gradually increasing the range calibration code until, after the range calibration code is increased from the first value to the second value, the duty cycle of the output differential clock signal is less than 50% or greater than 50% when the duty cycle calibration code is the preset minimum value and the preset maximum value, and selecting the first value as the automatically calibrated value of the range calibration code. By using the range calibration code and the duty cycle calibration code, first automatically calibrate the driving ability of the forward clock transmission circuit, and then adjust the duty cycle of the transmitted clock to the design value, such as 50%. In this way, the driving ability of the forward clock transmission circuit can be configured according to the frequency of the currently transmitted clock signal, and then the duty cycle of the output clock signal can be calibrated. In this way, for clock signals with a wide frequency range, the appropriate range calibration code can be found in combination with the frequency of the clock signal, and finally the corresponding code value of the duty cycle calibration code can be found within the allowed variation range of the designed duty cycle calibration code, and the design purpose of calibrating the duty cycle of the output clock signal to the design value, such as 50%, can be achieved. The code value of the duty cycle calibration code found in this way can not only meet the duty cycle calibration requirements but also necessarily not exceed the established data length.

[0040] In some embodiments, the fixed minimum value is less than the preset minimum value, and the fixed maximum value is greater than the preset maximum value. The difference between the fixed minimum value and the preset minimum value and the difference between the fixed maximum value and the preset maximum value are based on the design margin and the circuit state deviation margin for accommodating process voltage temperature condition variations. In this way, by reserving a certain space as the design margin, various situations can be better coped with. For example, the circuit state deviation margin for process voltage temperature condition variations, that is, considering the deviation of the actual circuit state caused by PVT condition variations, such as the deviation of logic gate delay, electrical characteristics of electronic devices, etc. This may cause the actual operation of the circuit to change with temperature and supply voltage. Reserving a design margin, such as 3 unit code values (from ±15 restricted to ±12), can be used for interval time calibration.

[0041] In a possible implementation manner, the duty cycle of the output differential clock signal is 50% after the duty cycle calibration by the duty cycle calibration module. In this way, in the face of the duty cycle calibration problem of clock signals with a wide frequency range, by using the two-layer calibration code design of the range calibration code and the duty cycle calibration code and their cooperation, and combining dedicated circuit designs such as the first inverter 201 and the second inverter 203 with adjustable pull-up and pull-down capabilities, the driving ability of the forward clock transmission circuit is automatically calibrated, decoupling the two dimensions of frequency and duty cycle. When transmitting high-speed clock signals, there is no need to add too much load on the clock path. When transmitting low-speed clock signals, a finer granularity at the output end can be achieved and high-precision adjustment can be realized. Moreover, there is no need to occupy a large amount of space to store calibration codes, which is beneficial to controlling the circuit scale, contributing to miniaturization, integration, and improving system stability.

[0042] In a possible implementation manner, the range calibration code is determined based on the frequency of the input differential clock signal. In this way, in the face of the duty cycle calibration problem of clock signals with a wide frequency range, by using the two-layer calibration code design of the range calibration code and the duty cycle calibration code and their cooperation, and combining dedicated circuit designs such as the first inverter 201 and the second inverter 203 with adjustable pull-up and pull-down capabilities, the driving ability of the forward clock transmission circuit is automatically calibrated, decoupling the two dimensions of frequency and duty cycle. When transmitting high-speed clock signals, there is no need to add too much load on the clock path. When transmitting low-speed clock signals, a finer granularity at the output end can be achieved and high-precision adjustment can be realized. Moreover, there is no need to occupy a large amount of space to store calibration codes, which is beneficial to controlling the circuit scale, contributing to miniaturization, integration, and improving system stability.

[0043] In a possible implementation, the output differential clock signal output by the duty cycle calibration circuit is for a subsequent module of the duty cycle calibration circuit. In this way, in the face of the duty cycle calibration problem of clock signals in a wide frequency range, by using the two-layer calibration code design of the range calibration code and the duty cycle calibration code and their cooperation, and combining special circuit designs such as the first inverter 201 and the second inverter 203 with adjustable pull-up and pull-down capabilities, the driving ability of the forward clock transmission circuit is automatically calibrated, decoupling the two dimensions of frequency and duty cycle. When transmitting high-speed clock signals, there is no need to add excessive loads on the clock path. When transmitting low-speed clock signals, it is also possible to achieve a finer granularity at the output end and realize high-precision adjustment, and there is no need to occupy a large amount of space to store calibration codes, which is beneficial to controlling the circuit scale and helps with miniaturization, integration, and improving system stability.

[0044] Figure 3 The flowchart of a duty cycle calibration method provided by an embodiment of this application is shown as Figure 3 follows. The duty cycle calibration method includes the following steps.

[0045] Step S301: Provide a first branch of the duty cycle calibration circuit. Among them, the first branch includes a first inverter with adjustable pull-up and pull-down capabilities. The positive pole of the input differential clock signal is the input signal of the first inverter. The output signal of the first inverter is inverted and used as the positive pole of the output differential clock signal. The duty cycle calibration of the output signal of the first inverter relative to the duty cycle of the input signal of the first inverter is executed by the duty cycle calibration module of the duty cycle calibration circuit.

[0046] Step S303: Provide a second branch of the duty cycle calibration circuit. Among them, the second branch includes a second inverter with adjustable pull-up and pull-down capabilities. The negative pole of the input differential clock signal is the input signal of the second inverter. The output signal of the second inverter is inverted and used as the negative pole of the output differential clock signal. The duty cycle calibration of the output signal of the second inverter relative to the duty cycle of the output signal of the second inverter is executed by the duty cycle calibration module.

[0047] Step S305: Adjust the pull-up and pull-down capabilities of the first inverter and the second inverter through the range calibration code, and configure the duty cycle calibration module through the duty cycle calibration code.

[0048] Figure 3The duty cycle calibration method shown, in the face of the duty cycle calibration problem of clock signals in a wide frequency range, uses a two-layer calibration code design of a range calibration code and a duty cycle calibration code and their cooperation, and combines dedicated circuit designs such as a first inverter and a second inverter with adjustable pull-up and pull-down capabilities to achieve automatic calibration of the driving ability of the forward clock transmission circuit, decouples the two dimensions of frequency and duty cycle, does not require adding excessive loads on the clock path when transmitting high-speed clock signals, can also achieve a finer granularity at the output end and high-precision adjustment when transmitting low-speed clock signals, and does not require occupying a large amount of space to store calibration codes, which is beneficial to controlling the circuit scale and helps with miniaturization, integration, and improving system stability.

[0049] Reference Figure 3 , in a possible implementation manner, the driving ability of the forward clock transmission circuit of the first branch is determined based on the pull-up and pull-down capabilities of the first inverter, and the range calibration code is used to configure the driving ability of the forward clock transmission circuit of the first branch. The driving ability of the forward clock transmission circuit of the second branch is determined based on the pull-up and pull-down capabilities of the second inverter, and the range calibration code is used to configure the driving ability of the forward clock transmission circuit of the second branch. In this way, the range calibration code is used to adjust the pull-up and pull-down capabilities of the first inverter, so as to automatically calibrate the driving ability of the forward clock transmission circuit for the first branch. Moreover, the range calibration code is used to adjust the pull-up and pull-down capabilities of the second inverter, so as to automatically calibrate the driving ability of the forward clock transmission circuit for the second branch. The driving ability of the forward clock transmission circuit can be configured according to the frequency of the currently transmitted clock signal, and then the duty cycle of the output clock signal is calibrated. It realizes the duty cycle calibration of clock signals in a wide frequency range, decouples the two dimensions of frequency and duty cycle, is beneficial to reducing the circuit scale and simplifying the calibration algorithm, and when transmitting high-speed clock signals, does not add excessive loads on the clock path, and when transmitting low-speed clock signals, can still achieve a large calibration range.

[0050] In a possible implementation, the duty cycle calibration code has a fixed maximum data length. The duty cycle calibration code increases or decreases at least one unit code value within the adjustment range of the duty cycle calibration code according to the unit code value. The adjustment range of the duty cycle calibration code is determined based on the fixed maximum data length. The time value for adjusting the high and low levels corresponding to the unit code value is determined based on the range calibration code. The unit code value refers to the minimum change amount by which the duty cycle calibration code increases or decreases within the adjustment range of the duty cycle calibration code. For example, if it is set that the duty cycle calibration code varies between positive and negative 15, the unit code value can be set to 1, that is, the duty cycle calibration code can increase from positive 8 to positive 9, or can decrease from negative 10 to negative 11. If the duty cycle calibration code is recorded in binary data format, 100 duty cycle calibration codes occupy 7 bits (2 to the power of 7 is 128), and 1000 duty cycle calibration codes occupy 10 bits (2 to the power of 10 is 1024). Here, the unit code value can be set as the least significant bit of the duty cycle calibration code, that is, the minimum change amount by which the duty cycle calibration code increases or decreases is the change amount caused by the least significant bit of the duty cycle calibration code changing from 0 to 1 or from 1 to 0. As described above, if adjusted from the aspect of the absolute driving ability of the calibration circuit, the adjustable high and low level time values obtained in this way are absolute time values, which means that the duty cycle adjustment fineness requirements of the output clock signal are met by a certain length of duty cycle calibration code, and the time value for adjusting the high and low levels that each duty cycle calibration code can provide is absolute. Therefore, the absolute time value corresponding to the longer minimum granularity duty cycle adjustment means more duty cycle calibration codes. For this reason, Figure 3The duty cycle calibration method shown above introduces the design of two layers of calibration codes, decoupling the two dimensions of the frequency of the clock signal and the duty cycle of the clock signal, thereby avoiding the drawbacks of the duty cycle calibration scheme in the prior art that depends on the absolute driving ability of the calibration circuit and the duty cycle calibration code to directly adjust the high and low level time values, which are absolute time values. By introducing the range calibration code and a dedicated circuit design, the two dimensions of the frequency of the clock signal and the duty cycle of the clock signal are decoupled, such that instead of relying on the absolute driving ability of the calibration circuit and directly adjusting the high and low level time values, which are absolute time values, according to the duty cycle calibration code, through the design of the two layers of calibration codes, namely the range calibration code and the duty cycle calibration code, the time value that can be adjusted for the high and low levels provided by the unit code value of the duty cycle calibration code in the duty cycle calibration circuit is determined by the range calibration code. The duty cycle calibration code can be set to vary within a fixed adjustment range, for example, vary between a fixed minimum value and a fixed maximum value, such as from -15 to +15, or from -12 to +12. Under the constraint of the fixed maximum data length of the duty cycle calibration code, the time adjustment ability that the duty cycle calibration code can provide is determined by the time value that can be adjusted for the high and low levels provided by the unit code value of the duty cycle calibration code and the maximum value (minimum value) of the duty cycle calibration code. Therefore, by adjusting the range calibration code, the time value that can be adjusted for the high and low levels provided by the unit code value of the duty cycle calibration code can be changed, and thus, based on the fixed maximum data length of the duty cycle calibration code, a flexibly adjustable time adjustment ability can be provided. In this way, the driving ability of the forward clock transmission circuit is automatically calibrated, the two dimensions of frequency and duty cycle are decoupled, there is no need to add excessive loads on the clock path when transmitting high-speed clock signals, and a finer granularity at the output end and high-precision adjustment can also be achieved when transmitting low-speed clock signals. Moreover, there is no need to occupy a large amount of space to store the calibration code, which is beneficial to controlling the circuit scale and contributes to miniaturization, integration, and improvement of system stability.

[0051] The method and device provided in the embodiments of this application are based on the same inventive concept. Since the principles for the method and device to solve problems are similar, the embodiments, implementation manners, examples, or implementation modes of the method and the device can be referred to each other, and the repeated parts will not be elaborated here. The embodiments of this application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that the system can implement can refer to the specific implementation steps in the method embodiments above and / or the specific functions described in the device embodiments above, which will not be elaborated here.

[0052] The embodiments of the present application also provide a computer-readable storage medium, in which computer instructions are stored. When the computer instructions run on a computer device (such as one or more processors), the method steps in the above method embodiments can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be elaborated here.

[0053] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. The present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. The embodiments of the present application can be implemented in whole or in part by software, hardware, firmware, or any other arbitrary combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The present application can adopt the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line) or a wireless manner (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access, or a data storage device such as a server or a data center containing one or more collections of available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium, or a semiconductor medium. The semiconductor medium can be a solid-state drive, or a random access memory, a flash memory, a read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory, a register, or any other suitable storage medium in any other form.

[0054] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing device produce means for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks. These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including instruction means that implement the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks. These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks.

[0055] In the above embodiments, the descriptions of the various embodiments have their own emphases. For parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method embodiments of the present application can be adjusted, combined, or deleted according to actual needs; the modules in the system embodiments of the present application can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and modifications.

Claims

1. A duty cycle calibration circuit, characterized in that The duty cycle calibration circuit includes: A first branch, wherein the first branch includes a first inverter with adjustable pull-up and pull-down capabilities. The positive pole of the input differential clock signal is the input signal of the first inverter. The output signal of the first inverter is inverted and used as the positive pole of the output differential clock signal. The duty cycle calibration of the output signal of the first inverter relative to the duty cycle of the input signal of the first inverter is performed by a duty cycle calibration module. The pull-up and pull-down capabilities of the first inverter are adjusted by a range calibration code, and the duty cycle calibration module is configured by a duty cycle calibration code; A second branch, wherein the second branch includes a second inverter with adjustable pull-up and pull-down capabilities. The negative pole of the input differential clock signal is the input signal of the second inverter. The output signal of the second inverter is inverted and used as the negative pole of the output differential clock signal. The duty cycle calibration of the output signal of the second inverter relative to the duty cycle of the output signal of the second inverter is performed by the duty cycle calibration module. The pull-up and pull-down capabilities of the second inverter are adjusted by the range calibration code, The duty cycle calibration code has a fixed maximum data length. The duty cycle calibration code increases or decreases at least one unit code value within the adjustment range of the duty cycle calibration code according to the unit code value. The adjustment range of the duty cycle calibration code is determined based on the fixed maximum data length. The time values of the high and low level adjustments corresponding to the unit code value are determined based on the range calibration code, The range calibration code is automatically calibrated based on the frequency of the input differential clock signal.

2. The duty cycle calibration circuit according to claim 1, wherein The driving ability of the positive clock transmission circuit of the first branch is determined based on the pull-up and pull-down capabilities of the first inverter. The range calibration code is used to configure the driving ability of the positive clock transmission circuit of the first branch. The driving ability of the positive clock transmission circuit of the second branch is determined based on the pull-up and pull-down capabilities of the second inverter. The range calibration code is used to configure the driving ability of the positive clock transmission circuit of the second branch.

3. The duty cycle calibration circuit according to claim 1, wherein When the range calibration code increases, the time values of the high and low level adjustments corresponding to the unit code value decrease. When the range calibration code decreases, the time values of the high and low level adjustments corresponding to the unit code value increase. Also, when the frequency of the input differential clock signal decreases, the range calibration code decreases. When the frequency of the input differential clock signal increases, the range calibration code increases.

4. The duty cycle calibration circuit according to claim 1, wherein The adjustment range of the duty cycle calibration code is from -15 to +15, and the unit code value is 1.

5. The duty cycle calibration circuit according to claim 1, wherein The duty cycle calibration code has a fixed adjustment range. The range calibration code is automatically calibrated based on the frequency of the input differential clock signal so that the duty cycle calibration module, when configured by the duty cycle calibration code of the first code value, performs duty cycle calibration to make the duty cycle of the output differential clock signal 50%, where the first code value is within the adjustment range.

6. The duty cycle calibration circuit according to claim 1, wherein The duty cycle calibration code varies between a fixed minimum value and a fixed maximum value. The automatic calibration of the range calibration code includes: Configuring the range calibration code to an initial value. Then, when the duty cycle of the output differential clock signal is less than 50% when the duty cycle calibration code is a preset minimum value and greater than 50% when the duty cycle calibration code is a preset maximum value, gradually increase the range calibration code until, after the range calibration code is increased from a first value to a second value, the duty cycle of the output differential clock signal is less than 50% or greater than 50% both when the duty cycle calibration code is the preset minimum value and the preset maximum value. Select the first value as the value of the range calibration code after automatic calibration.

7. The duty cycle calibration circuit according to claim 6, wherein The fixed minimum value is less than the preset minimum value, the fixed maximum value is greater than the preset maximum value. The difference between the fixed minimum value and the preset minimum value and the difference between the fixed maximum value and the preset maximum value are based on a design margin and a circuit state deviation margin for accommodating process voltage temperature condition variations.

8. The duty cycle calibration circuit according to claim 1, wherein The duty cycle of the output differential clock signal is 50% after the duty cycle calibration by the duty cycle calibration module.

9. The duty cycle calibration circuit according to claim 1, wherein The range calibration code is determined based on the frequency of the input differential clock signal.

10. The duty cycle calibration circuit according to claim 1, characterized in that, The output differential clock signal output by the duty cycle calibration circuit is for a subsequent module of the duty cycle calibration circuit.

11. A duty cycle calibration method, characterized in that, The duty cycle calibration method includes: Providing a first branch of the duty cycle calibration circuit, where the first branch includes a first inverter with adjustable pull-up and pull-down capabilities. The positive pole of the input differential clock signal is the input signal of the first inverter. The output signal of the first inverter is inverted and used as the positive pole of the output differential clock signal. The duty cycle calibration of the output signal of the first inverter relative to the duty cycle of the input signal of the first inverter is performed by the duty cycle calibration module of the duty cycle calibration circuit; Providing a second branch of the duty cycle calibration circuit, where the second branch includes a second inverter with adjustable pull-up and pull-down capabilities. The negative pole of the input differential clock signal is the input signal of the second inverter. The output signal of the second inverter is inverted and used as the negative pole of the output differential clock signal. The duty cycle calibration of the output signal of the second inverter relative to the duty cycle of the output signal of the second inverter is performed by the duty cycle calibration module; Adjusting the pull-up and pull-down capabilities of the first inverter and the second inverter through the range calibration code, and configuring the duty cycle calibration module through the duty cycle calibration code. The duty cycle calibration code has a fixed maximum data length. The duty cycle calibration code increases or decreases at least one unit code value within the adjustment range of the duty cycle calibration code according to the unit code value. The adjustment range of the duty cycle calibration code is determined based on the fixed maximum data length. The time values of the high and low level adjustments corresponding to the unit code value are determined based on the range calibration code. The range calibration code is automatically calibrated based on the frequency of the input differential clock signal.

12. The duty cycle calibration method according to claim 11, wherein The driving capability of the positive clock transmission circuit of the first branch is determined based on the pull-up and pull-down capabilities of the first inverter, and the range calibration code is used to configure the driving capability of the positive clock transmission circuit of the first branch. The driving capability of the positive clock transmission circuit of the second branch is determined based on the pull-up and pull-down capabilities of the second inverter, and the range calibration code is used to configure the driving capability of the positive clock transmission circuit of the second branch.

Images