A burst-mode clock data recovery circuit and method for a baud rate sampling architecture

Abstract

The application belongs to the field of electronic technology and relates to a burst mode clock data recovery circuit and method of baud rate sampling structure. The clock data recovery circuit comprises a sampling comparator circuit, a polarity flip detection circuit, a Mueller-Muller phase detector, a phase control state machine and a phase interpolator circuit. The sampling comparator circuit samples an input signal and a threshold amplitude to obtain a decision data signal and samples the input signal and a reference amplitude to obtain a decision error signal. The polarity flip detection circuit receives the decision data signal and outputs a phase lock signal. The Mueller-Muller phase detector receives the decision data signal and the decision error signal and outputs a phase too early / too late signal. The phase control state machine receives the phase lock signal and the phase too early / too late signal, and outputs a phase control code to the phase interpolator circuit to adjust the phase of a sampling clock. The application reduces the clock data recovery from three times oversampling to baud rate sampling, thereby reducing the power consumption and area of the circuit.

Description

Technical Field

[0001] This invention belongs to the field of electronic technology, and particularly to the field of high-speed interface integrated circuits. It relates to a burst mode clock data recovery circuit and method with a baud rate sampling structure. Background Technology

[0002] In high-speed serial communication, the transmitting end only sends data signals and not the corresponding clock signal. Therefore, a clock data recovery circuit is needed to recover a sampling clock synchronized with the data at the receiving end, so that the sampling clock samples at the data center point with the highest signal-to-noise ratio, reducing the bit error rate. In burst mode applications, clock recovery must be completed within a short time to achieve rapid locking of burst data packets.

[0003] Existing methods for burst mode clock data recovery, such as Figure 1 As shown, the system comprises a sampling comparator circuit 101, an oversampling logic unit 102, a digital phase control module 103, and a phase interpolator circuit 104. The sampling comparator circuit 101 oversamples the input signal DIN and the threshold amplitude VTH by three times to obtain decision data signals DATA1, DATA2, and DATA3, with sampling clocks CK1, CK2, and CK3, respectively. The oversampling logic unit 102 receives the three decision data signals to obtain the sampling phase position information, which is then sent to the digital phase control module 103. This module generates three phase control codes (PICODE) to control the three phase interpolator circuits 104, thereby adjusting the three sampling clocks. The sampling clock phase is continuously adjusted through a feedback loop to achieve phase locking, thus completing the clock data recovery in burst mode.

[0004] However, existing technologies use a triple oversampling circuit to recover clock data, which increases the design difficulty of the receiver clock path and leads to increased receiver power consumption. Summary of the Invention

[0005] To simplify the design of the receiver clock path and reduce receiver power consumption, this invention proposes a burst mode clock data recovery circuit and method with a baud rate sampling structure.

[0006] The technical solution adopted in this invention is as follows:

[0007] A burst-mode clock data recovery circuit with a baud rate sampling structure includes a sampling comparator circuit, a polarity reversal detection circuit, a Mueller-Muller phase detector, a phase control state machine, and a phase interpolator circuit. The sampling comparator circuit samples the input signal DIN and a threshold amplitude VTH to obtain a decision data signal DATA, and samples the input signal DIN and a reference amplitude VREF to obtain a decision error signal ERROR. The input terminal of the polarity reversal detection circuit is connected to the decision data signal DATA, and the output terminal of the polarity reversal detection circuit is connected to the first input terminal of the phase control state machine. The two input terminals of the Mueller-Muller phase detector are respectively connected to the decision data signal DATA and the decision error signal ERROR, and the output terminal of the Mueller-Muller phase detector is connected to the second input terminal of the phase control state machine. The input terminal of the phase interpolator circuit is connected to the output terminal of the phase control state machine, and the output terminal of the phase interpolator circuit is connected to the sampling comparator circuit.

[0008] Furthermore, the sampling comparator circuit uses CK as the sampling clock for sampling the input signal DIN and the threshold amplitude VTH, and the sampling comparator circuit uses CK as the sampling clock for sampling the input signal DIN and the reference amplitude VREF; the polarity reversal detection circuit receives the decision data signal DATA and outputs the phase lock signal LOCKED; the Mueller-Muller phase detector receives the decision data signal DATA and the decision error signal ERROR and outputs the phase too early / too late signal EL; the phase control state machine receives the phase lock signal LOCKED and the phase too early / too late signal EL and outputs the phase control code PICODE to the phase interpolator circuit to adjust the phase of the sampling clock CK.

[0009] A burst-mode clock data recovery method using the baud rate sampling structure implemented with the above circuit is characterized by comprising the following steps:

[0010] The sampling comparator circuit samples the input signal DIN and the threshold amplitude VTH to obtain the decision data signal DATA, with the sampling clock being CK;

[0011] The sampling comparator circuit samples the input signal DIN and the reference amplitude VREF to obtain the decision error signal ERROR, with the sampling clock being CK;

[0012] The polarity reversal detection circuit receives the decision data signal DATA and outputs the phase lock signal LOCKED.

[0013] The Mueller-Muller phase detector receives the decision data signal DATA and the decision error signal ERROR, and outputs the phase too early / too late signal EL.

[0014] The phase control state machine receives the phase lock signal LOCKED and the phase too early / too late signal EL, and outputs the phase control code PICODE to the phase interpolator circuit to adjust the phase of the sampling clock CK.

[0015] Furthermore, during the rapid locking phase, the sampling phase is changed by a polarity reversal detection circuit and a phase control state machine to achieve rapid phase locking.

[0016] Furthermore, during the data reception phase, the sampling phase is changed through a Mueller-Muller phase detector and a phase control state machine to achieve continuous phase tracking.

[0017] Furthermore, after fast locking begins, the sampling phase is initialized and phase scanning begins until the polarity of the previous and current sampling decision data is different. At this point, it indicates that the sampling point is at the edge of the eye diagram. After the sampling phase moves by 1 / 2 UI, fast locking is completed, and the clock resumes and enters MMCDR mode.

[0018] A receiver comprising a burst-mode clock data recovery circuit of the baud rate sampling structure described above.

[0019] The beneficial effects of this invention are:

[0020] This invention proposes a burst-mode clock data recovery device and method with a baud rate sampling structure, which simplifies the design of the receiver clock path. Compared with existing technologies, this invention reduces clock data recovery from triple oversampling to baud rate sampling, thereby reducing circuit power consumption and area. Attached Figure Description

[0021] Figure 1 This is a method for recovering clock data in burst mode, based on existing technologies.

[0022] Figure 2 This invention proposes a method for recovering burst-mode clock data using a baud rate sampling structure.

[0023] Figure 3 This is a schematic diagram illustrating the burst mode clock data recovery principle of a baud rate sampling structure proposed in this invention.

[0024] Figure 4 A logic block diagram illustrating the clock data recovery process of this invention.

[0025] Explanation of key component symbols:

[0026] DIN: Input signal

[0027] VTH: Threshold amplitude

[0028] VREF: Reference Range

[0029] CK, CK1, CK2, CK3: Sampling clocks

[0030] DATA, DATA1, DATA2, DATA3: Decision data signals

[0031] ERROR: Decision Error Signal

[0032] D[0], D[k-1], D[k]: Decision signals

[0033] EL: Early / Late Phase Signal

[0034] LOCKED: Phase-locked signal

[0035] PICODE: Phase Control Code Detailed Implementation

[0036] The invention will be further described below with reference to the accompanying drawings.

[0037] This invention proposes a burst-mode clock data recovery circuit and method with a baud rate sampling structure, such as... Figure 2 As shown, the device comprises a sampling comparator circuit 201, a polarity reversal detection circuit 202, a Mueller-Muller phase detector 203, a phase control state machine 204, and a phase interpolator circuit 205. The sampling comparator circuit 201 samples the input signal DIN and the threshold amplitude VTH to obtain the decision data signal DATA, with a sampling clock of CK. It also samples the input signal DIN and the reference amplitude VREF to obtain the decision error signal ERROR, with a sampling clock of CK. The polarity reversal detection circuit 202 receives the decision data signal DATA and outputs the phase lock signal LOCKED. The Mueller-Muller phase detector 203 receives the decision data signal DATA and the decision error signal ERROR and outputs a phase too early / too late signal EL. The phase control state machine 204 receives the phase lock signal LOCKED and the phase too early / too late signal EL and outputs a phase control code PICODE to the phase interpolator circuit 205 to adjust the phase of the sampling clock CK. During the fast locking phase, the sampling phase is changed by the polarity reversal detection circuit 202 and the phase control state machine 204 to achieve fast phase locking. During the data reception phase, the sampling phase is changed by the Mueller-Muller phase detector 203 and the phase control state machine 204 to achieve continuous phase tracking.

[0038] Figure 3This is a schematic diagram illustrating the principle of a burst mode clock data recovery method based on a baud rate sampling structure proposed in this invention. In burst mode, the receiver receives a preamble consisting of alternating 0s and 1s, which is equivalent to a clock signal at half the baud rate. For sample 301, fast locking begins, and the sampling phase is initialized. At this time, the data obtained from the sampling decision is D[0]. Phase scanning begins, with the phase increasing in steps of a certain size. For sample 302, the data obtained from the current sampling decision is D[k], and the data obtained from the previous sampling decision is D[k-1]. A reversal of the polarity of the sampling decision data is detected, indicating that the sampling point is at the edge of the eye diagram. The sampling phase is shifted by 1 / 2UI (UI is the Unit Interval). For sample 303, the sampling point is now at the center of the eye diagram, and fast locking ends. For sample 304, the receiver begins receiving the load signal. At this time, the sampling point is located at the center of the eye diagram, and the sampling phase is controlled by the Mueller-Muller phase detector.

[0039] Figure 4 The following is a logic block diagram illustrating the clock data recovery process of this invention. After fast locking begins, the sampling phase is initialized, and phase scanning begins until the polarity of the previous and current sampling decision data is different. At this point, the sampling point is located at the edge of the eye diagram. After the sampling phase shifts by 1 / 2 UI, fast locking is completed, and clock recovery enters MMCDR mode. Here, MMCDR stands for Mueller-Muller Clock Data Recovery, and the clock sampling phase is controlled by the Mueller-Muller phase detector.

[0040] contrast Figure 2 and Figure 1 It can be noted that the burst mode clock data recovery method proposed in this invention requires a lower sampling rate than existing technical solutions. This invention only requires baud rate sampling to achieve fast locking, while existing solutions require three times oversampling. Therefore, a beneficial effect of this invention is reduced receiver power consumption.

[0041] On the other hand, the burst mode clock data recovery method proposed in this invention does not require additional sampling circuitry; it achieves fast clock data recovery solely by reusing existing baud rate sampling circuitry. A fast locking mode is introduced based on the MMCDR loop, accelerating the loop locking speed.

[0042] Furthermore, in the method proposed in this invention, the preamble can be an alternating preamble of 0 and 1, or it can be extended to more types of preambles, such as alternating 00 and 11, alternating 000 and 111, etc.

[0043] The specific embodiments of the present invention disclosed above are intended to help understand the content of the present invention and to implement it accordingly. Those skilled in the art will understand that various substitutions, changes, and modifications are possible without departing from the spirit and scope of the present invention. The present invention should not be limited to the content disclosed in the embodiments of this specification; the scope of protection of the present invention is defined by the claims.

Claims

1. A burst-mode clock data recovery circuit with a baud rate sampling structure, characterized in that, The system includes a sampling comparator circuit, a polarity reversal detection circuit, a Mueller-Muller phase detector, a phase control state machine, and a phase interpolator circuit. The sampling comparator circuit samples the input signal DIN and the threshold amplitude VTH to obtain the decision data signal DATA, and samples the input signal DIN and the reference amplitude VREF to obtain the decision error signal ERROR. The input of the polarity reversal detection circuit is connected to the decision data signal DATA, and its output is connected to the first input of the phase control state machine. The two inputs of the Mueller-Muller phase detector are connected to the decision data signal DATA and the decision error signal ERROR, respectively, and its output is connected to the second input of the phase control state machine. The phase interpolator... The input of the circuit is connected to the output of the phase control state machine, and the output of the phase interpolator circuit is connected to the sampling comparator circuit. The sampling clock of the sampling comparator circuit for sampling the input signal DIN and the threshold amplitude VTH is CK. The sampling clock of the sampling comparator circuit for sampling the input signal DIN and the reference amplitude VREF is CK. The polarity reversal detection circuit receives the decision data signal DATA and outputs the phase lock signal LOCKED. The Mueller-Muller phase detector receives the decision data signal DATA and the decision error signal ERROR and outputs the phase too early / too late signal EL. The phase control state machine receives the phase lock signal LOCKED and the phase too early / too late signal EL and outputs the phase control code PICODE to the phase interpolator circuit to adjust the phase of the sampling clock CK. During the fast lock phase, the sampling phase is changed by the polarity reversal detection circuit and the phase control state machine to achieve fast phase lock. After the fast lock starts, the sampling phase is initialized and the phase scan begins. The sampling phase is shifted by 1 / 2UI until the polarity of the previous and current sampling decision data is different. Then the fast lock is completed and the clock is restored to enter MMCDR mode.

2. A method for recovering burst-mode clock data using a baud rate sampling structure, implemented using the burst-mode clock data recovery circuit of the baud rate sampling structure described in claim 1, characterized in that, The method includes the following steps: The sampling comparator circuit samples the input signal DIN and the threshold amplitude VTH to obtain the decision data signal DATA, with the sampling clock being CK; The sampling comparator circuit samples the input signal DIN and the reference amplitude VREF to obtain the decision error signal ERROR, with the sampling clock being CK; The polarity reversal detection circuit receives the decision data signal DATA and outputs the phase lock signal LOCKED. The Mueller-Muller phase detector receives the decision data signal DATA and the decision error signal ERROR, and outputs the phase too early / too late signal EL. The phase control state machine receives the phase lock signal LOCKED and the phase too early / too late signal EL, and outputs the phase control code PICODE to the phase interpolator circuit to adjust the phase of the sampling clock CK.

3. The method according to claim 2, characterized in that, During the data reception phase, the sampling phase is changed by a Mueller-Muller phase detector and a phase control state machine to achieve continuous phase tracking.

4. A receiver, characterized in that, The burst mode clock data recovery circuit includes the baud rate sampling structure described in claim 1.

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