Memory device and memory system for performing resistor offset calibration training

Abstract

According to one aspect of the present disclosure, a peripheral circuit is provided. The peripheral circuit may include a DQ circuit that includes a plurality of decision feedback equalization (DFE) components. The peripheral circuit may include a resistor offset calibration (RXOC) circuit. The RXOC circuit may include an oscillator. The oscillator may generate an internal clock source. The RXOC circuit may include a DQ selection component. The DQ selection component may select a DFE component of the plurality of DFE components for calibration. The DQ selection component may output a limiter result signal indicative of an offset value received from the DFE component. The RXOC circuit may include control logic. The control logic may transmit a calibration signal associated with the DFE component to the DQ circuit based on the limiter result signal.

Description

BACKGROUND OF THE DISCLOSURE

[0001] The present disclosure relates to a memory device and an operation method thereof.

[0002] Offset calibration training for adjusting DQ resistor offset calibration (RXOC) training can be performed during power-on and initialization training sequences to cope with static-dynamic random access memory (SDRAM) condition changes. SUMMARY OF THE DISCLOSURE

[0003] According to one aspect of the present disclosure, a peripheral circuit is provided. The peripheral circuit may include a DQ circuit including a plurality of decision feedback equalization (DFE) components. The peripheral circuit may include a resistor offset calibration (RXOC) circuit. The RXOC circuit may include an oscillator configured to generate an internal clock source. The RXOC circuit may include a DQ selection component configured to select a DFE component among the plurality of DFE components for calibration. The DQ selection component may be configured to output a limiter result signal indicating an offset value received from the DFE component. The RXOC circuit may include control logic configured to send a calibration signal associated with the DFE component to the DQ circuit based on the limiter result signal.

[0004] In some embodiments, the DQ selection component may include a first multiplexer (MUX) and a second MUX. In some embodiments, the first MUX is configured to select the DQ circuit. In some embodiments, the second MUX is configured to select the DFE component of the DQ circuit.

[0005] In some embodiments, the control logic may also be configured to receive the limiter result signal at a first edge of a clock cycle associated with the internal clock source.

[0006] In some embodiments, the control logic may also be configured to perform a binary search based on the limiter result signal to identify a pull-up code or a pull-down code for the DFE component.

[0007] In some embodiments, the control logic may also be configured to send the calibration signal to the DQ circuit at a second edge of a clock cycle associated with the internal clock source. In some embodiments, the first edge may be one of a rising edge or a falling edge. In some embodiments, the second edge may be the other of the rising edge or the falling edge. In some embodiments, the calibration signal may include a pull-up code or a pull-down code.

[0008] In some embodiments, the DQ circuit may also be configured to calibrate the DFE component based on the pull-up code or the pull-down code included in the calibration signal received from the control logic at the second edge of the clock cycle.

[0009] In some embodiments, the oscillator may also be configured to receive an RXOC participation signal. In some embodiments, an internal clock source may be generated in response to receiving an RXOC participation command.

[0010] In some embodiments, the oscillator may be enabled to generate an internal clock source without a column address strobe (CAS) command.

[0011] According to another aspect of the present disclosure, a memory device is provided. The memory device may include a memory array and a peripheral circuit coupled to the memory array. The peripheral circuit may include a DQ circuit that includes a plurality of DFE components. The peripheral circuit may include an RXOC circuit. The RXOC circuit may include an oscillator. The oscillator may be configured to generate an internal clock source. The RXOC circuit may include a DQ selection component. The DQ selection component may be configured to select a DFE component among the plurality of DFE components for calibration. The DQ selection component may be configured to output a limiter result signal indicative of an offset value received from the DFE component. The RXOC circuit may include control logic. The control logic may be configured to send a calibration signal associated with the DFE component to the DQ circuit based on the limiter result signal.

[0012] In some embodiments, the DQ selection component may include a first MUX and a second MUX. In some embodiments, the first MUX is configured to select the DQ circuit. In some embodiments, the second MUX is configured to select the DFE component of the DQ circuit.

[0013] In some embodiments, the control logic may also be configured to receive the limiter result signal at a first edge of a clock cycle associated with the internal clock source.

[0014] In some embodiments, the control logic may also be configured to perform a binary search based on the limiter result signal to identify a pull-up code or a pull-down code for the DFE component.

[0015] In some embodiments, the control logic may also be configured to send the calibration signal to the DQ circuit at a second edge of a clock cycle associated with the internal clock source. In some embodiments, the first edge may be one of a rising edge or a falling edge. In some embodiments, the second edge may be the other of a rising edge or a falling edge. In some embodiments, the calibration signal may include a pull-up code or a pull-down code.

[0016] In some embodiments, the DQ circuit may also be configured to calibrate the DFE component based on the pull-up code or the pull-down code included in the calibration signal received from the control logic at the second edge of the clock cycle.

[0017] In some embodiments, the oscillator may also be configured to receive an RXOC participation signal. In some embodiments, an internal clock source may be generated in response to receiving an RXOC participation command.

[0018] In some embodiments, the oscillator may be enabled to generate an internal clock source without a CAS command.

[0019] According to another aspect of the present disclosure, a method for RXOC by a peripheral circuit is provided. The method may include generating an internal clock source by an oscillator of an RXOC circuit. The method may include selecting a DFE component from a plurality of DFE components of a DQ circuit by a DQ selection component of the RXOC circuit for calibration. The method may include outputting a limiter result signal indicating an offset value received from the DFE component by the DQ selection component of the RXOC circuit. The method may include sending a calibration signal associated with the DFE component to the DQ circuit by control logic of the RXOC circuit based on the limiter result signal.

[0020] In some embodiments, the DQ selection component may include a first MUX and a second MUX. In some embodiments, the first MUX may be configured to select a DQ circuit. In some embodiments, the second MUX may be configured to select a DFE component of the DQ circuit.

[0021] In some embodiments, the method may include receiving the limiter result signal by control logic of the RXOC circuit at a first edge of a clock cycle associated with the internal clock source.

[0022] In some embodiments, the method may include performing a binary search by control logic of the RXOC circuit based on the limiter result signal to identify a pull-up code or a pull-down code for the DFE component.

[0023] In some embodiments, the method may include sending the calibration signal to the DQ circuit by control logic of the RXOC circuit at a second edge of a clock cycle associated with the internal clock source. In some embodiments, the first edge may be one of a rising edge or a falling edge. In some embodiments, the second edge may be the other of a rising edge or a falling edge. In some embodiments, the calibration signal may include a pull-up code or a pull-down code.

[0024] In some embodiments, the method may include calibrating the DFE component by the DQ circuit of the RXOC circuit based on the pull-up code or the pull-down code included in the calibration signal received from the control logic at the second edge of the clock cycle.

[0025] In some embodiments, the method may include receiving an RXOC participation signal by an oscillator of the RXOC circuit. In some embodiments, an internal clock source may be generated in response to receiving an RXOC participation command.

[0026] In some embodiments, the oscillator may be enabled to generate an internal clock source without a CAS command.

[0027] According to another aspect of the present disclosure, a memory system is provided. The memory system may include a memory array and a peripheral circuit. The peripheral circuit may include a DQ circuit, and the DQ circuit may include a plurality of DFE components. The peripheral circuit may include an RXOC circuit. The RXOC circuit may include an oscillator. The oscillator may be configured to generate an internal clock source. The RXOC circuit may include a DQ selection component. The DQ selection component may be configured to select a DFE component among the plurality of DFE components for calibration. The DQ selection component may be configured to identify an offset value associated with the DFE component. The DQ selection component may be configured to output a limiter result signal received from the DFE component based on the offset value. The RXOC circuit may include control logic. The control logic may be configured to send a calibration signal associated with the DFE component to the DQ circuit based on the limiter result signal.

[0028] In some embodiments, the DQ selection component may include a first MUX and a second MUX. In some embodiments, the first MUX is configured to select the DQ circuit. In some embodiments, the second MUX is configured to select a DFE component of the DQ circuit.

[0029] In some embodiments, the control logic may further be configured to receive the limiter result signal at a first edge of a clock cycle associated with the internal clock source.

[0030] In some embodiments, the control logic may further be configured to perform a binary search based on the limiter result signal to identify a pull-up code or a pull-down code for the DFE component.

[0031] In some embodiments, the control logic may further be configured to send the calibration signal to the DQ circuit at a second edge of a clock cycle associated with the internal clock source. In some embodiments, the first edge may be one of a rising edge or a falling edge. In some embodiments, the second edge may be the other of a rising edge or a falling edge. In some embodiments, the calibration signal may include a pull-up code or a pull-down code.

[0032] In some embodiments, the DQ circuit may further be configured to calibrate the DFE component based on the pull-up code or the pull-down code included in the calibration signal received from the control logic at the second edge of the clock cycle.

[0033] In some embodiments, the oscillator may also be configured to receive an RXOC participation signal. In some embodiments, an internal clock source may be generated in response to receiving an RXOC participation command.

[0034] In some embodiments, the oscillator may be enabled to generate an internal clock source without a CAS command. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings incorporated herein and forming a part of the specification illustrate aspects of the present disclosure, and together with the description further serve to explain the principles of the present disclosure and enable one of ordinary skill in the art to practice and use the present disclosure.

[0036] Figure 1 A schematic circuit diagram showing a memory device including a peripheral circuit and a memory cell array in accordance with some aspects of the present disclosure.

[0037] Figure 2 A block diagram showing a memory system including a memory array coupled to an example resistor offset calibration (RXOC) component and control logic in accordance with some aspects of the present disclosure.

[0038] Figure 3 A signal timing diagram showing an example RXOC process.

[0039] Figure 4 A detailed block diagram showing an example peripheral circuit including an RXOC circuit and a plurality of DQ circuits in accordance with some aspects of the present disclosure.

[0040] Figure 5 A block diagram showing an example DQ circuit in accordance with some aspects of the present disclosure.

[0041] Figure 6 Showing in accordance with some aspects of the present disclosure Figure 5 A diagram of a DFE component of the example DQ circuit shown in

[0042] Figure 7 A first example signal timing diagram for an example RXOC process in accordance with some aspects of the present disclosure.

[0043] Figure 8 A flowchart showing a first method of an RXOC process in accordance with some aspects of the present disclosure.

[0044] Figure 9 A second example signal timing diagram for an example RXOC process in accordance with some aspects of the present disclosure.

[0045] Figure 10 A flowchart showing a second method of an RXOC process in accordance with some aspects of the present disclosure.

[0046] Figure 11 A block diagram of a system including a memory system in accordance with some aspects of the present disclosure is shown.

[0047] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0048] Generally, terms may be understood, at least in part, in light of their usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," or "the" can also be understood to convey a singular usage or to convey a plural usage. Additionally, the term "based on" can be understood to not necessarily be intended to convey a set of exclusive factors and can alternatively allow for the presence of additional factors that are not necessarily expressly described, again depending at least in part on the context.

[0049] Figure 1 A schematic diagram of a memory device 100 including a peripheral circuit 102 and a memory cell array 101 in accordance with some aspects of the present disclosure is shown. In some embodiments as shown in Figure 1 each memory cell 103 may include a transistor 105 and a capacitor 107. The gate of the transistor 105 may be coupled to a word line 104, one of the source and drain of the transistor 105 may be coupled to a bit line 106, the other of the source and drain of the transistor 105 may be coupled to one electrode of the capacitor 107, and the other electrode of the capacitor 107 may be coupled to ground. Additional details of the memory device are provided below in connection with FIG. 12.

[0050] Referring to Figure 2 , a schematic circuit diagram of an example memory device 200 including a peripheral circuit in accordance with some aspects of the present disclosure is shown. As described above, the peripheral circuit may be coupled to at least two memory cell arrays and may include any suitable circuitry for facilitating the operation of the at least two memory cell arrays by applying voltage signals and / or current signals to each target memory cell of the at least two memory cell arrays and sensing voltage signals and / or current signals from each target memory cell of the at least two memory cell arrays. The peripheral circuit may include various types of peripheral circuits formed using CMOS technology, such as RXOC circuits.

[0051] For example, Figure 2FIG. 200 shows a memory device that includes a memory cell array 201 having one or more banks, and various example peripheral circuits, including control logic 202, a command (CMD) decoder 204, RXOC control logic 206, a register 208, an RXOC circuit 210, an address (ADD) register 212, a WL driver 214 (also referred to as a row decoder), bank control logic 216, a BL driver 218 (also referred to as a row decoder), a column decoder 220, a data I / O buffer 222, a DQ circuit 224, and an interface 226. It should be understood that in some examples, additional peripheral circuits may also be included.

[0052] The WL driver 214 may be configured to be controlled by the control logic 202 and select a bank of the memory cell array 201 and word lines of the selected bank. The WL driver 214 may also be configured to drive the memory cell array 201. For example, the WL driver 214 may use word line voltages generated from a voltage generator (not shown) to drive NAND memory cells and / or DFM cells of the memory cell array 201 coupled to the selected word lines.

[0053] The BL driver 218 may be configured to be controlled by the control logic 202 and select one or more 3D NAND memory strings and / or one or more 3D DFM cells of the memory cell array 201 by applying bit line voltages generated from a voltage generator (not shown). For example, the BL driver 218 may apply column signals to select an N-bit data set to be output in a read operation from a page buffer (not shown).

[0054] The control logic 202 may be coupled to each of the plurality of peripheral circuits and configured to control the operation of the plurality of peripheral circuits. The register 208 may be coupled to the control logic 202 and include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0055] The command decoder 204 may decode an input command signal to identify a corresponding command operation. An indication of the command operation may be sent to the register 208, which may identify an associated OP code and / or command address. The OP code and / or command address may be identified by comparing the identified command operation with a look-up table of OP codes and / or command addresses.

[0056] Interface 226 can be coupled to control logic 202 and is configured to interface the memory cell array 201 with one or more memory controllers (not shown). In some embodiments, interface 226 acts as a control buffer to buffer and relay control commands received from one or more memory controllers and / or a host (not shown) to control logic 202, and to buffer and relay status information received from control logic 202 to the memory controller and / or the host. Interface 226 can also be coupled to a page buffer (not shown) and a BL driver 218 via a data bus (not shown), and acts as an I / O interface and a data buffer to buffer and relay programming data received from one or more memory controllers and / or a host to the page buffer, and to buffer and relay read data from the page buffer to one or more memory controllers and / or the host. In some embodiments, interface 226 and the data bus (not shown) are part of the I / O circuitry of the peripheral circuit.

[0057] A voltage generator (not shown) can be configured to be controlled by control logic 202 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, and verify voltage) and bit line voltages to be provided to the memory cell array 201. In some embodiments, the voltage generator is part of a voltage source that provides various levels of voltage for different peripheral circuits, as described in detail below. Consistent with the scope of the present disclosure, in some embodiments, the voltages provided by the voltage generator to, for example, WL driver 214 and BL driver 218 are higher than certain levels sufficient to perform memory operations. For example, the voltage provided to the logic circuits in control logic 202 can be between 1.3V and 5V (e.g., 3.3V), and the voltages provided to the driver circuits in WL driver 214 and BL driver 218 can be between 5V and 30V.

[0058] The RXOC circuit 210 can be coupled to control logic 202 and includes an oscillator (see Figure 4 ), a DQ selection component (see Figure 4 ), and RXOC control logic 206. In some embodiments, RXOC control logic 206 can be part of control logic 202. In some other embodiments, RXOC control logic 206 can be separate from control logic 202. The oscillator can be configured to generate an internal clock source for, for example, RXOC control logic 206, the DQ selection component (see Figure 4 ), and the DQ circuit 224 (see Figure 5 ) (to name a few). By setting the internal clock source for RXOC control logic 206, the DQ selection component, and the DQ circuit 224, synchronous calibration of the peripheral circuit can be achieved.

[0059] RXOC training involves calculating the resistance of the DQ circuit, e.g., determining how many transistors are on or off. For example, a clock source is used to time the operations performed by the RXOC control logic and the DQ selection component. Conventional RXOC uses a full-rate write clock (WCK) as the clock source. To perform RXOC using the full-rate write clock, an additional column address strobe (CAS) command (CMD) (CAS CMD) is required before training can begin. Alternatively, a WCK-to-clock (WCK2CK) synchronization state from a previous operation is required. However, due to the undesirably large WCK frequency range (e.g., from 3200 MHz to 20 MHz), various challenges arise in designing the RXOC circuit. In Figure 3 the signal timing diagram 300 of

[0060] shows these drawbacks of the existing RXOC process. Figure 3 Referring to

[0061] To address one or more of the above problems, the present disclosure provides example full-synchronous RXOC training strategies. For example, an example internal clock source is provided in the RXOC circuit to synchronize the timing of the DFE selection component and the RXOC control logic. In other words, the example RXOC circuits described herein include an oscillator (e.g., an internal clock source), RXOC control logic, and a DFE selection component (e.g., one or more multiplexers (MUX)). The DFE selection component selects a DFE component from a plurality of DFE components (e.g., DQ circuits) of the RXOC circuit. Then, the DFE selection component selects a slicer offset result from a plurality of slicer offset results of the selected DFE component. The RXOC control logic implements a binary search for RXOC calibration. By including a local oscillator in the RXOC circuit, the use of CAS commands and / or the synchronization state from a previous operation is eliminated. In addition, using the local oscillator to synchronize the operations of the DFE selection component and the RXOC control logic reduces the silicon footprint of the RXOC circuit and improves the stability of calibration, while simplifying the operation of the RXOC control logic. The following describes in conjunction with Figure 4-1 2 provides additional details of the example RXOC circuit.

[0062] Figure 4 FIG. 400 is a detailed block diagram of an example peripheral circuit including an RXOC circuit and a plurality of DQ circuits in accordance with some aspects of the present disclosure. Figure 5 FIG. 500 is a block diagram of an example DQ circuit 502 in accordance with some aspects of the present disclosure. Figure 6 FIG. Figure 5 600 is a diagram of a DFE component 504 of the example DQ circuit 502 shown in Figure 7 FIG. 700 is a first example signal timing diagram of an example RXOC process for calibrating a DQ circuit in accordance with some aspects of the present disclosure. Figure 8 FIG. 800 is a flowchart of a first method 800 of an RXOC process in accordance with some aspects of the present disclosure. Figure 9 FIG. 900 is a second example signal timing diagram for an example RXOC process in accordance with some aspects of the present disclosure. FIGS. Figure 4 、 5 and 8 will be described together.

[0063] Referring to Figure 4 , the RXOC circuit may include, for example, an RXOC oscillator 404 (hereinafter referred to as "oscillator 404") and RXOC control logic 408. The plurality of DQ circuits may be included in a DFE block 406. By way of example and not limitation, the DQ circuit 224 in Figure 2 may correspond to Figure 4The DFE block 406) therein is shown as having four DQ circuits (e.g., DQ0, DQ1, DQ2, DQ3) and one RDQS circuit. However, without departing from the scope of the present disclosure, the DFE block 406 may include more or fewer than four DQ circuits and more or fewer than one RDQS circuit. The DFE selection component 410 may include a first MUX (e.g., the leftmost MUX) configured to select a DQ circuit of the DFE block 406 for calibration. Additionally, the DFE selection component 410 may include a second MUX (e.g., the rightmost MUX) configured to select a DFE of the DQ circuit selected by the first MUX for calibration. In Figure 4 , the DQ signals input to the DFE block 406 may be I / O data through the DQ pins of the memory device. For example, the DQ signals may be transmitted from the memory controller through the I / O buffer and then into the memory device. During RXOC calibration, in Figure 4 The ports shown on the left for the DQ signals and Vref DQ may be shorted.

[0064] Referring to Figure 4 and 8 , the RXOC operation may start (at 802) upon receipt of an RXOC-start (RXOC_en) signal. Once the RXOC_en signal is received, the oscillator 404 may generate (at 804) an internal clock source (osc_ck) having a predetermined frequency and send the internal clock source to the DFE block 406 and the RXOC control logic 408 to synchronize their respective operations. In the following example, it is assumed that the RXOC process is performed in the order of DQ0, DQ1, DQ2, DQ3, and RDQS, and each of these DQ circuits includes four DFE components.

[0065] For example, referring to Figure 4 , 5 and 8, the RXOC control logic 408 may perform (at 806) an RXOC process to calibrate the first DFE component 504a of the DQ circuit 502 (e.g., DQ0). Figure 5 Additional details of the DQ circuit 502 are shown in Figure 6 while additional details of the first DFE component 504a (which may be the same or similar in structure to other DFE components) are shown in

[0066] Referring to Figure 4 and 5, To perform the RXOC process, the first MUX can select DQ0 and the second MUX can select the first DFE component 504a of DQ0 for calibration. In some embodiments, the RXOC control logic 408 can send a DQ selection (dq_sel) signal to the first MUX and a slicer selection (slicer_sel) signal to the second MUX. The dq_sel signal can indicate which DQ circuit (e.g., DQ0, DQ1, DQ2, DQ3, RDQS, etc.) of the DFE block 406 is selected for calibration. The slicer_sel signal can indicate which DFE component (e.g., the first DFE component 504a, the second DFE component 504b, the third DFE component 504c, or the fourth DFE component 504d) of the selected DQ circuit is selected for calibration. Each DFE component can identify a slicer result signal, which is sent to the first MUX. The first MUX can output the slicer result signal from the DFE component of the selected DQ circuit. In this example, the first MUX can output the slicer result signal from the DFE component of DQ0. The second MUX can output a slicer result signal indicating an offset value (e.g., a resistance offset value, a voltage offset value, a current offset value, etc.) associated with the selected DFE component of DQ0. The RXOC control logic 408 can receive the slicer result signal at the rising or falling edge of the first clock cycle.

[0067] The RXOC control logic 408 can perform a binary search based on the slicer result (e.g., the offset value) to identify the pull-up code or pull-down code for the selected DFE component. The pull-up code or pull-down code can be used to calibrate the selected DFE component, e.g., i.e., how many MOSFETs are turned on or off (see Figure 6 ). For example, referring to Figure 6 , using the pull-up code or pull-down code to calibrate the selected DFE component can minimize the current difference between the left dashed box and the right dashed box. To perform the binary search, the RXOC control logic 408 can identify a target code, e.g., 0101. Using the non-limiting example target code 0101, the RXOC control logic can determine minus by comparing 0101 with 1000. Then, the RXOC control logic 408 can determine plus by comparing 0101 with 0100. Next, the RXOC control logic 408 can determine minus by comparing 0101 with 0110. Finally, the RXOC control logic can determine that the binary search is complete by comparing 0101 with 0101. Additional details of the binary search performed by the RXOC control logic 408 are described below in connection with Figure 4 and 9 .

[0068] For example, referring to Figure 4 and9 , the RXOC control logic 408 sets all RXOC codes to 0. Then, the RXOC control logic 408 sets all pull-up codes and pull-down codes to 0. Based on the limiter result signal received from the DQ selection component, the RXOC control logic 408 can determine how to change the pull-up code. Then, at the rising edge of the clock cycle, the RXOC control logic 408 can set the pull-up code to 1000. At the falling edge of the clock cycle, the RXOC control logic can perform a limiter operation. Then, the RXOC control logic 408 can perform a code decision to determine whether to hold the code as 1 or set it to 0. This can be performed for each bit in the code (e.g., two bits, three bits, four bits, etc.). This loop is executed until all four bits have been decided for the limiter result signal. Then, the calibration code (e.g., pull-up code or pull-down code) can be sent to the selected DFE component / DQ circuit. The following combines Figure 7 describes additional details of the calibration process.

[0069] Refer to Figure 7 , five clock pulses generated by the oscillator 404 are associated with the calibration of a DFE component. The first clock pulse can be used to indicate Figure 6 whether the transistors in the left dashed box or the right dashed box shown in Figure 4 are being calibrated. Then, each subsequent clock pulse can be associated with the calibration of one bit of the pull-up code or the pull-down code. For example, referring to 6 and 7, at the first clock pulse, the RXOC control logic 408 can indicate Figure 6 whether the transistors in the left dashed box or the right dashed box in

[0070] are being calibrated. At the second clock pulse, the RXOC control logic 408 can calibrate the first bit of the pull-up code or the pull-down code (e.g., corresponding to the dashed box indicated at the first pulse). At the third clock pulse, the RXOC control logic 408 can calibrate the second bit of the pull-up code or the pull-down code. At the fourth clock pulse, the RXOC control logic 408 can calibrate the third bit of the pull-up code or the pull-down code. Finally, at the fifth clock pulse, the RXOC control logic 408 can calibrate the fourth bit of the pull-up code or the pull-down code. Figure 4, the RXOC control logic 408 can generate a calibration signal including a pull-up code or a pull-down code to DQ0. The calibration signal can be sent to DQ0 at the rising edge or the falling edge of the first clock cycle. For example, if the limiter result signal is received at the rising edge of the first clock cycle, the calibration signal can be sent at the falling edge of the first clock cycle. Conversely, if the limiter result signal is received at the falling edge of the first clock cycle, the calibration signal can be sent at the rising edge of the first clock cycle. Each DFE component can calibrate multiple bits, for example, four bits; and each pulse of the clock cycle can be used to calibrate one bit.

[0071] Referring again to Figure 4 , 5 and 8, the RXOC control logic 408 can determine (at 808) whether the fourth DFE component 504d of DQ0 was calibrated in a previous operation (e.g., 806). If it is "no" at 808, the operation can return to 806, where the RXOC control logic 408 performs the above process for calibrating, for example, the second DFE component 504b of DQ0. Conversely, if it is "yes" at 808, the operation can move to 810, where the RXOC control logic 408 can perform (at 810) the RXOC process for DQ1. That is, operation 810 can include calibrating each of the four DFE components of DQ1. Once DQ1 is calibrated, the RXOC control logic 408 can determine (at 812) whether all five DQ circuits (e.g., DQ0, DQ1, DQ2, DQ3, and RDQS) are calibrated. If it is "no" at 812, the operation can return to 806, where the above RXOC process is performed for the next DQ circuit and / or the next DFE component of the same or different DQ circuits. Conversely, if it is "yes" at 812, the RXOC process of the DFE block 406 can end (at 814). Additional details of the operations provided in conjunction with Figure 4 , 5 and 9 are provided Figure 8 below.

[0072] Referring to Figure 4 , 5 and 9, in a non-limiting example, the DQ circuit can include five DQs, and each DQ can include four limiters (e.g., DFE components). As described above, Figure 5 and 9 The timing diagrams shown in are associated with the calibration of four bits of the pull-up code or the pull-down code. Referring to Figure 9 , at the rising edge of the stm_ck cycle (e.g., generated by the oscillator 404), the RXOC control logic 406 outputs a calibration code according to the slicer_result of the four-bit calibration. In the DFE loop, there are five clock pulses (e.g.,Figure 9 The dashed line in [ ] indicates the position of the rising edge), and the first clock pulse selects os. For example, that is, Figure 6 the left dashed box or the right dashed box in [ ]. At the first rising edge of the first clock pulse, os_sel_out outputs a high-level signal (set to 1). Still referring to Figure 9 , rxoc_out[0] - rxoc_out[3] represent the calibration results output by performing the above-mentioned binary search according to the slicer_result of each bit. In Figure 9 the non-limiting example shown in [ ], rxoc_out[3] rises to a high level (set to 1) at the rising edge of the first clock pulse and remains at a high level (remains 1) at the rising edge of the second clock pulse. At the rising edge of the second clock pulse, rxoc_out[2] rises to a high level (set to 1) and drops to a low level (set to 0) at the rising edge of the third clock pulse. At the rising edge of the third clock pulse, rxoc_out[1] rises to a high level (set to 1) and remains at a high level (remains 1) at the rising edge of the fourth clock pulse. At the rising edge of the fourth clock pulse, rxoc_out[0] rises to a high level (set to 1) and drops to a low level (set to 0) at the rising edge of the fifth pulse. It should be understood that the example target code 0101 and the calibrated target code 1010 are provided herein by way of example and not limitation. Other target codes and calibrated target codes may be used and / or implemented without departing from the scope of the present disclosure.

[0073] Figure 10 FIG. [ ] shows a flowchart of a method 1000 for operating a memory device including a peripheral circuit according to some aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein, such as the memory device 100. The method 1000 may be implemented by a peripheral circuit including an RXOC circuit and a DQ circuit. The internal circuit of the peripheral circuit may include, for example, one or more of the following: an oscillator 404, a DFE block 406, one or more DQ circuits in the DQ circuit of the DFE block 406, one or more DFE components of the DQ circuit, an RXOC control logic 408, and / or a DQ selection component 410. It should be understood that the operations shown in the method 1000 may not be exhaustive, and other operations may also be performed before, after, or between any of the shown operations. In addition, some operations may be performed simultaneously or in a different order than Figure 10 shown.

[0074] Referring to Figure 10 , at 1002, the oscillator of the RXOC circuit may generate an internal clock source. For example, referring to Figure 4, once the RXOC_en signal is received from outside the RXOC circuit, the oscillator 404 can generate (at 804) an internal clock source (osc_ck) with a predetermined frequency and send the internal clock source to the DFE block 406 and the RXOC control logic 408 to synchronize their respective operations.

[0075] At 1004, the DQ selection component of the RXOC circuit can select a DFE component from multiple DFE components of the DQ circuit for calibration. For example, refer to Figure 4 , to perform the RXOC process, the first MUX can select DQ0 and the second MUX can select the first DFE component 504a of DQ0 for calibration. In some embodiments, the RXOC control logic 408 can send a DQ selection (dq_sel) signal to the first MUX and a slicer selection (slicer_sel) signal to the second MUX.

[0076] At 1006, the DQ selection component of the RXOC circuit can output a slicer result signal indicating an offset value received from the DFE component. For example, refer to Figure 4 , in the above example, the first MUX can output the slicer result signal from the DFE component of DQ0. The second MUX can output a slicer result signal indicating an offset value associated with the selected DFE component of DQ0 (e.g., a resistance offset value, a voltage offset value, a current offset value, etc.).

[0077] At 1008, the control logic of the RXOC circuit can perform a binary search based on the slicer result signal to identify the pull-up code or pull-down code for the DFE component. For example, refer to Figure 4 , the RXOC control logic 408 can perform a binary search based on the slicer result signal to identify the pull-up code or pull-down code for the selected DFE component. To perform the binary search, the RXOC control logic 408 can identify a target code, such as 0101. Using the non-limiting example target code 0101, the RXOC control logic can determine negative by comparing 0101 with 1000. Then, the RXOC control logic 408 can determine positive by comparing 0101 with 0100. Next, the RXOC control logic 408 can determine negative by comparing 0101 with 0110. Finally, the RXOC control logic can determine that the binary search is complete by comparing 0101 with 0101.

[0078] At 1010, the control logic of the RXOC circuit can send a calibration signal associated with the pull-up code or pull-down code to the DQ circuit. For example, refer to Figure 4, the RXOC control logic 408 can generate a calibration signal including a pull-up code or a pull-down code to DQ0. The calibration signal can be sent to DQ0 at the rising edge or the falling edge of the first clock cycle. For example, if the limiter result signal is received at the rising edge of the first clock cycle, the calibration signal can be sent at the falling edge of the first clock cycle. Conversely, if the limiter result signal is received at the falling edge of the first clock cycle, the calibration signal can be sent at the rising edge of the first clock cycle.

[0079] At 1012, the DQ circuit can calibrate the DFE component based on the pull-up code or the pull-down code included in the calibration signal. For example, referring to Figure 4 , DQ0 can calibrate the first DFE component 504a based on the pull-up code or the pull-down code included in the calibration signal. For example, the pull-up code or the pull-down code can be used to calibrate the selected DFE component (e.g., the first DFE component 504a), e.g., i.e., how many MOSFETs are turned on or off (see Figure 6 ). For example, referring to Figure 6 , using the pull-up code or the pull-down code to calibrate the selected DFE component can minimize the current difference between the left dashed box and the right dashed box. For example, referring to Figure 4 and 9 , the RXOC control logic 408 sets all RXOC codes to 0. Then, the RXOC control logic 408 sets all pull-up codes and pull-down codes to 0. Based on the limiter result signal received from the DQ selection component, the RXOC control logic 408 can determine how to change the pull-up code. Then, at the rising edge of the clock cycle, the RXOC control logic 408 can set the pull-up code to 1000. At the falling edge of the clock cycle, the RXOC control logic can perform a limiter operation. Then, the RXOC control logic 408 can perform a code decision to determine whether to hold the code as 1 or set the code to 0. This can be performed for each bit in the code (e.g., two bits, three bits, four bits, etc.). The loop is executed until all four bits have been determined for the limiter result signal. Then, the calibration code (e.g., the pull-up code or the pull-down code) can be sent to the selected DFE component / DQ circuit. Additional details of the calibration process are described below in conjunction with Figure 7 . Referring to Figure 7 , five pulses generated by the oscillator 404 are associated with the calibration of a DFE component. The first pulse can be used to indicate Figure 6 whether the transistors in the left dashed box or the right dashed box shown in are being calibrated. Then, each subsequent pulse can be associated with the calibration of one bit of the pull-up code or the pull-down code. For example, referring to Figure 4 , 6 and 7, at the first pulse, the RXOC control logic 408 can indicate Figure 6whether the transistors in the left dashed box or the right dashed box in [the figure] are being calibrated. At the second pulse, the RXOC control logic 408 may calibrate the first bit of the pull-up code or the pull-down code (e.g., corresponding to the dashed box indicated at the first pulse). At the third pulse, the RXOC control logic 408 may calibrate the second bit of the pull-up code or the pull-down code. At the fourth pulse, the RXOC control logic 408 may calibrate the third bit of the pull-up code or the pull-down code. Finally, at the fifth pulse, the RXOC control logic 408 may calibrate the fourth bit of the pull-up code or the pull-down code.

[0080] FIG. 12 illustrates a block diagram of a system 1200 including a memory system 1202 in accordance with some aspects of the present disclosure. The system 1200 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. As shown in FIG. 12, the system 1200 may include a host 1208 and a memory system 1202 having one or more memory devices 1204 and a memory controller 1206. The host 1208 may be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 1208 may be configured to send data (also referred to as user data or host data) to the memory system 1202 or receive data from the memory system 1202. The memory system 1202 may be a storage product integrating the memory controller 1206 and one or more memory devices 1104, including volatile memory devices such as dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM), to name a few.

[0081] The memory device 1104 may communicate with the memory controller 1106 via a system bus 1101. Data, command / address (CMD / ADD), and clock signal CLK may be transmitted and received between the memory device 1104 and the memory controller 1106 via the system bus 1101. As described above, the memory controller 1106 may send an RXOC_en signal to the RXOC circuit to initiate an operation for RXOC calibration at the RXOC circuit.

[0082] According to some embodiments, the memory controller 1206 is coupled to the memory device 1204 and the host 1108, and is configured to control the memory device 1204. The memory controller 1206 can manage the data stored in the memory device 1204 and communicate with the host 1208. In some embodiments, the memory controller 1206 is designed to operate in a high duty cycle environment, where solid state drives (SSDs), embedded multimedia cards (eMMCs) are used as data storage devices for mobile devices (e.g., smart phones, tablets, laptop computers, etc.) and enterprise storage arrays. The memory controller 1206 can be configured to control the operations of the memory device 1204, such as read, program / write, and / or erase operations. The memory controller 1106 can also be configured to manage various functions regarding the data stored or to be stored in the memory device 1204, including but not limited to bad block management, garbage collection, logical to physical (L2P) address translation, wear leveling, etc. In some embodiments, the memory controller 1106 is also configured to process error correction codes (ECCs) regarding the data read from or written to the memory device 1204. Any other suitable functions can also be performed by the memory controller 1106, e.g., formatting the memory device 1204. The memory controller 1106 can communicate with external devices (e.g., the host 1208) according to a specific communication protocol. For example, the memory controller 1206 can communicate with external devices through at least one of various interface protocols, such as the Non-Volatile Memory Express (NVMe) protocol, the NVMe-over-fabrics (NVMe-OF) protocol, the Peripheral Component Interconnect Express (PCI-E) protocol, the Universal Serial Bus (USB) protocol, the Multimedia Card (MMC) protocol, the Peripheral Component Interconnect (PCI) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the FireWire protocol, etc.

[0083] In various aspects of the present disclosure, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as instructions on a non-transitory computer-readable medium. Computer-readable media include computer storage media. Storage media can be accessible by a memory controller (e.g., Figure 11any available medium accessed by the memory controller 1106) in. By way of example and not limitation, such computer-readable media can include RAM, ROM, electrically erasable programmable ROM (EEPROM), compact disc read only memory (CD-ROM) or other optical disc storage, hard disk drive (HDD) (e.g., magnetic disk storage or other magnetic storage devices), flash drive, SSD, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a processing system (e.g., a mobile device or a computer). As used herein, disk and optical discs include CD, laser disc, optical disc, digital video disc (DVD), and floppy disk, where disks typically reproduce data magnetically, while optical discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0084] The foregoing description of specific embodiments can be readily modified and / or adapted for a variety of applications. Accordingly, such adaptations and modifications are intended to be within the meaning and scope of the equivalent transformation of the disclosed embodiments based on the teachings and guidance presented herein.

[0085] The breadth and scope of the present disclosure should not be limited by any of the above example embodiments, but should be defined only in accordance with the appended claims and their equivalent transformations.

[0086] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Accordingly, other configurations and arrangements can be used without departing from the scope of the present disclosure. In addition, the subject matter described in the present disclosure can also be used in a variety of other applications. The functional and structural features described in the present disclosure can be combined, adapted, modified, and rearranged with each other and in a manner consistent with the scope of the present disclosure.

Claims

1. An external circuit, comprising: a DQ circuit, the DQ circuit including a plurality of decision feedback equalization (DFE) components; and a resistor offset calibration (RXOC) circuit, the resistor offset calibration (RXOC) circuit including: an oscillator configured to: generate an internal clock source; a DQ selection component configured to: select a DFE component from the plurality of DFE components for calibration; and output a limiter result signal indicating an offset value received from the DFE component; and control logic configured to: send a calibration signal associated with the DFE component to the DQ circuit based on the limiter result signal.

2. The external circuit according to claim 1, wherein: the DQ selection component includes a first multiplexer (MUX) and a second MUX, the first MUX is configured to select the DQ circuit, and the second MUX is configured to select the DFE component of the DQ circuit.

3. The external circuit according to claim 1, wherein, the control logic is further configured to: receive the limiter result signal at a first edge of a clock cycle associated with the internal clock source.

4. The external circuit according to claim 3, wherein, the control logic is further configured to: perform a binary search based on the limiter result signal to identify a pull-up code or a pull-down code for the DFE component.

5. The external circuit according to claim 4, wherein, the control logic is further configured to: send the calibration signal to the DQ circuit at a second edge of the clock cycle associated with the internal clock source, wherein the first edge is one of a rising edge or a falling edge, wherein the second edge is the other of the rising edge or the falling edge, and wherein the calibration signal includes the pull-up code or the pull-down code.

6. The external circuit according to claim 5, wherein, the DQ circuit is further configured to: calibrate the DFE component based on the pull-up code or the pull-down code included in the calibration signal received from the control logic at the second edge of the clock cycle.

7. The external circuit according to claim 1, wherein, the oscillator is further configured to: receive an RXOC participation signal, wherein the internal clock source is generated in response to receiving an RXOC participation command.

8. The external circuit according to claim 7, wherein, the oscillator is enabled to generate the internal clock source without a column address strobe (CAS) command.

9. A memory device, comprising: a memory array; and an external circuit coupled to the memory array, the external circuit including: a DQ circuit, the DQ circuit including a plurality of decision feedback equalization (DFE) components; and a resistor offset calibration (RXOC) circuit, the resistor offset calibration (RXOC) circuit including: an oscillator configured to: generate an internal clock source; a DQ selection component configured to: Select a DFE component among the plurality of DFE components for calibration; Output a limiter result signal indicating an offset value received from the DFE component; and Control logic configured to: Send a calibration signal associated with the DFE component to the DQ circuit based on the limiter result signal.

10. The memory device according to claim 9, wherein: The DQ selection component includes a first multiplexer (MUX) and a second MUX, The first MUX is configured to select the DQ circuit, and The second MUX is configured to select the DFE component of the DQ circuit.

11. The memory device according to claim 9, wherein, The control logic is further configured to: Receive the limiter result signal at a first edge of a clock cycle associated with the internal clock source.

12. The memory device according to claim 11, wherein, The control logic is further configured to: Perform a binary search based on the limiter result signal to identify a pull-up code or a pull-down code for the DFE component.

13. The memory device according to claim 12, wherein, The control logic is further configured to: Send the calibration signal to the DQ circuit at a second edge of the clock cycle associated with the internal clock source, wherein the first edge is one of a rising edge or a falling edge, wherein the second edge is the other of the rising edge or the falling edge, and wherein the calibration signal includes the pull-up code or the pull-down code.

14. The memory device according to claim 13, wherein, The DQ circuit is further configured to: Calibrate the DFE component based on the pull-up code or the pull-down code included in the calibration signal received from the control logic at the second edge of the clock cycle.

15. The memory device according to claim 9, wherein, The oscillator is further configured to: Receive an RXOC participation signal, wherein the internal clock source is generated in response to receiving an RXOC participation command.

16. The memory device according to claim 15, wherein, Cause the oscillator to generate the internal clock source without a column address strobe (CAS) command.

17. A method for resistor offset calibration (RXOC) by a peripheral circuit, comprising: Generating an internal clock source by an oscillator of an RXOC circuit; Selecting a DFE component from a plurality of decision feedback equalization (DFE) components of a DQ circuit by a DQ selection component of the RXOC circuit for calibration; Identifying an offset value associated with the DFE component by the DQ selection component of the RXOC circuit; Outputting a limiter result signal based on the offset value received from the DFE component by the DQ selection component of the RXOC circuit; and Sending a calibration signal associated with the DFE component to the DQ circuit by control logic of the RXOC circuit based on the limiter result signal.

18. The method according to claim 17, wherein: The DQ selection component includes a first multiplexer (MUX) and a second MUX, The first MUX is configured to select the DQ circuit, and The second MUX is configured to select the DFE component of the DQ circuit.

19. The method according to claim 17, further comprising: Receiving the limiter result signal at a first edge of a clock cycle associated with the internal clock source by the control logic of the RXOC circuit.

20. The method according to claim 19, further comprising: Performing a binary search by the control logic of the RXOC circuit based on the limiter result signal to identify a pull-up code or a pull-down code for the DFE component.

21. The method according to claim 20, further comprising: Sending the calibration signal to the DQ circuit at a second edge of the clock cycle associated with the internal clock source by the control logic of the RXOC circuit, wherein the first edge is one of a rising edge or a falling edge, wherein the second edge is the other of the rising edge or the falling edge, and wherein the calibration signal includes the pull-up code or the pull-down code.

22. The method according to claim 21, further comprising: Calibrating the DFE component by the DQ circuit of the RXOC circuit based on the pull-up code or the pull-down code included in the calibration signal received from the control logic at the second edge of the clock cycle.

23. The method according to claim 17, further comprising: Receiving an RXOC participation signal by the oscillator of the RXOC circuit, wherein the internal clock source is generated in response to receiving an RXOC participation command.

24. The method according to claim 23, wherein, The oscillator generates the internal clock source without a column address strobe (CAS) command.

25. A memory system, comprising: A memory device, the memory device including: A memory array; and A peripheral circuit, the peripheral circuit including: A DQ circuit, the DQ circuit including a plurality of decision feedback equalization (DFE) components; and A resistor offset calibration (RXOC) circuit, the resistor offset calibration (RXOC) circuit including: An oscillator, the oscillator being configured to: Generate an internal clock source; A DQ selection component, the DQ selection component being configured to: Select a DFE component from the plurality of DFE components for calibration; Output a limiter result signal indicating an offset value received from the DFE component; and Control logic, the control logic being configured to: Send a calibration signal associated with the DFE component to the DQ circuit based on the limiter result signal; and A memory controller, the memory controller being coupled to the memory device and being configured to control the operation of the memory device.

26. The memory system according to claim 25, wherein: The DQ selection component includes a first multiplexer (MUX) and a second MUX, The first MUX is configured to select the DQ circuit, and The second MUX is configured to select the DFE component of the DQ circuit.

27. The memory system according to claim 25, wherein, the control logic is further configured to: receive the limiter result signal at a first edge of a clock cycle associated with the internal clock source.

28. The memory system according to claim 27, wherein, the control logic is further configured to: perform a binary search based on the limiter result signal to identify a pull-up code or a pull-down code for the DFE component.

29. The memory system according to claim 28, wherein, the control logic is further configured to: send the calibration signal to the DQ circuit at a second edge of the clock cycle associated with the internal clock source, wherein the first edge is one of a rising edge or a falling edge, wherein the second edge is the other of the rising edge or the falling edge, and wherein the calibration signal includes the pull-up code or the pull-down code.

30. The memory system according to claim 29, wherein, the DQ circuit is further configured to: calibrate the DFE component based on the pull-up code or the pull-down code included in the calibration signal received from the control logic at the second edge of the clock cycle.

31. The memory system according to claim 25, wherein, the oscillator is further configured to: receive an RXOC participation signal, wherein the internal clock source is generated in response to receiving an RXOC participation command.

32. The memory system according to claim 31, wherein, cause the oscillator to generate the internal clock source without a column address strobe (CAS) command.

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